VIT

UNIVERSITY
(Estd. u/s 3 of UGC Act 1956)

SCHOOL OF ELECTRONICS ENGINEERING MODEL QUESTION PAPER B.Tech. Electronics and Communication Engineering V - Semester ECE301 VLSI System Design Max. Marks : 100 Time: 3 Hours Answer ALL Questions 1. The following figure shows a simple logic function realized with Boolean gates. (5)

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4. 5.

6.

Implement the function Z using static CMOS as a one stage Complex Gate. A maximum of 12 transistors is allowed. Design a negative level-sensitive D latch in which the Q output, by a signal RESET, may be reset to 0 independently of the state of the CLK signal (i.e., RESET=1 Q = 0) and explain the operation its functionality with suitable timing diagram. Discuss the following over the MOS transistor. (i) Body effect (ii) Channel length modulation (iii) Mobility degradation Derive the current flow equation for the nMOS in linear mode of operation with suitable diagrams. Consider an NMOS transistor with the following parameters: tox = 6 nm, L= 0.24m, W=0.36 m, LD = LS = 0.625 m, CO =3x 10-10 F/m, CjO =2 x 10-3 F/m2, and CjswO =2.75 x 10-10 F/m, ox = 3.97o, o = 8.85x10-14 F/cm, Determine the zero-bias value of all relevant capacitances. Determine Vo for each of the circuits shown. Assume that Vtn = |Vtp| = 0.5V, that there is no subthreshold conduction, that the capacitor is initially discharged and that there are no body effects.

(6)

(6)

(6) (6)

(2)

(i)

(ii)

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Let a 4x inverter have transistors four times as wide as those of a unit inverter. If a (5) unit inverter has three units of input capacitance and parasitic delay of Pinv, what is the input capacitance of a 4x inverter? What is the logical effort? What is the parasitic delay? (a) The following figure show two functions, X and Y, in static CMOS, where both (12) are functions of the inputs A, B, C, and D. All transistors have the minimum length L = 130 nm. The minimum transistor width is W = 160 nm, in this technology.

(i)

Determine the Boolean expression for both f(X) and f(Y). Do the two circuits implement the same function?

(ii)

The width W of all transistors with the input A is given in the figure, for a circuit that is assumed to be balanced. These values indicate what ratio between n- and p-channel transistors that should be used when balancing the circuit. Determine that ratio, i.e.kratio = kn/kp .

(iii)

Balance the left circuit. Assume worst case, i.e. when only single paths are open to supply or ground. The equivalent resistance in a minimum n-channel is Req-n = 14 k and in a minimum p-channel the resistance is Req-p = 35 k. Determine the lowest possible resistance from the supply VDD to the output X and from the output X to ground.

(iv)

(v)

The propagation delay is to be compared. Assume that the signals B, C, and D usually arrive early and that the signal A is late. One of the circuits can be expected have shorter propagation delay. Which circuit and which propagation delay, tpLH or tpHL. Give a brief motivation! (OR)

(b) (i) Draw the transistor diagram of a 3-input complementary CMOS NOR gate. Size the transistors so that the rise and fall times are the same. Assume n = (7) 2 p. And Determine the best case rise and fall propagation delays using Elmore delay model. (ii) In the figure shown below, calculate the path delay where the input capacitance of the inverter is x, for 2-input NAND gate is 2x and for 3-input NAND gate is 3x. Note: No need to evaluate the value of x. (5)

CL = 10x

9.

(a) Answer the following: (i) (ii) What is the difference between blocking and non-blocking statement? After the following statement, what value does A have? Give your answer in binary. wire [7:0] A = -7h34; (iii) Given A=4b1000, b= 4b0011,C= 3b1X0 and D= 4b110Z. Perform the following A ~^D C >>3 (or)

(8)

(b) Answer the following: (i) What is the difference between wire and reg? (ii) Given the following Verilog code, what value of "a" is displayed? always @(clk) begin a = 0; a <= 1; $display(a); end (iii)What is the final value of d in the following example? initial begin b= 1b1; c = 1b0; #10 b = 1b0; initial begin d = #25 (b|c); end (iv)Give the result of each Verilog expression (in binary) for the following inputs: A = 4b1001, B = 5b10010, and C = 5b11010. Assume A is a 4-bit wire and B and C are each 5-bit wires. Show your results using Verilog notation, such as 3b101. A & (B | C); (A < B) ? A : B;

10.

For the following pieces of Verilog code, identify what type of programming (6) (structural, behavioral, or RTL) is used? For each module list all types that are used. Also, draw a schematic (gates, latches, DFFs, wires) diagram for the circuits created by each of these modules. Label wires with the variable names. If wires are more than one bit, also label the wire with the number of bits.

(i) module a_module(input a, b, clock, output reg c); wire d = b & a; always @(posedge clock) c <= ~d;

endmodule

(ii) module b_module(input a, b, output d); wire c; and (c, a, b); not(d, c); endmodule

11.

Consider the truth table Inputs Enable G 0 1 1 1 1 B X 0 0 1 1 Select A X 0 1 0 1 Y3 0 0 0 0 1 Y2 0 0 0 1 0 Y1 0 0 1 0 0 Y0 0 1 0 0 0 Outputs

(10)

Write two Verilog module descriptions (designs must be synthesizable) of the same 2-4 line decoder described in the above table (i) using an always statement, and (ii) without using an always statement.

12.

For the following code snippets, indicate the values of the variables at each (6) timestep given in the associated chart. All values should be given as decimal numbers. Part of the table has already been filled in for you. reg [3:0] C; reg [3:0] A, B; always@(*) #1 C = A+B; initial begin #1 A <= 4;

#1 B <= A << 1; B <= #2 3; A <= #2 4; B <= #1 A + 1'b1; #2 A <= #1 B ^ A; end

13.

(i) Give a verilog structural level description of a 4-bit ripple carry adder. (ii) Write verilog code for 1 to 4 demultiplexer module by using 2 to 4 decoder?

(6) (6)

14.

Explain about setup time and hold time. What will happen if there is setup time and (4) hold tine violation, how to overcome this?

15.

The following figure shows a datapath with three registers, R1, R2 and R3 together (6) with a multiplexer M and blocks containing combinatorial logic, L. The registers have a setup-time tSu = 0.5 ns and a delay-time tR = 0.5 ns. The delay in a logical block L is tL = 3 ns and in the multiplexer, tM = 1 ns. A clock signal CLK that arrives at R2 after R1 and at R3 after R2 is denoted as positive clock skew. Consequently, when CLK arrives at R2 after R3 and at R1 after R2 is denoted as negative clock skew.

(i) (ii)

Determine the minimum clock period time if clock skew is disregarded. Determine the minimum clock period time if there is 1ns positive clock skew between adjacent registers.

(iii) Determine the minimum clock period time if there is 3ns positive clock skew between adjacent registers.