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Title
ANTIK, Solutions to Quizzes
File
ANTIK_0016_PM_quizSolutions_PA3.odt
Type
PM -- Promemoria
Area
es : docs : courses : antik
Created
J Jacob Wikner
Approved
J Jacob Wikner
Issued
J Jacob Wikner, jacwi50
Class
Public
Promemoria
ANTIK, Solutions to Quizzes
Description
This document contains the solutions to the quizzes for the TSEI09 (ANIK) and TSTE08 (ATIK)
courses for 2011.
Outline
Table of Contents
1.ATIK Quizzes......................................................................................................................................................2
1.1 Quiz 1: Single gain stages...........................................................................................................................................2
2.ANIK Quizzes......................................................................................................................................................4
2.1 Quiz 1: Simple gain stages..........................................................................................................................................4
History
Rev Date Comment Issued/created by
PA1 2011-01-26 Created document for the first quiz. J Jacob Wikner
PA2 2011-02-10- Updated with solutions to the second quiz. J Jacob Wikner
PA3 2011-02-17 Updated with solutions to the third quiz. J Jacob Wikner
P3A 2011-02-17 J Jacob Wikner
'
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Title ANTIK, Solutions to Quizzes ID jacwi50
1. ATIK QUIZZES
1.1 Quiz 1: Single gain stages
Assume an NMOS common-source stage with high-
impedance active PMOS load. Also assume hand-
calculation formulas. The input voltage is fixed at a certain
DC level. What handle(s) do I have to increase the DC
gain?
1) Increase the current
2) Increase the channel length of the CMOS
3) Decrease the transistor width
4) Decrease the bulk-source voltage
5) Increase the supply voltage
1.1.1 Solutions and motivations
The keywords of the quiz are:
hand-calculationsand input voltage is fixed at a certain DC
The latter one implies something important. Consider the current in the saturation region:
I
D
=
W
L
(V
i
V
T
)
2
(1.1)
Notice, that to maintain the same input level, if I increase the current, I also have to decrease the
width, W, to maintain the same input DC voltage. Let us instead look at the transfer function for
this stage, which is given by
A
0
=
g
mN
g
P
+g
N
(1.2)
where we know that (for hand-calculation)
g
mN
=
2I
D
V
effN
=
2I
D
V
i
V
T
=
2 I
D
V
i
V
T0
( .
V
SB
2
F

.
2
F
)
and g
p
\ I
D

\
0
I
D
L
(1.3)
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Which gives
A
0
=
L
\
0

1
V
i
V
T0
( .
V
SB
2
F

F
)
(1.4)
The parameters that are now handles corresponding to the bullets in the quiz are: the channel
length, L from (2), and the bulk-source voltage,
V
SB
from (4).
1) Increase the current
We could do that, but in that case we have to change, say W too or decrease the L . So, it is
not an option. One could argue that you could do 4x the W and then 2x the L to cover for a
2x in current. In that case, you need to add that to your comments. This is however more of a
re-design and touches upon (2) below.
2) Increase the channel length of the CMOS
That is definitely do-able. According to the equation, if we increase the L we will improve the
gain. If current changes, we do not care as it does not affect the DC gain expression.
3) Decrease the transistor width
If we decrease the transistor with we either have to (a) decrease current or (b) decrease the
channel length L , which would in turn reduce the gain, respectively. Once again, one could
elaborate on these steps: decrease 2x W > decrease 4x
I
D
> increase 2x L . But again, that
has to be motivated and it is more of a re-design and yet again boils down to bullet (2) above.
4) Decrease the bulk-source voltage
Decreasing the bulk voltage is the same as increasing the source-bulk voltage. An increase in
source-bulk voltage would increase the
V
T
and in turn would decrease the
V
eff
=V
i
V
T
.
According to the gain expression, that would increase the DC gain. One could argue on how to
do this for an NMOS common-source stage though. (Notice that the caveat: input voltage is
fixed at a certain DCis the one causing this somewhat contradictive conclusion).
5) Increase the supply voltage
The supply voltage does not play any role at all.
1.1.2 Correct answer
Statement (2) is correct and also (4) would be approved as a correct statement.
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1.2 Quiz 2: Switched capacitors
What happens if you increase the sample frequency in a standard switched-
capacitor accumulator?
1) The simulated resistance decreases
2) Higher requirements are put on OP unity gain frequency
3) The influence of parasitics increases
1.2.1 Solutions and motivations
From the theory behind a switched capacitor we know that the equivalent resistance is
R
eq
=
T
C
=
1
f
clk
C
(1.5)
If we increase the sample frequency, the equivalent/simulated resistance will decrease.
If the bandwidth of the amplifier is limited we have a settling problem. The OTA will not settle fast
enough. Remember that for an amplifier in a feedback configuration the bandwidth is
o
BW
=o
ug
(1.6)
The is dependent on the gain of the accumulator, and would be something like
=
C
1
C
1
+C
2
(1.7)
where
C
1
and
C
2
are the capacitors involved. Regardless of what we see that this term is always
smaller than unity, i.e., always lower than the unity-gain frequency. It would be very strange
otherwise, wouldn't it? So, if we increase the sample frequency, the gap between the unity-gain
frequency and sample frequency decreases - even vanishes. This means that we need to put
higher requriements on the OP unity-gain. The higher sample frequency, the more difficult:
f
clk
f
ug
(1.8)
Regarding capacitors: the higher frequency we want to reach the larger role the paraistic
capacitances play. Eventhough we have selected as parasitic-insensitive accumulator, such that
the stready-state transfer function is not affected, any extra capacitance may limited the obtainable
speed. The on-resistance of switches together with capacitance will make life worse and their
effects will be more visible with higher clock frequency.
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1.2.2 Correct answer
1, 2, and maybe 3 (I will accept 1,2 and 1,2,3).
1.3 Noise
In a common-source amplifier, to minimize the output-referred noise,
how should you design the transconductance of the active load?
1) To be as high as possible
2) To be as low as possible
3) The active load does not add noise to the output
1.3.1 Solutions and motivation
The transfer functions from input to output for the NMOS and PMOS transistors,
respectively, are given by
H
n
=
g
mN
g
N
+g
P
and H
p
=
g
mp
g
N
+g
P
(1.9)
The noise models for the NMOS and PMOS gates are given by
v
nn
2
( f )=4k T / g
mN
and v
np
2
( f )=4k T / g
mP
(1.10)
Using the superformula we get the noise at the output as
S
o
( f )=v
nn
2
(f )H
n
(f )
2
+v
np
2
( f )H
p
( f )
2
(1.11)
which equals
S
o
( f )=4k T
g
mN
( g
P
+g
N
)
2

(
1+
g
mP
g
mN
)
(1.12)
To minimize this expression we should minimize
g
mP
.
1.3.2 Correct answer
2.
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2. ANIK QUIZZES
2.1 Quiz 1: Simple gain stages
What happens if you use a passive device
(resistor) as load in an NMOS common-source
stage rather than an active PMOS?
1) The area becomes larger for the same gain
2) The power consumption increases for same
gain and DC levels
3) The gain increases with increasing input
level
Let us compare the gain for the two. The DC gain of the active load is (see section 1.1)
A
0

L
\
0

1
V
i
V
T0
(2.1)
and for the passive device we have
A
0
g
m
R
L
=
2I
D
V
i
V
T0
R
L
=2o( V
i
V
T0
)R
L
(2.2)
If we set the two expressions on DC gain to be equal and assume same DC levels, we get:
2 I
D
V
i
V
T0
R
L

1
\

1
V
i
V
T0
R
L
\/ 2I
D
(2.3)
1) The area becomes larger for the same gain
Yes, it does; resistors are generally more bulky than the transistors.
2) The power consumption increases for same gain and DC levels
The question was a bit ambiguous and I apologize for that. If we look at the formulas for the
active power consumption
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L
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Title ANTIK, Solutions to Quizzes ID jacwi50
P
1
=V
dd
I
D1
=V
dd
o
1
V
eff
2
=
V
dd
2
V
eff
g
m
=
V
dd
2
V
eff
g
out

g
m
g
out
=
V
dd
2
V
eff
g
out
A (2.4)
and the passive
P
2
=V
dd
I
D2
=V
dd
o
2
V
eff
2
=
V
dd
2
V
eff
g
m
=
V
dd
2
V
eff

A
R
L
(2.5)
Let us compare these two expressions and claim that
P
2
>P
1
according to the statement.
P
2
>P
1

V
dd
2
V
eff

A
R
L
>
V
dd
2
V
eff
Ag
out
R
L
>1/ g
out
=r
out
(2.6)
So, these formulas would indicate that a lower power consumption can be obtained if we make
the resistor smaller. But the objective here is to obtain high-gain for this device and the
resistance would become unreasonably big, see (1), to maintain gain with low current. Currently
simply has to be increased, thus power consumption. I will therefore accept (2) as a correct
answer since I messed up my line of thoughts looking at the equations above.
3) The gain increases with increasing input level
We see directly from the expression A
0
2o( V
i
V
T0
)R
L
that the gain increases with higher
V
eff
. You will also see this in the labs.
2.1.1 Correct answers
All bullets are true and/but I would accept a discussion around (2). I would also be kindw.r.t.
(1) as it was not clearly mentioned by me in the first lectures.
2.2 Gain stages
What is/are the drawback(s) with a cascoded gain stage?
1) It requires more current to achieve same gain as a two stage amplifier would
2) The voltage swing is lower than for a two-stage amplifier
3) The poles are unfortunately well separated
2.2.1 Solutions and motivation
The advantage with a cascoded gain stage is that you can save current to get the same gain as a
two-stage would require. The current is re-usedin the same branch and thus we save power in
some sense. Notice also that the output driving capability needs to be the same for both
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architectures. This means that the last stage of the multi-(two-)stage amplifier needs to be able to
deliver as much current as the cascoded gain stage does.
The drawback is that the gain is affected. The gain is reduced since we stack more transistors on
top of eachother. Essentially, for each transistor we loose some 100~mV.
Another advantage with cascoded stages is that they have their poles well separated. The internal
node (the node between the original drive transistor and the cascode) is normally just a small
metalstrip and will not have much capacitance besides the capacitance of the transistors
themselves.
2.2.2 Correct answers
2.
2.3 Current mirrors
What are the drawback(s) with a wideswing current mirror?
1) You need more biasing current
2) It has a relatively low output swing
3) It has a low output impedance
2.3.1 Solutions and motivation
The wideswing current mirror has almost only advantages over other current mirrors: It has a
relatively low output swing, it has a high output impedance and low input impedance. It requires
however an additional bias current and thus a bit more complicated to design and tune in well.
2.3.2 Correct answer
1.
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