Universiti Teknikal Malaysia Melaka

Faculty of Electronics and Computer Engineering

Department of Computer Engineering

BENM 2123 MICROPROCESSOR

TECHNOLOGY
Chapter 3:

The 68000 Hardware Architecture

07/08 Masrullizam Mat Ibrahim
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Introduction

The 68000 Hardware Architecture

The hardware requirement and software functions have to be understood before working with any microprocessor. This chapter will examine all 64 pins of MC68000. For interfacing with the bus system, the crucial thing is the understanding of input and output signals in MC68000. The signals functions are divided into 8 group:

Power and clock Processor status M6800 peripheral control System control Interrupt control Bus arbitration control Asynchronous bus control Address bus and data bus

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CPU Specification and Pin Descriptions

The 68000 Hardware Architecture

MC68000 specifications:

16 bits microprocessor (16 bit bidirectional data bus) 24 bits address bus (16 million bytes of memory) Control signal (take over 68000 buses) Interrupt lines (7 levels of external hardware interrupt) Control output ( decode of 8 internal CPU states) Clock speed (4 to 16 MHz) There are 3 package:

Pin configuration

Dual inline package (DIP)

Made from plastic and ceramic Popular and cheaper

Pin grid array (PGA)

Smaller than DIP More expensive than DIP Needed socket

Plastic leadless chip carrier (PLCC)

Latest package

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The 68000 Hardware Architecture

DIP LCC
(Leadless chip carrier)

PLCC

QFP

(Quad flat package)

PGA

Slot package

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Pin descriptions

The 68000 Hardware Architecture

There are 8 groups of pin which are;

+5V CLK VCC VCC D15 D0 A23 A1

Data bus Address bus Asynchronous bus control

FC2

Processor status

FC1 FC0 E VMA VPA

AS R/W UDS

M6800 peripheral control

68000

LDS

CPU

DTACK
BR BG BGACK

System control

BERR RESET HALT GND GND

Bus arbitration control Interrupt control

IPL0 IPL1
IPL2

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Power and Clock

The 68000 Hardware Architecture

These signals deals with processor power and clock inputs Power
There are 4 pins; Vcc (2 pins) and GND (2 pins). Vcc - 5 Volt 5% (pin 14 and 49) GND Ground (pin 16 and 53)
At 8MHz processor uses 1.5W and current around 300mA
14 5V 49

Clock

CLK pulses supply by clock circuit e.g. resonator, oscillator, RC network (pin 15) 8, 10, 12.5, 16 MHz frequency Must TTL-compatible with 50% duty cycle

Vcc Vcc Clock circuit

CLK 15 68000

GND GND 16 53

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Processor Status

The 68000 Hardware Architecture

This group of signals is used to output the encoded processor status. Pins of signals ; FC0, FC1 and FC2. These signals indicate the type of cycle microprocessor is currently executing. The function code outputs are valid when AS signal is active.
FC2
0 0 0 0 1 1 1 1

FC1
0 0 1 1 0 0 1 1

FC0
0 1 0 1 0 1 0 1

Cycle type
Reserved User data User program Reserved Reserved Supervisor data Supervisor program interrupt acknowledge

68000 AS* FC0 FC1 FC2 28 27 26 INTACK* 6

Circuit of interrupt acknowledge detection

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M6800 Peripherals Control

The 68000 Hardware Architecture

This group of signals to give the 68000 capability to control 6800 peripherals. Pins of signals; E, VMA and VPA E (enable)

Generate proper timing signal for 6800 peripherals It is used to inform the 68000 that it has addressed a 6800 peripheral and that the data transfer should be synchronized with E clock Goes LOW when processor synchronize with E clock

VPA (valid peripheral address)

VMA (valid memory address)

20 19 21

VMA
VPA 68000

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The 68000 Hardware Architecture

M6800 peripheral interface

D0-D7

D0-D7

A1-A23 Peripheral AS* 68000 LDS* address decoder

6800 Peripheral

CS2*

E VMA*

E CS1*

VPA*

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System Control

The 68000 Hardware Architecture

This group of signals is used to reset the processor, to halt the processor and to signal a bus error to the processor. Pin of signals; BERR (22), RESET (18), HALT (17) BERR (bus error)

To inform the processor that the cycle currently executing has a problem. The problem maybe:

No response from a device No interrupt vector number returned An illegal access request rejected by a memory management unit. Some other application-dependent error

Unidirectional input signal To stop the processor and tell the system that processor is not executing Bidirectional signal To reset the processor and reset the peripheral Bidirectional signal
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HALT

RESET

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Interrupt Control

The 68000 Hardware Architecture

This group of signals is to control the interrupt. Pins of signals; IPL2, IPL1, IPL0 The three inputs signals are used by external circuitry to request level of hardware interrupt. There are 7 levels of interrupt where level 7 is the highest priority.
IPL2* 1 1 1 1 0 0 0 0
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IPL1* 1 1 0 0 1 1 0 0

IPL0* 1 0 1 0 1 0 1 0

Interrupt Level 0 (lowest, none) 1 2 3 4 5 6 7 (highest, nonmaskable)

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Bus Arbitration Control

The 68000 Hardware Architecture

These signals to place the 68000 in a wait state while we make use of the hardware connected to its buses. Pins of signals; BR, BG and BGACK. BR (bus request)

to requests use of buses unidirectional input signal to permit bus master takes control the buses unidirectional output signal to inform processor it already takes control of the BUSES unidirectional input signal Requesting devices (bus master) request use of 68000s bus by activating BR input. The 68000 will respond to bus master by taking BG low. The 68000 will release control its buses until the end cycle. When the new bus master want to take control BGACK is asserted. Once BGACK asserted, the new bus master can bring BR to a high level

BG (bus grant)

BGACK (bus grant acknowledge)

Arbitration bus protocol works:

1.

2.
3. 4. 5.

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The 68000 Hardware Architecture

Connection of bus arbitration

A1-A23

68000 13 11 12 Alternate

BR* BG* BGACK*

bus
Master

D0-D15

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Asynchronous Bus Control

The 68000 Hardware Architecture

These signals are essential to the proper operation of external hardware (asynchronous data transfer). Pins of signals; AS (6), R/W (9), UDS (7), LDS (8) and DTACK (10). AS (address strobe)

This signal is used to indicate a valid memory address exist on the address bus. unidirectional output signal Determine whether read or write operation unidirectional output signal Controls data on even bytes (bit 8 to 15) unidirectional output signal Controls data on odd bytes (bit 0 to 7) unidirectional output signal
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R/W (read/write)

UDS (upper data strobe)

LDS (lower data strobe)

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The 68000 Hardware Architecture

Combination of signals and corresponding data on the bus

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The 68000 Hardware Architecture

DTACK (data acknowledge)

DTACK is used by external circuitry to perform asynchronous data transfer Inform processor that the data transfer has completed Unidirectional input signal Data is placed in data bus during read cycle when DTACK is activated and kept there until DTACK asserted by external hardware.
AS* DTACK*

68000 R/W*

LDR*

LDS* UDS*

UDR*

LDW*

UDW*
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Address & Data Buses

The 68000 Hardware Architecture

Address bus

Carry memory location address in normal operation During interrupt, A1, A2, A3 contain interrupt level, A4 to A23 are HIGH A0 is indirectly used to UDS* and LDS* unidirectional output signal (A1 A23) Carry information for data transfer between processor and external hardware during normal operation During interrupt, D0 to D7 transfer interrupt vector number from external devices bidirectional signal (D0 D15)

Data bus

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System Timing

The 68000 Hardware Architecture

Critical issue in the design of 68000 based system

To interpret CPU timing diagram supplied by manufacturer Instruction cycle - time for execution of an instruction Bus cycle time for read or write operation Clock cycle reciprocal of frequency State time half of clock cycle, S0 to S7

Relation between the cycle

Cycle state Clock cycle Cycle bus Instruction cycle for MOVE.W

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The 68000 Hardware Architecture

Processor HALT timing

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The 68000 Hardware Architecture

HALT timing protocol work:

While HALT* signal is asserted, address bus and data bus signals are tristated The processor goes into wait state When HALT is deactivated, processor uses few states to do some internal housekeeping Then new cycle of previous operation begin

Halt operation allow single-step debugging program

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The 68000 Hardware Architecture

Bus arbitration timing

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Exception Processing

The 68000 Hardware Architecture

A flexible method to recover from catastrophic system faults called exception handler Also define as operations of the processor outside the normal process External exception

Interrupt Bus error Reset Generated by instruction Tracing Execution error (divide by zero)

Internal exception

One of the state that processor might be functioning a part form normal and halted

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The 68000 Hardware Architecture

The sequence of processing:

Save contents of SR and set S bit to enter supervisor state Obtain exception vector Save PC and SR contents on stack Obtain a new context and resume execution at address specified by exception vector

Special exception:

Reset Externally generated at power on by system hardware Bus error BERR* signal activated Address error when processor tries to read a word form odd location Trace set T bit to allow single step debugging process Interrupt external interrupt sets three IPL* signals to select interrupt level

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Exception Handler

The 68000 Hardware Architecture

The actual section of source code that takes care of exception process Each code differs from one exception to another The operation look similar

The algorithms used must preserved the data that is altered during exception

For example, the final result of these two source codes is exactly same although the way it written is different
MOVE.L D0,-(A7) MOVE.L D1,-(A7) MOVE.L D2,-(A7) MOVEM.L D0-D2, -(A7)

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Privilege mode

The 68000 Hardware Architecture

Two privilege mode

Supervisor User

Provide security to the system S bit determine the types of privilege

S = 1 (supervisor) S = 0 (user)

Supervisor state can handle system operation

Higher privilege All instructions can be executed

User state only deals with application programming that Restricted from some instruction; STOP, RESET, RTE, etc. Exception can change the privilege mode which current S bit is saved, then S is set and resume in supervisor mode

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