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Statistical Design of the 6T SRAM Bit Cell

Gupta, V. ; Anis, M. ; Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada

This paper appears in: Circuits and Systems I: Regular Papers, IEEE Transactions on Issue Date : Jan. 2010 Volume : 57 , Issue:1 On page(s): 93 ISSN : 1549-8328 INSPEC Accession Number: 11147903 Digital Object Identifier : 10.1109/TCSI.2009.2016633 Date of Publication : 06 March 2009 Date of Current Version : 22 January 2010 Sponsored by : IEEE Circuits and Systems Society

ABSTRACT In this paper, a method for the statistical design of the static-random-access-memory bit cell is proposed to ensure a high memory yield while meeting design specifications for performance, stability, area, and leakage. The method generates the nominal design parameters, i.e., the widths and lengths of the bit-cell transistors, which provide maximum immunity to the variations in a transistor's dimensions and intrinsic thresholdvoltage fluctuations. Moreover, the need to deviate from the conventional bit-cell sizing strategy to obtain a high-yield low-leakage design in the nanometer regime is demonstrated.

INDEX TERMS

INSPEC Controlled Indexing SRAM chips , logic design , statistical analysis , transistors Non Controlled Indexing 6T SRAM bit cell , bit-cell sizing strategy , bit-cell transistors , high-yield low-leakage design , intrinsic threshold-voltage fluctuations , static-randomaccess-memory bit cell , statistical design Author Keywords Circuit optimization , design methodology , static-random-access-memory (SRAM) chips

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