BC0040

COMPUTER ORGANIZATION AND ARCHITECTURE

[1 MARK EACH] 1. Input necessary to write the data to the memory is a. Control signal which is memory write b. Address that gives the location of the memory where the data is to be written c. The data d. All of the above 2. How many outputs are generated for writing data to the memory a. Zero b. One c. Two d. Three 3. Interface of external device is referred to as _________ a. Driver b. Controller c. Post d. None of the above

4. A bus which carries a word to or from memory is called __________ a. Data Bar b. Address Bar c. Control bar d. None of the above 5. Width of address bus is equal to a. Size of data bar b. Number of bits in MAR c. Number of bits in MDR d. None of these 6. The processor send commands ________ and _______ to the memory which requires single wise a. Read, Execute

b. Write, execute c. Read, write d. None of those 7. ____________ Command is necessary for the I/O units a. Read b. Write c. Execute d. Start 8. Interrupt request refers to a. An interrupt has occurred b. An Interrupt is acknowledged c. An Interrupt is pending d. none of the above 9. Clock is used to______________ operations a. Regulate b. Synchronize c. Synchronize d. Deregulate 10. __________ Initializes all modules a. Clock b. I/O read c. I/O write d. Reset 11. Bus lines can be repeated into __________ types a. One b. Two c. Three d. Four 12. Which of these is not a bus type dictated a. Dedicated b. Multiplexed c. Non dictated d. None of the above

13. __________ Dedication of buses offer high throughout a. Functional b. Physical c. Both Physical and Function d. None of the above 14. In physical dedication there is ____________ bus contention a. High b. Very high c. Less d. Very less 15. Multiplexed is also referred to as _______________ a. Dedicated b. Non- dedicated c. Non-dictated d. None of the above 16. The method of using the same bus for multiple purpose is known as ________ a. Frequency division multiplexing b. Time multiplexing c. Wave division multiplexing d. None of the above 17. ALE stands for a. Address latch enable b. Address label enable c. Address line enable d. None of the above 18. synchronous timing is a. Simpler to implement b. Simples to test c. is less flexible d. All of the above 19. What is the main cause of performance suffering in device connected to the bus a. The more devices attached to the bus, the greater is the bus length b. The bus may become a bottle neck as the aggregate data transfer demand approaches the

capacity of the bus c. Both a& b d. None of the above 20. MAB stands for a. Memory address buffer b. Memory address bus c. Memory address batch d. None of the above 21. DMA stands for a. Direct memory access b. Dedicated memory access c. Direct managed access d. None of the above 22. PPU stands for a. Point to point unit b. Peripheral Processor unit c. Processors peripheral unit d. Powered processor unit 23. ISA stands for a. International standard Association b. Industry standard association c. Industry standard architecture d. International standard architecture 24. Source and Result operands can be in a. Main memory b. CPU register c. I/O device d. All of the above 25. Each instruction is represented by a sequence of ______ a. Bits b. Bytes c. Words d. Nibble

26. The _______ are written in symbolic represented of machine code using English like language called a. Mini micros, Instructions b. Instructions, Mnemonics c. Program, Mnemonics d. None of the above 27. Virtually all arithmetic and logic operations are a. Unary b. Binary c. Either unary or Binary d. Neither unary or binary 28. ASCII stands for a. Added source code to Instruction Index b. American standard code for information and inter change c. Argued standard code for information and Interrelate d. None of the above 29. General category of data is a. Addresses, b. Numbers c. Characters d. Logical data e. All of the above 30. All machine language in ___________ data type a. Character b. Logical c. Numeric d. Addresses 31. The numbers stored in computer are_____________ a. limited b. Unlimited c. Zero d. None of the above 32. Which type of numerical data are used in common computers

a. Integer or fixed point b. Flouting point c. Decimal d. All of the above 33. IRA stands for a. International Relocation address b. Instruction Relocation address c. International Reference alphabet d. International Reference address 34. ASCIT is represented by __________ pattern a. 6 bit b. 7 bits c. 8 bits d. 16 bits 35. ASCII encoded characters are usually stored and transferred as _____ per characters a. 6 bit b. 7 bits c. 8 bits d. 16 bits 36. Signed integers are stored in __________ form a. 1s compliment b. 2s compliment c. 3s compliment d. 9s compliment 37. In VAX data types all data types are in terms of __________ a. bits b. nibble c. byte d. Ward 38. Data transfer must specify a. The location of the source and destination b. Length of the data to be transferred c. Mode of addressing for each operand

d. All of the above 39. Programmers use organizations called _____________ to represent the data used in computations a. Data types b. Data storage c. Data Structure d. Data class 40. The different ways in which the location of an open and is specified in an instruction are referred to go ____________ a. Addressing mode b. Instruction format c. Memory I/O d. Programmed I/O [2 MARKS EACH] 41. Main memory stores ______ and _______. a. Data, instructions b. Data, address c. Address, instructions d. None of the above .. 42. I. For internal memory, unit of transfer is equal to the number of data lines int and out of the memory module. a. I is true b. II is true c. Both I and II True d. Both are false 43. I. In volatile memory, Information once recorded remains without deterioration until deliberately changed. II. In non-volatile memory, information decays naturally or is lost when electrical power is switched of. a. I is true b. II is true c. Both are true

d. Both are false 44. Identify the control sequence1. PC out, MAR in, read, clear, clear Y, set carry in to ALU, add, Z in 2. Z out, PC in, wait for MFC 3. MDR out, IR in 4. PC out, Y in 5. Address field of IR out, Add, Z in 6. Z out, PC in, End a. Branch instruction b. Conditional branch instruction c. Unconditional branch instruction d. Fetch instruction 45. Arrange the following in sequence the CPU must perform If one or both operands are in memory A Determine whether addressed item is in cache B. Calculate the memory address based on the address mode C. If not the issue command to memory module D. If the address refers to virtual memory, Translate from virtual to actual memory address a. A, B, C, D b. D, B, C, A c. B, C, D, A d. B, D, A, C 46. Arrange in sequence operations performed by CPU. A. I/o module transfers data from to CPU. B I/o module gets data from device C. CPU ready, CPU requests data transfer D. If ready, CPU requests data transfer E. I/o module returns device status a. A, B, C, D, E b. E, D, C, B, A c. C, E, D, A, B d. B, C, D, A, B 47. Arrange in increasing order actions that take place with programmed I/o. G) CPU may wait or come back H) I/o module does not interrupts CPU I) I/o module does not inform CPU directly

J) K) L) M)

CPU checks status bits periodically I/o module sets status bits I/o module performs operation CPU requests I/o operation

a. G, F, E, D, C, B, A b. A, B, C, D, E, F, G c. B, C, E, D, A, F, G d. D, A, B, C, F, G, E 48. Arrange the following in increasing orderA. A memory read control signal on the control bus. B. Control signals to logic that adds 1 to the contents of the PC and stores the result back in the PC> C. A control signal that opens the gate allowing the contents of the MAR on to the address bus. D. A control signal that opens gates allowing the contents of data bus to be stored in the MBR. a. A, B, C, D b. B. C. D. A c. D, C, B, A d. C, A, D, B 49. Arrange the following in increasing orderA. Store a word of data from a CPU register in a given memory location. B. Perform an arithmetic or logic operation and store the result in a CPU register. C. Fetch the content of a given memory location and load them into a CPU register. D. Transfer a word of data from one CPU register to ALU or another CPU register. a. C, A, D, B b. B, C, D, A c. A, B, C, D d. B, A, C, D 50. Match the following: A MAR B. MBR C. PC D. IR a. A:I, B:II, C:III, D:IV b. A:III, B:II, C:IV, D:I c. A:IV, B:III, C:II, D I. Holds the last instruction fetched II. Holds data to write or last data read III. Specify address for read or write operation IV. Holds the address of next instruction to be fetched

51. I. A signal applied to word line by the address decoder selects the cell either for Read or Write operation. II. Bit lines are used to transfer stored data and its compliment between the cell and data drivers. a. I is true b. II is true c. Both are true d. Both are false 52. Let tc, h, and tm represent the cache access time, hit ratio, and the main memory access time respectively, Then average access time can be determined by the eqn. a. t = htc + (1-h) (tc+tm) b. t = htc + h (tc+tm) c. t = htc + (1+h) (tc+tm) d. None of the above 53. Expression for the efficiency of a system that uses a cache can be delivered as : a. = 1/[r(1-h)] b. = 1/[1+r(1-h)] c. = 1/[1-r(1-h)] d. = 1/(1+1-h) 54. Peripheral of ten use different ________ and ___________ than the computer system to which theyre attached. a. Data format, word length b. Memory, size c. Data format, memory d. None of the above 55. Which statements are invalid in case of RAID. a. RAID is a set of physical disk drives viewed by the operating system as a single logical drive. b. Data are distributed across the physical drives of an array. c. Redundant disk capacity is used to store parity information, which guaranties data recoverability in case of a disk failure. d. All are valid 56. How many transistors and capacitors does a DRAM cell need? SRAM cell? a. DRAM: 0 Capacitor and 6 Transistor and SRAM: 1 Capacitors and 0 Transistors b. DRAM: 1 Capacitor and 0 Transistor and SRAM: 6 Capacitors and 1 Transistor

c. DRAM: 1 Capacitor and 1 Transistor and SRAM: 0 Capacitors and 6 Transistors dDRAM: 0 Capacitor and 1 Transistor and SRAM: 1 Capacitor and 6 Transistors 57. The time elapses between the initiation of an operation and completion of that operation is called _________, . __________ are used for the implementation of main memories.(Memory access time, Semi conductor integrated circuits) 58. Static RAM cells use __________ transistors to store a single bit of data. , Bit lines are also called ___________.(4-6 , Data lines) 59. . ___________ Instruction is just a special branch instruction that stores the contents of the PC in the link register and branches to the target address specified by the instruction , Branch to the address is contained in the ____________ register (Call , Link) 60. Semiconductor memories are ______________ and Basic element of semi conductor memory is _________ (Either volatile or non volatile , Memory cell ) [4 MARKS EACH] 61. Match the following A. I/O, System control B. Transfer of Control C. System control D. Logical a. A:IV, B:II, C:IV, D:I b. A:I, B:II, C:III, D:IV c. A:IV, B:III, C:II, D:I d. A:II, B:III, C:I, D:IV I. Test, compare, Shift, Rotate, Set etc II. Jump jump conditional, jump to subroutine etc III. Reserved for Operating system IV. Start I/O, Test I/O. etc

62. Match the following 1. Direct addressing mode 2. Indirect addressing mode 3. Index mode I. The effective address of the operand is the contents of a register specified the instrument II The effective address of the operand is generated by adding a constant value to the contents of a register III. The effective address of the operand is the contents of register or memory location whose address appears in the instructions

4. Auto increment mode a. 1:I, 2:II, 3:III, 4:IV b. 1:IV, 2:III, 3:II, 4:I c. 1:IV, 2:II, 3:III, 4:I d. 1:II, 2:III, 3:I, 4:IV 63. Match the following : A. Sequential directly accessed and addressed. B. Direct C. Random a or

IV. The operand is the given memory location

I. Any location can be selected at random and

II. Word is retrieved based on a portion of its contents rather Than its address III. Access is accomplished by direct access to reach General vicinity, plus sequential searching, counting Waiting to reach the final location.

D. Associative passed a. A: IV, B:II. C:III, D:I b. A: IV, B:III, C:II, D:I c. A: IV, B:III, C:I, D:II d. A: I, B:II, C:III, D:IV 64. Match the following : A. Semiconductor B. Magnetic C. Optical D. Magneto-optical a. A:II, B:I, C:III, D:IV b. A:II, B:I, C:IV, D:III c. A:I, B:III, C:II, D:IV d. A:IV, B:III, C:II, D:I

IV. Data is accessed sequentially, the records may be until the record that is searched is found.

I. Hard disks, Tape units II. Main Memory, Cache, RAM, ROM III. Optical laser is used. IV. CD-ROM, CD-RW

65. Match the following related to Memory hierarchy.

A. Faster access time B. Greater capacity C. Slower access time a. A:I, B:II, C:III b. C:I, B:II, A:III c. A:II, B:III, C:I d: A:III, B:I, C:II 66. Match the following: A. PROM needs to B. EPROM partially C. EEPROM a. A:III, B:I, C:II b. A:I, B:II, C:III c. A:III, B:II, C:I d. A:II, B:III, C:I 67. Match the following : A. Direct Mapping into sets memory to B. Associative mapping blocks of C. Set Associative mapping to any a. A:III, B:II, C:I b. A:I, B:II, C:III c. A:II, B:I, C:III d. A:II, B:III, C:I 68. Match the following:

I. Greater capacity II. Greater cost per bit III. Smaller cost per bit

I. It can be programmed multiple times. Whole capacity be erased by ultraviolet radiation before new programming activity. It cannot be partially programmed. II. It is erased and programmed electrically. It can be Programmed. III. It can only be programmed once after its fabrication.

I. In this case blocks of the cache are grouped and the mapping allows a block of main reside in any block of a particular set. II. Each line of cache can store specific main memory. III. Permits loading each main memory block line of the cache. Requires tag

a. Write policy to main b. Write through UPDATE c. Write back cache can be whether it has

I. All write operations are both directly alone memory II. Writes are only done to cache. There is an bit set when there is a write. III. Before a block that is resident in the replaces, it is necessary to consider been altered in the cache but not in the

main. a. A:III, B:I, C:II b. A:I, B:II C:III c. A:III, B:II, C:I d. A:II, B:I, C:III 69. Match the following : A. LRU B. FIFO time is to be over C. LFU block must be D. RANDOM experienced fewer a. A:I, B:II, C:III, D:IV b. A:III, B:IV, C:I, D:II c A:II, B:III, C:IV, D:I d. A:II, B:IV, C:III, D:I 70. Match the following : A. Human readable devices exchange data with B. Machine readable devices computer user. C. Communication devices equipments I. These devices allows a computer to remote devices. II. Suitable for communicating with the III. Suitable for communicating with I. Chooses a bloc to be over written in random. II. The block that has not referenced for the longest written. III. Remove the oldest block from a full set when a new Brought in. IV. Replaces that block in the set which has references.

a. A:I, B:II, C:III b. A:II, B:III, C:I c. A:III, B:II, C:I d. A:III, B:I, C:II 71. Match the following: A. Command Decoding address for B. Status Reporting CPU carried C. Address Recognition a. A:I, B:II, C:III b. A:III, B:II, C:I c. A:II, B:I, C:III d. A:II, B:III, C:I 72. Match the following data rate of various devices. A. Keyboard B. Mouse C. USB D. 56 Modem a. A:IV, B:I, C:III, D:II b. A:I, B:II, C:III, D:IV c. A:III, B:I, C:IV, D:I d. A:IV, B:III, C:II, D:I 73. Match the following : A. Control command the data bus and peripheral. B. Test command from the peripheral C. Read command associated with an I/o D. Write command I. It causes I/o module to take an item of data from subsequently transmit the data item to the II. It causes I/o module to obtain an item of data and place it in an internal buffer. III. It is used to test various status conditions module and its peripherals. IV. It is used to activate a peripheral and tell what to I. 100 bytes/sec II. 7 KB/sec III. 1.5 MB/sec IV. 10 bytes/sec I. I/o modules are recognized with an unique Each peripheral it controls. II. I/o module accepts commands from the on the control bus. III. I/o module report with the status signals

do. a. A:III, B:II, C:I, D:IV b. A:I, B:II, C:III, D:IV c. A:IV, B:III, C:II, D:I d. A:IV, B:I, C:II, D:III 74. Match the following: A MAR B. MBR C. PC D. IR a. A:I, B:II, C:III, D:IV b. A:III, B:II, C:IV, D:I c. A:IV, B:III, C:II, D d. A:II, B:III, C:IV, D:I, 75. Match the following A. Internal data paths bus B. External data paths C. Control Unit a. A:III, B:I, C:II b. A:II, B:I, C:III c. A:III, B:II, C:I d. A:I, B:II, C:III I. Are used to like registers and I/O modules, obtain by a system II. Causes operations to happen within the CPU III. Are used to move data between the registers and ALU I. Holds the last instruction fetched II. Holds data to write or last data read III. Specify address for read or write operation IV. Holds the address of next instruction to be fetched