Realizing Precision Timing With The MSP430

Precise Timing with MSP430 Peter Forstner
5/22/2008 1
Agenda Oscillators, the source of precise timing

Internal Oscillators DCO, VLO, REFO Crystal oscillators LFXT1 and XT2 FLL (Frequency locked loop) and calibration
Precise Timing with Peripherals

Temperature measurement with Comparator_A Software UART with Timer_A USART and USCI Sampling with ADC Sample rate of DAC
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MSP430F2xx Basic Clock Module+

VLO
Internal very low power, low frequency oscillator ~12kHz
Internal LP/LF Oscillator
10 Min. Puls Filter LFXT1CLK
else
DIVAx
Divider /1/2/4/8
ACLK Auxiliary Clock
Peripherals
OSCOFF XTS LFXT1Sx
LFXT1
Crystal Oscillator 32768Hz 400kHz 16MHz
XIN
0V LF LFOff 0V XT XT1Off DIVMx CPUOFF 00 01 10 11
XOUT
LFXT1 Oscillator
XCAPx Min. Puls Filter XT2Off XT2S
Divider /1/2/4/8
0 1
MCLK
CPU
XT2
Crystal Oscillator 400kHz 16MHz On high end MSP430
XT2IN XT XT2OUT
Connected only when XT2 not present on-chip
Main System Clock
XT2 Oscillator
MODx
VCC
DCO
Digitally Controlled Oscillator ~100kHz >16MHz
P2.5/Rosc
Modulator
DCOR SCG0 RSELx 0 1 off
DCOx
SELS 0 1 Min. Puls Filter 0 1
DIVSx
SCG1 0 1
DC Generator
n
DCO
n+1
DCOCLK
Divider /1/2/4/8
Peripherals
SMCLK
3
Sub System Clock
MSP430F4xx FLL+ Clock Module

FLL
Frequency Locked Loop
Peripherals LFXT1
Crystal Oscillator 32768Hz 400kHz 8MHz
DCO
CPU
XT2
Crystal Oscillator 400kHz 8MHz On high end MSP430
Peripherals
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MSP430F5xx Unified Clock System (UCS)

LFXT1
Crystal oscillator 32768Hz 400kHz >25MHz
LFXT1 VLO REFO ACLK
VLO
Internal very low power, low frequency oscillator ~12kHz
XT2
REFO
Internal 32768Hz Oscillator
XT2
Crystal Oscillator 400kHz >25MHz
Divider /1/2/4/8/16
FLLREFCLK
MCLK
FLL
Frequency Locked Loop
FLL
10-bit Frequency Integrator
DCO
DCOCLK DCO DCOCLKDIV SMCLK
MODOSC
Module Oscillator e.g. for ADC, Flash Controller etc.
MODOSC MODCLK Provided to Flash controller, ADC12
Low Frequency Clock Sources

Range of choices to fit application needs POWER XTAL REFO VLO
1uA 3uA <500nA
PRECISION
high medium low
COST
External Components $0 $0


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DCO (Digitally Controlled Oscillator)

Available on all MSP430 Internal high speed oscillator Very fast wakeup time
MSP430F1xx: 6us MSP430F2xx: 1us MSP430F4xx: 6us MSP430F5xx: 5us In most applications CPU runs from DCO
Different DCO frequency range on different MSP430 families

MSP430F1xx: MSP430F2xx: MSP430F4xx: MSP430F5xx: ~100kHz 5MHz or ~8Mhz with ROSC = 100k ~100kHz 16MHz ~100kHz 8MHz ~100kHz 25MHz
Different DCO frequency accuracy on different MSP430 families

See details see on next slides
DCO frequency adjustment

RSEL Bits
SR = fRsel+1 / fRsel
DCO Bits
SDCO = fDCO+1 / fDCO
MSP430F149 MSP430F249 MSP430F449 MSP430F5xx
1.35 2 < 1.55 1.49 2

(FN_x+1 / FN_x)
1.07 1.16 1.05 1.12 1.07 1.17 1.04 1.10

MODx
1.5 2.1
VCC
MSP430F5xx values are preliminary!
Modulator
DCOR SCG0 RSELx DCOx
0 1 P2.5/ROSC
off
DCO
n n+1
0 1
DCOCLK
DCO Modulation
eD ag er Av
CO
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Question: Does the DCO have jitter?
DCO Modulation allows fine tuning of the DCO frequency.
The modulator mixes two DCO frequencies, fDCOx and fDCOx+1 to produce an intermediate frequency between fDCOx and fDCOx+1 and spread the clock energy, reducing electromagnetic interference (EMI)
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Jitter Definitions Cycle-to-cycle jitter: (JEDEC Standard JESD65B)

The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs. MSP430 modulation can generate 5% ... 17% cycle-to-cycle jitter.
tcycle n
tcycle n+1
Period jitter: (JEDEC Standard JESD65B)

Period jitter measures the maximum change in a clocks output transition from its ideal over a large number of cycles (e.g. 1000 cycles) MSP430 modulation adds 0% long term jitter for n32 clock cycles.
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DCO accuracy
DV Drift with VCC variation DV 1.8V 3.6V
maximum over entire range
Dt Temperature drift VCC = 3V 0.33 0.43 %/C
Dt 0C 85C VCC = 3V
maximum over entire range
MSP430F149
0 10 %/V
0 18%
-28 -37%
MSP430F249
0 -2.5%/V
(from graph in DS)
-3% +3%
(Cal 1MHz 12MHz)
-0.03% +0.03 %/C
-2.5% +2.5%
(Cal 1MHz 12MHz)
MSP430F449
0 15 %/V
0 27 %
0.2 0.4%/C
-17 -34%
MSP430F4xx: LFXT1 & FLL stabilize DCO frequency

MSP430F5xx 0 10 %/V 0 18% -0.3% +0.3 %/C -25% +25%
MSP430F5xx: ~ 3.5% over all with REFO & FLL

All values from data sheets All MSP430F5xx values are preliminary!
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Influence of ROSC MSP430F1xx

MSP430F1xx: DCO frequency stability over temperature clearly improved with external resistor ROSC Without ROSC maximum f(DCO) ~ 5Mhz With ROSC = 100k maximum f(DCO) ~ 8MHz
MODx
VCC VCC DCOR SCG0 RSELx DCOx
Modulator
ROSC
0 1 P2.5/ROSC
off
DCO
n n+1
0 1
DCOCLK
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Influence of ROSC MSP430F2xx MSP430F2xx:

Slight improvement on temperature stability with external ROSC DCO without ROSC already has a great frequency stability over temperature (2.5%) and VCC (3%) Maximum f(DCO) > 16MHz ROSC not necessary to increase frequency range.
DCO Frequency - MHz
TA Temperature - C DCO Frequency - MHz
VCC Supply Voltage - V

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Calibrated DCO Frequencies
MSP430F2xx:
Calibrated DCO with values stored in Information Memory segment A for 1MHz, 8MHz , 12MHz and 16MHz: Code example:
if ((CALDCO_16MHZ != 0xFF) && (CALBC1_16MHZ != 0xFF)) if ((CALDCO_16MHZ != 0xFF) && (CALBC1_16MHZ != 0xFF)) {DCOCTL == CALDCO_16MHZ; // DCO == 16MHz calibrated {DCOCTL CALDCO_16MHZ; // DCO 16MHz calibrated BCSCTL1 == CALBC1_16MHZ; // DCO == 16MHz calibrated BCSCTL1 CALBC1_16MHZ; // DCO 16MHz calibrated }}
MSP430F5xx: REFO (3.5%) & FLL
DCO (~ 3.5%)
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VLO (Very Low Speed and Very Low Power Oscillator)

Fixed frequency ~12KHz Enables LPM3 operation like a 32kHz crystal, but without external components
Lower cost Less board-space Less sensitive to EMI and crosstalk
Lower LPM3 supply current consumption compared to 32kHz crystal Considerable higher frequency tolerance than LFXT1 with 32kHz crystal
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VLO specification in data sheet

internal very low power, low frequency oscillator (VLO)
PARAMETER fVLO dfVLO/dT dfVLO/dVCC VLO frequency VLO frequency temperature drift VLO frequency supply voltage drift See Note 6 See Note 7 TEST CONDITIONS VCC 2.2 V/3 V 2.2 V/3 V 1.8 V to 3.6 V MIN 4 TYP 12 0.5 4 MAX 20 UNIT kHz %/C %/V
NOTES: 6. Calculated using the box method: I version: (MAX(-40 to 85C) - MIN(-40 to 85C))/MIN(-40 to 85C)/(85C -- (-40C)) T version: (MAX(-40 to 105C) - MIN(-40 to 105C))/MIN(-40 to 105C)/(105C -- (-40C)) 7. Calculated using the box method: (MAX(1.8 to 3.6 V) - MIN(1.8 to 3.6 V))/MIN(1.8 to 3.6 V)/(3.6 V - 1.8 V)
VLO is ultra low power oscillator for LPM3, for cost sensitive applications where frequency accuracy is not important. Example: Supply current MSP430F249: ICC (VLO, LPM3, VCC=3V, 25C): ICC (LFXT1, LPM3, VCC=3V, 25C): typ. 0.4uA, max. 1uA typ. 1uA, max. 1.4uA
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REFO (Trimmed Reference Oscillator)

Available on MSP430F5xx Fixed frequency 32768Hz Moderate frequency tolerance over voltage/temp
Similar to calibrated DCO, much better than VLO Less accurate than 32kHz crystal
Power draw is higher than crystal or VLO Is the default FLL reference clock
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REFO specification in data sheet

internal reference, low frequency oscillator (REFO)
PARAMETER IREFO fREFO REFO oscillator current consumption REFO frequency calibrated REFO absolute tolerance calibrated Duty Cycle tSTART REFO startup time TEST CONDITIONS TA = 25C Measurement at ACLK TA = 25C Measurement at ACLK 40%/60% duty cycle VCC 1.8 V to 3.6 V 1.8 V to 3.6 V 1.8 V to 3.6 V 3V 1.8 V to 3.6 V 1.8 V to 3.6 V 40 TBD 50 0.4 60 MIN TYP MAX 3 32768 3.5 UNIT uA Hz
% % ms
REFO is a low power oscillator for LPM3, without external components, if moderate frequency accuracy is sufficient. Example: Supply current MSP430F5xx: ICC (REFO, LPM3, 25C): ICC (LFXT1): typ. ~5uA typ. ~2.6uA
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What Can You Do With REFO?

Improve DCO frequency stability with REFO & FLL Periodic wakeup for apps in which these are true
Dont need crystal accuracy Need better accuracy than VLO No external crystal required More cost-sensitive than power-sensitive
Can you do RTC?

Not really: 2% error means ~ 1/2 hour error every day But not bad as a walking wounded RTC mode in event of crystal failure!
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Standard Pierce Oscillator

~180 Inverter
~180
RD
CL1
32768Hz XTAL
CL2
The characteristics of the Inverter defines the oscillators performance and crystal constraints. The serial resistor RD helps to suppress the crystals overtone mode and can help to reduce the drive level. The chosen crystal and its specification should match the oscillator design and constraints. The load-capacitors CL1 and CL2 (regarded as in series) form the oscillators effective loadcapacitance.
Loop gain: At steady state, the closed-loop gain = 1 Phase shift: At the frequency of oscillation, the closed loop phase shift = 2n
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How to check a crystal oscillator? Effective Load-Capacitance

(frequency accuracy)
32768Hz Crystal metal-can packaged
OA Oscillation allowance
(negative-resistance model, Crystal constraints)
Assembly Ceramic Package CC
Board Layout
(minimize crosstalk and negative EMI effects)
32768Hz Tuning Fork Crystal
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FL dependent on CL : good match

Frequency FL CL dependent Required Effective Load Capacitance
Actual Effective Load Capacitance 7pF Frequency Shift [ppm] Frequency Target Correct frequency 32768 Hz F F
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source: MicroCrystal
FL dependent on CL : bad match

Frequency FL CL dependent Required Effective Load Capacitance
Actual Effective Load Capacitance 12pF Frequency Shift [ppm] Frequency Target Wrong frequency ~32770 Hz F F
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32kHz oscillator CL configurations

Internal CL (effective load capacitance) MSP430F1xx MSP430F2xx MSP430F4xx MSP430F5xx fixed 6pF ~0pF, 6pF, 10pF, 12pF ~0pF, 6pF, 8pF, 10pF 2pF, 5.5pF, 8.5pF, 12pF External CL In addition to internal CL free choice free choice free choice
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Determine correct CL
Measure crystal oscillator frequency with frequency counter Dont measure with probes directly at the crystal pins
Typical 32kHz load capacitance is 6pF 15pF Ultra-low-power oscillator input impedance > 5M Probe capacitance and impedance heavily influences oscillator
Measure at digital ACLK output pin

P2DIR == BIT0; // MSP430F24x pin P2.0/ACLK/CA2 P2DIR BIT0; // MSP430F24x pin P2.0/ACLK/CA2 P2SEL == BIT0; // P2.0/ACLK/CA2 => ACLK output P2SEL BIT0; // P2.0/ACLK/CA2 => ACLK output
P2.0/ACLK/CA2
Result on the frequency counter must be 32768 Hz This measurement includes parasitic capacitance of board and pins
32768 Hz
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ESR (Equivalent Series Resistance)

C0 32768Hz XTAL CM RM
LM
Equivalent electrical model of a crystal C0: Parasitic capacitance of package and pins CM: Motional capacitance LM: Motional inductance RM: Mechanical losses during oscillation
The ESR (Equivalent Series Resistance) is given in a crystals data sheet and can be calculated with the following formula from the equivalent circuit:
C ESR = RM 1 + 0 ; C L
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Oscillator Allowance
The Oscillation Allowance test is a method to measure the Oscillator-performance
Resistor Rx is placed in series to the crystal. Increase Rx until oscillation stops / starts.
Oscillation Stops
Inverter
Rx STOP
Oscillation Starts
RD Rx 32768Hz XTAL
Rx START
CL1
CL2
OA = RXSTART + ESRXTAL
Example:
OA = 200k + 50k
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Board Layout examples
Layout without and with external load capacitors (XIN and XOUT neighboring pins are standard function pins)
Layout with external capacitors and ground guard ring (XIN and XOUT neighboring pins are NC pins) Examples for MSP430F41x and MSP430F1232IRHB
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Temperature characteristics
curve for 0ppm crystal
20.0 0.0 -20.0 -40.0 -60.0 -80.0
AT-Cut
Delta F/F [ppm]
F F
-100.0 -120.0 -140.0 -160.0 -180.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Tem perature [C]
Tuning Fork
32768Hz crystals
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ppm = parts per million

1ppm 1 second off, after 11 days 13:46:40 hours ~31.5 seconds off per year 150ppm 1 second off, after 1:51:07 hours ~12 seconds off per day 32768 Hz crystal: 1ppm = 0.0328Hz 150ppm = 4.9152Hz
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Temperature compensation in software Measure temperature with Comparator_A or ADC Method 1:

Timer_A always divides by 32768 Depending on the temperature profile over time, add or subtract a second if the time is expected to be >0.5 second off.
Method 2:
Divide Timer_A by 32768 or 32769, depending on temperature Divide by 32768 0 ppm correction Divide by 32769 +30 ppm correction 1ppm correction with modulation of Timer_A in software: Within 30 cycles: n cycles divide by 32769 30-n cycles divide by 32768
This procedure needs frequent CPU interaction Higher power consumption! DMA can do modulation with much less power consumption.
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HF oscillator CL configurations
Internal CL MSP430F1xx MSP430F2xx MSP430F4xx MSP430F5xx no no no no External CL free choice free choice free choice free choice
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Temperature characteristics
curve for 0ppm crystal
20.0 0.0 -20.0 -40.0 -60.0 -80.0
AT-Cut
-100.0 -120.0 -140.0 -160.0 -180.0 -40 -30 -20 -10 0 10
Tuning Fork
AH is F cr no t u ystal ltra os low cilla po tor we r!
Delta F/F [ppm]
F F
AT-cut MHz crystals

20 30 40 50 60 70 80 Tem perature [C]
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MSP430F4xx and MSP430F5xx FLL

32768Hz
LFXT1
~ 32768Hz
DCO / (FLLDx * (N+1))
Divider
FLL compares frequencies at + and - input If (f(+) > f(-)) then increment DCO+MOD bits else decrement DCO+MOD bits
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FLL Frequency adjustment

Increasing DCO+MOD by 1 means within 32 clock cycles one more clock cycle at the frequency DCOx+1 one clock cycles less at the frequency DCOx
clock cycles 1 2 3 4 5 6 7 8 9 10 12 13 30 31 32
DCOx
act on no imp cle and to-cy Cycle- d jitter Perio

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DCOx
DCOx+1
DCOx
DCOx
DCOx
DCOx+1
DCOx
DCOx
DCOx
DCOx+1
DCOx
DCOx
DCOx
DCOx+1
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FLL at power-on
FLL loop control is turned on by default
Status Register Bit SCG0 = 0 (default value)
Directly after power-on the 32768Hz crystal oscillator starts oscillating and frequency < 32768Hz
FLL reduces the DCO frequency
After start-up of the 32786Hz crystal oscillator

FLL increases the DCO frequency until it reaches the programmed value
If the application requires to avoid DCO frequency reduction at start-up

Set SCG0=1 at the beginning of your software Reset SCG0 to 0 when the oscillator fault detection indicates a stable 32768Hz crystal oscillator
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MSP430F1xx/F2xx DCO Calibration with SW

4096Hz ACLK
// Partial SW FLL Code // Partial SW FLL Code if (244 << Compare )) // DCO too fast if (244 Compare // DCO too fast DCOCTL--; DCOCTL--; else DCOCTL++; // DCO too slow else DCOCTL++; // DCO too slow
VCC DCOR RSELx P2.5/ Rosc n DCOx n+1
1MHz
DCOCLK
Periodic loop can adjust DCO

Software FLL in case Hardware FLL is not present
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MSP430x1xx/F2xx Software FLL Example

Goal: Steps to take: Set f(DCO) = 1,000,000Hz with f(ACLK) = 4096Hz DCO id clock source for Timer_A f(DCO) = 1,000,000Hz f(ACLK) = 4096Hz Triggers 244us capture of f(DCO) on CCI2B Adjust f(DCO) until capture value is 244 (= 1,000,000 4096)
CCI2B_ISR
CCI2B_ISR
DCOCLK
>CLK
Timer_A CCR2
capture
;244 DCO clock cycles captured? ;244 DCO clock cycles captured? CCI2B_ISR push.w ;; TOS == temp save &CCR2 CCI2B_ISR push.w &CCR2 &CCR2 TOS temp save &CCR2 sub.w R15,&CCR2 ;; &CCR2 == capture sub.w R15,&CCR2 &CCR2 capture difference difference cmp.w #244,&CCR2 ;; Delta == SMCLK/(32768/8) cmp.w #244,&CCR2 Delta SMCLK/(32768/8) pop.w R15 ;; R15 == captured SMCLK pop.w R15 R15 captured SMCLK jlo IncDCO jlo IncDCO ;; DecDCO &DCOCTL ;; DecDCO dec.b dec.b &DCOCTL reti ;; reti IncDCO &DCOCTL ;; IncDCO inc.b inc.b &DCOCTL reti ;; reti
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Code Library Using the DCO
This library encapsulates routines used for setting the DCO to a specific speed based on a multiplication of a known clock, such as a 32-kHz crystal. These functions are written in assembly to be optimized for the MSP430 but can be called from any C program that includes their header files.
Download from http://www.ti.com/msp430 Code Examples (slaa336)
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VLO Calibration
The VLO frequency is fixed and can not be changed Temperature and VCC influence the VLO frequency Based on a calibrated DCO the actual frequency of the VLO can be measured with a Timer Once the VLO frequency is known, software can adjust timing
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Code Library Using the VLO

The VLO library contains only the function TI_measureVLO(), when called, performs the following actions:
1. 2. 3. 4. 5. 6. 7. Save the current clock settings in registers and on the stack. Set the DCO to the 1MHz calibrated value stored in flash. Set ACLK to the VLO/8. Measure the number of 1-MHz clock pulses in 1 ACLK (VLO/8) pulse. Store the measured result in the variable TI_8MHz_Counts_Per_VLO_Clock. Reload the previous clock settings. Return variable TI_8MHz_Counts_Per_VLO_Clock from the function. Code Examples (slaa340)
Download from http://www.ti.com/msp430
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Precise Timing
Precise timing Triggering in hardware
MSP430 peripherals offer trigger signals between peripherals e.g. Comparator_A Timer_A Timer_A ADC10 or ADC12 Timer_A DAC12 MSP430 peripherals have additional hardware for precise timing e.g. Timer_A SCCI latch Group load logic in Timer_B and DAC12
Triggering in software
This is not precise
Interrupts add delay to program execution Turn off Interrupts if timing is based on program execution Depending on the addressing mode used, MSP430 instruction execution needs between 1 and 6 MCLK clock cycles Interrupt latency uncertainty of 5 MCLK clock cycles
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Comparator_A+
Timer_A
TACLK ACLK SMCLK INCLK 16-bit Timer TAR Count Mode Set TAIFG CCR0 CCR1 CCI1A CCI1B GND VCC CCI SCCI
A Y EN
Capture Mode
TACCR 1 Comparator 1
Set CCIFG2 Output Unit2
CCR2
Timer_A can record a time-stamp of a Comparator_A input slope in TACCR

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Slope Conversion (simple method)

Slope conversion is an excellent method to measure resistors e.g. measure temperature Result of simple slope measurement depends on R, C, CAREF and VCC
t = - (R * C) * ln( Counts = t * f CAREF VCC )
Timer
CA1
CAREF
CAOUT
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Ratiometric Slope Conversion

Independent from C, CAREF and VCC
t_NTC = - RNTC * C * ln t_10k = - 10k * C * ln VCAREF Vcc
VCAREF Vcc VCAREF Vcc VCAREF Vcc
t_NTC = t_10k
- R NTC * C * ln - 10k * C * ln
CAREF = 0.25 VCC
R_NTC = 10k x
t_NTC t_10k
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Ratiometric Slope Conversion

Relatively slow, but very low cost measurement method for resistors Perfect for temperature measurement Measuring discharge time from VCC to 0.25 VCC removes influence of VCC and comparator threshold CAREF Comparison measurement of discharge time with a known resistor removes influence of capacitor C If made perfect, accuracy of more than 12 bits is realistic For details please see: Implementing An Ultralow-Power Thermostat With Slope A/D Conversion (slaa129b) Family Users Guides, chapter Comparator_A and/or ComparatorA+ for details
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Timer_A3
TA Clock 15 0 16-bit Timer TAR RC 16 Count Mode Set TAIFG CCR0 logic CCI1A CCI1B GND VCC Capture Mode TA Clock CCI A EN Output Unit1 Sync COV 15
Async 16-Bit timer/counter with four modes Int/ext clock source Three capture/ compare registers Outputs with PWM capability SCCI asynchronous input signal latching Interrupt vector register for fast decoding DMA enabled
TACLK ACLK SMCLK INCLK
/1/2/4/8
CCR1 TACCR1 Comparator 1 EQU1 0
SCCI
Set CCIFG1 EQU0
CCR2
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Low-Overhead UART Implementation
100% hardware bit latching and output Full speed from LPM3 and LPM4 Low CPU Overhead App Note SLAA078
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Timer_A UART TX SW
TA0_ISR TA0_ISR UART_TX UART_TX
TX_Next TX_Next TX_Space TX_Space TX_Test TX_Test
add.w add.w dec.w dec.w jne jne bic.w bic.w reti reti bic.w bic.w rra.w rra.w jc jc bis.w bis.w reti reti
#Bitime,&CCR0 #Bitime,&CCR0 BitCnt BitCnt TX_Next TX_Next #CCIE,&CCTL0 #CCIE,&CCTL0
;; Time to Next Bit Time to Next Bit ;; Dec bit counter Dec bit counter ;; Next bit? Next bit? ;; Done, disable int Done, disable int ;; #OUTMOD2,&CCTL0 ;; TX Mark #OUTMOD2,&CCTL0 TX Mark RXTXData ;; LSB->Carry RXTXData LSB->Carry TX_Test ;; Jump if bit == 11 TX_Test Jump if bit #OUTMOD2,&CCTL0 ;; TX Space #OUTMOD2,&CCTL0 TX Space ;;
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Timer_A UART RX SW
tS t1 t2 t3 t4 t5 t6 t7
ST
S sig CCI n a ca la nl t a atc t8 pr h a ed n ef y i i n np ed u tim t e 1 SP
Interrupts
1. Capture mode:
Wait for falling edge of start bit and store a time stamp tS of its occurrence in TACCR
TACLK ACLK SMCLK INCLK
16-bit Timer TAR
Count Mode Set TAIFG CCR0 CCR1
2. Compare mode:
1. Program TACCR to t1 = tS + 150% of a bit time This loads 1st bit of RX signal into SCCI latch 2. Program TACCR to t2 = t1 + 100% of a bit time This loads 2nd bit of RX signal into SCCI latch 3. Program TACCR to t3 = t2 + 100% of a bit time This loads 3rd bit of RX signal into SCCI latch .. (continue until all bits are captured)
CCI1A CCI1B GND VCC SCCI

A Y EN
Capture Mode
TACCR 1 Comparator 1
CCI Set CCIFG2
Output Unit2
CCR2
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Timer_A UART RX SW
TA0_ISR TA0_ISR RX_Edge RX_Edge RX_Bit RX_Bit RX_Test RX_Test RX_Comp RX_Comp RX_Next RX_Next
add.w add.w bit.w bit.w jz jz bic.w bic.w add.w add.w reti reti bit.w bit.w rrc.b rrc.b dec.w dec.w jnz jnz bic.w bic.w reti reti
#Bitime,&CCR0 #Bitime,&CCR0 ; Time to Next Bit ; Time to Next Bit #CAP,&CCTL0 ; Capture mode? #CAP,&CCTL0 ; Capture mode? RX_Bit ; Is start bit edge RX_Bit ; Is start bit edge #CAP,&CCTL0 ; Enable comp. mode #CAP,&CCTL0 ; Enable comp. mode #Bitime_5,&CCR0 ; Add 0.5 T_bit #Bitime_5,&CCR0 ; Add 0.5 T_bit ; ; #SCCI,&CCTL0 ; Read RX latch #SCCI,&CCTL0 ; Read RX latch RXTXData ; Store received bit RXTXData ; Store received bit BitCnt ; All bits RXed? BitCnt ; All bits RXed? RX_Next ; No, next bit RX_Next ; No, next bit #CCIE,&CCTL0 ; All bits RXed! #CCIE,&CCTL0 ; All bits RXed! ; ;
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CPU Load Using Timer_A UART
2X Baud = 2X CPU Load 2X MCLK = CPU Load Optimized Assembly ISRs

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USART The USART supports 2 or 3 operating modes: Asynchronous RS232 Mode Synchronous SPI Mode (3-Wire & 4 Wire) I2C interface MSP430F15x/16x/16xx (Master & Slave)
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USART Asynchronous Mode

Software selectable UART or SPI Auto-start from any LPMx Double buffered RX and TX shift registers Baud-rate UCLKI generator ACLK SMCLK 7 or 8-bit data SMCLK 9-bit addressing mode available Parity generation and detection Error detection and suppression
Receiver Buffer URXBUF Receiver Shift Register Baud-Rate Generator Baud-Rate Register UBR Baud-Rate Generator
SNYC RXE Listen MM SOMI SYNC URXD STE SYNC UCLKS UTXD SIMO
Transmit Shift Register Transmit Buffer UTXBUF CKPH SYNC CKPL UCLKI UCLKS
UCLK Clock Phase and Polarity
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USART Baud Rate Generator

UBR0 UCLKI ACLK SMCLK SMCLK 7 BRCLK 15-Bit Prescaler/Divider UBR1 8
Prescaler Factor UxBRx 3
N
15 Modulator 8 UMCTL BITCLK
Example1: SMCLK = 1MHz Baud rate = 19200 1,000,000/19,200 = 52.08 0x34 UBR1 | UBR0 = 0x00 0x34; +0.16% error
Example2: ACLK = 32,768Hz Baud rate = 9600 32,768/9,600 = 3.413 UBR1 | UBR0 = 0x00 0x03; UBR1 | UBR0 = 0x00 0x04; +13.8% error -14.7% error
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USART Baud Rate Modulation

UBR0 UCLKI ACLK SMCLK SMCLK 7 BRCLK 15-Bit Prescaler/Divider UBR1 8
Prescaler Factor UxBRx 3
N
15 Modulator 8 UMCTL BITCLK
Example: ACLK = 32,768 Baud = 9,600 = 32,768/9,600 = 13.68
UBR1 | UBR0 | UMCTL = 0x00 0x03 0x4A

UMCTL division factor TX/RX data
start bit bit 7 bit 6 bit 5 bit 4 bit 3
A 3 4 3 4 3 3
Table with Baud R Commonly Guide, ate Data, an Used Baud R d chapte a r USA Errors in Us tes, RT in UART ers Mode A
4
bit 2
3
bit 1
3
bit 0
4
stop bit
LSB first LSB first
Modulator mixes adjacent clock dividers to enable high baud rates even with low frequency XTAL.
67


68
34
USCI Baud Rate Generator

UCAxMCTL, bit UCOS16 = 0
Oversampling mode disabled

Same behavior like USART Baud Rate Generator Modulation according to the tables BITCLK Modulation Pattern and Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 0
69
USCI Baud Rate Modulation

Commonly Used Baud Rates, Settings, and Errors, UCOS16 = 0 BRCLK frequency [Hz] 32,768 32,768 32,768 32,768 1,048,576 1,048,576 1,048,576 Baud Rate [Baud] 1200 2400 4800 9600 9600 19200 38400 UCBRx 27 13 6 3 109 54 27 UCBRSx 2 6 7 3 2 5 2 UCBRFx 0 0 0 0 Max. TX Error [%] -2.8 -4.8 -12.1 -21.1 1.4 6.0 5.7 15.2
Bo th th T e Us abl er es s ar Max. RX Error [%] Gu e i id n e

-5.9 -9.7 -13.4 -44.3 -1.0 Bit 2 0 0 0 0 0 1 1 1 -1.53 Bit -5.9 0 0 0 1 1 1 1 1 Bit 4 0 0 0 0 0 0 0 1 2.0 8.3 19.0 21.3 0.8 2.5 5 Bit 2.0 0 0 1 1 1 1 1 1 Bit 6 0 0 0 0 0 0 0 1 Bit 7 0 0 0 0 1 1 1 1
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BITCLK Modulation Pattern 0 -.2 0.7 Bit 0 0 1.0Bit 1 UCBRSx -1.1 (Start Bit) 0 0 1 2 3 4 5 6 7 -2.8 0 0 0 0 0 0 0 0 1.2 0 1 1 1 1 1 1 1
Number of 1 in Modulation Pattern
35
USCI Baud Rate Generator

UCAxMCTL, bit UCOS16 = 1
Oversampling mode enabled

BR0 LSB BRCLK 7 15-Bit Prescaler/Divider BR1 8

BITCLK16
1st Modulator 16 BRFx
Two modulators RX sampled using BITCLK16 Majority vote always at the same location within one RX bit BITCLK16 supports IrDA TX pulse generation Quasi-standard for UART, IrDA & LIN
/16
2nd Modulator 8 BRSx
BITCLK
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Timer Triggers For ADC / DAC
Software ADC trigger Time uncertainty Voltage error Hardware ADC trigger with Timer eliminates phase error Precise timing Precise voltage
73
ADC12
12 Bit SAR 200ksps+ Autoscan Single, sequence, repeat-single, repeat-sequence Int/ext VRef Temp sensor Batt measure TA/TB trigger 16-word conversion buffer DMA enabled
1.5V or 2.5V
AVCC AVSS
ADC12OSC
Samp and Hold
VR-
V R+
/1 .. /8
12-bit SAR
ACLK MCLK SMCLK
/4 .. /1024
Sync
ADC12SC TA1 TB0 TB1
Batt Temp
16 x 12 Memory Buffer
16 x 8 Memory Control
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Analog wave output with DAC

MSP430 Timer_A
Flash
DMA
DAC
Amp
Timer_A generates sampling rate and triggers DMA DMA loads new digital value from Flash to DAC Wrong trigger sequence because of timing uncertainty for DMA data and address bus access!
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38
MSP430 DAC12
12-bit monotonic output 8- or 12-bit voltage output resolution Programmable settling time vs power consumption Internal or external reference selection Straight binary or 2s compliment data format Self-calibration option for offset correction Synchronized update capability for multiple DAC12s
77
Analog wave output with DAC

MSP430 Timer_A
Flash
DMA
DAC
Amp
Timer_A generates sampling rate and triggers DAC DAC loads output register ADC12_xLatch with value of shadow register ADC12_xDat DAC with empty shadow register ADC12_xDat triggers DMA to get next audio sample from Flash DMA copies digital audio data from Flash to DAC
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39
Summary
The complete clock chain is important for precise timing:
Oscillators are the source of precise timing
Peripherals offer features for precise timing

Comparator_A can trigger Timer SCCI latch in Timer_A to sample at a predefined time USART and USCI offer special features to fine tune timing Precise ADC sampling with hardware triggering Sample rate of DAC
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Thank you
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40

Realizing Precision Timing With The MSP430

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Precise Timing with MSP430 Peter Forstner

Agenda Oscillators, the source of precise timing

Precise Timing with Peripherals

MSP430F2xx Basic Clock Module+

ACLK Auxiliary Clock

OSCOFF XTS LFXT1Sx

0V LF LFOff 0V XT XT1Off DIVMx CPUOFF 00 01 10 11

Connected only when XT2 not present on-chip

Main System Clock

DCOR SCG0 RSELx 0 1 off

SELS 0 1 Min. Puls Filter 0 1

Sub System Clock

MSP430F4xx FLL+ Clock Module

MSP430F5xx Unified Clock System (UCS)

10-bit Frequency Integrator

Low Frequency Clock Sources

Agenda Oscillators, the source of precise timing

Precise Timing with Peripherals

DCO (Digitally Controlled Oscillator)

Different DCO frequency range on different MSP430 families

Different DCO frequency accuracy on different MSP430 families

DCO frequency adjustment

MSP430F149 MSP430F249 MSP430F449 MSP430F5xx

1.35 2 < 1.55 1.49 2

1.07 1.16 1.05 1.12 1.07 1.17 1.04 1.10

MSP430F5xx values are preliminary!

Question: Does the DCO have jitter?

DCO Modulation allows fine tuning of the DCO frequency.

Jitter Definitions Cycle-to-cycle jitter: (JEDEC Standard JESD65B)

Period jitter: (JEDEC Standard JESD65B)

Dt Temperature drift VCC = 3V 0.33 0.43 %/C

-0.03% +0.03 %/C

MSP430F4xx: LFXT1 & FLL stabilize DCO frequency

MSP430F5xx: ~ 3.5% over all with REFO & FLL

Influence of ROSC MSP430F1xx

VCC VCC DCOR SCG0 RSELx DCOx

Influence of ROSC MSP430F2xx MSP430F2xx:

TA Temperature - C DCO Frequency - MHz

VCC Supply Voltage - V

Calibrated DCO Frequencies

MSP430F5xx: REFO (3.5%) & FLL

Agenda Oscillators, the source of precise timing

Precise Timing with Peripherals

VLO (Very Low Speed and Very Low Power Oscillator)

VLO specification in data sheet

Agenda Oscillators, the source of precise timing

Precise Timing with Peripherals

REFO (Trimmed Reference Oscillator)

REFO specification in data sheet

What Can You Do With REFO?

Can you do RTC?

Agenda Oscillators, the source of precise timing

Precise Timing with Peripherals

Standard Pierce Oscillator

How to check a crystal oscillator? Effective Load-Capacitance

FL dependent on CL : good match

FL dependent on CL : bad match

32kHz oscillator CL configurations

Measure at digital ACLK output pin

ESR (Equivalent Series Resistance)

Board Layout examples

Delta F/F [ppm]