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MARRI EDUCATIONAL SOCIETYS GROUP OF INSTITUTIONS

MARRI LAXMAN REDDY INSTITUTE OF TECHNOLOGY & MANAGEMENT (Approved by AICTE, New Delhi & Affiliated JNTU, Hyderabad) Dundigal, Quthbullapur (M), Hyderabad 43 1 . 2 . 04.09.12 06.09.12
UNIT V

Department of CSE Lecture Plan For A.Y 2011-12


Input -Output interface

Peripheral devices

Name of the Faculty : SIVA RAMA PRASAD KOLLU Asynchronous data transfer 3 07.09.12 Designation : Assistant Professor . Subject with code : COMPUTER ORGANISATION
Course / Class 4 07.09.12 . 5 . 6 S.no . 10.09.12 11.09.12 Date : III B.Tech ISem(Branch ECE) / A Section Asynchronous data transfer

Modes of transfer Action Plan to Cover the back logs deficiencies if any

Unit

Priority interrupt

Name of the Topic

1 7 . 13.09.12 02.07.12 . 2 8 . 14.09.12 03.07.12 . 3 9 . 14.09.12 05.07.12 . 4 1 . 17.09.12 06.07.12 0 . 5 . 06.07.12 1 18.09.12 1 6 . . 09.07.12
UNIT VII

Direct memory access Computer Types, Functional Units

Input - output processor Basic Operational Concepts, Bus structures, Software

Serial communication Performance, Multiprocessors & Multi computers

ParallelTypes, complements Data processing

Fixed Point Representation, Floating Point Representation Pipelining Error Detection Codes Arithmetic pipeline

1 7 20.09.12 2 . 10.07.12 . 8 1 . 21.09.12 12.07.12 3 . 9 . 13.07.12 1 21.09.12 4 1 . 0 13.07.12 . 1 24.09.12 5 1 . 1 16.07.12 . 1 25.09.12 6 1 . 2 17.07.12 . 1 27.09.12 7 1 . 3 19.07.12 . 1 28.09.12 8 1 . 4 20.07.12 . 1 28.09.12 9 1 5 . 20.07.12

Register Transfer Language, Register Transfer


Instruction pipeline Bus & memory Transfers,

Arithmetic Micro Operations RISC pipeline

Logic Micro Operations, Shift Micro Operations Vector processing

Array processors Arithmetic Logic Shift Unit Instruction Codes, Computer Registers

Characteristics of multiproceesors

UNIT II

Interconnection structures Computer Instructions, Instruction Cycle Memory Reference Instructions Interconnection structures

1 6 .

23.07.12

Stack Organisation

2 1 0 7 24.07.12 01.10.12 . . 2 1 1 8 26.07.12 04.10.12 . . 2 1 2 9 27.07.12 05.10.12 . . 2 2 3 0 27.07.12 05.10.12 . . 2 1 . 2 2 . Faculty 2 3 . 2 4 . 2 5 . 2 6 . 2 7 . 2 8 . 2 9 . 3 0 . 3 1 . 3 2 . 3 3 .

Instruction Formats, Addressing Modes Interprocessor arbitration

UNIT VIII

Data Transfer & Manipulation Interprocessor communication & synchronization

Program Control, RISC Interprocessor communication & synchronization

Control Memory Cache coherence

30.07.12
Address Sequencing

UNIT III

31.07.12

MicroProgram Example

Design of HOD unit control

DIRECTOR

02.08.12

Hardwired control

03.08.12
Microprogrammed control

03.08.12 Addition & subtraction 06.08.12

07.08.12
Multiplication Algorithms

09.08.12
Multiplication Algorithms

10.08.12
Division Algorithms

13.08.12

Floating Point Arithmetic Operations

14.08.12

Floating Point Arithmetic Operations

16.08.12
Decimal Arithmetic Unit

17.08.12

Decimal Arithmetic Operations