8051 ADDRESSING MODES

THE CPU CAN ACCESS DATA IN VARIOUS WAYS.

THE DATA COULD BE IN REGISTER. THE DATA COULD BE IN MEMORY. THE DATA COULD BE PART OF INSTRUCTION.

VARIOUS WAYS OF ACCESSING DATA ARE CALLED

ADDRESSING MODES OF PROCESSOR/CONTROLLER

8051 ADDRESSING MODES ARE

IMMEDIATE REGISTER DIRECT REGISTER INDIRECT

INDEXED

IMMEDIATE ADDRESSING MODE

THE SOURCE OPERAND IS CONSTANT. THE IMMEDIATE DATA MUST BE PRECEDED BY #. THIS MODE IS USED TO LOAD DATA IN ANY REGISTER INCLUDING DPTR REGISTER. MOV MOV MOV MOV A, #20H R4, #71 B, #40H DPTR, #1234H ;LOAD 20H IN A ;LOAD DECIMAL VALUE 71 IN R4 ;LOAD 40H IN B ;DPTR=1234H

MOV
MOV

DPL, #34H
DPH, #12H

;DPTR LOWER=34H
;DPTR HIGHER=12H

REGISTER ADDRESSING
REGISTER ADDRESSING MODE INVOLVES THE USE OF REGISTERS TO HOLD DATA TO BE MANIPULATED

MOV MOV MOV MOV MOV

A, R0 R2, A A, R5 A, R7 R6,A

;A=R0 ;R2=A ;A=R5 ;A=R7 ;R6=A

MOV MOV MOV

DPTR, #1234H R7, DPL R6, DPH

THE DATA CAN NOT BE MOVED BETWEEN Rn REGISTERS

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ACCESSING MEMORY
DIRECT ADDRESSING MODE RAM 00 TO 1F 20 TO 2F 30 TO 7F REGISTER INDIRECT ADDRESSING MODE REGISTER BANKS 7 STACK BIT ADDRESABLE MEM. BYTE MEMORY

IN DIRECT ADD. MODE THE DATA IS IN RAM, WHOSE ADD IS KNOWN. THE ADD IS A PART OF INSTRUCTION

MOV MOV MOV MOV MOV MOV MOV

A, 4 ;IS SAME AS A, R4 ;A=R4 A, 7 ;IS SAME AS A, R7 ;A=R7 R0, 40H ;R0=CONTENTS OF RAM LOC. 40H 56H, A ;RAM LOC 56H =CONTENT OF A R4, 7FH ;R4=CONTENTS OF RAM LOC 7FH

# SIGN IS MISSING
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SPECIAL FUNCTION REGISTERS AND THEIR ADDRESSES

LIKE R0 TO R7, REGISTERS A, B, PSW, AND DPTR ARE PART OF GROUP OF REGISTERS KNOWN AS SFR (SPECIAL FUNCTION REGISTERS). THE SFRS ARE ACCESSED BY THEIR NAME OR BY THEIR ADDRESS.

MOV 0E0H, #55H MOV A, #55H MOV 0F0H, #22H MOV B, 22H MOV 0E0H, R2 MOV A, R2 MOV 0F0H, R0 MOV B, R0 MOV P1, A MOV 90H, A

;IS SAME AS ;A=55H ;IS SAME AS ;B=22H ;IS SAME AS ;A=(R2) ;IS SAME AS ;B=(R0) ;IS SAME AS ;P1=(A)

WRITE PROGRAM TO SEND 55H TO PORTS P1 AND P2 USING A)THEIR NAMES B)THEIR ADDRESES
MOV A, #55H MOV P1, A MOV P2, A ;A=55H ;P1=55H ;P2=55H

OR
MOV A, 55H ;A=55H MOV 90H, A ;P1=55H MOV 0A0H, A ;P2=55H

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STACK AND DIRECT ADDRESSING

ONLY DIRECT ADDRESING MODE IS PERMITTED FOR PUSH ON STACK. THE IS TRUE FOR IS VALID FOR POP INSTRUCTION TOO.

WRITE CODE TO PUSH R5, R6 AND A ON STACK. POP THEM IN R2, R3 AND B

PUSH 05 PUSH 06 PUSH 0E0H

POP 0F0H POP 02 POP 03

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REGISTER INDIRECT ADDRESSING MODE

IN THIS A REGISTER IS USED AS POINTER TO THE DATA IF DATA IS IN CPU, ONLY REGISTER R0 AND R1 ARE USED FOR THIS.. R2 TO R7 CANNOT HOLD ADD OF OPERAND LOCATED IN RAM. IN THIS MODE R0 AND R1 WILL BE PRECEDED BY @ MOV A, @R0 ;MOVE CONTENTS OF RAM LOCATION ;WHOSE ADDRESS IS IN R0 TO A @R1, B ;MOVE CONTENTS OF B TO RAM LOCATION ;WHOSE ADDRESS IS IN R1.

MOV

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WRITE PROGRAMS TO COPY THE VALUE 55H INTO RAM LOCATIONS 40H TO 45H USING A) DIRECT ADD, B) REGISTER INDIRECT ADDRESING WITHOUT LOOP AND C) WITH A LOOP.

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WRITE PROGRAM TO COPY THE VALUE 55H INTO RAM LOCATIONS 40H TO 45H USING A) DIRECT ADD, B) REGISTER INDIRECT ADDRESING WITHOUT LOOP AND C) WITH A LOOP.
DIRECT ADDRESING

MOV MOV MOV MOV MOV MOV MOV

A, #55H 40H, A 41H, A 42H, A 43H, A 44H, A 45H, A

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WRITE PROGRAM TO COPY THE VALUE 55H INTO RAM LOCATIONS 40H TO 45H USING A) DIRECT ADD, B) REGISTER INDIRECT ADDRESING WITHOUT LOOP AND C) WITH A LOOP.

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WRITE PROGRAM TO COPY THE VALUE 55H INTO RAM LOCATIONS 40H TO 45H USING A) DIRECT ADD, B) REGISTER INDIRECT ADDRESING WITHOUT LOOP AND C) WITH A LOOP.
REGISTER INDIRECT ADDRESING WITHOUT LOOP
MOV MOV MOV INC MOV INC MOV INC MOV INC MOV INC MOV A,# 55H R0, #40H @R0, A RO @R0, A RO @R0, A RO @R0, A RO @R0, A R0 @R0, A

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WRITE PROGRAM TO COPY THE VALUE 55H INTO RAM LOCATIONS 40H TO 45H USING A) DIRECT ADD, B) REGISTER INDIRECT ADDRESING WITHOUT LOOP AND C) WITH A LOOP.

REGISTER INDIRECT ADDRESING WITH A LOOP.

MOV MOV MOV AGAIN: MOV INC DJNZ

A, #55H RO, #40H R2, #05H @R0, A RO AGAIN

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WRITE A PROGRAM TO COPY A BLOCK OF 10 BYTES OF DATA FROM RAM LOCATIONS STARTING AT 35H TO RAM LOCATIONS 60H.

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WRITE A PROGRAM TO COPY A BLOCK OF 10 BYTES OF DATA FROM RAM LOCATIONS STARTING AT 35H TO RAM LOCATIONS 60H.

MOV R0,#35H ;source pointer MOV R1,#60H ;destination pointer MOV R3,#10 ;counter BACK: MOV A,@R0 ;get a byte from source MOV @R1,A ;copy it to destination INC R0 ;increment source pointer INC R1 ;increment destination pointer DJNZ R3,BACK ;keep doing it for all ten ;bytes

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IN THIS PROGRAM ABC IS BURNED IN ROM LOCATIONS STARTING AT 200H THE PROGRAM IS BURNED INTO ROM FROM 0. ANALYSE THE PROG.

ORG 0000H ;burn into ROM starting at 0 MOV DPTR,#200H ;DPTR=200H look-up table address CLR A ;clear A(A=0) MOVC A,@A+DPTR ;get the char from code space MOV R0,A ;save it in R0 INC DPTR ;DPTR=201 pointing to next char CLR A ;clear A(A=0) MOVC A,@A+DPTR ;get the next char MOV R1,A ;save it in R1 INC DPTR ;DPTR=202 pointing to next char CLR A ;clear A(A=0) MOVC A,@A+DPTR ;get the next char MOV R2,A ;save it in R2 HERE:SJMP HERE ;stay here ;Data is burned into code space starting at 200H ORG 200H DATA: DB ABC" END ;end of program

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ASSUMING THAT ROM SPACE STARTING AT 250H CONTAINS INDIA WRITE APROGRAM TO TRANSFER BYTES INTO RAM LOCATIONS AT 40H

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ASSUMING THAT ROM SPACE STARTING AT 250H CONTAINS INDIA WRITE APROGRAM TO TRANSFER BYTES INTO RAM LOCATIONS AT 40H
;(a) This method uses a counter ORG MOV DPTR,#MYDATA MOV R0,#40H MOV R2,#5 BACK: CLR A MOVC A,@A+DPTR MOV @R0,A INC DPTR

INC R0 DJNZ R2,BACK HERE: SJMP HERE ;----------ON-CHIP CODE SPACE USED FOR STORING DATA ORG 250H MYDATA: DB INDIA" END

;LOAD ROM POINTER ;LOAD RAM POINTER ;LOAD COUNTER ;A=0 ;MOVE DATA FROM CODE ;SPACE ;SAVE IT IN RAM ;INCREMENT ROM ;POINTER ;INCREMENT RAM POINTER ;LOOP UNTIL COUNTER=0

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;(b)

This method uses null char for end of string ORG 0000 MOV DPTR,#MYDATA ;LOAD ROM POINTER MOV R0,#40H ;LOAD RAM POINTER BACK: CLR A ;A=0 MOVC A,@A+DPTR ;MOVE DATA FROM CODE SPACE JZ HERE ;EXIT IF NULL CHAR MOV @R0,A ;SAVE IT IN RAM INC DPTR ;INCREMENT ROM POINTER R0 ;INCREMENT RAM POINTER SJMP BACK ;LOOP HERE: SJMP HERE

;----------ON-CHIP CODE SPACE USED FOR STORING DATA ORG 250H MYDATA: DB INDIA",0 ;notice null char for end of string END

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LOOK UP TABLE AND MOVC INSTRUCTION

WRITE A PROGRAM TO GET THE x VALUE FROM P1 AND SEND x*x TO P2 CONTINOUSLY

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WRITE A PROGRAM TO GET THE x VALUE FROM P1 AND SEND x*x TO P2 CONTINOUSLY

ORG 0 MOV DPTR,#300H MOV A,#0FFH MOV P1,A BACK: MOV A,P1 MOVC A,@A+DPTR MOV P2,A SJMP BACK

;LOAD LOOK-UP TABLE ADDRESS ;A=FF ;CONFIGURE P1 AS INPUT PORT ;GET X ;GET X SQAURE FROM TABLE ;ISSUE IT TO P2 ;KEEP DOING IT

ORG 300H XSQR_TABLE: DB 0,1,4,9,16,25,36,49,64,81 END ADD= (A)+ 16 BIT ADD IN DPTR. MOVC ADDRESSES. CODE IN ROM.
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INDEXED ADDRESSING MODE AND MOVX INSTRUCTION

THE 8051 HAS 64K BYTES OF CODE SPACE WHICH CAN BE ACCESSED USING PROGRAM COUNTER REGISTER. MOVC INSTRUCTION ACCESS A PART OF THIS 64K BYTE CODE SPACE AS DATA MEMORY. IN SOME CASES THE PROGRAM CODE DOES NOT LEAVE ANY ROOM TO SHARE WITH DATA.

ACCORDINGLY 8051 HAS ANOTHER 64K MEMORY SPACE

EXCLUSIVELY FOR DATA. THIS DATA SPACE IS REFERED AS EXTERNAL MEMORY AND IS ACCESSED ONLY BY MOVX INSTRUCTION. THE DATA SPACE CAN NOT BE SHARED WITH CODE SPACE.

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ACCESSING RAM LOCATIONS 30 T0 7FH AS SCRATCH PAD

WRITE A PROGRAM TO TOGGLE P1 A TOTAL OF 200 TIMES. USE RAM LOCATION 32H AS A COUNTER.

MOV MOV

P1, #55H 32H, 200

LOOP1: CPL P1 ACALL DELAY DJNZ 32H, LOOP1

;P1=55H ;LOAD COUNTER VALUE IN RAM ;LOCATION 32H ;TOGGLE P1 ;REPEAT 200 TIMES

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BIT ADDRESSES FOR I/O AND RAM

BIT ADDRESSABLE RAM
OF THE 128 BYTE OF INTERNAL RAM OF 8051, ONLY 16 BYTES ARE BIT ADDRESSABLE. THE REST CAN BE ACCESSED IN BYTE FORM. THE BIT ADDRESSABLE RAM LOCATIONS ARE FROM 20H TO 2FH. A TOTAL OF 128 BITS OF RAM ARE BIT ADDRESSABLE. THESE ARE ADDRESSED AS 0 TO 127(IN DECIMAL) OR 00 TO 7FH. THE BIT ADD 0 TO 7 ARE FOR FIRST BYTE OF INTERNAL RAM LOCATION 20H, AND 8 TO 0FH ARE THE BIT ADDRESSSES OF 2nd BYTE OF RAM LOCATION 21H AND SO ON. THE LAST BYTE OF 2FH HAS BIT ADDRESSES 78H TO 7FH.

RAM LOCTIONS 20 TO 2FH ARE BOTH BYTE AND BIT ADDRESSABLE

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16 BYTES OF INTERNAL RAM

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SINGLE BIT INSTRUCTIONS

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EVERY SFR REGISTER IS ASSIGNED A BYTE ADDRESS.

PORTS P0 TO P3 ARE PART OF SFR. P0 HAS BYTE ADDRESS OF 80H. P1 HAS BYTE ADDRESS OF 90H P2 HAS BYTE ADDRESS OF A0H P3 HAS BYTE ADDRESS OF B0H

INSTRUCTION SETB P1.0

ASSEMBLED AS SETB 90H AS P1.0 HAS RAM ADD. 90H

BIT ADDRESS 00 TO 7FH BELONG TO RAM BYTE ADDRESS OF 20 TO 2FH. THE BIT ADDRESS 80 TO F7H BELONG TO SFR OF P0, TCON, P1, SCON ETC.

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I/O PORT BIT ADDRESSES

SFR RAM ADDRESS(BYTE & BIT)

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BIT MEMORY MAP

00 TO 7FH 80 TO 87H 88 TO 8FH 90 TO 97H 98 TO 9FH A0 TO A7H A8 TO AFH B0 TO B7H B8 TO BFH C0 TO C7H C8 TO CFH D0 TO D7H D8 TO DFH E0 TO E7H E8 TO EFH F0 TO F7H F8 TO FFH

RAM LOCATIONS 20 TO 2FH PORT P0 TCON REGISTER PORT P1 SCON REGISTER PORT P2 IE REGISTER PORT P3 IP REGISTER NOT ASSIGNED NOT ASSIGNED PSW REGISTER NOT ASSIGNED A REGISTER NOT ASSIGNED B REGISTER NOT ASSIGNED
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BIT ADDRESSES FOR ALL PORTS

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SETB 86H CLR 87H

SETS P0.6 BIT OF P0 CLEARS P0.7 BIT OF P0 SETS P1.2 BIT OF P1 SETS P2.7 BIT OF P2

SETB 92H SETB 0A7H

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REGISTERS BIT ADDRESABILITY

ALL THE I/O PORTS ARE BIT ADDRESSABLE FOLLOWING REGISTERS ONLY ARE BIT ADDRESSABLE A B PSW

IP
IE SCON TCON

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BITS OF PSW
CY
F0

AC

RS1

RS0

OV

--

RS1RS0 0 0 0 1 1 0 1 1

REGISTER BANK 0 1 2 3

ADDRESS 00 TO 07H 08 TO 0FH 10 TO 1FH 17 TO 1FH

WRITE A PROGRAM TO SAVE THE ACCUMULATOR IN R7 OF BANK 2

CLR SETB MOV

PSW.3 PSW.4 R7, A

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THERE ARE NO INSTRUCTIONS TO CHECK THE OVERFLOW BIT. WRITE A PROGRAM TO CHECK STATUS OF OV

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THE OV FLAG IS THE PSW.2 OF PSW REGISTER. PSW IS BIT ADDRESSABLE REGISTER. FOLLOWING INSTRUCTION CAN T CHECK THE STATUS OF THE BIT

JB

PSW.2, TARGET ;JUMP IF PSW.2 ;THAT IS OV=1.

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WRITE PROGRAM TO CHECK IF THE RAM LOCATION 37H HAS AN EVEN VALUE. IF IT HAS, SEND IT TO P2, ELSE MAKE IT EVEN AND SEND TO P2.

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MOV

A, 37H

JNB ACC.0, YES

;LOAD RAM ;LOCATION ;37H IN ACC ;IS D0 OF A ;0? IF SO ;JUMP

YES :

INC A MOV

P2, A

;SEND TO P2
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THE STATUS OF BITS P1.2 AND P1.3 OF I/O PORT OF P1 MUST BE SAVED BEFORE THESE ARE CHANGED. WRITE A PROGRAM TO SAVE THE STATUS OF P1.2 IN BIT LOC. 06 AND OF P1.3 IN BIT LOC. 07.

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THE STATUS OF BITS P1.2 AND P1.3 OF I/O PORT OF P1 MUST BE SAVED BEFORE THESE ARE CHANGED. WRITE A PROGRAM TO SAVE THE STATUS OF P1.2 IN BIT LOC. 06 AND OF P1.3 IN BIT LOC. 07.
CLR CLR JNB SETB JNB SETB ------06 07 P1.2, OO 06 P1.3, NO 07 ;CLEAR BIT ADD 06 ;CLEAR BIT ADD 07 ;IF P1.2=0 THEN JUMP OO ;IF P1.2=1, SET BIT LOC 06 TO 1 ;IF P1.3=0 THEN JUMP NO ;IF P1.3=1, SET BIT LOC 07 TO 1

OO: NO:

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USE OF INSTRUCTIONS MOV BIT, C MOV C, BIT

WRITE A PROGRAM TO SAVE THE STATUS OF BIT P1.7 ON RAM ADDRESS BIT 05

MOV MOV

C, P1.7 ;GET BIT FROM PORT 05, C ;SAVE THE BIT

WRITE A PROGRAM TO GET STATUS OF BIT PIN P1.7 AND SEND TO PIN P2.0

HERE: MOV MOV SJMP

C, P1.7 ;GET BIT FROM PORT P2.0, C ;SEND BIT TO PORT HERE

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EXTRA 128 BYTE RAM IN 8052

FF DIRECT ACCESS (MOV 90H, #55H) 80 7F SFR REGISTERS ONLY 80 FF INDIRECT ACCESS (MOV @R0, A) UPPER RAM

20 1F 18 17 10 0F 08 07 00

BANK 3 BANK 2 BANK 1

BANK 0

Accumulator Registers Program Status Word Stack Pointer Ports Timers Serial Control Power Control Others

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WRITE A PROGRAM FOR 8052 TO PUT 55H IN THE UPPER RAM LOCATIONS OF 90 TO 99H

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WRITE A PROGRAM FOR 8052 TO PUT 55H IN THE UPPER RAM LOCATIONS OF 90 TO 99H

O R

ORG MOV MOV MOV

0 A, #55H R2, #10 R0, #90H

BACK: MOV
INC DJNZ

@R0, A
R0 R2, BACK

;ACCESS THE UPPER 128 ;BYTES OF ON CHIP RAM ;USE INDIRECT ADDRESSING ;MODE ;REPEAT FOR ALL ;LOCATIONS ;STAY HERE

SJMP END

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ASSUME THAT THE ON-CHIP ROM HAS A MESSAGE. WRITE APROGRAM TO COPY IT O FROM CODE SPACE TO UPPER MEMORYSPACE STARTING AT 80H. ALSO PLACE THE BYTE STORED AT RAM AT PORT P0.

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ASSUME THAT THE ON-CHIP ROM HAS A MESSAGE. WRITE APROGRAM TO COPY IT FROM CODE SPACE TO UPPER MEMORYSPACE STARTING AT 80H. ALSO PLACE THE BYTE STORED AT RAM AT PORT P0.
ORG MOV O O B1: MOV CLR MOVC MOV MOV JZ INC 0 DPTR, #MYDATA ;LOAD STARTING ADDRESS ;OF MESSAGE R1, #80H ;THE STARTING ADDRESS ;OF UPPER 128 BYTES A A, @A+DPTR ;COPY FROM CODE ROM @R1, A ;STORE IN UPPER RAM P0, A ;SEND COPY TO P0 EXIT ;JUMP IF LAST BYTE=0 DPTR ;POINT TOWARD NEXT ;ROM LOCATION R1 ;POINT TO NEXT RAM B1 ;REPEAT $ ;STAY HERE

INC SJMP EXIT: SJMP ; -----------ORG 300H MYDATA: DB THIS IS A TEST PROGRAM, 0 END

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AN EXTERNAL 256 BYTES RAM USING MULTIPLEXED ADD/DATA (COULD BE 8155) IS CONNECTED TO 8051 PORT P0. PORT P3 PROVIDES CONTROL LINES FOR EXTERNAL RAM. PORTS P1 AND P2 ARE USED FOR NORMAL I/O. REGISTERS 0 AND 1 CONTAIN 12H AND 34H. LOCATION 34H OF EXTERNAL RAM HOLDS THE VALUE 56H. WRITE INSTRUCTIONS TO COPY CONTENTS OF LOCATION 34H TO 12H.

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AN EXTERNAL 256 BYTES RAM USING MULTIPLEXED ADD/DATA (COULD BE 8155) IS CONNECTED TO 8051 PORT P0. PORT P3 PROVIDES CONTROL LINES FOR EXTERNAL RAM. PORTS P1 AND P2 ARE USED FOR NORMAL I/O. REGISTERS 0 AND 1 CONTAIN 12H AND 34H. LOCATION 34H OF EXTERNAL RAM HOLDS THE VALUE 56H. WRITE INSTRUCTIONS TO COPY CONTENTS OF LOCATION 34H TO 12H.

MOVX MOVX

A, @R1 @R0, A

;COPY CONTENTS OF(34) TO A ;COPY CONTENTS OF A TO (12)

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