UAS Report

Arditto Trianggada 13209046 | Tugas 6
Table of Contents
A. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. B. 1. 2. 3. 4. 5. 6. 7. 8. 9. C. 1. 2. 3. 4. 5. 6. Design of Pipelined Processor ......................................................................................................... 3 Basic Pipelined Processor............................................................................................................ 3 Adding j (jump) Instruction ....................................................................................................... 11 Adding shift Instructions ........................................................................................................... 12 Adding shift variable Instructions ............................................................................................. 14 Adding xor Instruction............................................................................................................... 14 Adding nor Instructions............................................................................................................. 15 Adding lui (load upper immediate) Instruction ......................................................................... 16 Adding slti (set less than immediate) Instruction ..................................................................... 16 Adding andi, ori, and xori Instructions ...................................................................................... 17 Adding Branch Instructions (bne, bltz, blez, and bgtz) ......................................................... 18 Adding jal (jump and link) Instruction................................................................................... 20 Adding jr (jump to register) Instruction ................................................................................ 21 Adding jalr (jump and link register) Instruction .................................................................... 25 Final Design ........................................................................................................................... 27
Dataflow of Instructions................................................................................................................ 33 Dataflow of beq Instruction ................................................................................................... 33 Dataflow of bne Instruction ................................................................................................... 36 Dataflow of bltz Instruction ................................................................................................... 39 Dataflow of blez Instruction .................................................................................................. 42 Dataflow of bgtz Instruction .................................................................................................. 45 Dataflow of j Instruction ........................................................................................................ 48 Dataflow of jal Instruction ..................................................................................................... 49 Dataflow of jr Instruction....................................................................................................... 50 Dataflow of jalr Instruction.................................................................................................... 54 Handling Hazard ............................................................................................................................ 58 ForwardAE and ForwardBE ....................................................................................................... 58 ForwardAD and Forward BD ..................................................................................................... 59 Forward JD ................................................................................................................................ 60 lwstall ........................................................................................................................................ 61 branchstall................................................................................................................................. 61 jrstall.......................................................................................................................................... 62
7. 8. 9. D. E.
Flushing ID stage ....................................................................................................................... 63 Flushing EX stage....................................................................................................................... 64 Hazard Unit VHDL Code ............................................................................................................ 64 VHDL Structural Description ......................................................................................................... 67 Moving Branch Decision into EX Stage ......................................................................................... 84
A. Design of Pipelined Processor

1. Basic Pipelined Processor Initially, we have a processor in the figure below:
CLK 0 1 PC' PC A RD Instr
25:21
CLK A1 A2 A3 WD3
20:16 15:11
CLK WE3 RD1 RD2 Register File 0 1 SignImm WriteReg 4:0 0 1 SrcA Zero ALUResult WE A RD ReadData 0 1
Instruction Memory
20:16
SrcB
ALU
WriteData
Data Memory WD
+
4
PCPlus4
15:0
Sign Extend
<<2
PCBranch
Result
This processor is a single-cycle processor which just can handle 9 instructions, theay are add, sub, and, or, slt, addi, lw, sw, and beq. Then, it is modified into the pipelined processor that shown below:
CLK CLK CLK 0 1
PC' PCF ALUOutW
CLK
InstrD
25:21
CLK A1 A2 A3 WD3
20:16 15:11
CLK WE3 RD1 RD2 Register File

RtE RdE SrcAE ZeroM ALUOutM
CLK WE A RD Data Memory

ReadDataW
RD
0 1
Instruction Memory
20:16
0 1
ALU SrcBE
WriteDataE WriteDataM
WD
WriteRegW 4:0
0 1
WriteRegE 4:0
WriteRegM 4:0
+
4
PCPlus4F
SignImmE
15:0
Sign Extend
<<2
+
PCPlus4E
PCBranchM
PCPlus4D
ResultW
Fetch
Decode
Execute
Memory
Writeback
After that, we give the control signals for the each stage which produced in ID stage.
CLK
RegWriteD RegWriteE MemtoRegE MemWriteE BranchE ALUControlE2:0 ALUSrcE RegDstE ALUOutW
CLK
RegWriteM MemtoRegM MemWriteM BranchM PCSrcM
CLK
RegWriteW MemtoRegW
Control MemtoRegD Unit

MemWriteD
31:26
BranchD Op ALUControlD ALUSrcD RegDstD Funct
5:0
CLK 0 1
PC' PCF
CLK
25:21
CLK
InstrD
20:16
CLK WE3 RD1 RD2

SrcAE ZeroM
ALU
RD
A1 A2
WE A RD Data Memory WD
ReadDataW
0 1
ALUOutM
Instruction Memory
A3 Register WD3 File

20:16 15:11
0 SrcBE 1
WriteDataE RtE RdE
WriteDataM
0 1
WriteRegE4:0
WriteRegM4:0
WriteRegW4:0
15:0
PCPlus4F
PCPlus4D
PCPlus4E
Sign Extend
SignImmE
<<2
PCBranchM
ResultW
This processor can handle 9 kinds of instructions just the same with the single-cycle processor. But, it still cant handle any hazard occur in advance. Therefore, we have to modify it:
Data forwarding This hazard occurred when one instruction requires data from any register which has not yet updated from any instruction before. This kind of hazard usually called Read after Write Hazard. It could be described by the figure below:
1 2 3 4 5 6 7 8
Time (cycles) IM add $s0, $s2, $s3 add $s2 RF $s3
+
DM
$s0
RF
and $t0, $s0, $s1 or $t1, $s4, $s0
IM and
$s0 RF $s1
&
DM
$t0
RF
IM or
$s4 RF $s0
DM
$t1
RF
sub $t2, $s0, $s5
IM sub
$s0 RF $s5
DM
$t2
RF
We can handle one of those three hazards above by using first half cycle for writing and reading register file when RF and ID stage fetched together. But, we still have two instructions which still occurred. Thus, we handle it by using Data Forwarding method in the following figure:
CLK Control Unit
31:26 5:0
CLK
RegWriteE MemtoRegE MemWriteE ALUControlE 2:0 ALUSrcE RegDstE BranchE BranchM PCSrcM RegWriteM MemtoRegM MemWriteM
CLK
RegWriteW MemtoRegW
RegWriteD MemtoRegD MemWriteD ALUControlD 2:0
Op Funct
ALUSrcD RegDstD BranchD
CLK 0 1
PC' PCF
CLK
InstrD
25:21
CLK A1 WE3 RD1

00 01 10 00 01 10 SrcAE ZeroM ALUOutM
CLK WE A RD Data Memory WD

ReadDataW
RD
Instruction Memory
20:16
A2 RD2 A3 Register WD3 File

RsD RtD RdD RsE RtE RdE
0 1
SrcBE
ALU
WriteDataM
WriteDataE
25:21 20:16 15:11
ALUOutW
1 0
0 1
WriteRegE 4:0 SignImmE
WriteRegM 4:0
WriteRegW 4:0
+
4
15:0
Sign Extend
SignImmD
<<2
+
PCPlus4F PCPlus4D PCPlus4E PCBranchM
ResultW
ForwardBE ForwardAE
RegWriteM
RegWriteW
Hazard Unit
The hazard unit signal ForwardAE and ForwardBE logic are given below:
If ((rsE != 0) AND (rsE == WriteRegM) AND RegWriteM) then ForwardAE = 10 else if ((rsE != 0) AND (rsE == WriteRegW) AND RegWriteW) then ForwardAE = 01 else ForwardAE = 00
If
((rtE != 0) AND (rtE == WriteRegM) AND RegWriteM) then ForwardBE = 10 else if ((rtE != 0) AND (rtE == WriteRegW) AND RegWriteW) then ForwardBE = 01 else ForwardBE = 00
The timing diagram after those hazards are handled is shown below
1 2 3 4 5 6 7 8
Time (cycles)
add $s0, $s2, $s3 and $t0, $s0, $s1 or $t1, $s4, $s0
IM
add
$s2 RF $s3
+
DM
$s0
RF
IM
and
$s0 RF $s1
&
DM
$t0
RF
IM
or
$s4 RF $s0
DM
$t1
RF
sub $t2, $s0, $s5
IM
sub
$s0 RF $s5
DM
$t2
RF
Stalling This hazard is similar with previous hazard. But, there is one instruction which requires data that has not been updated by previous instruction. It occurred in lw instruction. It could be described by this following figure:
1 2 3 4 5 6 7 8
Time (cycles)
lw $s0, 40($0) and $t0, $s0, $s1 or $t1, $s4, $s0
IM
lw
$0 RF 40
+
DM
$s0
RF
IM
and
$s0 RF $s1
Trouble!
&
DM
$t0
RF
IM
or
$s4 RF $s0
DM
$t1
RF
sub $t2, $s0, $s5
IM
sub
$s0 RF $s5
DM
$t2
RF
Then, we modify the hardware by adding a hazard unit signal as a flag when stalling will be executed.
CLK Control Unit

31:26 5:0
CLK
RegWriteE MemtoRegE MemWriteE ALUControlE 2:0 ALUSrcE RegDstE BranchE BranchM PCSrcM RegWriteM MemtoRegM MemWriteM
CLK
RegWriteW MemtoRegW
Op Funct
CLK 0 1
PC'
EN
CLK
PCF InstrD
25:21
CLK A1 WE3 RD1

00 01 10 00 01 10 SrcAE ZeroM ALUOutM
CLK WE A RD Data Memory WD

ReadDataW
RD
Instruction Memory
20:16

0 1
ALU SrcBE
WriteDataE WriteDataM
25:21 20:16 15:11
ALUOutW
1 0
0 1
WriteRegE 4:0 SignImmE
WriteRegM 4:0
WriteRegW 4:0
+
4
15:0
Sign Extend
SignImmD
<<2
+
PCPlus4F
EN
PCPlus4D
CLR
PCPlus4E PCBranchM
ResultW
StallF
StallD
FlushE
ForwardBE ForwardAE
MemtoRegE
RegWriteM
RegWriteW
Hazard Unit
The hazard unit signal, lwstall, logic is given below:

lwstall = ((rsD == rtE) OR (rtD == rtE)) AND MemtoRegE StallF = StallD = FlushE = lwstall
The timing diagram is changed:

1 2
$0 RF 40
+
9
Time (cycles)
lw $s0, 40($0)
IM
lw
DM
$s0
RF
and $t0, $s0, $s1 or $t1, $s4, $s0
IM
and
$s0 RF $s1 RF
$s0 $s1
&
DM
$t0
RF
IM
or
IM
or
$s4 RF $s0
|
DM
$t1
RF
Stall sub $t2, $s0, $s5

IM sub RF
$s0 $s5
-
DM
$t2
RF
Control Hazards Control hazard occurred due to beq instruction.

1 2
$t1 RF $t2
9
Time (cycles)
20 24 28 2C 30 ... 64
beq $t1, $t2, 40 IM and $t0, $s0, $s1 or $t1, $s4, $s0
lw
DM
RF
IM and
$s0 RF $s1
&
DM
RF Flush these instructions
IM or
$s4 RF $s0
DM
RF
sub $t2, $s0, $s5 ... slt $t3, $s2, $s3
IM sub
$s0 RF $s5
DM
RF
IM
slt
$s2 RF $s3
slt
DM
$t3
RF
In the figure above, we can see beq instruction gives 3 cycles penalty when finally the branch is taken. We can reduce the penalty by moving the branch decision into the ID stage.
CLK Control Unit

31:26 5:0
CLK
RegWriteE MemtoRegE MemWriteE ALUControlE 2:0 ALUSrcE RegDstE RegWriteM MemtoRegM MemWriteM
CLK
RegWriteW MemtoRegW
Op Funct
CLK 0 1
PC' PCF EN
CLK
InstrD
25:21
CLK A1 WE3 RD1
EqualD
PCSrcD SrcAE ALUOutM 00 01 10 RsD RtD RdE RsE RtE RdE
CLK
00 01 10
WE
RD
Instruction Memory
20:16
A2 RD2 A3 Register WD3 File 0 1
0 1
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
ReadDataW
25:21 20:16 15:11
ALUOutW WriteRegE 4:0 SignImmE WriteRegM 4:0
1 0
WriteRegW 4:0
+
4
CLR EN
15:0
Sign Extend
SignImmD
<<2
+
PCPlus4D PCBranchD
PCPlus4F
CLR
ResultW
StallF
StallD
FlushE
ForwardBE ForwardAE
MemtoRegE
RegWriteM
RegWriteW
Hazard Unit
The timing hazard after control hazard already handled:

1 2 3 4 5 6 7 8 9
Time (cycles)
20 24 28 2C 30 ... 64
beq $t1, $t2, 40 and $t0, $s0, $s1 or $t1, $s4, $s0
IM
lw
$t1 RF $t2
-
DM
RF
IM
and
$s0 RF $s1
&
DM
RF
Flush this instruction
sub $t2, $s0, $s5 ... slt $t3, $s2, $s3

slt $s2 RF $s3
slt
IM
DM
$t3
RF
As we can see in the figure above that penalty reduced into one cycle. Data hazard due to beq To handle data hazard that comes from beq instruction, we use both forwarding and stalling method. These are the cases when we should handle the hazard: Due to register writing instruction (1 cycle difference)
slti $t1, $s0, $t0
IM
Reg
ALU
DM
Reg
beq $t1, $0, done
IM
Reg
ALU
DM
Reg
IM
Reg
ALU
DM
Reg
Due to lw instruction
lw $t1, 4($s0)
IM
Reg
ALU
DM
Reg
addi $s1, $s1, $s0
IM
Reg
ALU
DM
Reg
beq $t1, $0, done
IM
Reg
ALU
DM
Reg
beq $t1, $0, done
IM
Reg
ALU
DM
Reg
As we can see from two cases above that beq will be stalled until the data is ready from previous instruction. Due to register writing instruction (2 cycle difference) Besides, there is a case why we should introduce a new data forwarding.
slti $t1, $s0, $t0
IM
Reg
ALU
DM
Reg
addi $s1, $s1, $s0
IM
Reg
ALU
DM
Reg
beq $t1, $0, done
IM
Reg
ALU
DM
Reg
There is no need to stall the instruction when the data that required by Beq instruction is ready in the MA stage at that moment. As a solution, we put a new multiplexer (also new hazard unit signal) to bypass the correct data from MA stage.
CLK
RegWriteD RegWriteE MemtoRegE MemWriteE ALUControlE 2:0 ALUSrcE RegDstE
CLK
RegWriteM MemtoRegM MemWriteM
CLK
RegWriteW MemtoRegW
Control Unit
31:26 5:0
MemtoRegD MemWriteD ALUControlD 2:0
Op Funct
CLK 0 1
PC'
EN
CLK A RD
InstrD
25:21
CLK A1 WE3 RD1 0 1
EqualD
PCSrcD
CLK
00 01 10 SrcAE ALUOutM 00 01 10
PCF
WE
Instruction Memory
20:16
0 1
0 1
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
ReadDataW
25:21 20:16 15:11
ALUOutW
1 0
0 1
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
+
4
CLR EN
15:0
Sign Extend
SignImmD
SignImmE
<<2
+
PCPlus4D PCBranchD
PCPlus4F
CLR
ResultW
StallF
StallD
BranchD
ForwardBD ForwardAD
FlushE
ForwardBE ForwardAE
MemtoRegE RegWriteE
RegWriteM
RegWriteW
Hazard Unit
Forwarding logic:
ForwardAD = (rsD !=0) AND (rsD == WriteRegM) AND RegWriteM ForwardBD = (rtD !=0) AND (rtD == WriteRegM) AND RegWriteM
Stalling logic:
branchstall = BranchD AND RegWriteE AND (WriteRegE == rsD OR WriteRegE == rtD) OR BranchD AND MemtoRegM AND (WriteRegM == rsD OR WriteRegM == rtD) StallF = StallD = FlushE = lwstall OR branchstall
Therefore, we have a basic pipelined processor which can handle 9 instructions below: add sub and or slt addi lw sw beq
Block diagram of data p ath
10
CLK
RegWriteD RegWriteE MemtoRegE MemWriteE ALUControlE 2:0 ALUSrcE RegDstE
CLK
CLK
RegWriteW MemtoRegW
Control Unit
31:26 5:0
Op Funct
CLK 0 1
PC'
EN
CLK A RD
InstrD
25:21
CLK A1 WE3 RD1 0 1
EqualD
PCSrcD
CLK
00 01 10 SrcAE ALUOutM 00 01 10
PCF
WE
Instruction Memory
20:16
0 1
0 1
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
ReadDataW
25:21 20:16 15:11
ALUOutW
1 0
0 1
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
+
4
CLR EN
15:0
Sign Extend
SignImmD
SignImmE
<<2
+
PCPlus4D PCBranchD
PCPlus4F
CLR
ResultW
StallF
StallD
BranchD
ForwardBD ForwardAD
FlushE
ForwardBE ForwardAE
MemtoRegE RegWriteE
RegWriteM
RegWriteW
Hazard Unit
Control unit
Control Unit Jump MemtoReg MemWrite Branch ALUSrc1:0 RegDst RegWrite
Main Opcode5:0 Decoder
ALUOp2:0 ALU Decoder ALUControl2:0
Funct5:0
Main Decoder:
Instr. R-Type addi lw sw beq Opcode[5:0] 00 0000 (0) 00 1000 (8) 10 0011 (35) 10 1011 (43) 00 0100 (4) AluOp[1:0] 1X 00 00 00 X1 RegWrite 1 1 1 0 0 RegDst 1 0 0 X X AluSrc 0 1 1 1 0 MemWrite 0 0 0 1 0 MemToReg 0 0 1 X X Branch 0 0 0 0 1 Jump 0 0 0 0 0
ALU Decoder:
Instr. add sub and Funct[5:0] 10 0000 10 0010 10 0100 AluOp[1:0] 1X 1X 1X AluCtrl[2:0] 010 110 000
11
or addi lw sw beq slt
10 0101 XX XXXX XX XXXX XX XXXX XX XXXX 10 1010
1X 00 00 00 X1 1X
A
N
001 010 010 010 110 111

B
N
ALU
ALUCtrl[2:0] 000 001 010 011 100 101 110 111 Operasi A AND B A OR B A+B n/a A AND B' A OR B' A-B A<B
0
ALUCtrl2
Cout
[N-1]
+ S
Zero Extend
N N N N
== 0 Zero
2
N
ALUCtrl1:0
2. Adding j (jump) Instruction Syntax : j label Instruction Set : Operasi :
0000 10ii iiii iiii iiii iiii iiii iiii nPC = PCPlus4[31:28] & imm & 00
To handle jump instruction, we modify the datapath and controller as shown below:
PCSrcD1:0
0 1
BranchTakenD
RegWriteD
CLK
RegWriteE MemtoRegE MemWriteE ALUControlE 2:0 ALUSrcE RegDstE
CLK
CLK
RegWriteW MemtoRegW
JumpD
Control Unit
31:26 5:0
Op Funct
CLK 0 1 2
PC'
EN
CLK A RD
InstrD
25:21
CLK A1 WE3 RD1 0 1
EqualD
CLK
00 01 10 SrcAE ALUOutM 00 01 10
PCF
WE
Instruction Memory
20:16
0 1
0 1
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
ReadDataW
25:21 20:16 15:11
ALUOutW
1 0
0 1
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
+
4
15:0
Sign Extend
SignImmD
SignImmE
<<2
+
EN CLR
PCPlus4F
PCPlus4D PCBranchD
CLR
FlushD BranchTakenD
ResultW
ForwardAE
ForwardBE
31:28
PCJumpD
27:0
RegWriteE
RegWriteM
<<2
BranchD
MemtoRegE
ForwardAD
ForwardBD
25:0
FlushE
JumpD
StallF
StallD
RegWriteW
Hazard Unit
12
The nextPC mux selector is removed by 2-bit signal that is a merged product by JumpD and the former PCSrcD (BranchTakenD). Then, we add one 32-bit input of the mux, PCJumpD, that is the same as we have previously design in single-cycle processor. The timing diagram of jump instruction execution is shown below:
j label
IM
Reg
ALU
DM
Reg
<PC+4>
IM
Reg
ALU
DM
Reg
label:
IM
Reg
ALU
DM
Reg
Initially, the instruction set of jump is fetched from the Instruction Memory. Then, dataflow enters the second phase that is ID stage of jump. On the previous phase, the instruction after jump (PC+4) is fetched because PCJumpD has not been finished yet. Then, on the next phase PCJumpD is produced. Thus, the instruction on PCJumpD can be fetched. At that moment, the PC+4 instruction is flushed by previous JumpD signal as the CLR signal of ID stage register (described in the hazard logic) Besides, JumpD instruction also flushed start from EX stage because it is no longer needed. In order to jump into the target address, we modifiy the and FlushD and FlushE logic:
FlushD = JumpD OR BranchTakenD FlushE = lwstall OR branchstall OR JumpD
3. Adding shift Instructions Syntax Instruction Set Operasi Syntax Instruction Set Operasi Syntax Instruction Set Operasi : : : : : : : : : sll 0000 $d = srl 0000 $d = sll 0000 $d = 00-- ---t tttt dddd dhhh hh00 0000 $t << h 00-- ---t tttt dddd dhhh hh00 0010 $t >> h 00-- ---t tttt dddd dhhh hh00 0011 $t >>> h
In this part, we will introduce shift instructions such as: Shift left logical (sll) Shift right logical (srl) Shift right arithmetic (sra)
13
Then, we must bypassing shamt bits from Instruction Set into ALU in EX stage. Besides, we must add some operators in ALU. For the better understanding, we have drawn in the figure below
PCSrcD1:0
0 1
BranchTakenD
RegWriteD
CLK
RegWriteE MemtoRegE MemWriteE ALUControlE 3:0 ALUSrcE RegDstE
CLK
CLK
RegWriteW MemtoRegW
JumpD
Control Unit
31:26 5:0
Op Funct
10:6
shamtE10:6
CLK 0 1 2
PC'
EN
CLK A RD
InstrD
25:21
CLK A1 WE3 RD1
EqualD
CLK
=
0 1 0 1
RsD RtD RdD RsE RtE RdE 00 01 10 00 01 10
SrcAE ALUOutM
PCF
WE
Instruction Memory
20:16
0 1
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
ReadDataW
25:21 20:16 15:11
ALUOutW
1 0
0 1
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
+
4
15:0
Sign Extend
SignImmD
SignImmE
<<2
+
EN CLR
PCPlus4F
PCPlus4D PCBranchD
CLR
FlushD BranchTakenD
ResultW
ForwardAE
ForwardBE
31:28
JumpTargetD
27:0
RegWriteE
RegWriteM
<<2
BranchD
MemtoRegE
ForwardAD
ForwardBD
25:0
FlushE
JumpD
StallF
StallD
RegWriteW
Hazard Unit
shamt4:0
5
A
N
B
N
ALUCtrl3
Cout
>>>
>>
<<
Zero Extend
[N-1]
+ S
2 N
ALUCtrl2:0
ALUCtrl[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Operasi A AND B A OR B A+B n/a B << shamt B >> shamt B >>> shamt n/a A AND B' A OR B' A-B A> shamt B >>> shamt n/a
0 0
14
4. Adding shift variable Instructions Syntax Instruction Set Operasi Syntax Instruction Set Operasi Syntax Instruction Set Operasi : : : : : : : : : sllv 0000 $d = srl 0000 $d = sll 0000 $d = 00-- ---t tttt dddd dhhh hh00 0100 $t << h 00-- ---t tttt dddd dhhh hh00 0110 $t >> h 00-- ---t tttt dddd dhhh hh00 0111 $t >>> h
In this part, we will introduce shift instructions such as: Shift left logical variable (sllv) Shift right logical variable (srlv) Shift right arithmetic (srav)
We set the MSB (ALU(3)) as a selector of the shifter for SrcB. When the instruction is shift variable (sllv, srlv, or srav), ALUCtrl(3) will become 1 and SrcA selected as the shifter . For the better understanding, we have drawn in the figure below:
shamt4:0 A4:0
5 5 N
A
N
B
N
ALUCtrl3
N
ALUCtrl3
Cout
>>>
>>
<<
Zero Extend
[N-1]
+ S
2 N
ALUCtrl2:0
ALUCtrl[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Operasi A AND B A OR B A+B n/a B << shamt B >> shamt B >>> shamt n/a A AND B' A OR B' A-B A> A B >>> A n/a
0 4
0 1 0
5. Adding xor Instruction Syntax : xor $d, $s, $t Instruction Set : Operasi : 0000 00ss ssst tttt dddd d--- --10 0110 $d = $s XOR $t
In order to handle the xor instruction, we introduce a new operator in the ALU that is XOR gate.
15
shamt4:0 A4:0
5 5
A
N
B
N
ALUCtrl3
N
ALUCtrl3
Cout
>>>
>>
<<
Zero Extend
[N-1]
+ S
2 N
ALUCtrl2:0
ALUCtrl[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Operasi A AND B A OR B A+B n/a B << shamt B >> shamt B >>> shamt A XOR B A AND B' A OR B' A-B A> A B >>> A A XOR B'
6. Adding nor Instructions Syntax : nor $d, $s, $t Instruction Set : Operasi : 0000 00ss ssst tttt dddd d--- --10 0111 $d = $s NOR $t
We add a new operator in the ALU, that is NOT gate placed after the OR ate before passing as an output of mux. Then, ALUCtrl width is expanded into 5-bit (ALUCtrl[4:0]).
7
N
6
N
5
>>>
shamt4:0 A4:0
5 5
A
N
B
N
ALUCtrl4
N
ALUCtrl4
Cout
>> <<
[N-1]
+ S
2 N
ALUCtrl3:0
ALUCtrl[4:0] 0 0000 0 0001 0 0010 0 0011 0 0100 0 0101 0 0110 0 0111 0 1000 1 0000 1 0001 1 0010 1 0011 1 0100 1 0101 1 0110 1 0111 1 1000
Operasi A AND B A OR B A+B n/a B << shamt B >> shamt B >>> shamt A XOR B A NOR B A AND B' A OR B' A-B A> A B >>> A A XOR B' A NOR B'
0
Zero Extend
16
7. Adding lui (load upper immediate) Instruction Syntax : lui $t, imm 0011 1100 000t tttt iiii iiii iiii iiii $t = imm & X0000 Instruction Set : Operasi :
This instruction will load the 16-bits immediate into the upper-bits of register $t. Therefore, we need an operator which can extend the immediate into 32-bit number that will be loaded into $t.
PCSrcD1:0
0 1
BranchTakenD
RegWriteD
CLK
RegWriteE MemtoRegE MemWriteE ALUControlE 4:0 ALUSrcE1:0 RegDstE
CLK
CLK
RegWriteW MemtoRegW
JumpD
Control Unit
31:26 5:0
Op Funct
ALUSrcD1:0 RegDstD BranchD
10:6
shamtE10:6
CLK 0 1 2
EN
CLK A RD
InstrD
25:21
CLK A1 WE3 RD1 0 1
EqualD
CLK
00 01 10 SrcAE ALUOutM 00 01 10
PC'
PCF
WE
Instruction Memory
20:16
0 1
0 1 2
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
ReadDataW
25:21 20:16 15:11
ALUOutW
1 0
+
4
15:0
Sign Extend
SignImmD
<<2
+
EN CLR
PCPlus4F
PCPlus4D PCBranchD
15:0
CLR
<<16
ImmUpperD
ImmUpperE
SignImmE
0 1
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
BranchTakenD
ResultW
25:0
FlushD
ForwardAD
ForwardBD
MemtoRegE
ForwardAE
ForwardBE
JumpTargetD
27:0
StallF
StallD
Hazard Unit
ALUSrc mux is expanded into 2-bit because we have add a new input, that is the output of ImmUpperD. ALUOut value is a result from add operation of imm<<16 and $rs ($0 = 0). Then, operation in the ALU is add operation (ALUCtrl = 0 0010).
Instr. lui Opcode[5:0] 00 1111 (15) AluOp[1:0] 00 RegWrite 1 RegDst 0 AluSrc[1:0] 10 MemWrite 0 MemToReg 0 Branch 0 Jump 0
Instr. lui
Funct[5:0] XX XXXX
AluOp[1:0] 00
AluCtrl[4:0] 0 0010
8. Adding slti (set less than immediate) Instruction

Syntax Instruction Set Operasi : : : slti $t, $s, imm 0010 10ss ssst tttt iiii iiii iiii iiii if ($s < SignExt(imm)) then $t = 1; else $t = 0
Nothing changed when we add a slti instruction. We just need to update the Control signal table:
Instr. slti Opcode[5:0] 00 1010 (10) AluOp[1:0] 11 RegWrite 1 RegDst 0 AluSrc[1:0] 01 MemWrite 0 MemToReg 0 Branch 0 Jump 0
RegWriteE
RegWriteM
BranchD
JumpD
RegWriteW
31:28
<<2
FlushE
17
Instr. slti
Funct[5:0] XX XXXX
AluOp[1:0] 11
AluCtrl[4:0] 1 0011
9. Adding andi, ori, and xori Instructions Syntax : andi Instruction Set : 0011 00ss ssst tttt iiii iiii iiii iiii Operasi : $t = $s AND imm Syntax : ori Instruction Set : 0011 01ss ssst tttt iiii iiii iiii iiii Operasi : $t = $s OR imm Syntax : xori Instruction Set : 0011 10ss ssst tttt iiii iiii iiii iiii Operasi : $t = $s XOR imm These instructions are the I-Type Instructions that load the result into the register that address pointed by $t. We no longer added any new operator in the ALU because we already have all of them before. Besides, we need a new control signal, namely ExtOp, to select the ZeroExtended of Immediate.
Instr. andi ori xori Instr. andi ori xori Opcode[5:0] 00 1100 (12) 00 1101 (13) 00 1110 (14) Funct[5:0] XX XXXX XX XXXX XX XXXX AluOp[2:0] 100 101 110 AluOp[2:0] 100 101 110 RegWrite 1 1 1 RegDst 0 0 0 AluSrc[1:0] 01 01 01 MemWrite 0 0 0 MemToReg 0 0 0 Branch 0 0 0 Jump 0 0 0 ExtOp 1 1 1
AluCtrl[3:0] 0000 0001 0111
PCSrcD1:0
0 1
BranchTakenD ExtOpD RegWriteD
CLK
CLK
CLK
RegWriteW MemtoRegW
JumpD
Control Unit
31:26 5:0
Op Funct
ALUSrcD1:0 RegDstD BranchD
10:6
CLK 0 1 2
PC'
EN
CLK A RD
InstrD
25:21
CLK A1 WE3 RD1 0 1
EqualD
shamtE10:6
CLK
00 01 10 SrcAE ALUOutM 00 01 10
PCF
WE
Instruction Memory
20:16
0 1
0 1 2
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
ReadDataW
25:21 20:16 15:11
ALUOutW
1 0
+
4
SignImmD
15:0
Extender <<2
ExtOpD
EN CLR
PCPlus4F
PCPlus4D PCBranchD
15:0
CLR
<<16
ImmUpperD
ImmUpperE
SignImmE
0 1
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
BranchTakenD
ResultW
25:0
FlushD
ForwardAD
ForwardBD
MemtoRegE
ForwardAE
ForwardBE
JumpTargetD
27:0
StallF
StallD
Hazard Unit
RegWriteE
RegWriteM
BranchD
JumpD
RegWriteW
31:28
<<2
FlushE
18
10. Adding Branch Instructions (bne, bltz, blez, and bgtz) Instruction set of branch not equal:
Syntax Instruction Set Operasi : : : bne $s, $t, label 0001 01ss ssst tttt iiii iiii iiii iiii if ($s /= $t) then (nPC = PC+4 + (SignExt(Imm)<<2))
Instruction set of branch less than zero:

Syntax Instruction Set Operasi : : : bltz $s, $t, label 0000 01ss ssst tttt iiii iiii iiii iiii if ($s < $t) then (nPC = PC+4 + (SignExt(Imm)<<2))
Instruction set of branch less than or equal zero:

Syntax Instruction Set Operasi : : : blez $s, $t, label 0001 10ss ssst tttt iiii iiii iiii iiii if ($s <= $t) then (nPC = PC+4 + (SignExt(Imm)<<2)
Instruction set of branch greater than zero:

Syntax Instruction Set Operasi : : : bgtz $s, $t, label 0001 11ss ssst tttt iiii iiii iiii iiii if ($s > $t) then (nPC = PC+4 + (SignExt(Imm)<<2))
For handling four branch instructions above, we modify the datapath as shown below:
PCSrcD1:0 RegWriteD MemtoRegD MemWriteD ALUControlD 4:0
CLK
ExtOpD
1 0
CLK
CLK
RegWriteW MemtoRegW
Control Unit
31:26 5:0
ALUSrcD1:0 RegDstD
JumpD BranchTakenD
Op Funct
BgtzD BltzD BneD BeqD
Branch Operator
shamtE10:6
10:6
CLK 0 1 2
PC'
EN
CLK A RD
InstrD
25:21
CLK A1 WE3 RD1 0 1 0 1

RsD RtD RdD SignImmD
15:0
CLK
00 01 10 00 01 10 SrcAE ALUOutM
PCF
WE
Instruction Memory
20:16
0 1 2
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
ReadDataW
25:21 20:16 15:11
RsE RtE RdE
ALUOutW
1 0
+
4
Extender <<2
ExtOpD
EN CLR
PCPlus4F
PCPlus4D PCBranchD
15:0
CLR
<<16
ImmUpperD
ImmUpperE
SignImmE
0 1
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
BranchTakenD
ResultW
25:0
FlushD
ForwardAD
ForwardBD
MemtoRegE
ForwardAE
ForwardBE
BltzD BneD
StallF
StallD
BeqD
27:0
BgtzD
JumpTargetD
Hazard Unit
In the figure, we see that previous branch decider is replaced by a block that contents operation to decide whether the branch is taken or not, namely Branch Operator. The contenct of Branch Operator is show below:
RegWriteE
RegWriteM
RegWriteW
31:28
<<2
JumpD
FlushE
19
PCSrcD(0) BranchOperator
BeqD BneD BltzD BgtzD
=
BranchSrcAD(31) 32 32
BranchSrcBD BranchSrcAD
BeqD, BneD, BltzD, and BgtzD signals will active depends on which branch type that fetched from instruction. For beq and bne, we use comparator to decide the branch (in bne we use NOT gate after the comparator). For bltz, we use the MSB of SrcA as sign bit to know whether that number is less than zero or not. For bgtz, we consider that as a number that is not less than zero and not equal with zero. When blez instruction is fetched, the beq and bltz will active together. Therefore, the branch will be taken if one of those two conditional branch fulfilled. Besides, we also should modify the logic of hazard unit:
BranchD = BeqD OR BneD OR BltzD OR BgtzD branchstall = BranchD AND RegWriteE AND (WriteRegE == rsD OR WriteRegE == rtD) OR BranchD AND MemtoRegM AND (WriteRegM == rsD OR WriteRegM == rtD) FlushD = JumpD OR BranchTakenD StallF = StallD = FlushE = lwstall OR branchstall
Control signal table:
20
11. Adding jal (jump and link) Instruction

Syntax Instruction Set Operasi : : : jal label 0000 11ii iiii iiii iiii iiii iiii iiii nPC = PC+4[31.28] & imm & 00; $31 = PC+4
Modified datapath:
PCSrcD1:0 RegWriteD
CLK
RegWriteE
CLK
RegWriteM
CLK
RegWriteW
JalD
JalE ExtOpD
MemtoRegE MemWriteE ALUControlE 4:0 ALUSrcE1:0 RegDstE1:0
1 0
JalM
MemtoRegM MemWriteM
JalW 1
MemtoRegW 0
ResultSelectW1:0
Control Unit
31:26 5:0
ALUSrcD1:0 RegDstD1:0
JumpD BranchTakenD
Op Funct
Branch Operator
shamtE10:6
PCPlus4M
PCPlus4W
InstD10:6
CLK 0 1 2
PC'
EN
CLK A RD
InstrD
CLK
25:21
CLK WE
ALUOutM
PCF
A1
WE3
RD1
Instruction Memory
0 1 0 1
00 01 10 00 01 10
SrcAE
20:16
0 1 2
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
25:21 20:16 15:11
ALUOutW
ReadDataW
2 1 0
+
4
ExtImmD
15:0
Extender <<2
ExtOpD
EN CLR
PCPlus4F
$sa= 1 1111
PCPlus4D PCBranchD
15:0
<<16
ImmUpperD
ImmUpperE
ExtImmE
0 1 2
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
PCPlus4E
BranchTakenD
ResultW
25:0
FlushD
ForwardAD
ForwardBD
MemtoRegE
ForwardAE
ForwardBE
BltzD BneD
StallF
StallD
BeqD
27:0
BgtzD
JumpTargetD
Hazard Unit
This instruction similar with j, the JumpD will active and caused the instruction jumped into the label address as j instruction does. The difference is, the jal instruction will load the value of PC+4 address into $31 or $ra register. Then, we need to extend the RegDst mux for automatically selecting $31 as WriteReg. We also need additional control signal to select PC+4 as a ResultW value filling the $31 register
Besides, FlushE is also modified:
RegWriteE
RegWriteM
JalD JumpD
RegWriteW
31:28
<<2
FlushE
21
FlushE = lwstall OR branchstall OR (JumpD AND NOT JalD)
Then, EX will not be flushed because it will be flushed if only in j instruction (JumpD=1 and JalD=0). We need to do this modification because jal still need WB stage to load PCPlus4 value to register $ra. 12. Adding jr (jump to register) Instruction
Syntax Instruction Set Operasi : : : jr $s 0000 00ss sss0 0000 0000 0000 0000 1000 nPC = $s
Modified datapath:
PCSrcD2:0 RegWriteD
CLK
RegWriteE
CLK
RegWriteM
CLK
RegWriteW
JalD
JalE ExtOpD
2 1 0
JalM
MemtoRegM MemWriteM
JalW 1
MemtoRegW 0
ResultSelectW1:0
Control Unit
ForwardJD1:0
31:26 5:0
ALUSrcD1:0 RegDstD1:0 JumpD JrD
Op Funct
2 1 0
ALUOutM PCPlus4M InstD10:6
BranchTakenD
Branch Operator
InstE10:6
PCPlus4M
PCPlus4W
CLK 0 1 2 4
PC'
EN
CLK A RD
InstrD
CLK
25:21
CLK WE3 RD1 0 1 0 1

RsD RtD RdD ExtImmD RsE RtE RdE 00 01 10 00 01 10 SrcAE ALUOutM
PCF
A1
WE
Instruction Memory
20:16
0 1 2
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
25:21 20:16 15:11
ALUOutW
ReadDataW
2 1 0
+
4
15:0
Extender <<2
ExtOpD
EN CLR
PCPlus4F
$sa= 1 1111
PCPlus4D PCBranchD
15:0
<<16
ImmUpperD
ImmUpperE
ExtImmE
0 1 2
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
PCPlus4E
FlushD BranchTakenD
ResultW
ForwardAD
ForwardBD
MemtoRegE
ForwardAE
ForwardBE
BltzD BneD
BeqD
StallF
StallD
JrD JalD
27:0
BgtzD
Hazard Unit
Jr is a conditional branch that similar with j. But, the target address of jr is different that is the value in $s register. Therefore, we bypass ReadData1D into the new input of PC Source signal mux. We add a new control signal, JrD, as a selector of mux when jr instruction is fetched.
JalM
JumpTargetD
RegWriteE
RegWriteM
JumpD
RegWriteW
31:28
<<2
ForwardJD1:0
25:0
FlushE
22
Control Unit JumpD JalD MemtoRegD MemWriteD BeqD BneD BltzD BgtzD ALUSrcD1:0 RegDstD1:0 RegWriteD ExtOpD
ALUOp2:0 ALU Decoder

JrD ALUControlD4:0
Funct5:0
Modified datapath above also designed to handle any hazard occurred. These are some cases of hazard: Data hazard caused by Jal (Read After Write Hazard)
jal label
IM
Reg
ALU
DM
Reg
add $s0, $s1, $s2
IM
Reg
ALU
DM
Reg
label: addi $s1, $t0, 3
IM
Reg
ALU
DM
Reg
jr $ra
IM
Reg
ALU
DM
Reg
sub $s2, $s2, $t0
IM
Reg
ALU
DM
Reg
add $s0, $s1, $s2
IM
Reg
ALU
DM
Reg
In this case, we can still handle it by using read register stage on the first half-cycle, and write register stage on the second half-cycle. Data hazard caused by Jal (Forwarding PCPlus4M)
23
jal label
IM
Reg
ALU
DM
Reg
add $s0, $s1, $s2
IM
Reg
ALU
DM
Reg
label: jr $ra
IM
Reg
ALU
DM
Reg
sub $s2, $s2, $t0
IM
Reg
ALU
DM
Reg
add $s0, $s1, $s2
IM
Reg
ALU
DM
Reg
This case is a little bit impossibly occurred because jal instruction jumping the program into the blank subroutine which have no instructions to be executed and straightly jump again by jr instruction. But, we can design the processor that can prevent undesired problem when this case occurred by a slopy programmer. Therefore, we modify the hazard unit as below:
ForwardJD = JalM AND JrD FlushE = lwstall OR branchstall OR (JumpD AND NOT JalD) OR JrD
A new hazard unit signal is added, namely ForwardJD which active data hazard on the figure occurred. FlushE will active in jr instruction, therefore we modify the hazard logic. Data hazard caused by register writing instruction (Forwarding ALUOutM)
add $s3, $s1, $t0
IM
Reg
ALU
DM
Reg
add $s0, $s1, $s2
IM
Reg
ALU
DM
Reg
jr $s3
IM
Reg
ALU
DM
Reg
This case occurred when jr jumps the program into PC address that has not updated by previous RType instruction. Then, we modify the hazard unit logic:
IF (JalM==1 AND JrD==1) THEN ForwardJD = 01 ELSE IF ((rsD!=0) AND (rsD==WriteRegM) AND RegWriteM) THEN
24
ForwardJD = 10 ELSE ForwardJD = 00
Data Hazard Caused by register writing instruction (jrstall)
add $s3, $s1, $t0
IM
Reg
ALU
DM
Reg
add $s0, $s1, $s2
IM
Reg
ALU
DM
Reg
jr $s0
IM
Reg
ALU
DM
Reg
jr $s0
IM
Reg
ALU
DM
Reg
To handle this kind of hazard we must use stalling method:

jrstall = JrD AND RegWriteE AND (WriteRegE == rsD ) AND (rsD != 0)
StallF = StallD = lwstall OR branchstall OR jrstall FlushE=lwstall OR branchstall OR jrstall OR (JumpD AND NOT JalD) OR JrD
Data Hazard Caused by lw (jrstall)
lw $s0, $s3, 8
IM
Reg
ALU
DM
Reg
add $s0, $s1, $s2
IM
Reg
ALU
DM
Reg
jr $s0
IM
Reg
ALU
DM
Reg
jr $s0
IM
Reg
ALU
DM
Reg
25
To handle this kind of hazard we must use stalling method:

jrstall = (JrD AND RegWriteE AND WriteRegE == rsD) OR (JrD AND MemtoRegM AND WriteRegM == rsD)
StallF = StallD = lwstall OR branchstall OR jrstall
13. Adding jalr (jump and link register) Instruction

Syntax Instruction Set : Operasi : jalr $d, $s 0000 00ss sss0 0000 1111 1000 0000 1001 : nPC = $s; $31 = PC+4
Modified datapath:
PCSrcD2:0 RegWriteD
CLK
RegWriteE
CLK
RegWriteM
CLK
RegWriteW
JalrD JalD
JumpLinkD ExtOpD
JumpLinkE
JumpLinkM
MemtoRegM MemWriteM
JumpLinkW 1
MemtoRegW 0
ResultSelectW1:0
Control Unit
ForwardJD1:0
31:26 5:0
Op Funct
2 1 0
ALUOutM PCPlus4M InstD10:6
ALUSrcD1:0 RegDstD1:0 2 JumpD 1 JrD 0 BranchTakenD BgtzD BltzD Branch BneD BeqD Operator
PCPlus4M
shamtE10:6
PCPlus4W
CLK 0 1 2 4
PC'
EN
CLK A RD
InstrD
CLK
25:21
CLK WE3 RD1 0 1 0 1

PCF
A1
WE
Instruction Memory
20:16
0 1 2
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
25:21 20:16 15:11
ALUOutW
ReadDataW
2 1 0
+
4
15:0
Extender <<2
ExtOpD
EN CLR
PCPlus4F
$sa= 1 1111
PCPlus4D PCBranchD
15:0
<<16
ImmUpperD
ImmUpperE
ExtImmE
0 1 2
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
PCPlus4E
BranchTakenD
ResultW
FlushD
ForwardAD
ForwardBD
MemtoRegE
ForwardAE
ForwardBE
JumpLinkM
BltzD BneD
StallF
StallD
BeqD
27:0
BgtzD
PCJumpD
Hazard Unit
We modify a little from the previous modified datapath. First, we add a new control unit signal namely jalr as an output of ALU decoder in control unit. Then, we introduce a new signal namely JumpLinkD as a result from OR operation of JalD and JalrD.
RegWriteE
RegWriteM
RegWriteW
31:28
<<2
ForwardJD1:0 JrD JumpLinkD JumpD
25:0
FlushE
26

JalrD JrD ALUControlD4:0
Funct5:0
Jalr instruction has a typical hazard with jr instruction. Therefore, we modify the hazard unit logic below:
--ForwardJD logic
IF (JumpLinkM==1 AND JrD==1) THEN ForwardJD = 01 ELSE IF ((rsD!=0) AND (rsD==WriteRegM) AND RegWriteM) THEN ForwardJD = 10 ELSE ForwardJD = 00
FlushE=lwstall OR branchstall OR jrstall OR((JumpD OR JrD) AND NOT JumpLinkD)
27
14. Final Design Block diagram
28
Control Unit

JalrD JrD ALUControlD4:0
Funct5:0
Main Decoder:
ALU Decoder:
Instr. add sub and or addi lw sw beq j slt sll srl sra sllv srlv srav Funct[5:0] 10 0000 10 0010 10 0100 10 0101 XX XXXX XX XXXX XX XXXX XX XXXX XX XXXX 10 1010 00 0000 00 0010 00 0011 00 0100 00 0110 00 0111 AluOp[2:0] 010 010 010 010 000 000 000 001 XXX 010 010 010 010 010 010 010 AluCtrl[4:0] 0 0010 1 0010 0 0000 0 0001 0 0010 0 0010 0 0010 1 0010 X XXXX 1 0011 0 0100 0 0101 0 0110 1 0100 1 0101 1 0110 Jr 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Jalr 0 0 0 0 0 X X X 0 0 0 0 0 0 0 0
29
xor nor lui slti andi ori xori bne bltz bgtz blez jal jr jalr
10 0110 10 0111 XX XXXX XX XXXX XX XXXX XX XXXX XX XXXX XX XXXX XX XXXX XX XXXX XX XXXX XX XXXX 00 1000 00 1001
010 010 000 011 100 101 110 001 001 001 001 XXX 010 010
0 0111 0 1000 0 0010 1 0011 0 0000 0 0001 0 0111 1 0010 1 0010 1 0010 1 0010 X XXXX X XXXX X XXXX
0 0 0 0 0 0 0 0 0 0 0 0 1 1
0 0 0 0 0 0 0 X X X X X 0 1
ALU
shamt4:0 A4:0
5 5 N
A
N
B
N
1
>>>
0
ALUCtrl4 Cout
<<
[N-1]
ALUCtrl4
>>
+ S
Zero Extend
3
N
ALUCtrl3:0
ALUCtrl[4:0] 0 0000 0 0001 0 0010 0 0011 0 0100 0 0101 0 0110 0 0111 0 1000
Operation A AND B A OR B A+B n/a B << shamt B >> shamt B >>> shamt A XOR B A NOR B
ALUCtrl[4:0] 1 0000 1 0001 1 0010 1 0011 1 0100 1 0101 1 0110 1 0111 1 1000
Operation A AND B' A OR B' A-B A> A B >>> A A XOR B' A NOR B'
Hazard Unit
30
RegWriteE RegWriteM RegWriteW MemtoRegE BeqD BneD BltzD BgtzD BranchTakenD JumpD JrD JumpLinkD JumpLinkM rsD4:0 rtD4:0 rsE4:0 rtE4:0 WriteRegE4:0 WriteRegM4:0 WriteRegW4:0
Hazard Unit
StallF StallD FlushE ForwardAD ForwardBD ForwardJD1:0 ForwardAE1:0 ForwardBE1:0
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY HazardUnit IS PORT( RegWriteE RegWriteM RegWriteW MemtoRegE BeqD BneD BltzD BgtzD BranchTakenD: JumpD JrD JumpLinkD JumpLinkM rsD rtD rsE rtE : : : : : : : : : : IN STD_LOGIC_VECTOR(1 DOWNTO 0); IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; : IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; : IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; : : : : IN STD_LOGIC_VECTOR(4 DOWNTO 0); IN STD_LOGIC_VECTOR(4 DOWNTO 0); IN STD_LOGIC_VECTOR(4 DOWNTO 0); IN STD_LOGIC_VECTOR(4 DOWNTO 0);
31
WriteRegE WriteRegM WriteRegW StallF StallD FlushE ForwardAE ForwardBE ForwardJD ForwardAD ForwardBD END HazardUnit;
: : :
IN STD_LOGIC_VECTOR(4 DOWNTO 0); IN STD_LOGIC_VECTOR(4 DOWNTO 0); IN STD_LOGIC_VECTOR(4 DOWNTO 0); : : : OUT STD_LOGIC_VECTOR; OUT STD_LOGIC; OUT STD_LOGIC;
: : : : :
OUT STD_LOGIC_VECTOR(1 DOWNTO 0); OUT STD_LOGIC_VECTOR(1 DOWNTO 0); OUT STD_LOGIC_VECTOR(1 DOWNTO 0); OUT STD_LOGIC_VECTOR; OUT STD_LOGIC_VECTOR);
ARCHITECTURE behaviour OF InstrMemory IS SIGNAL BranchD SIGNAL branchstall SIGNAL lwstall SIGNAL jrstall BEGIN --ForwardAE logic IF ((rsE != 0) AND (rsE == WriteRegM) AND RegWriteM) THEN ForwardAE = 10 ELSIF ((rsE != 0) AND (rsE == WriteRegW) AND RegWriteW) THEN ForwardAE = 01 ELSE ForwardAE = 00; : : : : STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC;
--ForwardBE logic IF ((rtE != 0) AND (rtE == WriteRegM) AND RegWriteM) THEN ForwardBE = 10 ELSIF ((rtE != 0) AND (rtE == WriteRegW) AND RegWriteW) THEN ForwardBE = 01 ELSE ForwardBE = 00;
--ForwardAD logic ForwardAD <= (rsD !=0) AND (rsD == WriteRegM) AND RegWriteM; --ForwardBD logic ForwardBD <= (rtD !=0) AND (rtD == WriteRegM) AND RegWriteM; --ForwardJD logic IF (JumpLinkM==1 AND JrD==1) THEN
32
ForwardJD = 01 ELSIF ((rsD!=0) AND (rsD==WriteRegM) AND RegWriteM) THEN ForwardJD = 10 ELSE ForwardJD = 00; --signal lwstall logic lwstall <= ((rsD == rtE) OR (rtD == rtE)) AND MemtoRegE; --signal branchstall logic BranchD <= BeqD OR BneD OR BltzD OR BgtzD; branchstall <= BranchD AND RegWriteE AND (WriteRegE == rsD OR WriteRegE == rtD) OR BranchD AND MemtoRegM AND (WriteRegM == rsD OR WriteRegM == rtD); --signal jrstall logic jrstall <= (JrD AND RegWriteE AND WriteRegE == rsD) OR (JrD AND MemtoRegM AND WriteRegM == rsD) ; --stall logic StallF <= StallD = lwstall OR branchstall OR jrstall; --FlushD logic FlushD <= JumpD OR JrD OR BranchTakenD; --FlushE logic FlushE <= lwstall OR branchstall OR ((JumpD OR JrD) AND NOT JumpLinkD); END behaviour;
33
B. Dataflow of Instructions
1. Dataflow of beq Instruction We will divide the dataflow of instruction beq into three conditions, such as: No hazard occurred
PCSrcD2:0 RegWriteD
CLK
RegWriteE
CLK
RegWriteM
CLK
RegWriteW
JalrD JalD
JumpLinkD ExtOpD
JumpLinkE
JumpLinkM
MemtoRegM MemWriteM
JumpLinkW 1
MemtoRegW 0
ResultSelectW1:0
Control Unit
31:26 5:0
ALUSrcD1:0 RegDstD1:0 JumpD=0 JrD=0
ForwardJD
Op Funct
2 1 0 0 1 2 4
ALUOutM PCPlus4M
BranchTakenD=1 BgtzD BltzD Branch BneD BeqD=1 Operator
2 1 0
PCPlus4M
shamtE10:6
PCPlus4W
ReadData1D
10:6
CLK
PC'
EN
CLK A RD
InstrD
CLK
25:21
CLK WE3 RD1 0 1 0 1

PCF
A1
WE
Instruction Memory
20:16
0 1 2
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
25:21 20:16 15:11
ALUOutW
ReadDataW
2 1 0
+
4
15:0
Extender <<2
ExtOpD
EN CLR
PCPlus4F
$sa= 1 1111
PCPlus4D PCBranchD
15:0
<<16
ImmUpperD
BranchTakenD=1
ImmUpperE
ExtImmE
0 1 2
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
PCPlus4E
ResultW
25:0
FlushD=1
ForwardAD
ForwardBD
MemtoRegE
ForwardAE
ForwardBE
BeqD=1
BgtzD
StallF
StallD
BltzD BneD
27:0
JumpD
PCJumpD
Hazard Unit
We can see on the figure above that the dataflow of beq are marked by the red lines. Handling data hazard using Forwarding When this hazard occurred, ForwardAD will turn into logic 1. Then, ALUOutM will be forwarded as BranchSrcA or an input of BranchOperator.
--ForwardAD logic ForwardAD = (rsD !=0) AND (rsD == WriteRegM) AND RegWriteM
RegWriteE
RegWriteM
JumpLinkM
RegWriteW
31:28
<<2
ForwardJD1:0 JrD JumpLinkD
FlushE
34
PCSrcD2:0 RegWriteD
CLK
RegWriteE
CLK
RegWriteM
CLK
RegWriteW
JalrD JalD
JumpLinkD ExtOpD
JumpLinkE
JumpLinkM
MemtoRegM MemWriteM
JumpLinkW 1
MemtoRegW 0
ResultSelectW1:0
Control Unit
31:26 5:0
ForwardJD
Op Funct
2 1 0 0 1 2 4
ALUOutM PCPlus4M
2 1 0
PCPlus4M
shamtE10:6
PCPlus4W
ReadData1D
10:6
CLK
PC'
EN
CLK A RD
InstrD
CLK
25:21
CLK WE3 RD1 0 1 0 1

PCF
A1
WE
Instruction Memory
20:16
0 1 2
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
25:21 20:16 15:11
ALUOutW
ReadDataW
2 1 0
+
4
15:0
Extender <<2
ExtOpD
EN CLR
PCPlus4F
$sa= 1 1111
PCPlus4D PCBranchD
15:0
<<16
ImmUpperD
BranchTakenD=1
ImmUpperE
ExtImmE
0 1 2
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
PCPlus4E
ResultW
25:0
FlushD=1
ForwardAD=1
ForwardBD
MemtoRegE
ForwardAE
ForwardBE
BeqD=1
BgtzD
StallF
StallD
BltzD BneD
27:0
JumpD
PCJumpD
Hazard Unit
Handling data hazard using Stall When this case occurred, the branchstall signal inside the hazard unit will be activated. Then, StallF, StallD, and FlushE will be logic 1.
BranchD = BeqD OR BneD OR BltzD OR BgtzD = 1 branchstall = BranchD AND RegWriteE AND (WriteRegE == rsD OR WriteRegE == rtD) OR BranchD AND MemtoRegM AND (WriteRegM == rsD OR WriteRegM == rtD) StallF = StallD = lwstall OR branchstall OR jrstall = 1 --FlushE logic FlushE = lwstall OR branchstall OR ((JumpD OR JrD) AND NOT JumpLinkD) = 1
RegWriteE
RegWriteM
JumpLinkM
RegWriteW
31:28
<<2
FlushE
35
PCSrcD2:0 RegWriteD
CLK
RegWriteE
CLK
RegWriteM
CLK
RegWriteW
JalrD JalD
JumpLinkD ExtOpD
JumpLinkE
JumpLinkM
MemtoRegM MemWriteM
JumpLinkW 1
MemtoRegW 0
ResultSelectW1:0
Control Unit
31:26 5:0
ForwardJD
Op Funct
2 1 0 0 1 2 4
ALUOutM PCPlus4M
2 1 0
PCPlus4M
shamtE10:6
PCPlus4W
ReadData1D
10:6
CLK
PC'
EN
CLK A RD
InstrD
CLK
25:21
CLK WE3 RD1 0 1 0 1

PCF
A1
WE
Instruction Memory
20:16
0 1 2
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
25:21 20:16 15:11
ALUOutW
ReadDataW
2 1 0
+
4
15:0
Extender <<2
ExtOpD
EN CLR
PCPlus4F
$sa= 1 1111
PCPlus4D PCBranchD
15:0
<<16
ImmUpperD
ImmUpperE
ExtImmE
0 1 2
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
PCPlus4E
BranchTakenD
ResultW
25:0
FlushD
ForwardAD
ForwardBD
MemtoRegE
ForwardAE
ForwardBE
BeqD=1
BgtzD
StallF=1
StallD=1
BltzD BneD
27:0
JumpD
PCJumpD
Hazard Unit
We have shown the data flow of beq instruction in the datapath. But, we have not given dataflow inside the BranchOperator yet. In the figure below, we can see that when beq fetched, the BeqD signal will turn into logic 1 and activate the AND gate as a branch decider.
BeqD=1 BneD BltzD BgtzD
=
RegWriteE
RegWriteM
JumpLinkM
FlushE=1
RegWriteW
31:28
<<2
36
2. Dataflow of bne Instruction We will divide the dataflow of instruction bne into three conditions, such as: No hazard occurred
PCSrcD2:0 RegWriteD
CLK
RegWriteE
CLK
RegWriteM
CLK
RegWriteW
JalrD JalD
JumpLinkD ExtOpD
JumpLinkE
JumpLinkM
MemtoRegM MemWriteM
JumpLinkW 1
MemtoRegW 0
ResultSelectW1:0
Control Unit
31:26 5:0
ForwardJD
Op Funct
2 1 0 0 1 2 4
ALUOutM PCPlus4M
BranchTakenD=1 BgtzD BltzD Branch BneD=1 BeqD Operator
2 1 0
PCPlus4M
shamtE10:6
PCPlus4W
ReadData1D
10:6
CLK
PC'
EN
CLK A RD
InstrD
CLK
25:21
CLK WE3 RD1 0 1 0 1

PCF
A1
WE
Instruction Memory
20:16
0 1 2
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
25:21 20:16 15:11
ALUOutW
ReadDataW
2 1 0
+
4
15:0
Extender <<2
ExtOpD
EN CLR
PCPlus4F
$sa= 1 1111
PCPlus4D PCBranchD
15:0
<<16
ImmUpperD
BranchTakenD=1
ImmUpperE
ExtImmE
0 1 2
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
PCPlus4E
ResultW
25:0
FlushD=1
ForwardAD
ForwardBD
MemtoRegE
ForwardAE
ForwardBE
BltzD BneD=1
BgtzD
StallF
StallD
BeqD
27:0
JumpD
PCJumpD
Hazard Unit
We can see on the figure above that the dataflow of bne are marked by the red lines. Handling data hazard using Forwarding When this hazard occurred, ForwardAD will turn into logic 1. Then, ALUOutM will be forwarded as BranchSrcA or an input of BranchOperator.
RegWriteE
RegWriteM
JumpLinkM
RegWriteW
31:28
<<2
FlushE
37
PCSrcD2:0 RegWriteD
CLK
RegWriteE
CLK
RegWriteM
CLK
RegWriteW
JalrD JalD
JumpLinkD ExtOpD
JumpLinkE
JumpLinkM
MemtoRegM MemWriteM
JumpLinkW 1
MemtoRegW 0
ResultSelectW1:0
Control Unit
31:26 5:0
ForwardJD
Op Funct
2 1 0 0 1 2 4
ALUOutM PCPlus4M
2 1 0
PCPlus4M
shamtE10:6
PCPlus4W
ReadData1D
10:6
CLK
PC'
EN
CLK A RD
InstrD
CLK
25:21
CLK WE3 RD1 0 1 0 1

PCF
A1
WE
Instruction Memory
20:16
0 1 2
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
25:21 20:16 15:11
ALUOutW
ReadDataW
2 1 0
+
4
15:0
Extender <<2
ExtOpD
EN CLR
PCPlus4F
$sa= 1 1111
PCPlus4D PCBranchD
15:0
<<16
ImmUpperD
BranchTakenD=1
ImmUpperE
ExtImmE
0 1 2
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
PCPlus4E
ResultW
25:0
FlushD=1
ForwardAD
ForwardBD
MemtoRegE
ForwardAE
ForwardBE
BgtzD
StallF
StallD
BeqD
27:0
JumpD
PCJumpD
Hazard Unit
RegWriteE
RegWriteM
BltzD BneD=1
JumpLinkM
RegWriteW
31:28
<<2
FlushE
38
PCSrcD2:0 RegWriteD
CLK
RegWriteE
CLK
RegWriteM
CLK
RegWriteW
JalrD JalD
JumpLinkD ExtOpD
JumpLinkE
JumpLinkM
MemtoRegM MemWriteM
JumpLinkW 1
MemtoRegW 0
ResultSelectW1:0
Control Unit
31:26 5:0
ForwardJD
Op Funct
2 1 0 0 1 2 4
ALUOutM PCPlus4M
2 1 0
PCPlus4M
shamtE10:6
PCPlus4W
ReadData1D
10:6
CLK
PC'
EN
CLK A RD
InstrD
CLK
25:21
CLK WE3 RD1 0 1 0 1

PCF
A1
WE
Instruction Memory
20:16
0 1 2
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
25:21 20:16 15:11
ALUOutW
ReadDataW
2 1 0
+
4
15:0
Extender <<2
ExtOpD
EN CLR
PCPlus4F
$sa= 1 1111
PCPlus4D PCBranchD
15:0
<<16
ImmUpperD
ImmUpperE
ExtImmE
0 1 2
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
PCPlus4E
BranchTakenD
ResultW
25:0
FlushD
ForwardAD
ForwardBD
MemtoRegE
ForwardAE
ForwardBE
BgtzD
StallF=1
StallD=1
BeqD
27:0
JumpD
PCJumpD
Hazard Unit
We have shown the data flow of bne instruction in the datapath. But, we have not given dataflow inside the BranchOperator yet. In the figure below, we can see that when bne fetched, the BneD signal will turn into logic 1 and activate the AND gate as a branch decider.
BeqD BneD=1 BltzD BgtzD
=
RegWriteE
RegWriteM
JumpLinkM
FlushE=1
BltzD BneD=1
RegWriteW
31:28
<<2
39
3. Dataflow of bltz Instruction We will divide the dataflow of instruction bltz into three conditions, such as: No hazard occurred
PCSrcD2:0 RegWriteD
CLK
RegWriteE
CLK
RegWriteM
CLK
RegWriteW
JalrD JalD
JumpLinkD ExtOpD
JumpLinkE
JumpLinkM
MemtoRegM MemWriteM
JumpLinkW 1
MemtoRegW 0
ResultSelectW1:0
Control Unit
31:26 5:0
ForwardJD
Op Funct
2 1 0 0 1 2 4
ALUOutM PCPlus4M
BranchTakenD=1 BgtzD BltzD=1 Branch BneD BeqD Operator
2 1 0
PCPlus4M
shamtE10:6
PCPlus4W
ReadData1D
10:6
CLK
PC'
EN
CLK A RD
InstrD
CLK
25:21
CLK WE3 RD1 0 1 0 1

PCF
A1
WE
Instruction Memory
20:16
0 1 2
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
25:21 20:16 15:11
ALUOutW
ReadDataW
2 1 0
+
4
15:0
Extender <<2
ExtOpD
EN CLR
PCPlus4F
$sa= 1 1111
PCPlus4D PCBranchD
15:0
<<16
ImmUpperD
BranchTakenD=1
ImmUpperE
ExtImmE
0 1 2
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
PCPlus4E
ResultW
25:0
FlushD=1
ForwardAD
ForwardBD
MemtoRegE
ForwardAE
ForwardBE
BltzD=1 BneD
BgtzD
StallF
StallD
BeqD
27:0
JumpD
PCJumpD
Hazard Unit
We can see on the figure above that the dataflow of bltz are marked by the red lines. Handling data hazard using Forwarding When this hazard occurred, ForwardAD will turn into logic 1. Then, ALUOutM will be forwarded as BranchSrcA or an input of BranchOperator.
RegWriteE
RegWriteM
JumpLinkM
RegWriteW
31:28
<<2
FlushE
40
PCSrcD2:0 RegWriteD
CLK
RegWriteE
CLK
RegWriteM
CLK
RegWriteW
JalrD JalD
JumpLinkD ExtOpD
JumpLinkE
JumpLinkM
MemtoRegM MemWriteM
JumpLinkW 1
MemtoRegW 0
ResultSelectW1:0
Control Unit
31:26 5:0
ForwardJD
Op Funct
2 1 0 0 1 2 4
ALUOutM PCPlus4M
2 1 0
PCPlus4M
shamtE10:6
PCPlus4W
ReadData1D
10:6
CLK
PC'
EN
CLK A RD
InstrD
CLK
25:21
CLK WE3 RD1 0 1 0 1

PCF
A1
WE
Instruction Memory
20:16
0 1 2
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
25:21 20:16 15:11
ALUOutW
ReadDataW
2 1 0
+
4
15:0
Extender <<2
ExtOpD
EN CLR
PCPlus4F
$sa= 1 1111
PCPlus4D PCBranchD
15:0
<<16
ImmUpperD
BranchTakenD=1
ImmUpperE
ExtImmE
0 1 2
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
PCPlus4E
ResultW
25:0
FlushD=1
ForwardAD
ForwardBD
MemtoRegE
ForwardAE
ForwardBE
BgtzD
StallF
StallD
BeqD
27:0
JumpD
PCJumpD
Hazard Unit
RegWriteE
RegWriteM
BltzD=1 BneD
JumpLinkM
RegWriteW
31:28
<<2
FlushE
41
PCSrcD2:0 RegWriteD
CLK
RegWriteE
CLK
RegWriteM
CLK
RegWriteW
JalrD JalD
JumpLinkD ExtOpD
JumpLinkE
JumpLinkM
MemtoRegM MemWriteM
JumpLinkW 1
MemtoRegW 0
ResultSelectW1:0
Control Unit
31:26 5:0
ForwardJD
Op Funct
2 1 0 0 1 2 4
ALUOutM PCPlus4M
2 1 0
PCPlus4M
shamtE10:6
PCPlus4W
ReadData1D
10:6
CLK
PC'
EN
CLK A RD
InstrD
CLK
25:21
CLK WE3 RD1 0 1 0 1

PCF
A1
WE
Instruction Memory
20:16
0 1 2
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
25:21 20:16 15:11
ALUOutW
ReadDataW
2 1 0
+
4
15:0
Extender <<2
ExtOpD
EN CLR
PCPlus4F
$sa= 1 1111
PCPlus4D PCBranchD
15:0
<<16
ImmUpperD
ImmUpperE
ExtImmE
0 1 2
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
PCPlus4E
BranchTakenD
ResultW
25:0
FlushD
ForwardAD
ForwardBD
MemtoRegE
ForwardAE
ForwardBE
BgtzD
StallF=1
StallD=1
BeqD
27:0
JumpD
PCJumpD
Hazard Unit
We have shown the data flow of bltz instruction in the datapath. But, we have not given dataflow inside the BranchOperator yet. In the figure below, we can see that when bltz fetched, the BltzD signal will turn into logic 1 and activate the AND gate as a branch decider.
BeqD BneD BltzD=1 BgtzD
=
RegWriteE
RegWriteM
BltzD=1 BneD
JumpLinkM
FlushE=1
RegWriteW
31:28
<<2
42
4. Dataflow of blez Instruction We will divide the dataflow of instruction blez into three conditions, such as: No hazard occurred
PCSrcD2:0 RegWriteD
CLK
RegWriteE
CLK
RegWriteM
CLK
RegWriteW
JalrD JalD
JumpLinkD ExtOpD
JumpLinkE
JumpLinkM
MemtoRegM MemWriteM
JumpLinkW 1
MemtoRegW 0
ResultSelectW1:0
Control Unit
31:26 5:0
ForwardJD
Op Funct
2 1 0 0 1 2 4
ALUOutM PCPlus4M
BranchTakenD=1 BgtzD BltzD=1 Branch BneD BeqD=1 Operator
2 1 0
PCPlus4M
shamtE10:6
PCPlus4W
ReadData1D
10:6
CLK
PC'
EN
CLK A RD
InstrD
CLK
25:21
CLK WE3 RD1 0 1 0 1

PCF
A1
WE
Instruction Memory
20:16
0 1 2
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
25:21 20:16 15:11
ALUOutW
ReadDataW
2 1 0
+
4
15:0
Extender <<2
ExtOpD
EN CLR
PCPlus4F
$sa= 1 1111
PCPlus4D PCBranchD
15:0
<<16
ImmUpperD
BranchTakenD=1
ImmUpperE
ExtImmE
0 1 2
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
PCPlus4E
ResultW
25:0
FlushD=1
ForwardAD
ForwardBD
MemtoRegE
ForwardAE
ForwardBE
BeqD=1
BltzD=1 BneD
StallF
StallD
BgtzD
27:0
JumpD
PCJumpD
Hazard Unit
We can see on the figure above that the dataflow of blez are marked by the red lines. Handling data hazard using Forwarding When this hazard occurred, ForwardAD will turn into logic 1. Then, ALUOutM will be forwarded as BranchSrcA or an input of BranchOperator.
RegWriteE
RegWriteM
JumpLinkM
RegWriteW
31:28
<<2
FlushE
43
PCSrcD2:0 RegWriteD
CLK
RegWriteE
CLK
RegWriteM
CLK
RegWriteW
JalrD JalD
JumpLinkD ExtOpD
JumpLinkE
JumpLinkM
MemtoRegM MemWriteM
JumpLinkW 1
MemtoRegW 0
ResultSelectW1:0
Control Unit
31:26 5:0
ForwardJD
Op Funct
2 1 0 0 1 2 4
ALUOutM PCPlus4M
2 1 0
PCPlus4M
shamtE10:6
PCPlus4W
ReadData1D
10:6
CLK
PC'
EN
CLK A RD
InstrD
CLK
25:21
CLK WE3 RD1 0 1 0 1

PCF
A1
WE
Instruction Memory
20:16
0 1 2
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
25:21 20:16 15:11
ALUOutW
ReadDataW
2 1 0
+
4
15:0
Extender <<2
ExtOpD
EN CLR
PCPlus4F
$sa= 1 1111
PCPlus4D PCBranchD
15:0
<<16
ImmUpperD
BranchTakenD=1
ImmUpperE
ExtImmE
0 1 2
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
PCPlus4E
ResultW
25:0
FlushD=1
ForwardAD
ForwardBD
MemtoRegE
ForwardAE
ForwardBE
BeqD=1
StallF
StallD
BgtzD
27:0
JumpD
PCJumpD
Hazard Unit
RegWriteE
RegWriteM
BltzD=1 BneD
JumpLinkM
RegWriteW
31:28
<<2
FlushE
44
PCSrcD2:0 RegWriteD
CLK
RegWriteE
CLK
RegWriteM
CLK
RegWriteW
JalrD JalD
JumpLinkD ExtOpD
JumpLinkE
JumpLinkM
MemtoRegM MemWriteM
JumpLinkW 1
MemtoRegW 0
ResultSelectW1:0
Control Unit
31:26 5:0
ForwardJD
Op Funct
2 1 0 0 1 2 4
ALUOutM PCPlus4M
2 1 0
PCPlus4M
shamtE10:6
PCPlus4W
ReadData1D
10:6
CLK
PC'
EN
CLK A RD
InstrD
CLK
25:21
CLK WE3 RD1 0 1 0 1

PCF
A1
WE
Instruction Memory
20:16
0 1 2
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
25:21 20:16 15:11
ALUOutW
ReadDataW
2 1 0
+
4
15:0
Extender <<2
ExtOpD
EN CLR
PCPlus4F
$sa= 1 1111
PCPlus4D PCBranchD
15:0
<<16
ImmUpperD
ImmUpperE
ExtImmE
0 1 2
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
PCPlus4E
BranchTakenD
ResultW
25:0
FlushD
ForwardAD
ForwardBD
MemtoRegE
ForwardAE
ForwardBE
BeqD=1
StallF=1
StallD=1
BgtzD
27:0
JumpD
PCJumpD
Hazard Unit
We have shown the data flow of blez instruction in the datapath. But, we have not given dataflow inside the BranchOperator yet. In the figure below, we can see that when blez fetched, the BlteD signal will turn into logic 1 and activate the AND gate as a branch decider.
BeqD=1 BneD BltzD=1 BgtzD
=
RegWriteE
RegWriteM
BltzD=1 BneD
JumpLinkM
FlushE=1
RegWriteW
31:28
<<2
45
5. Dataflow of bgtz Instruction We will divide the dataflow of instruction bgtz into three conditions, such as: No hazard occurred
PCSrcD2:0 RegWriteD
CLK
RegWriteE
CLK
RegWriteM
CLK
RegWriteW
JalrD JalD
JumpLinkD ExtOpD
JumpLinkE
JumpLinkM
MemtoRegM MemWriteM
JumpLinkW 1
MemtoRegW 0
ResultSelectW1:0
Control Unit
31:26 5:0
ForwardJD
Op Funct
2 1 0 0 1 2 4
ALUOutM PCPlus4M
BranchTakenD=1 BgtzD=1 BltzD Branch BneD BeqD Operator
2 1 0
PCPlus4M
shamtE10:6
PCPlus4W
ReadData1D
10:6
CLK
PC'
EN
CLK A RD
InstrD
CLK
25:21
CLK WE3 RD1 0 1 0 1

PCF
A1
WE
Instruction Memory
20:16
0 1 2
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
25:21 20:16 15:11
ALUOutW
ReadDataW
2 1 0
+
4
15:0
Extender <<2
ExtOpD
EN CLR
PCPlus4F
$sa= 1 1111
PCPlus4D PCBranchD
15:0
<<16
ImmUpperD
BranchTakenD=1
ImmUpperE
ExtImmE
0 1 2
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
PCPlus4E
ResultW
25:0
FlushD=1
ForwardAD
ForwardBD
MemtoRegE
ForwardAE
ForwardBE
BltzD BneD
StallF
StallD
BeqD
27:0
JumpD
PCJumpD
Hazard Unit
We can see on the figure above that the dataflow of bgtz are marked by the red lines. Handling data hazard using Forwarding When this hazard occurred, ForwardAD will turn into logic 1. Then, ALUOutM will be forwarded as BranchSrcA or an input of BranchOperator.
RegWriteE
BgtzD=1
RegWriteM
JumpLinkM
RegWriteW
31:28
<<2
FlushE
46
PCSrcD2:0 RegWriteD
CLK
RegWriteE
CLK
RegWriteM
CLK
RegWriteW
JalrD JalD
JumpLinkD ExtOpD
JumpLinkE
JumpLinkM
MemtoRegM MemWriteM
JumpLinkW 1
MemtoRegW 0
ResultSelectW1:0
Control Unit
31:26 5:0
ForwardJD
Op Funct
2 1 0 0 1 2 4
ALUOutM PCPlus4M
2 1 0
PCPlus4M
shamtE10:6
PCPlus4W
ReadData1D
10:6
CLK
PC'
EN
CLK A RD
InstrD
CLK
25:21
CLK WE3 RD1 0 1 0 1

PCF
A1
WE
Instruction Memory
20:16
0 1 2
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
25:21 20:16 15:11
ALUOutW
ReadDataW
2 1 0
+
4
15:0
Extender <<2
ExtOpD
EN CLR
PCPlus4F
$sa= 1 1111
PCPlus4D PCBranchD
15:0
<<16
ImmUpperD
BranchTakenD=1
ImmUpperE
ExtImmE
0 1 2
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
PCPlus4E
ResultW
25:0
FlushD=1
ForwardAD
ForwardBD
MemtoRegE
ForwardAE
ForwardBE
BltzD BneD
StallF
StallD
BeqD
27:0
JumpD
PCJumpD
Hazard Unit
RegWriteE
BgtzD=1
RegWriteM
JumpLinkM
RegWriteW
31:28
<<2
FlushE
47
PCSrcD2:0 RegWriteD
CLK
RegWriteE
CLK
RegWriteM
CLK
RegWriteW
JalrD JalD
JumpLinkD ExtOpD
JumpLinkE
JumpLinkM
MemtoRegM MemWriteM
JumpLinkW 1
MemtoRegW 0
ResultSelectW1:0
Control Unit
31:26 5:0
ForwardJD
Op Funct
2 1 0 0 1 2 4
ALUOutM PCPlus4M
2 1 0
PCPlus4M
shamtE10:6
PCPlus4W
ReadData1D
10:6
CLK
PC'
EN
CLK A RD
InstrD
CLK
25:21
CLK WE3 RD1 0 1 0 1

PCF
A1
WE
Instruction Memory
20:16
0 1 2
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
25:21 20:16 15:11
ALUOutW
ReadDataW
2 1 0
+
4
15:0
Extender <<2
ExtOpD
EN CLR
PCPlus4F
$sa= 1 1111
PCPlus4D PCBranchD
15:0
<<16
ImmUpperD
ImmUpperE
ExtImmE
0 1 2
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
PCPlus4E
BranchTakenD
ResultW
25:0
FlushD
ForwardAD
ForwardBD
MemtoRegE
ForwardAE
ForwardBE
BltzD BneD
StallF=1
StallD=1
BeqD
27:0
JumpD
PCJumpD
Hazard Unit
We have shown the data flow of bgtz instruction in the datapath. But, we have not given dataflow inside the BranchOperator yet. In the figure below, we can see that when bgtz fetched, the BgtzD signal will turn into logic 1 and activate the AND gate as a branch decider.
BeqD BneD BltzD BltzD=1
=
RegWriteE
BgtzD=1
RegWriteM
JumpLinkM
FlushE=1
RegWriteW
31:28
<<2
48
6. Dataflow of j Instruction
FlushE and FlushD will be activated by using this hazard logic below:
--FlushD logic FlushD <= JumpD OR JrD OR BranchTakenD; --FlushE logic FlushE=lwstall OR branchstall OR jrstall OR((JumpD OR JrD) AND NOT JumpLinkD)
49
7. Dataflow of jal Instruction
FlushD will be activated, but FlushE will not be activated because of this hazard logic below:
Therefore, jal still can use the WB stage to writing PCPlus4 value into register $ra.
50
8. Dataflow of jr Instruction There are some conditions of jr instruction dataflow: Without hazard
PCSrcD2:0 RegWriteD
CLK
RegWriteE
CLK
RegWriteM
CLK
RegWriteW
JalrD=0 JalD=0
JumpLinkD=0 ExtOpD
JumpLinkE
JumpLinkM
MemtoRegM MemWriteM
JumpLinkW 1
MemtoRegW 0
ResultSelectW1:0
Control Unit
31:26 5:0
ForwardJD1:0=00
Op Funct
2 1 0 0 1 2 4
ALUOutM PCPlus4M
BranchTakenD=0 BgtzD=0 BltzD=0 Branch BneD=0 BeqD=0 Operator
2 1 0
PCPlus4M
shamtE10:6
PCPlus4W
RD1D
10:6
CLK
PC'
EN
CLK A RD
InstrD
CLK
25:21
CLK WE3 RD1 0 1 0 1

RsD RtD RdD ImmExtD RsE RtE RdE 00 01 10 00 01 10 SrcAE ALUOutM
PCF
A1
WE
Instruction Memory
20:16
0 1 2
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
25:21 20:16 15:11
ALUOutW
ReadDataW
2 1 0
+
4
15:0
Extender <<2
ExtOpD
EN CLR
PCPlus4F
$sa= 1 1111
PCPlus4D PCBranchD
15:0
<<16
ImmUpperD
BranchTakenD
ImmUpperE
ImmExtE
0 1 2
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
PCPlus4E
ResultW
25:0
FlushD
ForwardAD
ForwardBD
MemtoRegE
ForwardAE
ForwardBE
BgtzD
BltzD BneD
StallF
StallD
BeqD
27:0
JumpD
PCJumpD
Hazard Unit
FlushD and FlushE will be activated by using this hazard logic below:
Forwarding PCPlus4M
jal label
IM
Reg
ALU
DM
Reg
add $s0, $s1, $s2
IM
Reg
ALU
DM
Reg
label: jr $ra
IM
Reg
ALU
DM
Reg
sub $s2, $s2, $t0
IM
Reg
ALU
DM
Reg
add $s0, $s1, $s2
IM
Reg
ALU
DM
Reg
RegWriteE
RegWriteM
JumpLinkM
RegWriteW
31:28
<<2
FlushE
51
Then, we by using this hazard logic:

--ForwardJD logic
IF (JumpLinkM==1 AND JrD==1) THEN ForwardJD = 01
we can handle the hazard. The data flow of instruction is shown below:
PCSrcD2:0 RegWriteD
CLK
RegWriteE
CLK
RegWriteM
CLK
RegWriteW
JalrD JalD
JumpLinkD ExtOpD
JumpLinkE
JumpLinkM
MemtoRegM MemWriteM
JumpLinkW 1
MemtoRegW 0
ResultSelectW1:0
Control Unit
31:26 5:0
ForwardJD1:0=01
Op Funct
2 1 0 0 1 2 4
ALUOutM PCPlus4M
2 1 0
PCPlus4M
shamtE10:6
PCPlus4W
RD1D
10:6
CLK
PC'
EN
CLK A RD
InstrD
CLK
25:21
CLK WE3 RD1 0 1 0 1

PCF
A1
WE
Instruction Memory
20:16
0 1 2
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
25:21 20:16 15:11
ALUOutW
ReadDataW
2 1 0
+
4
15:0
Extender <<2
ExtOpD
EN CLR
PCPlus4F
$sa= 1 1111
PCPlus4D PCBranchD
15:0
<<16
ImmUpperD
BranchTakenD
ImmUpperE
ImmExtE
0 1 2
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
PCPlus4E
ResultW
25:0
FlushD
ForwardAD
ForwardBD
MemtoRegE
ForwardAE
ForwardBE
BgtzD
BltzD BneD
StallF
StallD
BeqD
27:0
JumpD
PCJumpD
Hazard Unit
Forwarding ALUOutM
add $s3, $s1, $t0
IM
Reg
ALU
DM
Reg
add $s0, $s1, $s2
IM
Reg
ALU
DM
Reg
jr $s3
IM
Reg
ALU
DM
Reg

ELSE IF ((rsD!=0) AND (rsD==WriteRegM) AND RegWriteM) THEN ForwardJD = 10
RegWriteE
RegWriteM
JumpLinkM
RegWriteW
31:28
<<2
FlushE
52
PCSrcD2:0 RegWriteD
CLK
RegWriteE
CLK
RegWriteM
CLK
RegWriteW
JalrD JalD
JumpLinkD ExtOpD
JumpLinkE
JumpLinkM
MemtoRegM MemWriteM
JumpLinkW 1
MemtoRegW 0
ResultSelectW1:0
Control Unit
31:26 5:0
ForwardJD1:0=10
Op Funct
2 1 0 0 1 2 4
ALUOutM PCPlus4M
2 1 0
PCPlus4M
shamtE10:6
PCPlus4W
RD1D
10:6
CLK
PC'
EN
CLK A RD
InstrD
CLK
25:21
CLK WE3 RD1 0 1 0 1

RsD RtD RdD ImmExtD RsE RtE RdE
ImmExtE
PCF
A1
00 01 10 00 01 10
SrcAE ALUOutM
WE
Instruction Memory
20:16
0 1 2
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
25:21 20:16 15:11
ALUOutW
ReadDataW
2 1 0
+
4
0 1 2
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
15:0
Extender <<2
ExtOpD
EN CLR
PCPlus4F
$sa= 1 1111
ImmUpperE
PCPlus4D PCBranchD
15:0
<<16
ImmUpperD
PCPlus4E
BranchTakenD
ResultW
25:0
31:28
FlushD
ForwardAD
ForwardBD
MemtoRegE
ForwardAE
ForwardBE
BgtzD
BltzD BneD
StallF
StallD
BeqD
27:0
JumpD
PCJumpD
Hazard Unit
Stalling by jrstall Stalling is needed when one of these two cases occurred:
add $s3, $s1, $t0
IM
Reg
ALU
DM
Reg
add $s0, $s1, $s2
IM
Reg
ALU
DM
Reg
jr $s0
IM
Reg
ALU
DM
Reg
jr $s0
IM
Reg
ALU
DM
Reg
or
RegWriteE
RegWriteM
JumpLinkM
RegWriteW
<<2
FlushE
53
lw $s0, $s3, 8
IM
Reg
ALU
DM
Reg
add $s0, $s1, $s2
IM
Reg
ALU
DM
Reg
jr $s0
IM
Reg
ALU
DM
Reg
jr $s0
IM
Reg
ALU
DM
Reg

jrstall = (JrD AND RegWriteE AND WriteRegE == rsD) OR (JrD AND MemtoRegM AND WriteRegM == rsD) --stall logic StallF = StallD = lwstall OR branchstall OR jrstall --FlushE logic FlushE=lwstall OR branchstall OR jrstall OR((JumpD OR JrD) AND NOT JumpLinkD)
we can handle the hazard. Thus, the instruction will be stalled by activating StallF, StallD, and FlushE.
54
9. Dataflow of jalr Instruction There are some conditions of jr instruction dataflow: Without hazard
PCSrcD2:0 RegWriteD
CLK
RegWriteE
CLK
RegWriteM
CLK
RegWriteW
JalrD=1 JalD
JumpLinkD=1 ExtOpD
JumpLinkE=1
JumpLinkM=1
MemtoRegM MemWriteM
JumpLinkW=1 1
MemtoRegW 0
ResultSelectW1:0
Control Unit
31:26 5:0
ForwardJD1:0=00
Op Funct
2 1 0 0 1 2 4
ALUOutM PCPlus4M
2 1 0
PCPlus4M
shamtE10:6
PCPlus4W
RD1D
10:6
CLK
PC'
EN
CLK A RD
InstrD
CLK
25:21
CLK WE3 RD1 0 1 0 1

PCF
A1
WE
Instruction Memory
20:16
0 1 2
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
25:21 20:16 15:11
ALUOutW
ReadDataW
2 1 0
+
4
15:0
Extender <<2
ExtOpD
EN CLR
PCPlus4F
$sa= 1 1111
PCPlus4D PCBranchD
15:0
<<16
ImmUpperD
BranchTakenD
ImmUpperE
ImmExtE
0 1 2
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
PCPlus4E
ResultW
25:0
FlushD=1
ForwardAD
ForwardBD
MemtoRegE
ForwardAE
ForwardBE
BgtzD
BltzD BneD
StallF
StallD
BeqD
27:0
JumpD
PCJumpD
Hazard Unit
FlushD and FlushE will be activated by using this hazard logic below:
Forwarding PCPlus4M
jal label
IM
Reg
ALU
DM
Reg
add $s0, $s1, $s2
IM
Reg
ALU
DM
Reg
label: jalr $ra
IM
Reg
ALU
DM
Reg
sub $s2, $s2, $t0
IM
Reg
ALU
DM
Reg
add $s0, $s1, $s2
IM
Reg
ALU
DM
Reg
RegWriteE
RegWriteM
JumpLinkM
RegWriteW
31:28
FlushE=0
<<2
55

--ForwardJD logic
IF (JumpLinkM==1 AND JrD==1) THEN ForwardJD = 01
PCSrcD2:0 RegWriteD
CLK
RegWriteE
CLK
RegWriteM
CLK
RegWriteW
JalrD=1 JalD
JumpLinkD=1 ExtOpD
JumpLinkE=1
JumpLinkM=1
MemtoRegM MemWriteM
JumpLinkW=1 1
MemtoRegW 0
ResultSelectW1:0
Control Unit
31:26 5:0
ForwardJD1:0=00
Op Funct
2 1 0 0 1 2 4
ALUOutM PCPlus4M
2 1 0
PCPlus4M
shamtE10:6
PCPlus4W
RD1D
10:6
CLK
PC'
EN
CLK A RD
InstrD
CLK
25:21
CLK WE3 RD1 0 1 0 1

PCF
A1
WE
Instruction Memory
20:16
0 1 2
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
25:21 20:16 15:11
ALUOutW
ReadDataW
2 1 0
+
4
15:0
Extender <<2
ExtOpD
EN CLR
PCPlus4F
$sa= 1 1111
PCPlus4D PCBranchD
15:0
<<16
ImmUpperD
BranchTakenD
ImmUpperE
ImmExtE
0 1 2
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
PCPlus4E
ResultW
25:0
FlushD=1
ForwardAD
ForwardBD
MemtoRegE
ForwardAE
ForwardBE
BgtzD
BltzD BneD
StallF
StallD
BeqD
27:0
JumpD
PCJumpD
Hazard Unit
Forwarding ALUOutM
add $s3, $s1, $t0
IM
Reg
ALU
DM
Reg
add $s0, $s1, $s2
IM
Reg
ALU
DM
Reg
jalr $s3
IM
Reg
ALU
DM
Reg

ELSE IF ((rsD!=0) AND (rsD==WriteRegM) AND RegWriteM) THEN ForwardJD = 10
RegWriteE
RegWriteM
JumpLinkM
RegWriteW
31:28
FlushE=0
<<2
56
PCSrcD2:0 RegWriteD
CLK
RegWriteE
CLK
RegWriteM
CLK
RegWriteW
JalrD=1 JalD
JumpLinkD=1 ExtOpD
JumpLinkE=1
JumpLinkM=1
MemtoRegM MemWriteM
JumpLinkW=1 1
MemtoRegW 0
ResultSelectW1:0
Control Unit
31:26 5:0
ForwardJD1:0=00
Op Funct
2 1 0 0 1 2 4
ALUOutM PCPlus4M
2 1 0
PCPlus4M
shamtE10:6
PCPlus4W
RD1D
10:6
CLK
PC'
EN
CLK A RD
InstrD
CLK
25:21
CLK WE3 RD1 0 1 0 1

RsD RtD RdD ImmExtD RsE RtE RdE
ImmExtE
PCF
A1
00 01 10 00 01 10
SrcAE ALUOutM
WE
Instruction Memory
20:16
0 1 2
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
25:21 20:16 15:11
ALUOutW
ReadDataW
2 1 0
+
4
0 1 2
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
15:0
Extender <<2
ExtOpD
EN CLR
PCPlus4F
$sa= 1 1111
ImmUpperE
PCPlus4D PCBranchD
15:0
<<16
ImmUpperD
PCPlus4E
BranchTakenD
ResultW
25:0
31:28
FlushD=1
ForwardAD
ForwardBD
MemtoRegE
ForwardAE
ForwardBE
BgtzD
BltzD BneD
StallF
StallD
BeqD
27:0
JumpD
PCJumpD
Hazard Unit
Stalling by jrstall Stalling is needed when one of these two cases occurred:
add $s3, $s1, $t0
IM
Reg
ALU
DM
Reg
add $s0, $s1, $s2
IM
Reg
ALU
DM
Reg
jalr $s0
IM
Reg
ALU
DM
Reg
jr $s0
IM
Reg
ALU
DM
Reg
or
RegWriteE
RegWriteM
JumpLinkM
RegWriteW
FlushE=0
<<2
57
lw $s0, $s3, 8
IM
Reg
ALU
DM
Reg
add $s0, $s1, $s2
IM
Reg
ALU
DM
Reg
jalr $s0
IM
Reg
ALU
DM
Reg
jr $s0
IM
Reg
ALU
DM
Reg

jrstall = (JrD AND RegWriteE AND WriteRegE == rsD) OR (JrD AND MemtoRegM AND WriteRegM == rsD) --stall logic StallF = StallD = lwstall OR branchstall OR jrstall --FlushE logic FlushE=lwstall OR branchstall OR jrstall OR((JumpD OR JrD) AND NOT JumpLinkD)
we can handle the hazard. Thus, the instruction will be stalled by activating StallF, StallD, and FlushE.
58
C. Handling Hazard
From designing process and explanation before, we will review for each of hazard logic signals:
RegWriteE RegWriteM RegWriteW MemtoRegE BeqD BneD BltzD BgtzD JrD JumpLinkD JumpLinkM JumpD rsD4:0 rtD4:0 rsE4:0 rtE4:0 WriteRegE4:0 WriteRegM4:0 WriteRegW4:0
Hazard Unit
StallF StallD FlushE ForwardAD ForwardBD ForwardJD1:0 ForwardAE1:0 ForwardBE1:0
1. ForwardAE and ForwardBE These hazard unit output signal are used when cases below occurred:
1 2 3 4 5 6 7 8
Time (cycles)
add $s0, $s2, $s3 and $t0, $s0, $s1 or $t1, $s4, $s0
IM
add
$s2 RF $s3
+
DM
$s0
RF
IM
and
$s0 RF $s1
&
DM
$t0
RF
IM
or
$s4 RF $s0
DM
$t1
RF
sub $t2, $s0, $s5
IM
sub
$s0 RF $s5
DM
$t2
RF
As we can see beq instruction need a data from register $t1 that not has been updated yet on the ID phase of beq. Then, data from ALUOutM is forwarded to the ID stage. Modification of datapath is shown below:
Then, we set the hazard logic:

--ForwardAE logic
59
IF ((rsE != 0) AND (rsE == WriteRegM) AND RegWriteM) THEN ForwardAE = 10 ELSIF ((rsE != 0) AND (rsE == WriteRegW) AND RegWriteW) THEN ForwardAE = 01 ELSE ForwardAE = 00; --ForwardBE logic IF ((rtE != 0) AND (rtE == WriteRegM) AND RegWriteM) THEN ForwardBE = 10 ELSIF ((rtE != 0) AND (rtE == WriteRegW) AND RegWriteW) THEN ForwardBE = 01 ELSE ForwardBE = 00;
2. ForwardAD and Forward BD These hazard unit output signals are used when cases below occurred:
slti $t1, $s0, $t0
IM
Reg
ALU
DM
Reg
addi $s1, $s1, $s0
IM
Reg
ALU
DM
Reg
beq $t1, $0, done
IM
Reg
ALU
DM
Reg
As we can see beq instruction need a data from register $t1 that not has been updated yet on the ID phase of beq. Then, data from ALUOutM is forwarded to the ID stage. Modification of datapath is shown below:
Then, we set the hazard logic:

--ForwardAD logic ForwardAD <= (rsD !=0) AND (rsD == WriteRegM) AND RegWriteM; --ForwardBD logic ForwardBD <= (rtD !=0) AND (rtD == WriteRegM) AND RegWriteM;
60
3. Forward JD There are 2 conditions that cause hazard handling by using ForwardJD: Jr or Jalr instruction need a data that has not beed updated yet by jal or jalr instruction
jal label
IM
Reg
ALU
DM
Reg
add $s0, $s1, $s2
IM
Reg
ALU
DM
Reg
label: jr $ra
IM
Reg
ALU
DM
Reg
sub $s2, $s2, $t0
IM
Reg
ALU
DM
Reg
add $s0, $s1, $s2
IM
Reg
ALU
DM
Reg
Jr or Jalr instruction need a data that has not beed updated yet by register writing instruction
add $s3, $s1, $t0
IM
Reg
ALU
DM
Reg
add $s0, $s1, $s2
IM
Reg
ALU
DM
Reg
jr $s3
IM
Reg
ALU
DM
Reg
Modfication of datapath is shown below:
61
Then, we set he hazard logic:

--ForwardJD logic IF (JumpLinkM==1 AND JrD==1) THEN ForwardJD = 01 ELSIF ((rsD!=0) AND (rsD==WriteRegM) AND RegWriteM) THEN ForwardJD = 10 ELSE ForwardJD = 00;
4. lwstall This stalling is used when this case below occurred

1 2
$0 RF 40
+
9
Time (cycles)
lw $s0, 40($0)
IM
lw
DM
$s0
RF
and $t0, $s0, $s1 or $t1, $s4, $s0
IM
and
$s0 RF $s1 RF
$s0 $s1
&
DM
$t0
RF
IM
or
IM
or
$s4 RF $s0
|
DM
$t1
RF
Stall sub $t2, $s0, $s5

IM sub RF
$s0 $s5
-
DM
$t2
RF
As we can see the sub instruction need a data that has not been updated yet by lw instruction. Therefore, we have to stall the instruction until the data is ready on the next phase (1 cycle stalling). Then, we set the hazard logic:
--signal lwstall logic lwstall <= ((rsD == rtE) OR (rtD == rtE)) AND MemtoRegE;
5. branchstall There are two conditions that cause haard handling by using branchstall logic Due to register writing instruction (1 cycle difference)
slti $t1, $s0, $t0
IM
Reg
ALU
DM
Reg
beq $t1, $0, done
IM
Reg
ALU
DM
Reg
IM
Reg
ALU
DM
Reg
Due to lw instruction
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lw $t1, 4($s0)
IM
Reg
ALU
DM
Reg
addi $s1, $s1, $s0
IM
Reg
ALU
DM
Reg
beq $t1, $0, done
IM
Reg
ALU
DM
Reg
beq $t1, $0, done
IM
Reg
ALU
DM
Reg
As we can see from two cases above that beq will be stalled until the data is ready from previous instruction. Then, we set the hazard logic:
--signal branchstall logic BranchD <= BeqD OR BneD OR BltzD OR BgtzD; branchstall <= BranchD AND RegWriteE AND (WriteRegE == rsD OR WriteRegE == rtD) OR BranchD AND MemtoRegM AND (WriteRegM == rsD OR WriteRegM == rtD);
6. jrstall There are two conditions that cause haard handling by using branchstall logic Data Hazard Caused by register writing instruction (jrstall)
add $s3, $s1, $t0
IM
Reg
ALU
DM
Reg
add $s0, $s1, $s2
IM
Reg
ALU
DM
Reg
jr $s0
IM
Reg
ALU
DM
Reg
jr $s0
IM
Reg
ALU
DM
Reg
Data Hazard Caused by lw (jrstall)
63
lw $s0, $s3, 8
IM
Reg
ALU
DM
Reg
add $s0, $s1, $s2
IM
Reg
ALU
DM
Reg
jr $s0
IM
Reg
ALU
DM
Reg
jr $s0
IM
Reg
ALU
DM
Reg
As we can see that data in register $s0 is not updated yet in the ID phase of jr instruction. Then, we set the hazard logic:
--signal jrstall logic jrstall <= (JrD AND RegWriteE AND WriteRegE == rsD) OR (JrD AND MemtoRegM AND WriteRegM == rsD) ;
7. Flushing ID stage We need to flush ID stage when program is branched by branches or jumps instructions. This is an example of j instruction flushing the instruction after it.
Therefore, the program will be jumped into the target address (PCBranchD, PCJumpD, or PCJrD) and the next instruction (PCPlus4 instruction) will be flushed.
--FlushD logic FlushD <= JumpD OR JrD OR BranchTakenD;
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8. Flushing EX stage EX stage will be flushed when the program is branched by j and jr instruction. Therefore, we need to add a NOT JumpLinkD logic because jal and jalr still need the WB stage to writing data into the register.
--FlushE logic FlushE <= lwstall OR branchstall jrstall OR ((JumpD OR JrD) AND NOT JumpLinkD);
9. Hazard Unit VHDL Code By putting all of previous hazard logic together, we can obtain the hazard unit design below:
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY HazardUnit IS PORT( RegWriteE RegWriteM RegWriteW MemtoRegE BeqD BneD BltzD BgtzD BranchTakenD: JumpD JrD JumpLinkD JumpLinkM rsD rtD rsE rtE WriteRegE WriteRegM WriteRegW StallF StallD FlushE ForwardAE ForwardBE ForwardJD ForwardAD : : : : : : : : : : : : : : : : : IN STD_LOGIC_VECTOR(1 DOWNTO 0); IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; : IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; : IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; : : : : IN STD_LOGIC_VECTOR(4 DOWNTO 0); IN STD_LOGIC_VECTOR(4 DOWNTO 0); IN STD_LOGIC_VECTOR(4 DOWNTO 0); IN STD_LOGIC_VECTOR(4 DOWNTO 0);
OUT STD_LOGIC_VECTOR(1 DOWNTO 0); OUT STD_LOGIC_VECTOR(1 DOWNTO 0); OUT STD_LOGIC_VECTOR(1 DOWNTO 0); OUT STD_LOGIC_VECTOR;
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ForwardBD END HazardUnit;
OUT STD_LOGIC_VECTOR);
ARCHITECTURE behaviour OF InstrMemory IS SIGNAL BranchD SIGNAL branchstall SIGNAL lwstall SIGNAL jrstall BEGIN --ForwardAE logic IF ((rsE != 0) AND (rsE == WriteRegM) AND RegWriteM) THEN ForwardAE = 10 ELSIF ((rsE != 0) AND (rsE == WriteRegW) AND RegWriteW) THEN ForwardAE = 01 ELSE ForwardAE = 00; : : : : STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC;
--ForwardBE logic IF ((rtE != 0) AND (rtE == WriteRegM) AND RegWriteM) THEN ForwardBE = 10 ELSIF ((rtE != 0) AND (rtE == WriteRegW) AND RegWriteW) THEN ForwardBE = 01 ELSE ForwardBE = 00;
--ForwardAD logic ForwardAD <= (rsD !=0) AND (rsD == WriteRegM) AND RegWriteM; --ForwardBD logic ForwardBD <= (rtD !=0) AND (rtD == WriteRegM) AND RegWriteM; --ForwardJD logic IF (JumpLinkM==1 AND JrD==1) THEN ForwardJD = 01 ELSIF ((rsD!=0) AND (rsD==WriteRegM) AND RegWriteM) THEN ForwardJD = 10 ELSE ForwardJD = 00; --signal lwstall logic lwstall <= ((rsD == rtE) OR (rtD == rtE)) AND MemtoRegE; --signal branchstall logic BranchD <= BeqD OR BneD OR BltzD OR BgtzD;
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branchstall <=
BranchD AND RegWriteE AND (WriteRegE == rsD OR WriteRegE == rtD) OR BranchD AND MemtoRegM AND (WriteRegM == rsD OR WriteRegM == rtD);
--signal jrstall logic jrstall <= (JrD AND RegWriteE AND WriteRegE == rsD) OR (JrD AND MemtoRegM AND WriteRegM == rsD) ; --stall logic StallF <= StallD = lwstall OR branchstall OR jrstall; --FlushD logic FlushD <= JumpD OR JrD OR BranchTakenD; --FlushE logic FlushE <= lwstall OR jrstall OR branchstall OR ((JumpD OR JrD) AND NOT JumpLinkD); END behaviour;
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D. VHDL Structural Description

LIBRARY IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY PipelinedMIPS IS PORT( Clock Reset --PCF_out --InstrD_out --ALUCtrlD_out --ReadData1D_out --ReadData2D_out --WriteRegD_out --ALUOutE_out --ResultW_out --WriteDataM_out --BeqD_out --BneD_out --BltzD_out --BlezD_out --BgtzD_out --JumpD_out --JalD_out --JrD_out --JalrD_out --RegWriteD_out --MemWriteD_out END SingleCycleMIPS; ARCHITECTURE structural OF PipelinedMIPS IS COMPONENT mux3 GENERIC(WIDTH: INTEGER); PORT( d0,d1,d2 s q END COMPONENT; COMPONENT mux4 GENERIC(WIDTH: INTEGER); PORT( d0,d1,d2,d3 : s q : : IN IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); STD_LOGIC_VECTOR(2 DOWNTO 0); : : : IN IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); STD_LOGIC_VECTOR(1 DOWNTO 0); : : : : IN STD_LOGIC; : IN STD_LOGIC : : : : : : : : : : : : : : : : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); OUT STD_LOGIC_VECTOR(31 DOWNTO 0); OUT STD_LOGIC_VECTOR(4 DOWNTO 0); OUT STD_LOGIC_VECTOR(31 DOWNTO 0); OUT STD_LOGIC_VECTOR(31 DOWNTO 0); OUT STD_LOGIC_VECTOR(4 DOWNTO 0); OUT STD_LOGIC_VECTOR(31 DOWNTO 0); OUT STD_LOGIC_VECTOR(31 DOWNTO 0); OUT STD_LOGIC_VECTOR(31 DOWNTO 0); OUT STD_LOGIC; OUT STD_LOGIC; OUT STD_LOGIC; OUT STD_LOGIC; OUT STD_LOGIC; OUT STD_LOGIC; OUT STD_LOGIC; : OUT STD_LOGIC; OUT STD_LOGIC; OUT STD_LOGIC; OUT STD_LOGIC);
--Output pin for simulation
OUT STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0));
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END COMPONENT; COMPONENT mux2 GENERIC(WIDTH: INTEGER); PORT( d0,d1 : s q : : IN IN STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0); STD_LOGIC_VECTOR;
END COMPONENT; COMPONENT adder PORT( x y z : : : IN STD_LOGIC_VECTOR(31 DOWNTO 0); IN STD_LOGIC_VECTOR(31 DOWNTO 0); OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END COMPONENT; COMPONENT concat16 PORT( d q : : IN STD_LOGIC_VECTOR(15 DOWNTO 0); OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END COMPONENT; COMPONENT concat2 PORT( d q : : IN STD_LOGIC_VECTOR(25 DOWNTO 0); OUT STD_LOGIC_VECTOR(27 DOWNTO 0));
END COMPONENT; COMPONENT shiftby2 PORT( d q : : IN STD_LOGIC_VECTOR(15 DOWNTO 0); OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END COMPONENT; COMPONENT Extender PORT( Op d q : : : IN STD_LOGIC; IN STD_LOGIC_VECTOR(15 DOWNTO 0); OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END COMPONENT; COMPONENT ALU PORT( x y shift : Control z : : : : IN STD_LOGIC_VECTOR(31 DOWNTO 0); IN STD_LOGIC_VECTOR(31 DOWNTO 0); IN STD_LOGIC_VECTOR(4 DOWNTO 0); OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
IN STD_LOGIC_VECTOR(4 DOWNTO 0);
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END COMPONENT; COMPONENT InstrMemory PORT( A RD : : IN STD_LOGIC_VECTOR(31 DOWNTO 0); OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END COMPONENT; COMPONENT RegFile PORT( CLK --RST WE3 A1 A2 A3 WD RD1 RD2 END COMPONENT; COMPONENT DataMemory PORT( CLK --RST WE A WD RD END COMPONENT; COMPONENT ControlUnit IS PORT( Opcode Funct RegDst RegWrite Beq Bne Bltz Bgtz MemtoReg MemWrite ALUCtrl : : : : : : : : : : : IN STD_LOGIC_VECTOR(5 DOWNTO 0); IN STD_LOGIC_VECTOR(5 DOWNTO 0); OUT STD_LOGIC_VECTOR(1 DOWNTO 0); OUT STD_LOGIC; OUT STD_LOGIC; OUT STD_LOGIC; OUT STD_LOGIC; OUT STD_LOGIC; OUT STD_LOGIC; OUT STD_LOGIC; OUT STD_LOGIC_VECTOR (4 DOWNTO 0); : : : : : : IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC_VECTOR(31 DOWNTO 0); IN STD_LOGIC_VECTOR(31 DOWNTO 0); OUT STD_LOGIC_VECTOR(31 DOWNTO 0)); : : : : : : : : : IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC_VECTOR(4 DOWNTO 0); IN STD_LOGIC_VECTOR(4 DOWNTO 0); IN STD_LOGIC_VECTOR(4 DOWNTO 0); IN STD_LOGIC_VECTOR(31 DOWNTO 0); OUT STD_LOGIC_VECTOR(31 DOWNTO 0); OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
70
ALUSrc ExtOp Jump Jal Jr Jalr END COMPONENT;
: : : : : :
OUT STD_LOGIC(1 DOWNTO 0); OUT STD_LOGIC; OUT STD_LOGIC; OUT STD_LOGIC; OUT STD_LOGIC; OUT STD_LOGIC);
COMPONENT HazardUnit IS PORT( RegWriteE RegWriteM RegWriteW MemtoRegE BeqD BneD BltzD BgtzD BranchTakenD: JumpD JrD JumpLinkD JumpLinkM rsD rtD rsE rtE WriteRegE WriteRegM WriteRegW StallF StallD FlushE ForwardAE ForwardBE ForwardJD ForwardAD ForwardBD END COMPONENT; COMPONENT BranchOperator IS : : : : : : : : : : : : : : : : : : IN STD_LOGIC_VECTOR(1 DOWNTO 0); IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; : IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; : IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; : : : : IN STD_LOGIC_VECTOR(4 DOWNTO 0); IN STD_LOGIC_VECTOR(4 DOWNTO 0); IN STD_LOGIC_VECTOR(4 DOWNTO 0); IN STD_LOGIC_VECTOR(4 DOWNTO 0);
OUT STD_LOGIC_VECTOR(1 DOWNTO 0); OUT STD_LOGIC_VECTOR(1 DOWNTO 0); OUT STD_LOGIC_VECTOR(1 DOWNTO 0); OUT STD_LOGIC_VECTOR; OUT STD_LOGIC_VECTOR);
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PORT( BeqD BneD BltzD BgtzD BranchSrcA BranchSrcB BranchD END COMPONENT; COMPONENT flopr IS GENERIC(width: INTEGER) PORT( clk, reset d q END COMPONENT; COMPONENT floprc IS GENERIC(width: INTEGER) PORT( clk, reset clear d q END COMPONENT; COMPONENT flopenrc IS GENERIC(width: INTEGER) PORT( clk, reset enable clear d q END COMPONENT; COMPONENT flopenr IS GENERIC(width: INTEGER) PORT( clk, reset enable d q END COMPONENT; : : : : IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC_VECTOR(width-1 DOWNTO 0); IN STD_LOGIC_VECTOR(width-1 DOWNTO 0)); : : : : : IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC_VECTOR(width-1 DOWNTO 0); IN STD_LOGIC_VECTOR(width-1 DOWNTO 0)); : : : : IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC_VECTOR(width-1 DOWNTO 0); IN STD_LOGIC_VECTOR(width-1 DOWNTO 0)); : : : IN STD_LOGIC; IN STD_LOGIC_VECTOR(width-1 DOWNTO 0); IN STD_LOGIC_VECTOR(width-1 DOWNTO 0)); : : : : : : : IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC_VECTOR(31 DOWNTO 0); IN STD_LOGIC_VECTOR(31 DOWNTO 0); IN STD_LOGIC);
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--stage F SIGNAL PCPlus4F SIGNAL nPC SIGNAL PCF SIGNAL StallF SIGNAL InstrF --stage D SIGNAL InstrD SIGNAL OpCodeD SIGNAL FunctD SIGNAL shamtD SIGNAL ImmD SIGNAL ImmJumpD SIGNAL ReadData1D SIGNAL ReadData2D SIGNAL BranchSrcAD SIGNAL BranchSrcBD SIGNAL rsD SIGNAL rtD SIGNAL rdD SIGNAL ImmExtD SIGNAL BranchLabelD SIGNAL PCPlus4D SIGNAL PCBranchD SIGNAL ImmUpperD SIGNAL PCJumpD SIGNAL RegWriteD SIGNAL RegDstD SIGNAL ALUSrcD SIGNAL ALUCtrlD SIGNAL MemWriteD SIGNAL MemtoRegD SIGNAL ExtOpD SIGNAL BeqD SIGNAL BneD SIGNAL BltzD SIGNAL BgtzD SIGNAL BranchTakenD SIGNAL JumpD SIGNAL JalD : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC_VECTOR(5 DOWNTO 0); STD_LOGIC_VECTOR(5 DOWNTO 0); STD_LOGIC_VECTOR(4 DOWNTO 0); STD_LOGIC_VECTOR(15 DOWNTO 0); STD_LOGIC_VECTOR(25 DOWNTO 0); STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC_VECTOR(4 DOWNTO 0); STD_LOGIC_VECTOR(4 DOWNTO 0); STD_LOGIC_VECTOR(4 DOWNTO 0); STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC; STD_LOGIC_VECTOR(1 DOWNTO 0); STD_LOGIC_VECTOR(1 DOWNTO 0); STD_LOGIC_VECTOR(4 DOWNTO 0); STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; : : : : : STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC; STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL JrD SIGNAL JalrD SIGNAL JumpLinkD SIGNAL PCSrcD SIGNAL PCJrD SIGNAL StallD SIGNAL ForwardJD SIGNAL ForwardAD SIGNAL ForwardBD SIGNAL FlushD --stage E SIGNAL RegWriteE SIGNAL RegDstE SIGNAL ALUSrcE SIGNAL ALUCtrlE SIGNAL MemWriteE SIGNAL MemtoRegE SIGNAL JumpLinkE SIGNAL shamtE SIGNAL ReadData1E SIGNAL ReadData2E SIGNAL rsE SIGNAL rtE SIGNAL rdE SIGNAL ImmExtE SIGNAL ImmUpperE SIGNAL PCPlus4E SIGNAL FlushE SIGNAL ForwardAE SIGNAL ForwardBE SIGNAL SrcAE SIGNAL SrcBE SIGNAL WriteDataE SIGNAL ALUOutE SIGNAL WriteRegE --stage M SIGNAL RegWriteM SIGNAL MemWriteM SIGNAL MemtoRegM SIGNAL JumpLinkM SIGNAL PCPlus4M : : : : : :
: : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :
STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC_VECTOR(2 DOWNTO 0); STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC; STD_LOGIC_VECTOR(1 DOWNTO 0); STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC_VECTOR(1 DOWNTO 0); STD_LOGIC_VECTOR(1 DOWNTO 0); STD_LOGIC_VECTOR(4 DOWNTO 0); STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC_VECTOR(4 DOWNTO 0); STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC_VECTOR(4 DOWNTO 0); STD_LOGIC_VECTOR(4 DOWNTO 0); STD_LOGIC_VECTOR(4 DOWNTO 0); STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC; STD_LOGIC_VECTOR(1 DOWNTO 0); STD_LOGIC_VECTOR(1 DOWNTO 0); STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC_VECTOR(31 DOWNTO 0);
STD_LOGIC_VECTOR(4 DOWNTO 0); STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC_VECTOR(31 DOWNTO 0);
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SIGNAL ALUOutM SIGNAL WriteRegM SIGNAL ReadDataM --stage W SIGNAL RegWriteW SIGNAL MemtoRegW SIGNAL JumpLinkW SIGNAL PCPlus4W SIGNAL ReadDataW SIGNAL ALUOutW SIGNAL WriteRegW SIGNAL ResultW BEGIN
: : : : : : : : : : :
STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC_VECTOR(4 DOWNTO 0); STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC; STD_LOGIC; STD_LOGIC; STD_LOGIC_VECTOR(1 DOWNTO 0); STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC_VECTOR(31 DOWNTO 0); STD_LOGIC_VECTOR(4 DOWNTO 0); STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL WriteDataM :
SIGNAL ResultSelectW:
--Output signal used for simulation if necessary --PC_out --Instr_out --ALUCtrl_out --ReadData1_out --ReadData2_out --WriteReg_out --ALUResult_out --Result_out --WriteData --Beq_out --Bne_out --Bltz_out --Blez_out --Bgtz_out --Zero_out --LTZ_out --J_out --Jal_out --Jr_out --Jalr_out --MemWrite_out --RegWrite_out Get_nPC: mux4 GENERIC MAP(32) <= PC; <= Instr; <= ALUCtrl; <= SrcA; <= RegReadData2; <= WriteReg; <= ALUResult; <= Result; <= WriteData; <= Beq; <= Bne; <= Bltz; <= Blez; <= Bgtz; <= Zero; <= Zero; <= Jump; <= Jal; <= Jr; <= Jalr; <= MemWrite; <= '0' WHEN WriteReg = "00000" ELSE RegWrite;
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PORT MAP(
d0 d1 d2 d3 s q
=> PCPlus4F, => PCBranchD, => PCJrD, => PCJumpD, => PCSrcD, => nPC);
Get_PCJrD mux3 GENERIC MAP(32) PORT MAP( d0 d1 d2 s q regF: flopenr GENERIC MAP(32) PORT MAP( clk reset enable d q Get_PCPlus4F: adder PORT MAP( x y z Get_Instr: InstrMemory A RD regD: flopenrc GENERIC MAP(32) PORT MAP( clk enable clear => d q => Clock, Reset, => => => NOT StallD, InstrF, InstrD); FlushD, reset => => => PCF, Instr); => => => PCF, X"00000004", PCPlus4F); => Clock, => Reset, => NOT StallF, => nPC, => PCF); => ReadData1, => PCPlus4M, => ALUOutM, => ForwardJD, => PCJrD);
PORT MAP(
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OpCodeD FunctD shamtD rsD rtD rdD ImmD <= ImmJumpD<=
<= <= <= <= <= <=
InstrD(31 DOWNTO 26); InstrD(5 DOWNTO 0); InstrD(10 DOWNTO 6); InstrD(25 DOWNTO 21); InstrD(20 DOWNTO 16); InstrD(15 DOWNTO 11);
InstrD(15 DOWNTO 0); InstrD(25 DOWNTO 0); RegFile CLK WE3 A1 A2 A3 WD3 RD1 RD2 => => => => => => => => Clock, Reset, RegWriteW, rsD, rtD, WriteRegW, ResultW, ReadData1D, ReadData2D); --RST =>
RegisterFile: PORT MAP(
GetControlSignal: ControlUnit PORT MAP( Opcode Funct RegDst RegWrite Beq Bne Bltz Bgtz MemtoReg MemWrite ALUCtrl ALUSrc ExtOp J Jal Jr Jalr JumpLinkD <= => OpCodeD, => FunctD, => RegDstD, => RegWriteD, => BeqD, => BneD, => BltzD, => BgtzD, => MemtoRegD, => MemWriteD, => ALUCtrlD, => ALUSrcD, => ExtOpD, => JumpD, => JalD, => JrD, => JalrD);
JalD OR JalrD;
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Get_ImmExtD: PORT MAP(
Extender Op d q => => => ExtOpD, ImmD, ImmExtD);
GetBranchLabelD: shiftby2 PORT MAP( d q GetPCBranchD: adder PORT MAP( x y z GetImmUpperD: concat16 PORT MAP( d q GetJumpLabelD: concat2 PORT MAP( d q PCJumpD <= => => ImmJumpD, JumpLabelD); => => ImmD, ImmUpperD); => => => BranchLabelD, PCPlus4D, PCBranchD); => => ImmExtD, BranchLabelD);
PCPlus4D(31 DOWNTO 28) & JumpLabelD(27 DOWNTO 0);
Get_BranchSrcA: mux2 GENERIC MAP(32) PORT MAP( d0 d1 s q Get_BranchSrcB: mux2 GENERIC MAP(32) PORT MAP( d0 d1 s q BranchDecider: PORT MAP( => ReadData2D, => ALUOutM, => ForwardBD, => BranchSrcB); => ReadData1D, => ALUOutM, => ForwardAD, => BranchSrcA);
BranchOperator Beq BneD => => BeqD, BneD,
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BltzD BgtzD
=> =>
BltzD, BgtzD, BranchSrcAD, BranchSrcBD, BranchD);
BranchSrcAD => BranchSrcBD => BranchTakenD=> reg1E: floprc GENERIC MAP(32) PORT MAP( clk => Clock, Reset, reset => clear => d q reg2E: floprc GENERIC MAP(32) PORT MAP( clk => Clock, Reset, reset => clear => d q reg3E: floprc GENERIC MAP(32) PORT MAP( clk => Clock, Reset, reset => clear => d q reg4E: floprc GENERIC MAP(32) PORT MAP( clk => Clock, Reset, reset => clear => d q reg5E: floprc GENERIC MAP(32) PORT MAP( clk => Clock, => => => => => => => =>
FlushE, ReadData1D, ReadData1E);
FlushE, ReadData2D, ReadData2E);
FlushE, ImmExtD, ImmExtE);
FlushE, ImmUpperD, ImmUpperE);
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reset => clear => d q rD reg6E: <= => =>
Reset, FlushE, PCPlus4D, PCPlus4E);
rsD & rtD & rdD & shamtD; floprc
GENERIC MAP(20) PORT MAP( clk => Clock, Reset, FlushE, rD, rE); reset => clear => d q rsE rtE rdE shamtE CtrlSigD <= <= <= <= <= => =>
rE(19 DOWNTO 15); rE(14 DOWNTO 10); rE(9 DOWNTO 5); rE(4 DOWNTO 0); RegWriteD & JumpLinkD & MemtoRegD & MemWriteD &
ALUCtrlD & ALUSrcD & RegDstD; reg7E: floprc GENERIC MAP(13) PORT MAP( clk => Clock, Reset, FlushE, CtrlSigD, CtrlSigE); reset => clear => d q RegWriteE JumpLinkE MemtoRegE MemWriteE ALUCtrlE ALUSrcE RegDstE GetSrcAE: <= <= <= <= <= <= <= mux3 => =>
CtrlSigE(12); CtrlSigE(11); CtrlSigE(10); CtrlSigE(9); CtrlSigE(8 DOWNTO 4); CtrlSigE(3 DOWNTO 2); CtrlSig(1 DOWNTO 0);
GENERIC MAP(32)
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PORT MAP(
d0 d1 d2 s q
=> => => => =>
ReadData1, ResultW, ALUOutM, ForwardAE, SrcAE);
GetWriteDataE: PORT MAP(
mux3 d0 d1 d2 s q => => => => => ReadData2, ResultW, ALUOutM, ForwardBE, WriteDataE);
GENERIC MAP(32)
GetSrcBE:
mux3 d0 d1 d2 s q => => => => => WriteDataE, ImmExtE, ImmUpperE, ALUSrcE, SrcBE);
GENERIC MAP(32) PORT MAP(
GetWriteRegE: PORT MAP(
mux3 d0 d1 d2 s q => => => => => rtE, rdE, "11111", RegDstE, WriteRegE);
GENERIC MAP(5)
GetALUOutE: ALU PORT MAP( x y shift Control z reg1M: flopr GENERIC MAP(32) PORT MAP( clk => Clock, Reset, reset => => => => => => SrcAE, SrcBE, shamtE, ALUCtrlE, ALUOutE);
81
d q reg2M: flopr GENERIC MAP(32) PORT MAP( clk d q reg3M: flopr GENERIC MAP(32) PORT MAP( clk d q reg4M: flopr GENERIC MAP(5) PORT MAP( clk d q reg5M: flopr GENERIC MAP(4) PORT MAP( clk d q RegWriteM JumpLinkM MemtoRegM MemWriteM <= <= <= <=
=> =>
ALUOutE, ALUOutM);
=> => =>
Clock, Reset, WriteDataE, WriteDataM);
reset =>
=> => =>
Clock, Reset, PCPlus4E, PCPlus4M);
reset =>
=> => =>
Clock, Reset, WriteRegE, WriteRegM);
reset =>
=> => =>
Clock, Reset, CtrlSigE(12 DOWNTO 9), CtrlSigM);
reset =>
CtrlSigM(3); CtrlSigM(2); CtrlSigM(1); CtrlSigM(0);
DataMem: DataMemory PORT MAP( CLK WE A => => => Clock, Reset, MemWriteM, ALUOutM, --RST =>
82
WD RD reg1W: flopr GENERIC MAP(32) PORT MAP( clk d q reg2W: flopr GENERIC MAP(32) PORT MAP( clk d q reg3W: flopr GENERIC MAP(32) PORT MAP( clk d q reg4W: flopr GENERIC MAP(5) PORT MAP( clk d q reg5W: flopr GENERIC MAP(3) PORT MAP( clk d q RegWriteW JumpLinkW MemtoRegW <= <= <=
=> =>
WriteDataM, ReadDataM);
=> => =>
Clock, Reset, ReadDataM, ReadDataW);
reset =>
=> => =>
Clock, Reset, ALUOutM, ALUOutW);
reset =>
=> => =>
Clock, Reset, PCPlus4M, PCPlus4W);
reset =>
=> => =>
Clock, Reset, WriteRegM, WriteRegW);
reset =>
=> => =>
Clock, Reset, CtrlSigM(3 DOWNTO 1), CtrlSigW);
reset =>
CtrlSigW(2); CtrlSigM(1); CtrlSigM(0);
83
ResultSelectW <= GetResultW: mux3
JumpLinkW & MemtoRegW;
GENERIC MAP(32) PORT MAP( d0 d1 d2 s q GetHazardSignal: PORT MAP( RegWriteE RegWriteM RegWriteW MemtoRegE BeqD BneD BltzD BgtzD JumpD JrD JumpLinkD JumpLinkM rsD rtD rsE rtE WriteRegE WriteRegM WriteRegW StallF StallD FlushE ForwardAE ForwardBE ForwardJD ForwardAD ForwardBD END structural; => => => => => => => => => => => => => => => => => => => => => => => => => => => RegWriteE, RegWriteM, RegWriteW, MemtoRegE, BeqD, BneD, BltzD, BgtzD, BranchTakenD, JumpD, JrD, JumpLinkD, JumpLinkM, rsD, rtD, rsE, rtE, WriteRegE, WriteRegM, WriteRegW, StallF, StallD, FlushE, ForwardAE, ForwardBE, ForwardJD, ForwardAD, ForwardBD); => => => => => ALUOutW, ReadDataW, PCPlus4W, ResultSelectW, ResultW);
HazardUnit
BranchTakenD=>
84
E. Moving Branch Decision into EX Stage

The datapath and controller of Pipelined MIPS Processor before modified (decision whether the branch taken or not taken is finished in the Execute (ID) stage):
PCSrcD2:0 RegWriteD
CLK
RegWriteE
CLK
RegWriteM
CLK
RegWriteW
JalrD JalD
JumpLinkD ExtOpD
JumpLinkE
JumpLinkM
MemtoRegM MemWriteM
JumpLinkW 1
MemtoRegW 0
ResultSelectW1:0
Control Unit
31:26 5:0
ALUSrcD1:0 RegDstD1:0 JumpD JrD
ForwardJD
Op Funct
2 1 0
PCJrD
ALUOutM PCPlus4M
BranchTakenD
2 1 0
Branch Operator
shamtE10:6
PCPlus4M
PCPlus4W
ReadData1D
10:6
CLK 0 1 2 4
PC'
EN
CLK A RD
InstrD
CLK
25:21
CLK WE3 RD1 0 1 0 1

PCF
A1
WE
Instruction Memory
20:16
0 1 2
SrcBE
ALU
WriteDataM
WriteDataE
RD Data Memory WD
25:21 20:16 15:11
ALUOutW
ReadDataW
2 1 0
+
4
15:0
Extender <<2
ExtOpD
EN CLR
PCPlus4F
$sa= 1 1111
PCPlus4D PCBranchD
15:0
<<16
ImmUpperD
CLR
BranchTakenD
ImmUpperE
ImmExtE
0 1 2
WriteRegE 4:0
WriteRegM 4:0
WriteRegW 4:0
PCPlus4E
ResultW
25:0
FlushD
ForwardAD
ForwardBD
MemtoRegE
ForwardAE
ForwardBE
BgtzD
BltzD BneD
StallF
StallD
BeqD
27:0
JumpD
PCJumpD
Hazard Unit
Then, we will improve the performance by putting the PCSrc in the Execute (EX) stage. On the other words, the decision is finished in the EX stage. Things to be modified: The BranchOperator is moved into the EX stage The Branch signals such as BeqD, BneD, BltzD, and BgtzD are forwarded to the EX stage before used in the BranchOperator The PCBranch is forwarded to the EX stage (PCBranchE) before used by nextPC select multiplexer No longer using stall to handle data hazard because we can still use forwarding from ALUOutM or ResultW. In other words, hazard unit output signal branchStall no more exists. Then, signal branchD, RegWriteE, and WriteRegE are removed from their usage as a hazardunit input signal nPC mux input is re-arranged: Before: After:
RegWriteE
RegWriteM
JumpLinkM
RegWriteW
31:28
<<2
FlushE
85
It is rearranged to prevent a new hazard below occurred:
As we see in the figure above, if there is a jump instruction (j, jal, jr, and jalr) after branch instruction, JumpD and BranchTakenD will be active in unison. Because beq is the first instruction fetched before jump, we must prior the PCBranchD as the nextPC signal. Therefore, we rearrage the mux as we have shown above. The EX and ID register CLR signal (FlushD and FlushE) is modified.
On the stall signals equation, branchstall is removed:
Modifying result:
86
Hazard logic:
87
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY HazardUnit IS PORT( RegWriteE RegWriteM RegWriteW MemtoRegE JumpD JrD JumpLinkD JumpLinkM rsD rtD rsE rtE WriteRegE WriteRegM WriteRegW StallF StallD FlushE ForwardAE ForwardBE ForwardJD END HazardUnit; ARCHITECTURE behaviour OF InstrMemory IS SIGNAL lwstall SIGNAL jrstall BEGIN --ForwardAE logic IF ((rsE != 0) AND (rsE == WriteRegM) AND RegWriteM) THEN ForwardAE = 10 ELSIF ((rsE != 0) AND (rsE == WriteRegW) AND RegWriteW) THEN ForwardAE = 01 ELSE ForwardAE = 00; : : STD_LOGIC; STD_LOGIC; : : : : : : : : : : : : : : : : : : : : : IN STD_LOGIC_VECTOR(1 DOWNTO 0); IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC; IN STD_LOGIC_VECTOR(4 DOWNTO 0); IN STD_LOGIC_VECTOR(4 DOWNTO 0); IN STD_LOGIC_VECTOR(4 DOWNTO 0); IN STD_LOGIC_VECTOR(4 DOWNTO 0); IN STD_LOGIC_VECTOR(4 DOWNTO 0); IN STD_LOGIC_VECTOR(4 DOWNTO 0); IN STD_LOGIC_VECTOR(4 DOWNTO 0); OUT STD_LOGIC_VECTOR; OUT STD_LOGIC; OUT STD_LOGIC; OUT STD_LOGIC_VECTOR(1 DOWNTO 0); OUT STD_LOGIC_VECTOR(1 DOWNTO 0); OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
BranchTakenE:
--ForwardBE logic
88
IF
((rtE != 0) AND (rtE == WriteRegM) AND RegWriteM) THEN
ForwardBE = 10 ELSIF ((rtE != 0) AND (rtE == WriteRegW) AND RegWriteW) THEN ForwardBE = 01 ELSE ForwardBE = 00;
--ForwardJD logic IF (JumpLinkM==1 AND JrD==1) THEN ForwardJD = 01 ELSIF ((rsD!=0) AND (rsD==WriteRegM) AND RegWriteM) THEN ForwardJD = 10 ELSE ForwardJD = 00; --signal lwstall logic lwstall <= ((rsD == rtE) OR (rtD == rtE)) AND MemtoRegE; --signal jrstall logic jrstall <= (JrD AND RegWriteE AND WriteRegE == rsD) OR (JrD AND MemtoRegM AND WriteRegM == rsD) ; --stall logic StallF <= StallD = lwstall OR jrstall; --FlushD logic FlushD <= JumpD OR JrD OR BranchTakenD; --FlushE logic FlushE <= lwstall OR BranchTakenE OR ((JumpD OR JrD) AND NOT JumpLinkD); END behaviour;

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Arditto Trianggada 13209046 | Tugas 6

Arditto Trianggada 13209046 | Tugas 6

Arditto Trianggada 13209046 | Tugas 6

A. Design of Pipelined Processor

CLK WE3 RD1 RD2 Register File

CLK WE A RD Data Memory

Control MemtoRegD Unit

BranchD Op ALUControlD ALUSrcD RegDstD Funct

CLK WE3 RD1 RD2

A3 Register WD3 File

Arditto Trianggada 13209046 | Tugas 6

and $t0, $s0, $s1 or $t1, $s4, $s0

sub $t2, $s0, $s5

RegWriteD MemtoRegD MemWriteD ALUControlD 2:0

ALUSrcD RegDstD BranchD

CLK A1 WE3 RD1

CLK WE A RD Data Memory WD

A2 RD2 A3 Register WD3 File

25:21 20:16 15:11

WriteRegE 4:0 SignImmE

Arditto Trianggada 13209046 | Tugas 6

sub $t2, $s0, $s5

lw $s0, 40($0) and $t0, $s0, $s1 or $t1, $s4, $s0

sub $t2, $s0, $s5

Arditto Trianggada 13209046 | Tugas 6

CLK Control Unit

RegWriteD MemtoRegD MemWriteD ALUControlD 2:0

ALUSrcD RegDstD BranchD

CLK A1 WE3 RD1

CLK WE A RD Data Memory WD

A2 RD2 A3 Register WD3 File

25:21 20:16 15:11

WriteRegE 4:0 SignImmE

The hazard unit signal, lwstall, logic is given below:

The timing diagram is changed:

and $t0, $s0, $s1 or $t1, $s4, $s0

Stall sub $t2, $s0, $s5

Control Hazards Control hazard occurred due to beq instruction.

RF Flush these instructions

sub $t2, $s0, $s5 ... slt $t3, $s2, $s3

Arditto Trianggada 13209046 | Tugas 6

CLK Control Unit

RegWriteD MemtoRegD MemWriteD ALUControlD 2:0

ALUSrcD RegDstD BranchD

CLK A1 WE3 RD1

PCSrcD SrcAE ALUOutM 00 01 10 RsD RtD RdE RsE RtE RdE

A2 RD2 A3 Register WD3 File 0 1

25:21 20:16 15:11

ALUOutW WriteRegE 4:0 SignImmE WriteRegM 4:0

The timing hazard after control hazard already handled:

Flush this instruction

sub $t2, $s0, $s5 ... slt $t3, $s2, $s3

slti $t1, $s0, $t0

beq $t1, $0, done

Arditto Trianggada 13209046 | Tugas 6

addi $s1, $s1, $s0

beq $t1, $0, done

beq $t1, $0, done

slti $t1, $s0, $t0

addi $s1, $s1, $s0

beq $t1, $0, done

Arditto Trianggada 13209046 | Tugas 6

MemtoRegD MemWriteD ALUControlD 2:0

ALUSrcD RegDstD BranchD