Apple Macbook PRO A1286 (Late 2008-Early 2009), Laptop Logic Board Schematic Diagram

8
3
REV
2
ZONE ECN DESCRIPTION OF CHANGE
1
CK APPD ENG APPD DATE DATE
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. 2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. 3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
SCHEM,MBP 15"MLB
08/18/2008 Sync
N/A N/A 12/12/2007 T18_MLB 12/12/2007 T18_MLB N/A N/A N/A N/A 07/22/2008 DDR N/A N/A (MASTER) (MASTER) (MASTER) (MASTER) 10/17/2007 M87_MLB 10/17/2007 M87_MLB 10/17/2007 M87_MLB 01/08/2008 M99_MLB 06/18/2008 T18_MLB 06/18/2008 T18_MLB 06/18/2008 T18_MLB 06/18/2008 T18_MLB 06/18/2008 T18_MLB 06/18/2008 T18_MLB 06/18/2008 T18_MLB 06/18/2008 T18_MLB 06/18/2008 T18_MLB 03/31/2008 T18_MLB 06/18/2008 T18_MLB 06/18/2008 AMASON_M98_MLB 12/17/2007 T18_MLB 07/22/2008 DDR 07/22/2008 DDR 07/22/2008 DDR 06/18/2008 T18_MLB 07/02/2008 YITE_M98_MLB 07/02/2008 YITE_M98_MLB 07/01/2008 SUMA_M98_MLB 07/01/2008 SUMA_M98_MLB 07/01/2008 SUMA_M98_MLB 08/14/2008 SENSOR 08/14/2008 SENSOR 08/14/2008 SENSOR 07/01/2008 CHANG_M98_MLB 07/02/2008 AMASON_M98_MLB 07/01/2008 CHANG_M98_MLB 06/18/2008 T18_MLB 06/18/2008 AMASON_M98_MLB 07/01/2008 CHANG_M98_MLB 07/22/2008 DDR
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
Page
TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
(.csa)
Contents
Table of Contents System Block Diagram Power Block Diagram Power Block Diagram BOM Configuration JTAG Scan Chain Functional / ICT Test Power Aliases Signal Aliases CPU FSB CPU Power & Ground CPU Decoupling & VID eXtended Debug Port(MiniXDP) MCP CPU Interface MCP Memory Interface MCP Memory Misc MCP PCIe Interfaces MCP Ethernet & Graphics MCP PCI & LPC MCP SATA & USB MCP HDA & MISC MCP Power & Ground MCP79 A01 Silicon Support MCP Standard Decoupling MCP Graphics Support SB Misc FSB/DDR3/FRAMEBUF Vref Margining DDR3 SO-DIMM Connector A DDR3 SO-DIMM Connector B DDR3 Support Right Clutch Connector ExpressCard Connector Ethernet PHY (RTL8211CL) Ethernet & AirPort Support Ethernet Connector FireWire LLC/PHY (FW643) FireWire Port Power FireWire Ports SATA Connectors External USB Connectors Front Flex Support SMC SMC Support LPC+SPI Debug Connector M98 SMBus Connections
Date
Page
TABLE_TABLEOFCONTENTS_HEAD
(.csa)
Contents
Current & Voltage Sensing Current Sensing Thermal Sensors Fan Connectors WELLSPRING 1 WELLSPRING 2 Sudden Motion Sensor (SMS) SPI ROM AUDIO:CODEC AUDIO: LINE IN AUDIO: HEADPHONE AMP AUDIO:SPEAKER AMP AUDIO: JACKS AUDIO: JACK TRANSLATORS DC-In & Battery Connectors PBus Supply & Battery Charger IMVP6 CPU VCore Regulator 5V / 3.3V Power Supply 1.5V DDR3 Supply 1.05V / MCP Core Regulator CPU VTT Power Supply Misc Power Supplies Power Control Power FETs NV G96 PCI-E NV G96 Core/FB Power NV G96 Frame Buffer I/F GDDR3 Frame Buffer A (Top) GDDR3 Frame Buffer B (Top) NV G96 GPIO/MIO/Misc G96 GPIOs & Straps NV G96 Video Interfaces GPU (G84M) Core Supply LVDS Display Connector Muxed Graphics Support DisplayPort Connector 1.1V / 1V8 FB Power Supply Graphics MUX (GMUX) LCD BACKLIGHT DRIVER LCD Backlight Support Misc Power Supplies CPU/FSB Constraints Memory Constraints MCP Constraints 1 MCP Constraints 2
Sync
08/14/2008 SENSOR 08/14/2008 SENSOR 08/14/2008 SENSOR 10/17/2007 M87_MLB 06/18/2008 AMASON_M98_MLB 05/12/2008 PWRSQNC 08/14/2008 SENSOR 07/01/2008 CHANG_M98_MLB 07/09/2008 AUDIO 07/09/2008 AUDIO 07/09/2008 AUDIO 07/09/2008 AUDIO 07/09/2008 AUDIO 07/09/2008 AUDIO 12/06/2007 T18_MLB 12/10/2007 M99_MLB 10/17/2007 M87_MLB 01/09/2008 M99_MLB 12/13/2007 M99_MLB 01/08/2008 M99_MLB 12/14/2007 M99_MLB 12/14/2007 M99_MLB 05/12/2008 PWRSQNC 05/12/2008 PWRSQNC 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/09/2008 MUXGFX 07/10/2008 MUXGFX 10/17/2007 M87_MLB 02/25/2008 MUXGFX 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/10/2008 MUXGFX 07/02/2008 YITE_M98_MLB 07/02/2008 YITE_M98_MLB 02/01/2008 MUXGFX 02/18/2008 MUXGFX 02/18/2008 MUXGFX 02/18/2008 MUXGFX 02/18/2008 MUXGFX
Date
Page
TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
(.csa)
Contents
Ethernet Constraints FireWire Constraints SMC Constraints GPU (G96) Constraints Project Specific Constraints PCB Rule Definitions
Sync
02/18/2008 MUXGFX 02/18/2008 MUXGFX 02/18/2008 MUXGFX 02/18/2008 MUXGFX 02/21/2008 MUXGFX 01/22/2008 M99_MLB
Date
TABLE_TABLEOFCONTENTS_ITEM
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 24 25 26 28 29 31 32 33 34 35 37 38 39 41 42 43 45 46 48 49 50 51 52
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
53 54 55 56 57 58 59 61 62 63 65 66 67 68 69 70 71 72 73 75 76 77 78 79 80 81 82 84 85 86 87 88 89 90 93 94 95 96 97 98 99 100 101 102 103
91 92 93 94 95 96
104 105 106 107 108 109
www.laptop-schematics.com
Schematic / PCB #s
PART NUMBER
051-7546 820-2330
DRAWING
DIMENSIONS ARE IN MILLIMETERS
XX
METRIC
DRAFTER DESIGN CK
APPLE INC.
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING
X.XX
X.XXX ENG APPD ANGLES MFG APPD
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART QA APPD DO NOT SCALE DRAWING DESIGNER TITLE
QTY
1 1
DESCRIPTION
SCHEM,FIBBO,M98 PCBF,FIBBO,M98
REFERENCE DES
SCH PCB
CRITICAL
CRITICAL CRITICAL
BOM OPTION
RELEASE
SCALE NONE SIZE
SCHEM,MBP 15MLB
DRAWING NUMBER
TITLE=MLB ABBREV=DRAWING
LAST_MODIFIED=Mon Aug 18 01:48:34 2008
THIRD ANGLE PROJECTION
MATERIAL/FINISH NOTED AS APPLICABLE
051-7546
SHT
REV.
A.0.0
OF
96
6
U1000
5
U1300
INTEL CPU
2.X OR 3.X GHZ PENRYN
PG 9
XDP CONN
PG 12
FSB 64-Bit 800/1067/1333 MHz

PG 13 J2900 J6950
D
DC/BATT
PG 60
POWER SUPPLY
GPIOs
FSB INTERFACE
MAIN MEMORY
PG 14
2 UDIMMs DDR2-800MHZ DDR3-1067/1333MHZ
DIMM
U4900 PG 25,26
TEMP SENSOR
CLK SYNTH
J4510
Misc
PG 24 U6100
PG 41
SATA Conn HD
J4520
SPI
1.05V/3GHZ. PG 38 PG 20
SPI Boot ROM

PG 52
POWER PGSENSE 45
J5650,5600,5610,5611,5660,5720,5730,5750
FAN CONN AND CONTROL

PG 48,49
NVIDIA
SATA Conn ODD
1.05V/3GHZ. PG 38
J4900
B,0 BSB
ADC
SATA
PG 19
MCP79
LPC
SMC
PG 41 PG 18
Fan Ser Prt
J5100
LPC Conn Port80,serial

PG 43
U1400
J9000
LVDS CONN
PG 71
PWR
LVDS OUT RGB OUT
J4720 J4700 J4710 J4710 J3900,4635,4655
CTRL
J9400
DP OUT HDMI OUT 0 1 2 3 4 5 6 7 8 9 DVI OUT

PG 71
Bluetooth
PG 40
TRACKPAD/ KEYBOARD
PG 40
IR
PG 40
CAMERA
PG 40
EXTERNAL USB
Connectors
PG 39
TMDS OUT
PG 17
(UP TO 12 DEVICES)
DISPLAY PORT CONN
USB PCI-E
PG 19
UP TO 20 LANES3
PG 16
B
SMB
PG 20
SMB CONN
DIMMs
PG 44
RGMII
PG 17
(UP TO FOUR PORTS)

PG 18
PCI
HDA
PG 20
U6200
Audio Codec
PG 53
U3700
U6301
U6400
U6500
U6600,6605,6610,6620
System Block Diagram

SYNC_MASTER=T18_MLB SYNC_DATE=12/12/2007
88E1116
PG 31
GB E-NET
Line In Amp
PG 54
HEADPHONE Amp
PG 55
Line Out Amp

PG 56
Speaker Amps
PG 57

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
J3400
U3900 J6800,6801,6802,6803
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
Mini PCI-E AirPort

PG 28
E-NET Conn
PG 33
Audio Conns
PG 59
SIZE
DRAWING NUMBER
REV.
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
96
3
SMC PWRGD RN5VD30A-FSMC_RESET_L U5000 (PAGE 43)
M98 POWER SYSTEM ARCHITECTURE

D6905
PPVIN_G3H_P3V42G3H
ENABLE
3.425V G3HOT
D6905
PBUSB_VSENSE PPBUS_G3H
D
CHGR_EN (S5)
8A FUSE PPVBAT_G3H_CHGR_REG
Q5315
PP3V42_G3H_REG LT3470 U6990 (PAGE 59)
VIN
CPUVTTS0_EN
EN_PSV
VOUT
SMC_GPU_VSENSE
PPCPUVTT_S0_REG (6A MAX CURRENT)
U5498
AC DCIN(16.5V) ADAPTER IN
6A FUSE
U5705 ENABLES
A U5715
(PAGE 78)
VR_PWRGD_CLKENVRMPWRGD PLT_RST_L PLTRST*
SMC_BATT_ISENSE
ISL6258A U7000
J6950
U5400
CPU VCORE VOUT VIN ISL9504B
3S2P
Q7055
BATT_POS_F
IMVP_VR_ON_R U7100 VR_ON

PPVBAT_G3H_CHGR_R
PGOOD
PPVCORE_CPU_S0 CPUVCORE_IOUT VR_PWRGD_CLKEN_L VR_PWRGOOD_DELAY Q7920

PP5V_S0_FET
SMC_CPU_VSENSE
RSMRST*
MCP_PS_PWRGD CPU_PWRGD PWROK CPUPWRGD(GPIO49)
U2850
U1400 (PAGE 14~22)
(9 TO 12.6V)
(PAGE 61)
CHGR_BGATE
PPBUS_G3H
P5VS0_SS
MCP79
SLP_S5#(H17)
P3V3S3_EN P5VS3_EN LIO_S3_EN
P1V1GPU_EN EN1 P1V8FB_EN EN2 U7859
U1000 (PAGE 10,11) RESET*
CPU
C
PWRGOOD
VIN
VOUT1 VOUT2
PP1V1_S0GPU_REG PP1V8_GPU_REG
Q7900
1.103V(L/H)
PP5V_S3_FET
SMC
U4900 (S5) (PAGE 42)
P60 SMC_PM_G2_EN
1.8V(R/H) TPS51124 U9500 (PAGE 82)
P5VS3_SS
VIN
SLP_S3#(G17)
U1400
(PAGE 14~22)
(L/H)
5V
VOUT1 PP5V_S5_REG (8A MAX CURRENT) VOUT2 PP3V3_S5_REG (5.5A MAX CURRENT)
PP5V_S3 PP3V3_S5 PP1V05_S5_MCP
3.3V
(R/H)
P3V3S5_EN VIN U7400 PP5V_RT_REG VOUT EN/PSV SC417 P5V_RT_EN (PAGE 64) P5V_RT_PGOOD ENL PGOOD
EN0 U7201
TPS51125
Q7910
PP3V3_S3_FET
(PAGE 62) PGOOD1,2 VREG3

P3V3S3_SS
P5V3V3_S5_PGOOD
ISL8009 V4 U7750 (PAGE 66)
Q7930
PP3V3_S0GPU_FET
Q3805
B
Q3801
WOW_EN
PM_ENET_EN
PM_WLAN_EN_L
VIN
P3V3S0_SS
ALL_SYS_PWRGD
GOSHAWK6P
PM_RSMRST_L RSMRST_OUT(P15)
PWRGD(P12)
SMC
BKLT_EN
U9701 ENA VOUT (PAGE 84)
PPVOUT_S0_LCDBKLT
Q7970
PP3V3_S0_FET
RSMRST_PWRGD SMC_ONOFF_L
IMVP_VR_ON IMVP_VR_ON(P16) RSMRST_IN(P13) PLT_RST* PWR_BUTTON(P90) PM_PWRBTN_L P17(BTN_OUT)
99ms DLY
P1V2ENET_EN
PM_ENET_EN_L
ENETAVDD_EN
VINLTC3407 VOUT1 RUN2 U3850 (PAGE 33) RUN1 VOUT2
P3V3GPU_SS PP1V9_ENET_REG
Q3810
P3V3_ENET_FET
PP1V2_ENET_REG P3V3ENET_EN_L
P1V05S0_PGOOD P5VRIGHT_PGOOD MCPCORES0_PGOODPM_SLP_S5_L CPUVTTS0_PGOOD PM_SLP_S4_L

P1V8S0_PGOOD P1V5S0_PGOOD S0PGOOD_PWROK
PM_SLP_S3_L
RST* SMC_RESET_L
SLP_S5_L(P95) SLP_S4_L(P94) SLP_S3_L(P93)
Q3800 WOL_EN PM_ENET_EN_L SMC_ADAPTER_EN PM_SLP_S3_L P5VRIGHT_EN RC DELAY P1V8S0_EN RC DELAY MCPDDR_EN RC DELAY CPUVTTS0_EN RC DELAY MCPCORES0_EN RC DELAY
RC DELAY
PPVIN_S0_DDRREG_LDO
VIN
VLDOIN
U4900 (PAGE 42)
DDRREG_EN DDRVTT_EN
1.8V S5 VOUT1 PPDDR_S3_REG (12A MAX CURRENT) S3 0.9VVOUT2

PPVTT_S0_DDR_LDO
RST*
PP5V_S0 PP3V3_S0 V1 V2 V3 LTC2900 PP1V5_S0_REG V4 U7870
Power Block Diagram

P5VS0_EN
(S0)
TPS51116 U7300 (PAGE 63) MCP_CORE

P3V3S0_EN (S0) PBUSVSENS_EN (S0)

PM_SLP_S3_DELAY_L
MCPCORES0_EN P1V05S0_EN
EN2
VOUT2
MCPCPCORE_S0_REG PP5V_RT_REG
(25A MAX CURRENT) (5A MAX CURRENT)
(PAGE 68)
1.1V
EN1
II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.
VOUT1
(S0)
VIN U7500 (PAGE 65)
ISL6236
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
96
(PAGE 60) LIO_DCIN_ISENSE PBUS SUPPLY/ BATTERY CHARGER
GPU VCORE VOUT VIN ISL6263B U8900 PM_GPUVCORE_EN EN_PSV

PGOOD
1.05V
TPS51117 U7600 (PAG 66)
PGOOD
PPVCORE_GPU_REG
(18A MAX CURRENT) GPUVCORE_IOUT
CPUVTTS0_PGOOD
VIN
VOUT
GPUVCORE_PGOOD
MCP79
CK_PWRGD
U2830
PWRBTN#
Power Block Diagram
SYNC_MASTER=N/A
SYNC_DATE=N/A

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
96
7
BOM NAME PCBA,2.4GHZ,256SAM_VRAM,M98 PCBA,2.4GHZ,256HYN_VRAM,M98 PCBA,2.5GHZ,512SAM_VRAM,M98 PCBA,2.5GHZ,512QIM_VRAM,M98 PCBA,2.8GHZ,512SAM_VRAM,M98 PCBA,2.8GHZ,512QIM_VRAM,M98
6
TABLE_BOMGROUP_HEAD
5
TABLE_BOMGROUP_ITEM
BOM Variants
BOM NUMBER 630-9334 630-9335 630-9336 630-9337 630-9585 630-9586 BOM OPTIONS
M98_COMMON,EEE_0ZA,CPU_2_4GHZ,FB_256_SAMSUNG
TABLE_BOMGROUP_ITEM
M98_COMMON,EEE_0ZB,CPU_2_4GHZ,FB_256_HYNIX
TABLE_BOMGROUP_ITEM
M98_COMMON,EEE_0ZC,CPU_2_5GHZ,FB_512_SAMSUNG
TABLE_BOMGROUP_ITEM
M98_COMMON,EEE_0ZD,CPU_2_5GHZ,FB_512_QIMONDA
TABLE_BOMGROUP_ITEM
M98_COMMON,EEE_2NH,CPU_2_8GHZ,FB_512_SAMSUNG
TABLE_BOMGROUP_ITEM
M98_COMMON,EEE_2NJ,CPU_2_8GHZ,FB_512_QIMONDA
M98 BOM Groups

TABLE_BOMGROUP_HEAD
D
TABLE_BOMGROUP_ITEM
BOM GROUP M98_COMMON M98_COMMON1 M98_COMMON2 M98_COMMON3 M98_DEBUG M98_PROGPARTS
BOM OPTIONS ALTERNATE,COMMON,M98_COMMON1,M98_COMMON2,M98_COMMON3,M98_DEBUG,M98_PROGPARTS

TABLE_BOMGROUP_ITEM
ONEWIRE_PU,ISL6258A,MEMRESET_HW,MEMRESET_MCP,MCP_B02,MCP_PROD,MCPSEQ_SMC
TABLE_BOMGROUP_ITEM
BKLT_PLL_NOT,BMON_ENG,MIKEY,BOOT_MODE_USER,GPUVID_1P00V,MUXGFX
TABLE_BOMGROUP_ITEM
DPMUX_EN_S0,DP_ESD,EG_PWRSEQ_HW,DP_CA_DET_EG_PLD,MCP_CS1_NO
TABLE_BOMGROUP_ITEM
SMC_DEBUG_YES,XDP,LPCPLUS,VREFMRGN
TABLE_BOMGROUP_ITEM
GMUX_PROG,BOOTROM_PROG,SMC_PROG,TPAD_PROG
TABLE_BOMGROUP_HEAD
BOM GROUP
FB_256_SAMSUNG FB_256_HYNIX FB_512_SAMSUNG FB_512_QIMONDA
BOM OPTIONS
TABLE_BOMGROUP_ITEM
VRAM4,VRAM_256_SAMSUNG
TABLE_BOMGROUP_ITEM
VRAM4,VRAM_256_HYNIX
TABLE_BOMGROUP_ITEM
VRAM4,VRAM_512_SAMSUNG
TABLE_BOMGROUP_ITEM
VRAM4,VRAM_512_QIMONDA
Bar Code Labels / EEE #s

C
PART NUMBER
826-4393 826-4393 826-4393 826-4393 826-4393 826-4393
QTY
1 1 1 1 1 1
DESCRIPTION
LBL,P/N LABEL,PCB,28MM X 6 MM LBL,P/N LABEL,PCB,28MM X 6 MM LBL,P/N LABEL,PCB,28MM X 6 MM LBL,P/N LABEL,PCB,28MM X 6 MM LBL,P/N LABEL,PCB,28MM X 6 MM LBL,P/N LABEL,PCB,28MM X 6 MM
REFERENCE DES
[EEE:0ZA] [EEE:0ZB] [EEE:0ZC] [EEE:0ZD] [EEE:2NH] [EEE:2NJ]
CRITICAL
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
BOM OPTION
EEE_0ZA EEE_0ZB EEE_0ZC EEE_0ZD EEE_2NH EEE_2NJ
Module Parts
PART NUMBER
337S3639 337S3640 338S0554 338S0570 338S0523 338S0600 338S0563 341S2289
QTY
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 4 4 4
DESCRIPTION
IC,PDC,SLB4N,PRQ,2.4G,25W,1066,M0,3M,BGA IC,PDC,SL3BX,PRQ,2.53G,35W,1066,C0,6M,BGA
REFERENCE DES
U1000 U1000 U8000 U3700 U4100 U1400 U4900 U4900 U6100 U6100 U8770 U4800 U1400 U5701 U1000
U8400,U8450,U8500,U8550 U8400,U8450,U8500,U8550 U8400,U8450,U8500,U8550 U8400,U8450,U8500,U8550
CRITICAL
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
BOM OPTION
CPU_2_4GHZ CPU_2_5GHZ
IC,GPU,55nm,NV G96-GS,BGA969,LF
IC,RTL8211CL,GIGE TRANSCEIVER,48P TQFP
IC,FW643-06,1394B PHY/OHCI LINK/PCI-E,12
IC,GMCP,MCP79-B01,35x35MM,BGA1437
MCP_B01
SMC_BLANK SMC_PROG BOOTROM_BLANK BOOTROM_PROG HDCP_YES
IC,SMC,HS8/2117,9MMX9MM,TLP IC,SMC,DEVELOPMENT,M98
IC,32MBIT 8-PIN SPI SERIAL FLASH,SOIC8
335S0384 341S2366 341S2272 341S2384 338S0635 341S2383 337S3641 333S0482 333S0483 333S0481 333S0472
PART NUMBER
IC,EFI ROM,DEVELOPMENT,M98
IC,HDCP ROM,NVG96, 8 PIN SOIC,LF,HF IR,ENCORE II, CY7C63803-LQXC IC,GMCP,MCP79-B02,35x35MM,BGA1437
MCP_B02
TPAD_PROG
IC,PSOC +W/USB,56PIN,MLF,M98
IC,PDC,SLB43,PRQ,2.8G,35W,1066,C0,6M,BGA
CPU_2_8GHZ
VRAM_256_SAMSUNG VRAM_256_HYNIX VRAM_512_SAMSUNG VRAM_512_QIMONDA
IC,SGRAM,GDDR3,16Mx32,800MHZ,136 FBGA IC,SGRAM,GDDR3,16Mx32,900MHZ,136 FBGA IC,SGRAM,GDDR3,32Mx32,900MHZ,136 FBGA IC,SGRAM,GDDR3,32Mx32,900MHZ,136 FBGA
TABLE_ALT_HEAD
ALTERNATE FOR PART NUMBER 138S0602 353S1294 152S0683 341S2366 152S0867 157S0055 353S1466 514-0607 514-0608 152S0796
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_ITEM
138S0603 353S1681 152S0276 341S2367
ALL ALL ALL ALL ALL ALL ALL ALL ALL ALL
Murata alt to Samsung

TABLE_ALT_ITEM
LMV2011,OPAMP. GBW
TABLE_ALT_ITEM
Maglayers alt to Dale/Vishay

TABLE_ALT_ITEM
BOM Configuration
SYNC_MASTER=N/A SYNC_DATE=N/A
Macronix alt to SST

TABLE_ALT_ITEM
152S0876 157S0058 353S2312 514-0612 514-0613 152S0915
Maglayer alt to Delta

TABLE_ALT_ITEM

Delta alt to TDK Magnetics

TABLE_ALT_ITEM
INTERSIL ALT TO INTERSIL

TABLE_ALT_ITEM
FOXLINK XCVR ALT TO FOXCONN

TABLE_ALT_ITEM
FOXLINK RCVR ALT TO FOXCONN

TABLE_ALT_ITEM
Maglayers alt to Cyntec IND
SIZE
DRAWING NUMBER
REV.
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
96
1.05V TO 3.3V LEVEL TRANSLATOR (M98: ON ICT FIXTURE)

=PP3V3_S0_XDP
13 8 6
=PP1V05_S0_CPU
62 13 12 11 10 8
From XDP connector

JTAG_ALLDEV
1
JTAG_ALLDEV
1
C0601
0.1UF
C0602
0.1UF
87 13 10 6 87 13 10 87 13 10 6 87 13 10 6
IN IN IN IN
20% 2 10V CERM 402
20% 2 10V CERM 402
XDP_TCK XDP_TDI XDP_TMS XDP_TRST_L
U1000 CPU
87 10
To XDP connector and/or level translator

XDP
R0603
XDP_TDO
1
PLACEMENT_NOTE=Place near pin U1000.AB3

XDP_TDO_CONN
OUT
13
JTAG_ALLDEV
R06011
10K
5% 1/16W MF-LF 402 2
VCCA VCCB
87 13 10 6
XDP_TCK XDP_TMS XDP_TRST_L
NOSTUFF
R0602
0
87 13 10 6 87 13 10 6
2 3 4 5 12
UQFN A1 B1 A2 B2 A3 B3 JTAG_ALLDEV A4 B4 OE* GND 6
NLSV4T244
U0600
From XDP connector or via level translator

10 9 8 7
1
MAKE_BASE=TRUE
MAKE_BASE=TRUE
JTAG_MCP_TCK JTAG_MCP_TDI JTAG_MCP_TMS JTAG_MCP_TRST_L
U1400 MCP
13 21 13 21 23 13 21 23 13 21 21
XDP
R0604
JTAG_MCP_TDO
1
PLACEMENT_NOTE=Place near pin U1400.F19

JTAG_MCP_TDO_CONN
OUT
13
5% 1/16W MF-LF 402 2
JTAG_LVL_TRANS_EN_L
R0606
10K
5% 1/16W MF-LF 402
XDP connector
5% 1/16W MF-LF 2 402

MAKE_BASE=TRUE
C
NOSTUFF
VCC
74LVC1G07
2 A Y 4 SOT886 GND 3 NC 5
U0601
GMUX CPLD Programming Port

CRITICAL
NC
1 NC
GPU_JTAG_TCK GPU_JTAG_TDI GPU_JTAG_TMS GPU_JTAG_TRST_L

NC
U8000 GPU
75 75 6 75 75 75
R0605
76 75 8
PLACEMENT_NOTE=Place close to U8000 GPU_JTAG_TMS

6 75
=PP3V3_GPU_VDD33
10K
5% 1/16W MF-LF 402
GPU_JTAG_TDO
TP_GPU_JTAG_TDO
MAKE_BASE=TRUE
1909782
M-RT-SM
7 1 2 3 4
J0600
PLACEMENT_NOTE=Place close to U0600
=PP3V3_S0_XDP
6 8 13
TDO TDI TMS TCK JTAG_GMUX_TCK JTAG_GMUX_TDI JTAG_GMUX_TMS

83 9 83 9 83
5 6
U9200 GMUX
83 9
B
JTAG_GMUX_TDO
JTAG Scan Chain
SYNC_MASTER=DDR
SYNC_DATE=07/22/2008

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
96
5% 1/16W MF-LF 402
XDP connector
11
Functional Test Points

Fan Connectors
FUNC_TEST
ICT Test Points

CPU FSB NO_TESTs
NO_TEST TRUE TRUE TRUE
FSB_A_L<31..3> FSB_ADS_L FSB_ADSTB_L<1..0>
10 14 87 10 14 87 10 14 87
TRUE TRUE TRUE TRUE TRUE TRUE
=PP5V_S0_FAN_LT FAN_LT_PWM FAN_LT_TACH FAN_RT_PWM FAN_RT_TACH GND
8 49
3 TPs per Fan

TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
FSB_D_L<63..0> FSB_DINV_L<3..0> FSB_DSTB_L_N<3..0> FSB_DSTB_L_P<3..0> FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_REQ_L<4..0>
D
10 14 87 10 14 87 10 14 87 10 14 87 10 14 87 10 14 87 10 14 87 10 14 87
49 49
49 49
5 TPs per Fan
FUNC_TEST
I568 I567 I570 I571 I572 I573 I569
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
=PP3V3_S0_DDC_LCD PP3V3_SW_LCD
8 76 79 79 79 84 79 80 79 80 79 80 94
BKL_SYNC LVDS_DDC_CLK LVDS_DDC_DATA LVDS_CONN_A_DATA_N<0> LVDS_CONN_A_DATA_P<0>

LVDS_CONN_A_DATA_N<1> LVDS_CONN_A_DATA_P<1> LVDS_CONN_A_DATA_N<2> LVDS_CONN_A_DATA_P<2> LVDS_CONN_A_CLK_F_N LVDS_CONN_A_CLK_F_P LVDS_CONN_B_DATA_N<0> LVDS_CONN_B_DATA_P<0> LVDS_CONN_B_DATA_N<1> LVDS_CONN_B_DATA_P<1> LVDS_CONN_B_DATA_N<2> LVDS_CONN_B_DATA_P<2> LVDS_CONN_B_CLK_F_N LVDS_CONN_B_CLK_F_P LED_RETURN_1 LED_RETURN_2 LED_RETURN_3 LED_RETURN_4 LED_RETURN_5 LED_RETURN_6
Speaker Connectors
FUNC_TEST
I557 I558 I559
79 80 94
I574 I566
79 80 94
I560
79 80 94
I561 I562
79 80 94
I575
I563
79 80 94
I576 I577 I578 I579 I580
I564
79 94 79 94 79 80 94 79 80 94
I565
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
BI_MIC_LO BI_MIC_SHIELD BI_MIC_HI SPKRCONN_L_P_OUT SPKRCONN_L_N_OUT SPKRCONN_R_P_OUT SPKRCONN_R_N_OUT SPKRCONN_S_P_OUT SPKRCONN_S_N_OUT GND
58 59 58 59 58 59 57 58 95 57 58 95 57 58 95 57 58 95 57 58 95 57 58 95
I757 I758 I759
TRUE 6 TPs
I581 I582
79 80 94 79 80 94
I756 I753 I752
I583 I584 I585 I586 I587 I588 I590 I589 I592 I591
79 80 94 79 80 94
I754 I755
79 94 79 94
SATA ODD Connectors

FUNC_TEST 4 TPs
PP5V_SW_ODD SMC_ODD_DETECT
39 39 42
I751 I749 I750 I748 I746 I747

39 89
79 84
I595
79 84
I594
79 84
I596
79 84
I597
79 84
I593
79 84
I598
TRUE TRUE TRUE TRUE TRUE TRUE TRUE
SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_D2R_C_N SATA_ODD_D2R_C_P GND
I745
39 89
I744
39 89
I743
39 89
I741 I742
5 TPs
I740 I739
EXCARD Connector
FUNC_TEST
I640
POWER RAILS
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
IPD_FLEX_CONN PP3V3_S3_LDO TRUE PP18V5_S3 TRUE TPAD_GND_F TRUE Z2_CS_L TRUE Z2_DEBUG3 TRUE Z2_MOSI TRUE Z2_MISO TRUE Z2_SCLK TRUE Z2_BOOST_EN TRUE Z2_HOST_INTN TRUE Z2_BOOT_CFG1 TRUE Z2_CLKIN TRUE Z2_KEY_ACT_L TRUE Z2_RESET TRUE PSOC_MISO TRUE PSOC_MOSI TRUE PSOC_SCLK TRUE SMBUS_SMC_A_S3_SDA TRUE SMBUS_SMC_A_S3_SCL TRUE PSOC_F_CS_L TRUE PICKB_L TRUE KEYBOARD CONN
51
51 7 51 50 51 50 51 50 51 50 51 50 51 51 50 51 50 51
50 51 50 51 50 51
50 51 50 51
50 51 45 93 45 93
50 51
50 51
PM_SLP_S3_L
21 34 37 42 44 68 81 83
I642 I643 I644 I645 I646 I648 I647 I650 I649 I651 I653 I652 I654 I655 I641 I657 I656
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
USB2_EXCARD_CONN_N 32 95 USB2_EXCARD_CONN_P 32 95 PCIE_CLK100M_EXCARD_CONN_N 32 95 PCIE_CLK100M_EXCARD_CONN_P 32 95 PCIE_EXCARD_R2D_N 32 89 95 PCIE_EXCARD_R2D_P 32 89 95 PCIE_EXCARD_D2R_P 17 32 89 PCIE_EXCARD_D2R_N 17 32 89 PP3V3_S3_EXCARD_SWITCH 32 PP3V3_S0_EXCARD_SWITCH 32 PP1V5_S0_EXCARD_SWITCH 32 PLT_RESET_SWITCH_L 32 EXCARD_CPPE_L 32 EXCARD_CPUSB_L 32 EXCARD_CLKREQ_CONN_L 32
SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA
13 21 45 90 13 21 45 90
I602 I603 I604 I605 I607 I606 I609 I608 I610 I612 I611 I613 I600 I625 I624 I623 I622 I620 I621 I618 I619 I617 I615 I616 I614
PPBUS_G3H PPBUS_CPU_IMVP_ISNS PP3V42_G3H PP5V_S3 PP5V_S0 PPVCORE_S0_CPU PPVCORE_S0_MCP_REG PPVCORE_S0_MCP PP3V3_S5 PP3V3_S3 PP3V3_S0 PP2V5_S0 PP1V2_S0
PP1V8_S0 PP1V8R1V5_S3 PP1V8R1V5_S0_FET PPMCPDDR_ISNS PP1V05_S0_REG PP1V2R1V05_S5 PPCPUVTT_S0 PPCPUFSB_ISNS_R PP0V9R0V75_S0_DDRVTT
8 46 8
B
7 8 43 50 50 50 50 50 50
I736
7 8 43
I737
8
I735
8
I734
8
I733
8
I731 I732
8 95
I730
8
I728
8 95
I729
8
I726
8
I727
8
I725
8
I724
8
I723
8
I721
8
I722
8
I720
8
I718 I719
8
I627 I626 I639 I638 I637 I636 I709 I760 I761 I762 I765
PP1V2R1V05_ENET PP3V3_ENET_PHY PPVP_FW PP1V0_FW PP3V3_S0GPU

PP1V1_S0GPU_REG
I717
8
I715
8
I716
8
I713
8
I714
8
I712
8
PP1V8_S0GPU_ISNS PPVCORE_GPU PP1V8_S0GPU_ISNS_R PP3V3_S5_AVREF_SMC PPVOUT_S0_LCDBKLT PPDCIN_G3H PPVTTDDR_S3 PP1V8_GPUIFPX
I711
8
I710
8
I763
8
I764
42 43 79 84 8
TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
PP3V42_G3H WS_KBD1 WS_KBD2 WS_KBD3 WS_KBD4 WS_KBD5 WS_KBD6 WS_KBD7 WS_KBD8 WS_KBD9 WS_KBD10 WS_KBD11 WS_KBD12 WS_KBD13 WS_KBD14 WS_KBD15_CAP WS_KBD16_NUM WS_KBD17 WS_KBD18 WS_KBD19 WS_KBD20 WS_KBD21 WS_KBD22 WS_KBD23 WS_KBD_ONOFF_L WS_LEFT_SHIFT_KBD WS_LEFT_OPTION_KBD WS_CONTROL_KBD KBDLED_ANODE TPAD_GND_F
50 50 50
50 50 50 50 50 50 50 50
50 50 50 50 50 50 50
Functional / ICT Test

SYNC_MASTER=N/A SYNC_DATE=N/A
50 50

50 51 7 51
8 8
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
96
LVDS Connectors
8
61
7
PPBUS_G3H
MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V MAKE_BASE=TRUE
7 46 63
6
3.3V-2.5V Rails
=PP3V3_S5_REG PP3V3_S5
5
7 95 67
4
1.8V/DDR 1.5V Rails
=PP1V8_S0_REG PP1V8_S0
3
7
2
"FW" (FireWire) Rails
PPVP_FW
"G3Hot" (Always-Present) Rails

=PPBUS_G3H
500 mA max supply

23 44
=PPVIN_S5_P5VP3V3
63
=PP3V3_S5_MCP_A01 =PP3V3_S5_ROM =PP3V3_S5_MEMRESET =PP3V3_S3_P3V3S3FET =PP3V3_S5_LCD =PP3V3_S0_P3V3S0FET =PP3V3_GPU_P3V3GPUFET =PP3V3_S5_PWRCTL =PP3V3_S5_P1V05FET =PP3V3_S5_MCP =PP3V3_S5_MCP_GPIO =PP3V3_FW_LATEVG_ACTIVE
190 mA
=PP3V3R1V8_S0_MCP_IFP_VDD
18 25
37
=PPBUS_S5_FW_FET
44 53 30 69 79 69 69 68 69 22 24 18 20 69 37 64
=PPVIN_S0_CPUVTTS0 =PPBUS_S0_LCDBKLT
=PPDDR_S3_REG
PP1V8R1V5_S3
66 85
=PPVP_FW_PORT1 =PPVP_FW_PHY_CPS_FET
38 38
=PPBUS_S5_FWPWRSW =PPVIN_GPU_GPUVCORE
37 78
=PPVIN_S5_CPU_IMVP_ISNS_R =PPVIN_S0_P5VRTS0_MCPCORE =PPVIN_S3_DDRREG =PPVIN_S0GPU_P1V8P1V1 =PPVBAT_G3H_P3V42G3H =PPVIN_S0_P1V05S5
46 65 64 82 60 67
=PP1V8R1V5_S0_MCP_FET =PPVIN_S0_DDRREG_LDO =PP1V5_S3_MEM_A =PP1V5_S3_MEM_B =PP1V5_S3_MEMRESET =PP1V8R1V5_S0_FET PP1V8R1V5_S0_FET

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2mm VOLTAGE=1.5V MAKE_BASE=TRUE
69 64 28 29 30 8 7
D
=PP3V3_FW_REG =PP3V3_FW_FWPHY
36 38
=PP3V3_FW_P1V0FW
47 11 12 32 68 32 7 67
67
46
=PPVIN_S5_CPU_IMVP_ISNS
PPBUS_CPU_IMVP_ISNS
34 81 24 16
=PP1V5_FC_CON
=PP1V8R1V5_S0_MCP_MEM PPMCPDDR_ISNS
=PP1V0_FW_REG
PP1V0_FW
=PPVIN_S5_CPU_IMVP
60
62
69
=PP3V3_S3_FET
PP3V3_S3
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE
=PP1V0_FW_FWPHY
36
=PP18V5_DCIN_CONN
PPDCIN_G3H
=PP1V5_S0_MEM_A =PP1V5_S0_MEM_B
28 29 47 69
=PPMCPDDR_ISNS
"GPU" Rails
=PP3V3_S0GPU_FET PP3V3_S0GPU
7
=PPDCIN_S5_CHGR
60
61
=PP3V42_G3H_REG
PP3V42_G3H
7 43
=PP3V3_FW_REG =PP3V3_S3_SMBUS_SMC_A_S3 =PP3V3_S3_SMS =PP3V3_S3_REMTHMSNS =PP3V3_S3_TPAD =PP3V3_S3_WLAN =PP3V3_S3_MCP_GPIO =PP3V3_S3_VREFMRGN =PP3V3_S3_SMBUS_SMC_MGMT =PP3V3_S3_EXCARD =PP3V3_S3_P1V8S0
69
8 45 52 48 50 69
=PP1V05_S0_FET
PP1V05_S0_REG
1034 mA
31 21 27 45 32 67 24 8
=PP3V42_G3H_SMCUSBMUX =PP3V42_G3H_SMBUS_SMC_BSA =PP3V42_G3H_LIDSWITCH =PP3V3_S5_SMC =PP3V3_S5_LPCPLUS =PPVIN_S5_SMCVREF =PP3V42_G3H_PWRCTL =PP3V42_G3H_CHGR =PP3V3_S5_RTC_D =PP3V42_G3H_BATT =PP3V42_G3H_TPAD =PP3V42_G3H_BMON_ISNS =PP3V42_G3H_CPUCOREISNS
40 45 41 42 43 52 44 43 63 68 61 26 60 50 46 46
=PP1V05_S0_MCP_AVDD_UF =PP1V05_S0_MCP_PEX_DVDD =PP1V05_S0_MCP_PLL_UF =PP1V05_S0_MCP_SATA_DVDD =PP1V05_S0_MCP_HDMI_VDD =PP1V05_S0_VMON
24 8 24 24 8 24 18 25 68
=PP3V3_GPU_VDD33 =PP3V3_GPU_MIO
=PP3V3_GPU_LVDS_DDC
6 75 76 75 76
80
=PP3V3_GPU_PWRCTL =PP3V3_GPU_VCORELOGIC =PP3V3_GPU_P1V8S0
68 78
=PP1V05_S0_MCP_PEX_DVDD
=PP3V3_S0_FET
PP3V3_S0
=PP1V05_S0_MCP_PEX_DVDD0 =PP1V05_S0_MCP_PEX_DVDD1 =PP1V05_S0_MCP_PEX_AVDD0 =PP1V05_S0_MCP_PEX_AVDD1 =PP1V05_S0_MCP_SATA_DVDD0 =PP1V05_S0_MCP_SATA_AVDD0
67
17 17
7 95
24
PP1V05_S0_MCP_PEX_AVDD
MAKE_BASE=TRUE
17 17
82
=PP1V1_S0GPU_REG
PP1V1_S0GPU_REG
5V Rails
63
=PP5V_S3_REG
PP5V_S3
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V MAKE_BASE=TRUE
=PP5V_S3_SYSLED =PP5V_S3_BTCAMERA =PP5V_S3_WLAN =PP5V_S3_IR =PP5V_S3_DDRREG =PP5V_S3_GPUVCORE =PP5V_S3_RTUSB
43 31 31 41
=PP3V3_S0_LPCPLUS =PP3V3_S0_SMC =PP3V3_S0_SMBUS_SMC_B_S0 =PP3V3_S0_MCPDDRISNS =PP3V3_S0_GPU1V8ISNS =PP3V3_S0_CPUTHMSNS =PP3V3_S0_GPUTHMSNS =PP3V3_S0_FAN_LT =PP3V3_S0_FAN_RT =PP3V3_S0_IMVP =PP3V3_S0_PWRCTL =PP3V3_S0_DDC_LCD =PP3V3_S0_XDP =PP3V3_S0_MCPCOREISNS
=PPSPD_S0_MEM_A =PPSPD_S0_MEM_B
44 43 45 47 47 48 48 67 49 49 62 68 7 76 79 6 13 47 66 24 24 8
=PP1V05_S0_MCP_SATA_DVDD
20
PP1V05_S0_MCP_SATA_AVDD
MAKE_BASE=TRUE
20
=PP1V05_S5_MCP
PP1V2R1V05_S5
(1.1V for A01)

7
241 mA max load 105 mA/241 mA 139 mA/ 0 mA
=PP1V05_S5_MCP_VDD_AUXC =PP1V05_ENET_P1V05ENETFET =PP1V05_S5_P1V05S0FET

PPCPUVTT_S0
=PP1V1_GPU_PEX_IOVDDQ =PP1V1_GPU_PEX_IOVDD =PP1V1_GPU_PEX_PLLXVDD =PP1V1_GPU_PLLVDD =PP1V1_GPU_H_PLLVDD =PP1V1_GPU_VID_PLLVDD =PP1V1_GPU_FBPLLAVDD =PP1V1_GPU_IFPCD_IOVDD
70 70 70 75 75 75 72 77
22 24 34 69 67
=PP1V8_GPUIFPX_REG
PP1V8_GPUIFPX
=PPCPUVTT_S0_REG 5300 mA
64 78 40 51 69 69 69 9 28 29
4500 mA 1182 mA
=PP5V_S3_TPAD
B
65
=PP5V_S3_P1V05S0FET =PP5V_S3_MCPDDRFET =PP5V_S3_VTTCLAMP =PP5V_S3_AUDIO_PWR =PP5V_RT_REG PP5V_S0

MIN_LINE_WIDTH=0.60 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=5V MAKE_BASE=TRUE
=PP1V05_S0_CPU =PP1V05_S0_SMC_LS =PP1V05_S0_MCP_FSB
=PP1V8_GPU_IFPX
6 10 11 12 13 62 43 9 14 22 24
77
=PP3V3_S0_SMBUS_MCP_0 =PP3V3_S0_GMUX =PP3V3_S0_DPMUX =PP3V3_S0_DPCONN

=PP3V3_S0_P1V2P2V5
45 47 83 80 81 86 18 19 21 25 21 24 24 25 64 25 21 22 24 54 58 59 39 68 45 32 64 27
B
=PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS
7
=PP5V_S0_FAN_LT =PP5V_S0_FAN_RT =PP5V_S0_CPU_IMVP =PP5V_S0_CPUVTTS0 =PP5V_S0_KBDLED =PP5V_S0GPU_P1V1P1V8_GPU =PP5V_S0_LPCPLUS =PP5V_S0_ODD =PP5V_S0_HDD
7 49 49 62 66 51 82 44 39 39
=PP3V3_S0_MCP_GPIO =PP3V3_S0_HDCPROM =PP3V3R1V5_S0_MCP_HDA =PP3V3_S0_MCP_PLL_UF =PP3V3_S0_MCP_VPLL_UF =PP3V3_S0_MCP_DAC_UF =PP3V3_S0_MCP =PP3V3_S0_AUDIO =PP3V3_S0_ODD =PP3V3_S0_VMON =PP3V3_S0_SMBUS_MCP_1 =PP3V3_FC_CON
=PPVTT_S3_DDR_BUF
PPVTTDDR_S3
=PP1V8_GPU_FB_VDD =PP1V8_GPU_FB_VDDQ =PP1V8_GPU_FBVDDQ =PP1V8_GPU_FBIO
73 74 9 73 74 71 72
=PPVTT_S0_DDR_LDO
PP0V9R0V75_S0_DDRVTT
MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.9V MAKE_BASE=TRUE
78 46 7
=PPVCORE_GPU_REG
PPVCORE_GPU
=PP0V75_S0_MEM_VTT_A =PP0V75_S0_MEM_VTT_B =PPVTT_S0_VTTCLAMP OR 0.75V
=PPVCORE_GPU
28 29 69 82
71
=PP1V8_GPU_REG
PP1V8_S0GPU_ISNS_R
=PP3V3_S0_EXCARD =PP3V3_S0_LVDSDDCMUX
ENET Rails
32 80 48 45 51 34
=PP1V05_ENET_FET
Chipset "VCore" Rails

62
=PP3V3_S0_BATTCHARGERTMPSNSR
=PP3V3_GPU_SMBUS_SMC_0_S0 =PP3V3_S0_TPAD
7
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE
PP1V2R1V05_ENET
=PP1V8_S0GPU_ISNS_R
7
47
=PPVCORE_S0_CPU_REG
PPVCORE_S0_CPU
=PP1V05_ENET_MCP_PLL_MAC =PP1V05_ENET_MCP_RMGT =PP1V05_ENET_PHY
24
Power Aliases
SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
18 24 33
A
65
=PPVCORE_S0_CPU
=PPMCPCORE_S0_REG PPVCORE_S0_MCP_REG
11 12 46
86
=PP2V5_S0_REG
PP2V5_S0
7 34
=PP3V3_ENET_FET
=PP2V5_S0_GMUX
86
83
PP3V3_ENET_PHY
=PP3V3_ENET_MCP_RMGT
22 24 46
18 24
II NOT TO REPRODUCE OR COPY IT
=PPVCORE_S0_MCP
=PP1V2_S0_REG
PP1V2_S0
=PP3V3_ENET_PHY
33
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.
=PP1V2_S0_GMUX
83
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
96
=PP3V3_S5_MCPPWRGD =PP3V3_FW_LATEVG =PP3V3_S5_P1V05ENETFET =PP3V3_S5_P3V3ENETFET =PP3V3_S5_DP_PORT_PWR
26 38 34
4771 mA 130 mA 500 mA
=PPMCPDDR_ISNS_R =PP1V5_S0_CPU =PP1V5_S0_EXCARD =PP1V5_S0_VMON
7
Thermal Module Holes
ZT0984 ZT0982
STDOFF-4.5OD.98H-1.1-3.48-TH
Top GPU Right TM Hole
6
ZT0981
STDOFF-4.5OD.98H-1.1-3.48-TH
4
CPU signals TP_IMVP6_CLKEN_L
3
VR_PWRGD_CLKEN_L
IMVP6_VID<0..6> =MCP_BSEL<0..2> =DDRVTT_EN
62 87 14 62
2
TP_USB_EXTDP
MAKE_BASE=TRUE
1
USB_EXTD_P USB_EXTD_N
SH0902
2.0DIA-TALL-EMI-MLB-M97-M98
MAKE_BASE=TRUE CPU_VID<0..6> 87 11
MAKE_BASE=TRUE
87 10
20 90
TP_USB_EXTDN
MAKE_BASE=TRUE
20 90
ZT0985
STDOFF-4.5OD.98H-1.1-3.48-TH
SM
1
SH0900
SM
1
CPU_BSEL<0..2>
MAKE_BASE=TRUE
STDOFF-4.5OD.98H-1.1-3.48-TH
26
MEM_VTT_EN
MAKE_BASE=TRUE
64 69
TP_USB_MINIP
MAKE_BASE=TRUE
21 44
USB_MINI_P USB_MINI_N
20 90
TP_SPI_CS1_R_L_USE_MLB
MAKE_BASE=TRUE
=SPI_CS1_R_L_USE_MLB
ZT0983
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0986
SM
TP_USB_MININ
MAKE_BASE=TRUE
20 90
D
Left CPU TM Hole Right CPU TM Hole
STDOFF-4.5OD.98H-1.1-3.48-TH ZT0980 SH0903 STDOFF-4.5OD.98H-1.1-3.48-TH 2.0DIA-TALL-EMI-MLB-M97-M98
GPU signals
89 70
PEG_D2R_P<0..15>
MAKE_BASE=TRUE
=PEG_D2R_P<0..15> =PEG_D2R_N<0..15>
17
89 70
PEG_D2R_N<0..15>
MAKE_BASE=TRUE
D
17 83 17
17
Bottom Left GPU TM Hole
ZT0930
STDOFF-4.5OD.98H-1.1-3.48-TH
SH0901
SM
1
89 70
PEG_R2D_C_P<0..15>
MAKE_BASE=TRUE
=PEG_R2D_C_P<0..15> =PEG_R2D_C_N<0..15>
ZT0987
STDOFF-4.5OD.98H-1.1-3.48-TH
89 70
PEG_R2D_C_N<0..15>
MAKE_BASE=TRUE
GMUX_INT
MAKE_BASE=TRUE
=DVI_HPD_GMUX_INT
18
95 32
PCIE_CLK100M_FC_P
MAKE_BASE=TRUE
TP_PCIE_CLK100M_PE4P TP_PCIE_CLK100M_PE4N TP_PCIE_PE4_R2D_CP TP_PCIE_PE4_R2D_CN TP_PE4_CLKREQ_L TP_PE4_PRSNT_L TP_PCIE_PE4_D2RP TP_PCIE_PE4_D2RN
R0903
17 21 17
MCP_SPKR
SMC_MCP_SAFE_MODE
42
95 32
PCIE_CLK100M_FC_N
MAKE_BASE=TRUE
MAKE_BASE=TRUE
Frame Holes
ZT0915
3R2P5
1
61 60
R0900
=PP1V8_GPU_FB_VDDQ
10
GPU_FB_A_VREF_DIV
MAKE_BASE=TRUE
GND_BATT_CHGND
1% 1/16W MF-LF 402
=PP1V8_GPU_FB_VREF_A
73
FC_CLKREQ_L 32 1.4DIA-SHORT-EMI-MLB-M97-M98SH0911 MAKE_BASE=TRUE SM 1.4DIA-SHORT-EMI-MLB-M97-M98 FC_PRSNT_L 32 SM

1
MAKE_BASE=TRUE
SH0910
95 32
PCIE_FC_R2D_C_N
MAKE_BASE=TRUE
17
TP_MEM_A_A<15>
MAKE_BASE=TRUE
MEM_A_A<15> MEM_B_A<15> USB_EXTC_P USB_EXTC_N CPU_PECI_MCP AUD_IP_PERIPHERAL_DET
28
17
TP_MEM_B_A<15>
MAKE_BASE=TRUE
29
17
TP_USB_EXTCP
MAKE_BASE=TRUE
20 90
R0901
10
GPU_FB_B_VREF_DIV
MAKE_BASE=TRUE
1
95 32
PCIE_FC_D2R_P
MAKE_BASE=TRUE
17
TP_USB_EXTCN
MAKE_BASE=TRUE
20 90
SH0912
1.4DIA-SHORT-EMI-MLB-M97-M98
74
95 32
PCIE_FC_D2R_N
MAKE_BASE=TRUE
17
TP_CPU_PECI_MCP
MAKE_BASE=TRUE
14
1% 1/16W MF-LF 402
=PP1V8_GPU_FB_VREF_B
SM
1
SH0913
SM
1
1.4DIA-SHORT-EMI-MLB-M97-M98
TP_MCP_GPIO_17
MAKE_BASE=TRUE
17
ZT0940
3R2P5
1
GMUX ALIASES
26 17
PCIE_RESET_L
MAKE_BASE=TRUE
FC_RESET_L
32
GND_CHASSIS_LVDS
83
LCD_BKLT_EN
MAKE_BASE=TRUE
LVDS_BKL_ON =MCP_HDMI_TXC_P =MCP_HDMI_TXC_N
85
89 80
DP_IG_ML_P<3>
MAKE_BASE=TRUE
AUDIO ALIASES
18 54 18
ZT0945
3R2P5
1
GND_CHASSIS_USB
Extra FSB Pull-ups

Exist in MRB but not Intel designs. Here for CYA. If found to be necessary, will move to page14.csa
24 22 14 8
89 80
DP_IG_ML_N<3>
MAKE_BASE=TRUE
HDA_BITCLK
MAKE_BASE=TRUE
HDA_BIT_CLK
21 90
89 80
DP_IG_ML_P<2..0>
MAKE_BASE=TRUE
=MCP_HDMI_TXD_P<0..2> =MCP_HDMI_TXD_N<0..2> =MCP_HDMI_DDC_CLK =MCP_HDMI_DDC_DATA =MCP_HDMI_HPD ALL_EG_PGOOD LVDS_MUX_SEL_EG GPU_RESET_L

18
18 8 18
XW0900 SM
=PP5V_S3_AUDIO_PWR
2 SM 2 1 1
89 80
DP_IG_ML_N<2..0>
MAKE_BASE=TRUE
PP5V_S3_AUDIO
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V
54 56
ZT0950 TH
GND_CHASSIS_FAN
SL-3.1X2.7-6CIR-NSP
80 76
DP_IG_DDC_CLK
MAKE_BASE=TRUE
=PP1V05_S0_MCP_FSB
80 76
PP5V_S3_AUDIO_AMP
57
DP_IG_DDC_DATA
MAKE_BASE=TRUE
18
NO STUFF
NO STUFF
NO STUFF
R09501
5% 1/16W MF-LF 402 2
220
R09701
5% 1/16W MF-LF 402 2
200
R09901
1% 1/16W MF-LF 402 2
Bosses for VRAM HS

68
DP_IG_HPD
MAKE_BASE=TRUE
18
XW0901 R0902
1
150
PM_ALL_GPU_PGOOD
MAKE_BASE=TRUE
10K
83
AUD_IPHS_SWITCH_EN
MAKE_BASE=TRUE
19 59
ZT0951
4.0OD1.65H-M1.6X0.35
1
TP_LVDS_MUX_SEL_EG
MAKE_BASE=TRUE
83
83
5% 1/16W MF-LF 402
ZT0965
3R2P5
1
NO STUFF
1
NO STUFF
1
EG_RESET_L
MAKE_BASE=TRUE
70
ETHERNET ALIASES
19
GND_CHASSIS_CLUTCH
R0960
62
R0980
150
ZT0960
3R2P5
1
87 62 14 10
5% 1/16W MF-LF 2 402

OUT OUT OUT OUT OUT
1% 1/16W MF-LF 2 402
ZT0952
4.0OD1.65H-M1.6X0.35
1
83 6
JTAG_GMUX_TDI
MAKE_BASE=TRUE
GMUX_JTAG_TDI GMUX_JTAG_TMS
83 6
JTAG_GMUX_TMS
MAKE_BASE=TRUE
19 34
=P3V3ENET_EN =P1V05ENET_EN
PM_SLP_RMGT_L
MAKE_BASE=TRUE
21
GND_CHASSIS_SATA
87 14 10 87 14 13 10 87 14 10
ZT0990
3R2P5
1
87 14 10
CPU_DPRSTP_L FSB_BREQ0_L FSB_CPURST_L CPU_INTR CPU_NMI
34 83 6
JTAG_GMUX_TDO
MAKE_BASE=TRUE
GMUX_JTAG_TDO IG_BKLT_EN IG_LCD_PWR_EN
17 33
4.0OD1.65H-M1.6X0.35
1
ZT0953
=PP3V3_ENET_PHY_VDDREG =RTL8211_REGOUT
TP_PP3V3_ENET_PHY_VDDREG
MAKE_BASE=TRUE
18
LVDS_IG_BKL_ON
MAKE_BASE=TRUE
83
33
NC_RTL8211_REGOUT
MAKE_BASE=TRUE
18
LVDS_IG_PANEL_PWR
MAKE_BASE=TRUE
83
=RTL8211_ENSWREG
33
GND_CHASSIS_BATTCONN
B
ZT0931 ZT0934
STDOFF-4.0OD3.0H-TH
1
B
STDOFF-4.0OD3.0H-TH 1 VENICE
MCP79 PCIe PRSNT# Straps

9
=PP1V05_S0_MCP_SATA_DVDD1 =PP1V05_S0_MCP_SATA_AVDD1
20
20
NC_LVDS_B_DATAP<3>
MAKE_BASE=TRUE NO_TEST=TRUE
LVDS_B_DATA_P<3> LVDS_B_DATA_N<3>
NO_TEST=TRUE
These need work.
Add other PRSNT# straps if needed. .
NC_LVDS_B_DATAN<3>
MAKE_BASE=TRUE
ZT0932
STDOFF-4.0OD3.0H-TH
1
9
NC_LVDS_A_DATAP<3>
LVDS_A_DATA_P<3> LVDS_A_DATA_N<3>
NO_TEST=TRUE
VENICE
NC_LVDS_A_DATAN<3>
MAKE_BASE=TRUE
R0925
0 PCIE_FW_PRSNT_L
MAKE_BASE=TRUE
OUT
17
ZT0935
STDOFF-4.0OD3.0H-TH
1
ZT0933
STDOFF-4.0OD3.0H-TH
1
VENICE
TP_LVDS_IG_B_CLKP MAKE_BASE=TRUE TP_LVDS_IG_B_CLKN MAKE_BASE=TRUE TP_LVDS_IG_BKL_PWM

MAKE_BASE=TRUE
LVDS_IG_B_CLK_P LVDS_IG_B_CLK_N LVDS_IG_BKL_PWM
18 89 18 89 18
5% 1/16W MF-LF 402
R0927
0
5% 1/16W MF-LF 402
NO STUFF PEG_PRSNT_L
MAKE_BASE=TRUE
OUT
17
Digital Ground
GND
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.09MM VOLTAGE=0V
IN
83
R0926
0
EG_CLKREQ_OUT_L
5% 1/16W MF-LF 402
ZT0988
STDOFF-4.5OD.98H-1.1-3.48-TH
1
NC_LVDS_IG_A_DATAP<3>
MAKE_BASE=TRUE
LVDS_IG_A_DATA_P<3> LVDS_IG_A_DATA_N<3> LVDS_IG_B_DATA_P<3> LVDS_IG_B_DATA_N<3> LVDS_A_DATA_P<3> LVDS_A_DATA_N<3> LVDS_B_DATA_P<3> LVDS_B_DATA_N<3>
18 89
NC_LVDS_IG_A_DATAN<3>
18 89
ZT0989
STDOFF-4.5OD.98H-1.1-3.48-TH
MAKE_BASE=TRUE
MCP_MII_PD
MAKE_BASE=TRUE
18 89
=MCP_MII_RXER =MCP_MII_CRS
18
Signal Aliases
SYNC_MASTER=(MASTER) SYNC_DATE=(MASTER)
NC_LVDS_IG_B_DATAP<3>
MAKE_BASE=TRUE
18
ZT0991
STDOFF-4.5OD.98H-1.1-3.48-TH
1
9
NC_LVDS_IG_B_DATAN<3>
MAKE_BASE=TRUE
18 89
R0930
47K
=MCP_MII_COL
18

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT
NC_LVDS_A_DATAP<3>
MAKE_BASE=TRUE
NC_LVDS_A_DATAN<3>
MAKE_BASE=TRUE
5% 1/16W MF-LF 2 402
NC_LVDS_B_DATAP<3>
MAKE_BASE=TRUE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

9
NC_LVDS_B_DATAN<3>
MAKE_BASE=TRUE
SIZE
9
DRAWING NUMBER
REV.
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
96
95 32
PCIE_FC_R2D_C_P
17
5% 1/16W MF-LF 402
8
87 14 7 87 14 7 87 14 7 87 14 7 87 14 7 87 14 7 87 14 7 87 14 7 87 14 7
7
OMIT
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
6
U1000
ADS* BNR* BPRI* DEFER* DRDY* DBSY* BR0* IERR* INIT* LOCK* H1 E2 G5 H5 F21 E1 F1 D20 B3 H4
87
5
BI BI BI
7 14 87 14 87 14 87
87 14 7 87 14 7 87 14 7 87 14 7 87 14 7 87 14 7
FSB_A_L<3> FSB_A_L<4> FSB_A_L<5> FSB_A_L<6> FSB_A_L<7> FSB_A_L<8> FSB_A_L<9> FSB_A_L<10> FSB_A_L<11> FSB_A_L<12> FSB_A_L<13> FSB_A_L<14> FSB_A_L<15> FSB_A_L<16> FSB_ADSTB_L<0> FSB_REQ_L<0> FSB_REQ_L<1> FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4> FSB_A_L<17> FSB_A_L<18> FSB_A_L<19> FSB_A_L<20> FSB_A_L<21> FSB_A_L<22> FSB_A_L<23> FSB_A_L<24> FSB_A_L<25> FSB_A_L<26> FSB_A_L<27> FSB_A_L<28> FSB_A_L<29> FSB_A_L<30> FSB_A_L<31> FSB_A_L<32> FSB_A_L<33> FSB_A_L<34> FSB_A_L<35> FSB_ADSTB_L<1> CPU_A20M_L CPU_FERR_L CPU_IGNNE_L CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L TP_CPU_RSVD0 TP_CPU_RSVD1 TP_CPU_RSVD2 TP_CPU_RSVD3 TP_CPU_RSVD4 TP_CPU_RSVD5 TP_CPU_RSVD6 TP_CPU_RSVD7 TP_CPU_RSVD8
J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1
A3* A4* PENRYN FCBGA A5* 1 OF 4 A6* A7* A8* A9* A10* A11* A12* A13* A14* A15* A16* ADSTB0* ADDR GROUP0 CONTROL
FSB_ADS_L FSB_BNR_L FSB_BPRI_L FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L FSB_BREQ0_L CPU_IERR_L CPU_INIT_L FSB_LOCK_L FSB_CPURST_L FSB_RS_L<0> FSB_RS_L<1> FSB_RS_L<2> FSB_TRDY_L FSB_HIT_L FSB_HITM_L XDP_BPM_L<0> XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3> XDP_BPM_L<4> XDP_BPM_L<5> XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L XDP_DBRESET_L
=PP1V05_S0_CPU
BI BI BI
14 87 14 87 14 87
6 8 10 11 12 13 62
R1002
54.9
BI
9 14 87
1% 1/16W MF-LF 2 402
PLACE TESTPOINT ON FSB_IERR_L WITH A GND 0.1" AWAY
IN
14 87
BI
7 14 87
87 14 7 87 14 7 87 14 7 87 14 7 87 14 7
BI BI BI BI BI
OMIT
HIT* HITM* BPM0* BPM1* BPM2* BPM3* PRDY* PREQ* TCK TDI TDO TMS TRST* DBR* G6 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20
BI BI
7 14 87 7 14 87
87 14 7 87 14 7 87 14 7 87 14 7 87 14 7 87 14 7 87 14 7 87 14 7 87 14 7 87 14 7 87 14 7 87 14 7
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
87 14 7 87 14 7 87 14 7 87 14 87 14 87 14 87 14 87 14 7
Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1
=PP1V05_S0_CPU
A17* A18* A19* A20* A21* A22* A23* A24* A25* A26* A27* A28* A29* A30* A31* A32* A33* A34* A35* ADSTB1*
6 8 10 11 12 13 62 87 14 7 87 14 7
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
BI BI BI BI BI
13 87 13 87 13 87 13 87 13 87
R10031
54.9
1% 1/16W MF-LF 402 2
BI
13 87
87 14 7 87 14 7 87 14 7 87 14 7 87 14 7 87 14 7 87 14 7 87 14 7 87 14 7 87 14 7 87 14 7
IN IN OUT IN IN OUT
6 10 13 87 6 10 13 87 6 10 87 6 10 13 87 6 10 13 87 13 26
R1004
68
87 14 7 87 14 7 87 14 7 87 14 7 87 14 7
THERMAL PROCHOT* THERMDA THERMDC THERMTRIP* ICH D21 A24 B25 C7
5% 1/16W MF-LF 2 402
CPU_PROCHOT_L CPU_THERMD_P CPU_THERMD_N PM_THRMTRIP_L
OUT OUT OUT

48 95 48 95
14 43 62 87
87 14 7
FSB_D_L<0> FSB_D_L<1> FSB_D_L<2> FSB_D_L<3> FSB_D_L<4> FSB_D_L<5> FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9> FSB_D_L<10> FSB_D_L<11> FSB_D_L<12> FSB_D_L<13> FSB_D_L<14> FSB_D_L<15> FSB_DSTB_L_N<0> FSB_DSTB_L_P<0> FSB_DINV_L<0>
E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25
D0* D1* D2* D3* D4* D5* D6* D7* D8* D9* D10* D11* D12* D13* D14* D15* DSTBN0* DSTBP0* DINV0*
U1000
PENRYN
FCBGA 2 OF 4
D32* D33* D34* D35* D36* D37* D38* D39* D40* D41* D42* D43* D44* D45* D46* D47* DSTBN2* DSTBP2* DINV2*
Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22
FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36> FSB_D_L<37> FSB_D_L<38> FSB_D_L<39> FSB_D_L<40> FSB_D_L<41> FSB_D_L<42> FSB_D_L<43> FSB_D_L<44> FSB_D_L<45> FSB_D_L<46> FSB_D_L<47> FSB_DSTB_L_N<2> FSB_DSTB_L_P<2> FSB_DINV_L<2>
7 14 87 7 14 87 7 14 87 7 14 87 7 14 87 7 14 87 7 14 87 7 14 87 7 14 87 7 14 87 7 14 87 7 14 87 7 14 87 7 14 87 7 14 87 7 14 87 7 14 87 7 14 87 7 14 87
87 14 87 14 87 14
IN OUT IN
A6 A20M* A5 FERR* C4 IGNNE* D5 C6 B4 A3 M4 N5 T2 V3 B2 F6 D2 D22 D3 STPCLK* LINT0 LINT1 SMI* RSVD0 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8
OUT
14 43 87
H CLK
PM_THRMTRIP# SHOULD CONNECT TO ICH AND GMCH WITHOUT T (NO STUB)
87 14 87 14 9 87 14 9 87 14
IN IN IN IN
BCLK0 BCLK1
A22 A21
FSB_CLK_CPU_P FSB_CLK_CPU_N
IN IN
14 87 14 87
62 13 12 11 10 8 6
=PP1V05_S0_CPU
R1005
1K
B
R1020
87 13 10 6
1% 1/16W MF-LF 402 2
R10061
2.0K =PP1V05_S0_CPU
6 8 10 11 12 13 62
XDP_TMS
54.9
1% 1/16W MF-LF 402
1% 1/16W MF-LF 402 2

1
R1021
87 13 10 6
XDP_TDI
54.9
1% 1/16W MF-LF 402
54.9 XDP_TDO 87 10 6 1% PLACEMENT_NOTE=Place R1024 near ITP connector (if present) 1/16W
MF-LF 402
R1024
PLACE C1000 CLOSE TO CPU_TEST4 PIN. MAKE SURE CPU_TEST4 IS REFERENCED TO GND
N22 FSB_D_L<16> K25 FSB_D_L<17> P26 FSB_D_L<18> 87 14 7 BI R23 FSB_D_L<19> 87 14 7 BI L23 FSB_D_L<20> 87 14 7 BI M24 FSB_D_L<21> 87 14 7 BI L22 FSB_D_L<22> 87 14 7 BI M23 FSB_D_L<23> 87 14 7 BI P25 FSB_D_L<24> 87 14 7 BI P23 FSB_D_L<25> 87 14 7 BI P22 FSB_D_L<26> 87 14 7 BI T24 FSB_D_L<27> 87 14 7 BI R24 FSB_D_L<28> 87 14 7 BI L25 FSB_D_L<29> 87 14 7 BI T25 FSB_D_L<30> 87 14 7 BI N25 FSB_D_L<31> 87 14 7 BI FSB_DSTB_L_N<1> L26 87 14 7 BI FSB_DSTB_L_P<1> M26 87 14 7 BI N24 FSB_DINV_L<1> 87 14 7 BI 0.5" MAX LENGTH FOR CPU_GTLREF AD26 87 27 CPU_GTLREF C23 CPU_TEST1 D25 CPU_TEST2 C24 TP_CPU_TEST3 AF26 CPU_TEST4 AF1 TP_CPU_TEST5 NOSTUFF A26 TP_CPU_TEST6 C1000 0.1uF C3 TP_CPU_TEST7 10% 16V B22 CPU_BSEL<0> 87 9 OUT X5R 402 B23 CPU_BSEL<1> 87 9 OUT C21 CPU_BSEL<2> 87 9 OUT
87 14 7 87 14 7
BI BI
D16* D17* D18* D19* D20* D21* D22* D23* D24* D25* D26* D27* D28* D29* D30* D31* DSTBN1* DSTBP1* DINV1* GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL0 BSEL1 BSEL2
D48* D49* D50* D51* D52* D53* D54* D55* D56* D57* D58* D59* D60* D61* D62* D63* DSTBN3* DSTBP3* DINV3* COMP0 COMP1 COMP2 COMP3 DPRSTP* DPSLP* DPWR* PWRGOOD SLP* PSI*
AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 R26 U26 AA1 Y1 E5 B5 D24 D6 D7 AE6
87 87 87 87
FSB_D_L<48> FSB_D_L<49> FSB_D_L<50> FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59> FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63> FSB_DSTB_L_N<3> FSB_DSTB_L_P<3> FSB_DINV_L<3> CPU_COMP<0> CPU_COMP<1> CPU_COMP<2> CPU_COMP<3> CPU_DPRSTP_L CPU_DPSLP_L FSB_DPWR_L CPU_PWRGD FSB_CPUSLP_L CPU_PSI_L
7 14 87 7 14 87 7 14 87 7 14 87 7 14 87 7 14 87 7 14 87 7 14 87 7 14 87 7 14 87 7 14 87 7 14 87 7 14 87 7 14 87 7 14 87 7 14 87 7 14 87 7 14 87 7 14 87
RESERVED
DATA GRP 1
DATA GRP 3
LAYOUT NOTE: COMP0,2 CONNECT WITH ZO=27.4OHM, MAKE TRACE LENGTH SHORTER THAN 0.5". COMP1,3 CONNECT WITH ZO=55OHM, MAKE TRACE LENGTH SHORTER THAN 0.5".
R1016
27.4
1% 1/16W MF-LF 402
R1017
54.9
1% 1/16W MF-LF 402
R1018
27.4
1% 1/16W MF-LF 402
MISC
R1019
54.9
1% 1/16W MF-LF 402 IN IN IN IN IN OUT
9 14 62 87 14 87 14 87 13 14 87 14 87 62
NOSTUFF
R1030
0 NOSTUFF
R1022
87 13 10 6
XDP_TCK
54.9
1% 1/16W MF-LF 402
R10121
5% 1/16W MF-LF 402 2
R1023
87 13 10 6
1K
5% 1/16W MF-LF 402
NOSTUFF
1
R1007
1K
XDP_TRST_L
649
1% 1/16W MF-LF 402
5% 1/16W MF-LF 2 402
CPU FSB
SYNC_MASTER=M87_MLB SYNC_DATE=10/17/2007

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
10
96
K3 H2 K2 J3 L1
REQ0* REQ1* REQ2* REQ3* REQ4*
RESET* RS0* RS1* RS2* TRDY*
C1 F3 F4 G3 G2
IN IN IN IN IN
9 13 14 87 14 87 14 87 14 87 14 87
XDP/ITP SIGNALS
ADDR GROUP1
DATA GRP 0
DATA GRP 2
(CPU CORE POWER) =PPVCORE_S0_CPU

8 11 12 46
Standard Voltage:
Low Voltage:
23.0 A (Design Target) 21.0 A (HFM) 18.7 A (LFM) TBD A (SuperLFM) TBD TBD TBD TBD TBD TBD TBD TBD A (Auto-Halt/Stop-Grant HFM) A (Auto-Halt/Stop-Grant SuperLFM) A (Sleep HFM) A (Sleep SuperLFM) A (Deep Sleep HFM) A (Deep Sleep SuperLFM) A (Deeper Sleep) A (Enhanced Deeper Sleep)
Ultra Low Voltage:

17.0 A (Design Target) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD A (HFM) A (LFM) A (Auto-Halt/Stop-Grant HFM) A (Auto-Halt/Stop-Grant LFM) A (Sleep HFM) A (Sleep LFM) A (Deep Sleep HFM) A (Deep Sleep LFM) A (Deeper Sleep) A (Enhanced Deeper Sleep)
11.5 A (Deeper Sleep) 9.4 A (Enhanced Deeper Sleep)
VCC
VCC
(CPU IO POWER 1.05V) =PP1V05_S0_CPU

6 8 10 12 13 62
VSS
VSS
VCCP
G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21
4500 mA (before VCC stable) 2500 mA (after VCC stable)
V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25
(CPU INTERNAL PLL POWER 1.5V) =PP1V5_S0_CPU

8 12
B26 VCCA C26 VID0 VID1 VID2 VID3 VID4 VID5 VID6 AD6 AF5 AE5 AF4 AE3 AF3 AE2
130 mA CPU_VID<0> CPU_VID<1> CPU_VID<2> CPU_VID<3> CPU_VID<4> CPU_VID<5> CPU_VID<6>

OUT OUT OUT OUT OUT OUT OUT
9 87 9 87 9 87 9 87 9 87 9 87 9 87
=PPVCORE_S0_CPU
1
8 11 12 46
R1100
100
1% 1/16W MF-LF
2 402
PLACEMENT_NOTE=Place within 1 inch of CPU, no stub. VCCSENSE AF7
CPU_VCCSENSE_P
OUT
62 87
VSSSENSE AE7
CPU_VCCSENSE_N
1
OUT
62 87
R1101
100
1% 1/16W MF-LF 2 402 PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.
CPU Power & Ground
SYNC_MASTER=M87_MLB

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
11
96
Current numbers from Merom for Santa Rosa EMTS, doc #22221.
A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18
OMIT
U1000
PENRYN
FCBGA 3 OF 4
AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20
44.0 A (Design Target) 41.0 A (HFM) 30.4 A (LFM) 25.5 A (SuperLFM) 27.4 A (Auto-Halt/Stop-Grant HFM) 17.0 A (Auto-Halt/Stop-Grant SuperLFM) 27.4 A (Sleep HFM) 16.8 A (Sleep SuperLFM) 25.0 A (Deep Sleep HFM) 16.0 A (Deep Sleep SuperLFM)
A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 B1
OMIT
U1000
PENRYN
FCBGA 4 OF 4
P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5
46 11 8
=PPVCORE_S0_CPU CRITICAL
4x 330uF, 20x 22uF 0805

CRITICAL CRITICAL
1
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
C1250 1
330UF
20% 2.0V 2 POLY-TANT D2T-SM2 3
C1251 1
330UF
20% 2.0V 2 POLY-TANT D2T-SM2 3
C1200
22UF
C1201
22UF
20% 6.3V X5R-CERM 603
C1202
22UF
20% 6.3V X5R-CERM 603
C1203
22UF
20% 6.3V X5R-CERM 603
C1204
22UF
20% 6.3V X5R-CERM 603
C1205
22UF
20% 6.3V X5R-CERM 603
C1206
22UF
20% 6.3V X5R-CERM 603
C1207
22UF
20% 6.3V X5R-CERM 603
C1208
22UF
20% 6.3V X5R-CERM 603
C1209
22UF
20% 6.3V X5R-CERM 603
20% 2 6.3V X5R-CERM 603
PLACEMENT_NOTE=Place in CPU center cavity. PLACEMENT_NOTE=Place in CPU center cavity.
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
C1252 1
330UF
C1253 1
330UF
3 20% 2.0V 2 POLY-TANT D2T-SM2 3
C1210
22UF
20% 6.3V X5R-CERM 603
C1211
22UF
20% 6.3V X5R-CERM 603
C1212
22UF
20% 6.3V X5R-CERM 603
C1213
22UF
20% 6.3V X5R-CERM 603
C1214
22UF
20% 6.3V X5R-CERM 603
C1215
22UF
20% 6.3V X5R-CERM 603
C1216
22UF
20% 6.3V X5R-CERM 603
C1217
22UF
20% 6.3V X5R-CERM 603
C1218
22UF
20% 6.3V X5R-CERM 603
C1219
22UF
20% 6.3V X5R-CERM 603
20% 2.0V 2 POLY-TANT D2T-SM2
PLACEMENT_NOTE=Place in CPU center cavity. PLACEMENT_NOTE=Place in CPU center cavity.
VCCP (CPU I/O) DECOUPLING

62 13 11 10 8 6
=PP1V05_S0_CPU
1x 470uF, 6x 0.1uF 0402

1
CRITICAL
C1235 1
470UF
20% 2.5V 2 POLY D2T 3
C1236
0.1UF
C1237
0.1UF
C1238
0.1UF
C1239
0.1UF
C1240
0.1UF
C1241
0.1UF
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
WF: Consider sharing bulk cap with NB Vtt?
B
11 8
VCCA (CPU AVdd) DECOUPLING

=PP1V5_S0_CPU
1x 10uF, 1x 0.01uF
1
C1280 1
10uF
20% 6.3V 2 X5R 603
C1281
0.01UF
10% 2 16V CERM 402 PLACEMENT_NOTE=Place near CPU pin B26.
CPU Decoupling & VID
SYNC_MASTER=M87_MLB

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
12
96
CPU VCORE HF AND BULK DECOUPLING
Mini-XDP Connector
NOTE: This is not the standard XDP pinout.
Use with 920-0620 adapter board to support CPU, MCP debugging.
MCP79-specific pinout
8 6 62 12 11 10 8 6
XDP
R13151
54.9
1% 1/16W MF-LF 402 2
CRITICAL XDP_CONN
J1300
LTH-030-01-G-D-NOPEGS
F-ST-SM 2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
87 10 87 10
BI BI
XDP_BPM_L<5> XDP_BPM_L<4> XDP_BPM_L<3> XDP_BPM_L<2> XDP_BPM_L<1> XDP_BPM_L<0> TP_XDP_OBSFN_B0 TP_XDP_OBSFN_B1 TP_XDP_OBSDATA_B0 TP_XDP_OBSDATA_B1
OBSFN_A0 OBSFN_A1 OBSDATA_A0 OBSDATA_A1 OBSDATA_A2 OBSDATA_A3 OBSFN_B0 OBSFN_B1 OBSDATA_B0 OBSDATA_B1 OBSDATA_B2 OBSDATA_B3 XDP_OBS20 PWRGD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 SDA SCL TCK1 TCK0 XDP
4 6 8
OBSFN_C0 OBSFN_C1 OBSDATA_C0 OBSDATA_C1 OBSDATA_C2 OBSDATA_C3 OBSFN_D0 OBSFN_D1 OBSDATA_D0 OBSDATA_D1 OBSDATA_D2 OBSDATA_D3
JTAG_MCP_TDO_CONN JTAG_MCP_TRST_L MCP_DEBUG<0> MCP_DEBUG<1> MCP_DEBUG<2> MCP_DEBUG<3> JTAG_MCP_TDI JTAG_MCP_TMS MCP_DEBUG<4> MCP_DEBUG<5> MCP_DEBUG<6> MCP_DEBUG<7>
IN OUT
6 6 21
87 10 87 10
BI IN
10 12 14
BI BI
19 90 19 90
87 10 87 10
IN IN
16 18 20 22 24 26 28 30 32
BI BI
19 90 19 90
OUT OUT
6 21 23 6 21 23
BI BI
19 90 19 90
XDP
R1399
87 14 10
TP_XDP_OBSDATA_B2 TP_XDP_OBSDATA_B3 XDP_PWRGD
34 36 38 40 42 44 46 48 50
BI BI
19 90 19 90
IN
CPU_PWRGD
1K
5% 1/16W MF-LF 402

23 19 21 6
IN OUT
PM_LATRIGGER_L JTAG_MCP_TCK SMBUS_MCP_0_DATA SMBUS_MCP_0_CLK XDP_TCK
90 45 21 7 90 45 21 7
BI BI
52 54
NC
56 58 60
87 10 6
OUT
FSB_CLK_ITP_P ITPCLK/HOOK4 IN 14 87 FSB_CLK_ITP_N ITPCLK#/HOOK5 IN 14 87 VCC_OBS_CD 87 XDP_CPURST_L RESET#/HOOK6 XDP_DBRESET_L DBR#/HOOK7 OUT 10 26 NOTE: XDP_DBRESET_L must be pulled-up to 3.3V. XDP_TDO_CONN TDO IN 6 XDP_TRST_L TRSTn OUT 6 10 87 XDP_TDI TDI OUT 6 10 87 XDP_TMS TMS OUT 6 10 87 XDP_PRESENT# XDP
1
XDP
R1303
1
1K
FSB_CPURST_L
IN
9 10 14 87
5% 1/16W MF-LF 402
PLACEMENT_NOTE=Place close to CPU to minimize stub.
C1300 1
0.1uF
10% 16V 2 X5R 402
C1301
0.1uF
10% 2 16V X5R 402
998-1571
Direction of XDP module

Please avoid any obstructions on even-numbered side of J1300
eXtended Debug Port(MiniXDP)
SYNC_MASTER=M99_MLB

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
13
96
=PP3V3_S0_XDP =PP1V05_S0_CPU
5
OMIT
4
U1400
MCP79-TOPO-B
BGA (1 OF 11)
87 10 7 87 10 7 87 10 7
BI BI BI BI BI BI BI BI BI BI BI BI
FSB_DSTB_L_P<0> FSB_DSTB_L_N<0> FSB_DINV_L<0> FSB_DSTB_L_P<1> FSB_DSTB_L_N<1> FSB_DINV_L<1> FSB_DSTB_L_P<2> FSB_DSTB_L_N<2> FSB_DINV_L<2> FSB_DSTB_L_P<3> FSB_DSTB_L_N<3> FSB_DINV_L<3> FSB_A_L<3> FSB_A_L<4> FSB_A_L<5> FSB_A_L<6> FSB_A_L<7> FSB_A_L<8> FSB_A_L<9> FSB_A_L<10> FSB_A_L<11> FSB_A_L<12> FSB_A_L<13> FSB_A_L<14> FSB_A_L<15> FSB_A_L<16> FSB_A_L<17> FSB_A_L<18> FSB_A_L<19> FSB_A_L<20> FSB_A_L<21> FSB_A_L<22> FSB_A_L<23> FSB_A_L<24> FSB_A_L<25> FSB_A_L<26> FSB_A_L<27> FSB_A_L<28> FSB_A_L<29> FSB_A_L<30> FSB_A_L<31> FSB_A_L<32> FSB_A_L<33> FSB_A_L<34> FSB_A_L<35> FSB_ADSTB_L<0> FSB_ADSTB_L<1> FSB_REQ_L<0> FSB_REQ_L<1> FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4> FSB_ADS_L FSB_BNR_L FSB_BREQ0_L FSB_BREQ1_L FSB_DBSY_L FSB_DRDY_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_TRDY_L CPU_PECI_MCP CPU_PROCHOT_L
T40 CPU_DSTBP0# U40 CPU_DSTBN0# V41 CPU_DBI0# W39 CPU_DSTBP1# W37 CPU_DSTBN1# V35 CPU_DBI1# N37 CPU_DSTBP2# L36 CPU_DSTBN2# N35 CPU_DBI2# M39 CPU_DSTBP3# M41 CPU_DSTBN3# J41 CPU_DBI3# AC34 AE38 AE34 AC37 AE37 AE35 AB35 AF35 AG35 AG39 AE33 AG37 AG38 AG34 AN38 AL39 AG33 AL33 AJ33 AN36 AJ35 AJ37 AJ36 AJ38 AL37 AL34 AN37 AJ34 AL38 AL35 AN34 AR39 AN35 CPU_A3# CPU_A4# CPU_A5# CPU_A6# CPU_A7# CPU_A8# CPU_A9# CPU_A10# CPU_A11# CPU_A12# CPU_A13# CPU_A14# CPU_A15# CPU_A16# CPU_A17# CPU_A18# CPU_A19# CPU_A20# CPU_A21# CPU_A22# CPU_A23# CPU_A24# CPU_A25# CPU_A26# CPU_A27# CPU_A28# CPU_A29# CPU_A30# CPU_A31# CPU_A32# CPU_A33# CPU_A34# CPU_A35#
87 10 7 87 10 7 87 10 7
87 10 7 87 10 7 87 10 7
87 10 7 87 10 7 87 10 7
87 10 7 87 10 7 87 10 7 87 10 7 87 10 7 87 10 7 87 10 7 87 10 7 87 10 7 87 10 7 87 10 7 87 10 7 87 10 7 87 10 7 87 10 7 87 10 7 87 10 7 87 10 7 87 10 7
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87
87 10 7 87 10 7 87 10 7 87 10 7 87 10 7 87 10 7 87 10 7 87 10 7 87 10 7 87 10 7 87 10 87 10 87 10 87 10
87 10 7 87 10 7
AE36 CPU_ADSTB0# AK35 CPU_ADSTB1# AC38 AA33 AC39 AC33 AC35 AD42 AD43 AE40 AL32 AD39 AD41 AB42 AD40 AC43 AE41 E41 AJ41 AG43 AH40 CPU_REQ0# CPU_REQ1# CPU_REQ2# CPU_REQ3# CPU_REQ4# CPU_ADS# CPU_BNR# CPU_BR0# CPU_BR1# CPU_DBSY# CPU_DRDY# CPU_HIT# CPU_HITM# CPU_LOCK# CPU_TRDY# CPU_PECI CPU_PROCHOT# CPU_THERMTRIP# CPU_FERR#
87 10 7
BI BI BI BI BI
24 22 14 9 8
=PP1V05_S0_MCP_FSB
87 10 7 87 10 7 87 10 7
R14101
54.9
1% 1/16W MF-LF 402 2
R14151
62
5% 1/16W MF-LF 402 2
R1416
62
87 10 7
5% 1/16W MF-LF 2 402
87 10 7 87 10 87 10 9
BI BI BI
87
B
87 43 10 87 10
IN IN
PM_THRMTRIP_L CPU_FERR_L
87 10 87 10 87 10 7 87 10 7 87 10 7 87 10
BI BI BI BI IN OUT
CPU_BPRI# AA41 CPU_DEFER# AA40
FSB_BPRI_L FSB_DEFER_L FSB_CLK_CPU_P FSB_CLK_CPU_N FSB_CLK_ITP_P FSB_CLK_ITP_N

87 87
OUT OUT
10 87 10 87
NO STUFF
NO STUFF
NO STUFF
1
R1420
1K
R1421
1K
R1422
1K
9 87 62 43 10
OUT OUT
BCLK_OUT_CPU_P G42 BCLK_OUT_CPU_N G41 BCLK_OUT_ITP_P AL43 BCLK_OUT_ITP_N AL42 BCLK_OUT_NB_P AL41 BCLK_OUT_NB_N AK42
OUT OUT OUT OUT
10 87 10 87
5% 1/16W MF-LF 402 2

9 9 9
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 2 402
13 87 13 87
IN IN IN
=MCP_BSEL<2> =MCP_BSEL<1> =MCP_BSEL<0>

87 10 87 10 87 10
(MCP_BSEL<2>) (MCP_BSEL<1>) (MCP_BSEL<0>)

OUT OUT OUT
F42 CPU_BSEL2 D42 CPU_BSEL1 F41 CPU_BSEL0 AC41 CPU_RS0# AB41 CPU_RS1# AC42 CPU_RS2#
FSB_CLK_MCP_P FSB_CLK_MCP_N Loop-back clock for delay matching.
FSB_RS_L<0> FSB_RS_L<1> FSB_RS_L<2>
BCLK_IN_N AK41 BCLK_IN_P AJ40
R14301
49.9
1% 1/16W MF-LF 402 2
R1435
49.9
1% 1/16W MF-LF 2 402
PP1V05_S0_MCP_PLL_FSB 24 270 mA (A01) 206 mA 20 mA 29 mA 15 mA

87 87
AG27 AH27 AG28 AH28
+V_DLL_DLCELL_AVDD +V_PLL_MCLK +V_PLL_FSB +V_PLL_CPU
A
R14311
49.9
1% 1/16W MF-LF 402 2 1
CPU_A20M# CPU_IGNNE# CPU_INIT# CPU_INTR CPU_NMI CPU_SMI#
AF41 AH39 AH42 AF42 AG41 AH41
CPU_A20M_L CPU_IGNNE_L CPU_INIT_L CPU_INTR CPU_NMI CPU_SMI_L CPU_PWRGD FSB_CPURST_L FSB_CPUSLP_L CPU_DPSLP_L FSB_DPWR_L CPU_STPCLK_L CPU_DPRSTP_L
OUT OUT OUT OUT OUT OUT
10 87 10 87 10 87 9 10 87 9 10 87 10 87
=PP1V05_S0_MCP_FSB NO STUFF
1
8 9 14 22 24
R1440
150
MCP_BCLK_VML_COMP_VDD MCP_BCLK_VML_COMP_GND MCP_CPU_COMP_VCC MCP_CPU_COMP_GND
5% 1/16W MF-LF 2 402 OUT

10 13 87
MCP CPU Interface

AM39 BCLK_VML_COMP_VDD AM40 BCLK_VML_COMP_GND AM43 CPU_COMP_VCC AM42 CPU_COMP_GND
CPU_PWRGD AH43 CPU_RESET# H38 CPU_SLP# CPU_DPSLP# CPU_DPWR# CPU_STPCLK# CPU_DPRSTP# AM33 AN33 AM32 AG42 AN32

9 10 13 87
87
10 87 10 87 10 87 10 87 9 10 62 87
R1436
49.9
87
1% 1/16W MF-LF 2 402
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
14
96
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
CPU_D0# CPU_D1# CPU_D2# CPU_D3# CPU_D4# CPU_D5# CPU_D6# CPU_D7# CPU_D8# CPU_D9# CPU_D10# CPU_D11# CPU_D12# CPU_D13# CPU_D14# CPU_D15# CPU_D16# CPU_D17# CPU_D18# CPU_D19# CPU_D20# CPU_D21# CPU_D22# CPU_D23# CPU_D24# CPU_D25# CPU_D26# CPU_D27# CPU_D28# CPU_D29# CPU_D30# CPU_D31# CPU_D32# CPU_D33# CPU_D34# CPU_D35# CPU_D36# CPU_D37# CPU_D38# CPU_D39# CPU_D40# CPU_D41# CPU_D42# CPU_D43# CPU_D44# CPU_D45# CPU_D46# CPU_D47# CPU_D48# CPU_D49# CPU_D50# CPU_D51# CPU_D52# CPU_D53# CPU_D54# CPU_D55# CPU_D56# CPU_D57# CPU_D58# CPU_D59# CPU_D60# CPU_D61# CPU_D62# CPU_D63#
Y43 W42 Y40 W41 Y39 V42 Y41 Y42 P42 U41 R42 T39 T42 T41 R41 T43 W35 AA37 W33 W34 AA36 AA34 AA38 AA35 U38 U36 U35 U33 U34 W38 R33 U37 N34 N33 R34 R35 P35 R39 R37 R38 L37 L39 L38 N36 N38 J39 J38 J37 L42 M42 P41 N41 N40 M40 H40 K42 H41 L41 H43 H42 K41 J40 H39 M43
FSB_D_L<0> FSB_D_L<1> FSB_D_L<2> FSB_D_L<3> FSB_D_L<4> FSB_D_L<5> FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9> FSB_D_L<10> FSB_D_L<11> FSB_D_L<12> FSB_D_L<13> FSB_D_L<14> FSB_D_L<15> FSB_D_L<16> FSB_D_L<17> FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24> FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29> FSB_D_L<30> FSB_D_L<31> FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36> FSB_D_L<37> FSB_D_L<38> FSB_D_L<39> FSB_D_L<40> FSB_D_L<41> FSB_D_L<42> FSB_D_L<43> FSB_D_L<44> FSB_D_L<45> FSB_D_L<46> FSB_D_L<47> FSB_D_L<48> FSB_D_L<49> FSB_D_L<50> FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59> FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63>
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87 7 10 87
FSB
7
OMIT
3
OMIT
U1400
MCP79-TOPO-B
BGA (2 OF 11)
88 28 88 28 88 28 88 28
U1400
MCP79-TOPO-B
BGA (3 OF 11) AL10 AL11 AR8 AR9 AW7 AW8 AP13 AR13 AV25 AW25 AU30 AU29 AT35 AU35 AU39 AT39
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI OUT OUT OUT OUT OUT OUT OUT OUT
88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28
BI
28 88
88 29 88 29
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI OUT OUT OUT OUT OUT OUT OUT OUT
BI
29 88
MEMORY PARTITION 0
88 29 88 29 88 29
MRAS0# AV17 MCAS0# AP17 MWE0# AR17
MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L
MEMORY PARTITION 1
88 29
OUT OUT OUT
28 88 28 88 28 88
88 29 88 29 88 29 88 29 88 29 88 29 88 29 88 29
MRAS1# AW16 MCAS1# BA15 MWE1# BA16
MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L
OUT OUT OUT
29 88 29 88 29 88
88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28
MBA0_2 AP23 MBA0_1 AP19 MBA0_0 AW17
MEM_A_BA<2> MEM_A_BA<1> MEM_A_BA<0>
OUT OUT OUT
28 88 28 88 28 88
88 29 88 29 88 29 88 29 88 29 88 29 88 29
MBA1_2 BB29 MBA1_1 BB18 MBA1_0 BB17
MEM_B_BA<2> MEM_B_BA<1> MEM_B_BA<0>
OUT OUT OUT
29 88 29 88 29 88
MA0_14 MA0_13 MA0_12 MA0_11 MA0_10 MA0_9 MA0_8 MA0_7 MA0_6 MA0_5 MA0_4 MA0_3 MA0_2 MA0_1 MA0_0
AR23 AU15 AN23 AW21 AN19 AV21 AR22 AU21 AP21 AR21 AN21 AV19 AU19 AT19 AR19
MEM_A_A<14> MEM_A_A<13> MEM_A_A<12> MEM_A_A<11> MEM_A_A<10> MEM_A_A<9> MEM_A_A<8> MEM_A_A<7> MEM_A_A<6> MEM_A_A<5> MEM_A_A<4> MEM_A_A<3> MEM_A_A<2> MEM_A_A<1> MEM_A_A<0>
88 29
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
28 88 88 29 28 88 88 29 28 88 88 29 28 88 88 29 28 88 88 29 28 88 88 29 28 88 88 29 28 88 88 29 28 88 88 29 28 88 88 29 28 88 88 29 28 88 88 29 28 88 88 29 28 88 88 29 28 88 88 29 88 29
MA1_14 MA1_13 MA1_12 MA1_11 MA1_10 MA1_9 MA1_8 MA1_7 MA1_6 MA1_5 MA1_4 MA1_3 MA1_2 MA1_1 MA1_0
BA29 BA14 AW28 BC28 BA17 BB28 AY28 BA28 AY27 BA27 BA26 BB26 BA25 BB25 BA18
MEM_B_A<14> MEM_B_A<13> MEM_B_A<12> MEM_B_A<11> MEM_B_A<10> MEM_B_A<9> MEM_B_A<8> MEM_B_A<7> MEM_B_A<6> MEM_B_A<5> MEM_B_A<4> MEM_B_A<3> MEM_B_A<2> MEM_B_A<1> MEM_B_A<0>
29 88 29 88 29 88 29 88 29 88 29 88 29 88 29 88 29 88 29 88 29 88 29 88 29 88 29 88 29 88
MEMORY CONTROL 0A
MCLK0A_2_P AW33 MCLK0A_2_N AV33 MCLK0A_1_P BA24 MCLK0A_1_N AY24 MCLK0A_0_P BB20 MCLK0A_0_N BC20 MCS0A_1# AT15 MCS0A_0# AR18 MODT0A_1 AP15 MODT0A_0 AV15 MCKE0A_1 AU23 MCKE0A_0 AT23
88 29 88 29 88 29
MEMORY CONTROL 1A
MCLK1A_2_P BA42 MCLK1A_2_N BB42 MCLK1A_1_P BB22 MCLK1A_1_N BA22 MCLK1A_0_P BA19 MCLK1A_0_N AY19 MCS1A_1# BB14 MCS1A_0# BB16 MODT1A_1 BB13 MODT1A_0 AY15 MCKE1A_1 AY31 MCKE1A_0 BB30
88 28 88 28 88 28 88 28 88 28 88 28 88 28
TP_MEM_A_CLK2P TP_MEM_A_CLK2N MEM_A_CLK_P<1> MEM_A_CLK_N<1> MEM_A_CLK_P<0> MEM_A_CLK_N<0> MEM_A_CS_L<1> MEM_A_CS_L<0> MEM_A_ODT<1> MEM_A_ODT<0> MEM_A_CKE<1> MEM_A_CKE<0>
OUT OUT OUT OUT
28 88 28 88
88 29 88 29 88 29 88 29 88 29 88 29 28 88 88 29 28 88 88 29
TP_MEM_B_CLK2P TP_MEM_B_CLK2N MEM_B_CLK_P<1> MEM_B_CLK_N<1> MEM_B_CLK_P<0> MEM_B_CLK_N<0> MEM_B_CS_L<1> MEM_B_CS_L<0> MEM_B_ODT<1> MEM_B_ODT<0> MEM_B_CKE<1> MEM_B_CKE<0>
OUT OUT OUT OUT
29 88 29 88
B
29 88 29 88
88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28
MEM_A_DM<7> MEM_A_DM<6> MEM_A_DM<5> MEM_A_DM<4> MEM_A_DM<3> MEM_A_DM<2> MEM_A_DM<1> MEM_A_DM<0>
AN5 AU5 AR10 AN13 AN27 AW29 AV35 AR34
MDQM0_7 MDQM0_6 MDQM0_5 MDQM0_4 MDQM0_3 MDQM0_2 MDQM0_1 MDQM0_0
OUT OUT
28 88 28 88
88 29 88 29 88 29
OUT OUT
28 88 28 88
88 29 88 29 88 29
OUT OUT
28 88 28 88
88 29 88 29
MEM_B_DM<7> MEM_B_DM<6> MEM_B_DM<5> MEM_B_DM<4> MEM_B_DM<3> MEM_B_DM<2> MEM_B_DM<1> MEM_B_DM<0>
AT5 BA2 AY7 BA11 BB34 BB38 AY43 AR42
MDQM1_7 MDQM1_6 MDQM1_5 MDQM1_4 MDQM1_3 MDQM1_2 MDQM1_1 MDQM1_0
OUT OUT
29 88 29 88
OUT OUT
29 88 29 88
OUT OUT
29 88 29 88
MCP Memory Interface
SYNC_MASTER=T18_MLB

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
15
96
MEM_A_DQ<63> MEM_A_DQ<62> MEM_A_DQ<61> MEM_A_DQ<60> MEM_A_DQ<59> MEM_A_DQ<58> MEM_A_DQ<57> MEM_A_DQ<56> MEM_A_DQ<55> MEM_A_DQ<54> MEM_A_DQ<53> MEM_A_DQ<52> MEM_A_DQ<51> MEM_A_DQ<50> MEM_A_DQ<49> MEM_A_DQ<48> MEM_A_DQ<47> MEM_A_DQ<46> MEM_A_DQ<45> MEM_A_DQ<44> MEM_A_DQ<43> MEM_A_DQ<42> MEM_A_DQ<41> MEM_A_DQ<40> MEM_A_DQ<39> MEM_A_DQ<38> MEM_A_DQ<37> MEM_A_DQ<36> MEM_A_DQ<35> MEM_A_DQ<34> MEM_A_DQ<33> MEM_A_DQ<32> MEM_A_DQ<31> MEM_A_DQ<30> MEM_A_DQ<29> MEM_A_DQ<28> MEM_A_DQ<27> MEM_A_DQ<26> MEM_A_DQ<25> MEM_A_DQ<24> MEM_A_DQ<23> MEM_A_DQ<22> MEM_A_DQ<21> MEM_A_DQ<20> MEM_A_DQ<19> MEM_A_DQ<18> MEM_A_DQ<17> MEM_A_DQ<16> MEM_A_DQ<15> MEM_A_DQ<14> MEM_A_DQ<13> MEM_A_DQ<12> MEM_A_DQ<11> MEM_A_DQ<10> MEM_A_DQ<9> MEM_A_DQ<8> MEM_A_DQ<7> MEM_A_DQ<6> MEM_A_DQ<5> MEM_A_DQ<4> MEM_A_DQ<3> MEM_A_DQ<2> MEM_A_DQ<1> MEM_A_DQ<0>
AL8 AL9 AP9 AN9 AL6 AL7 AN6 AN7 AR6 AR7 AV6 AW5 AN10 AR5 AU6 AV5 AU7 AU8 AW9 AP11 AW6 AY5 AU9 AV9 AU11 AV11 AV13 AW13 AR11 AT11 AR14 AU13 AR26 AU25 AT27 AU27 AP25 AR25 AP27 AR27 AP29 AR29 AP31 AR31 AV27 AN29 AV29 AN31 AU31 AR33 AV37 AW37 AT31 AV31 AT37 AU37 AW39 AV39 AR37 AR38 AV38 AW38 AR35 AP35
MDQ0_63 MDQ0_62 MDQ0_61 MDQ0_60 MDQ0_59 MDQ0_58 MDQ0_57 MDQ0_56 MDQ0_55 MDQ0_54 MDQ0_53 MDQ0_52 MDQ0_51 MDQ0_50 MDQ0_49 MDQ0_48 MDQ0_47 MDQ0_46 MDQ0_45 MDQ0_44 MDQ0_43 MDQ0_42 MDQ0_41 MDQ0_40 MDQ0_39 MDQ0_38 MDQ0_37 MDQ0_36 MDQ0_35 MDQ0_34 MDQ0_33 MDQ0_32 MDQ0_31 MDQ0_30 MDQ0_29 MDQ0_28 MDQ0_27 MDQ0_26 MDQ0_25 MDQ0_24 MDQ0_23 MDQ0_22 MDQ0_21 MDQ0_20 MDQ0_19 MDQ0_18 MDQ0_17 MDQ0_16 MDQ0_15 MDQ0_14 MDQ0_13 MDQ0_12 MDQ0_11 MDQ0_10 MDQ0_9 MDQ0_8 MDQ0_7 MDQ0_6 MDQ0_5 MDQ0_4 MDQ0_3 MDQ0_2 MDQ0_1 MDQ0_0
MDQS0_7_P MDQS0_7_N MDQS0_6_P MDQS0_6_N MDQS0_5_P MDQS0_5_N MDQS0_4_P MDQS0_4_N MDQS0_3_P MDQS0_3_N MDQS0_2_P MDQS0_2_N MDQS0_1_P MDQS0_1_N MDQS0_0_P MDQS0_0_N
MEM_A_DQS_P<7> MEM_A_DQS_N<7> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<0> MEM_A_DQS_N<0>
28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88 28 88
88 29 88 29 88 29 88 29 88 29 88 29 88 29 88 29 88 29 88 29 88 29 88 29 88 29 88 29 88 29
MEM_B_DQ<63> MEM_B_DQ<62> MEM_B_DQ<61> MEM_B_DQ<60> MEM_B_DQ<59> MEM_B_DQ<58> MEM_B_DQ<57> MEM_B_DQ<56> MEM_B_DQ<55> MEM_B_DQ<54> MEM_B_DQ<53> MEM_B_DQ<52> MEM_B_DQ<51> MEM_B_DQ<50> MEM_B_DQ<49> MEM_B_DQ<48> MEM_B_DQ<47> MEM_B_DQ<46> MEM_B_DQ<45> MEM_B_DQ<44> MEM_B_DQ<43> MEM_B_DQ<42> MEM_B_DQ<41> MEM_B_DQ<40> MEM_B_DQ<39> MEM_B_DQ<38> MEM_B_DQ<37> MEM_B_DQ<36> MEM_B_DQ<35> MEM_B_DQ<34> MEM_B_DQ<33> MEM_B_DQ<32> MEM_B_DQ<31> MEM_B_DQ<30> MEM_B_DQ<29> MEM_B_DQ<28> MEM_B_DQ<27> MEM_B_DQ<26> MEM_B_DQ<25> MEM_B_DQ<24> MEM_B_DQ<23> MEM_B_DQ<22> MEM_B_DQ<21> MEM_B_DQ<20> MEM_B_DQ<19> MEM_B_DQ<18> MEM_B_DQ<17> MEM_B_DQ<16> MEM_B_DQ<15> MEM_B_DQ<14> MEM_B_DQ<13> MEM_B_DQ<12> MEM_B_DQ<11> MEM_B_DQ<10> MEM_B_DQ<9> MEM_B_DQ<8> MEM_B_DQ<7> MEM_B_DQ<6> MEM_B_DQ<5> MEM_B_DQ<4> MEM_B_DQ<3> MEM_B_DQ<2> MEM_B_DQ<1> MEM_B_DQ<0>
AT4 AT3 AV2 AV3 AR4 AR3 AU2 AU3 AY4 AY3 BB3 BC3 AW4 AW3 BA3 BB2 BB5 BA5 BA8 BC8 BB4 BC4 BA7 AY8 BA9 BB10 BB12 AW12 BB8 BB9 AY12 BA12 BC32 AW32 BA35 AY36 BA32 BB32 BA34 AY35 BC36 AW36 BA39 AY40 BA36 BB36 BA38 AY39 BB40 AW40 AV42 AV41 BA40 BC40 AW42 AW41 AT40 AT41 AP41 AN40 AU40 AU41 AR41 AP42
MDQ1_63 MDQ1_62 MDQ1_61 MDQ1_60 MDQ1_59 MDQ1_58 MDQ1_57 MDQ1_56 MDQ1_55 MDQ1_54 MDQ1_53 MDQ1_52 MDQ1_51 MDQ1_50 MDQ1_49 MDQ1_48 MDQ1_47 MDQ1_46 MDQ1_45 MDQ1_44 MDQ1_43 MDQ1_42 MDQ1_41 MDQ1_40 MDQ1_39 MDQ1_38 MDQ1_37 MDQ1_36 MDQ1_35 MDQ1_34 MDQ1_33 MDQ1_32 MDQ1_31 MDQ1_30 MDQ1_29 MDQ1_28 MDQ1_27 MDQ1_26 MDQ1_25 MDQ1_24 MDQ1_23 MDQ1_22 MDQ1_21 MDQ1_20 MDQ1_19 MDQ1_18 MDQ1_17 MDQ1_16 MDQ1_15 MDQ1_14 MDQ1_13 MDQ1_12 MDQ1_11 MDQ1_10 MDQ1_9 MDQ1_8 MDQ1_7 MDQ1_6 MDQ1_5 MDQ1_4 MDQ1_3 MDQ1_2 MDQ1_1 MDQ1_0
MDQS1_7_P MDQS1_7_N MDQS1_6_P MDQS1_6_N MDQS1_5_P MDQS1_5_N MDQS1_4_P MDQS1_4_N MDQS1_3_P MDQS1_3_N MDQS1_2_P MDQS1_2_N MDQS1_1_P MDQS1_1_N MDQS1_0_P MDQS1_0_N
AT2 AT1 AY2 AY1 BB6 BA6 BA10 AY11 BB33 BA33 BB37 BA37 BA43 AY42 AT42 AT43
MEM_B_DQS_P<7> MEM_B_DQS_N<7> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<0> MEM_B_DQS_N<0>
29 88 29 88 29 88 29 88 29 88 29 88 29 88 29 88 29 88 29 88 29 88 29 88 29 88 29 88 29 88
OMIT
U1400
MCP79-TOPO-B
BGA (4 OF 11)
MEMORY CONTROL 0B
TP_MEM_A_CLK4P TP_MEM_A_CLK4N TP_MEM_A_CLK3P TP_MEM_A_CLK3N TP_MEM_A_CS_L<2> TP_MEM_A_CS_L<3> TP_MEM_A_ODT<2> TP_MEM_A_ODT<3> TP_MEM_A_CKE<2> TP_MEM_A_CKE<3>
24 16 8
MEMORY CONTROL 1B
TP_MEM_A_CLK5P TP_MEM_A_CLK5N
AU33 MCLK0B_2_P AU34 MCLK0B_2_N BB24 MCLK0B_1_P BC24 MCLK0B_1_N BA21 MCLK0B_0_P BB21 MCLK0B_0_N AU17 MCS0B_0# AR15 MCS0B_1# AN17 MODT0B_0 AN15 MODT0B_1 AV23 MCKE0B_0 AN25 MCKE0B_1
MCLK1B_2_P BA41 MCLK1B_2_N BB41 MCLK1B_1_P AY23 MCLK1B_1_N BA23 MCLK1B_0_P BA20 MCLK1B_0_N AY20 MCS1B_0# BC16 MCS1B_1# BA13 MODT1B_0 AY16 MODT1B_1 BC13 MCKE1B_0 BA30 MCKE1B_1 BA31
TP_MEM_B_CLK5P TP_MEM_B_CLK5N TP_MEM_B_CLK4P TP_MEM_B_CLK4N TP_MEM_B_CLK3P TP_MEM_B_CLK3N TP_MEM_B_CS_L<2> TP_MEM_B_CS_L<3> TP_MEM_B_ODT<2> TP_MEM_B_ODT<3> TP_MEM_B_CKE<2> TP_MEM_B_CKE<3>
=PP1V8R1V5_S0_MCP_MEM
R16101
40.2
1% 1/16W MF-LF 402 2
PP1V05_S0_MCP_PLL_CORE 24 17 mA 87 mA (A01) 12 mA 19 mA 39 mA MCP_MEM_COMP_VDD MCP_MEM_COMP_GND
T27 U28 U27 T28
+V_PLL_XREF_XS +V_PLL_DP +V_PLL_CORE +V_VPLL
MRESET0# AY32
MCP_MEM_RESET_L OUT TP or NC for DDR2.
30
88 88
AN41 MEM_COMP_VDD AM41 MEM_COMP_GND +VDD_MEM1 +VDD_MEM2 +VDD_MEM3 +VDD_MEM4 +VDD_MEM5 +VDD_MEM6 +VDD_MEM7 +VDD_MEM8 +VDD_MEM9 +VDD_MEM10 +VDD_MEM11 +VDD_MEM12 +VDD_MEM13 +VDD_MEM14 +VDD_MEM15 +VDD_MEM16 +VDD_MEM17 +VDD_MEM18 +VDD_MEM19 +VDD_MEM20 +VDD_MEM21 +VDD_MEM22 +VDD_MEM23 +VDD_MEM24 +VDD_MEM25 +VDD_MEM26 +VDD_MEM27 +VDD_MEM28 +VDD_MEM29 +VDD_MEM30 +VDD_MEM31 +VDD_MEM32 +VDD_MEM33 +VDD_MEM34 +VDD_MEM35 +VDD_MEM36 +VDD_MEM37 +VDD_MEM38 +VDD_MEM39 +VDD_MEM40 +VDD_MEM41 +VDD_MEM42 +VDD_MEM43 +VDD_MEM44 +VDD_MEM45 GND55 GND56 GND57 GND58 GND59 GND60 GND61 GND62 GND63 GND64 AM17 AM19 AM21 AM23 AM25 AM27 AM29 AN16 BC29 AN20 AN24 AT17 AP16 AN22 AP20 AP24 AV16 AR16 AR20 AR24 AW15 AP22 AP18 AU16 AN18 AU24 AT21 AY29 AV24 AU20 AU22 AW27 BC17 AV20 AY17 AY18 AM15 AU18 AY25 AY26 AW19 AW24 BC25 AL30 AM31 T33 T34 T35 T37 T38 T7 T9 U18 U20 U22
R16111
=PP1V8R1V5_S0_MCP_MEM 4771 mA (A01, DDR3)
8 16 24
40.2
1% 1/16W MF-LF 402 2
AA22 AP12 G30 P10 T10 T6 V10 V34 W5 AA39 AB22 AB7 AD22 AE20 AF24 AG24 AH35 AK7 AM28 AT25 AP30 AR36 AU10 F28 BC21 AY9 BC9 D34 F24 G32 H31 K7 M38 M5 M6 M7 M9 N39 N8 P33 P34 P37 P4 P40 P7 R36 R40 R43 R5 T18 T20 AK11 T24 T26
GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND21 GND22 GND23 GND24 GND25 GND26 GND27 GND28 GND29 GND30 GND31 GND32 GND33 GND34 GND35 GND36 GND37 GND38 GND39 GND40 GND41 GND42 GND43 GND44 GND45 GND46 GND47 GND48 GND49 GND50 GND51 GND52 GND53 GND54
MCP Memory Misc


D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
16
96
5
OMIT
4
U1400
MCP79-TOPO-B
BGA (5 OF 11)
9 9 9 9 9 9 9
IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN
9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9
PCI EXPRESS
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
9 9 9 9 9 9 9 9 9 9 9 9 9 9
IN
PEG_PRSNT_L MINI_CLKREQ_L PCIE_MINI_PRSNT_L FW_CLKREQ_L PCIE_FW_PRSNT_L EXCARD_CLKREQ_L PCIE_EXCARD_PRSNT_L

9 9
Int PU C9 PE0_PRSNT_16#
D5 PEB_CLKREQ#/GPIO_49 D9 PEB_PRSNT# Int PU
PE0_REFCLK_P E11 PE0_REFCLK_N D11 PE1_REFCLK_P G11 PE1_REFCLK_N F11 PE2_REFCLK_P J11 PE2_REFCLK_N J10 PE3_REFCLK_P G13 PE3_REFCLK_N F13 PE4_REFCLK_P J13 PE4_REFCLK_N H13 PE5_REFCLK_P L14 PE5_REFCLK_N K14 PE6_REFCLK_P N14 PE6_REFCLK_N M14 PEX_RST0# K11 PE1_TX0_P D8 PE1_TX0_N C8 PE1_TX1_P B8 PE1_TX1_N A8 PE1_TX2_P A7 PE1_TX2_N B7 PE1_TX3_P B6 PE1_TX3_N C6
PEG_CLK100M_P PEG_CLK100M_N PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N TP_PCIE_CLK100M_PE4P TP_PCIE_CLK100M_PE4N TP_PCIE_CLK100M_PE5P TP_PCIE_CLK100M_PE5N TP_PCIE_CLK100M_PE6P TP_PCIE_CLK100M_PE6N PCIE_RESET_L PCIE_MINI_R2D_C_P PCIE_MINI_R2D_C_N PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_EXCARD_R2D_C_P PCIE_EXCARD_R2D_C_N TP_PCIE_PE4_R2D_CP TP_PCIE_PE4_R2D_CN =PP1V05_S0_MCP_PEX_AVDD0 206 mA (A01, AVDD0 & 1)
OUT OUT
70 89 70 89
Int PU
31 31
IN IN
OUT OUT
31 89 31 89
36 9
IN IN
Int PU E8 PEC_CLKREQ#/GPIO_50 C10 PEC_PRSNT# Int PU Int PU M15 PED_CLKREQ#/GPIO_51 B10 PED_PRSNT# Int PU
L16 PEE_CLKREQ#/GPIO_16 L18 PEE_PRSNT#/GPIO_46
OUT OUT
36 89 36 89
32 32
IN IN
OUT OUT
32 89 32 89
TP_PE4_CLKREQ_L TP_PE4_PRSNT_L AUD_IP_PERIPHERAL_DET GMUX_JTAG_TCK_L TP_MCP_GPIO_18 GMUX_JTAG_TDO PCIE_WAKE_L PCIE_MINI_D2R_P PCIE_MINI_D2R_N PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_EXCARD_D2R_P PCIE_EXCARD_D2R_N
Int PU Int PU
9 9
Int PU
9 83
IN OUT
M16 PEF_CLKREQ#/GPIO_17 M18 PEF_PRSNT#/GPIO_47

M17 PEG_CLKREQ#/GPIO_18 M19 PEG_PRSNT#/GPIO_48
Int PU
Int PU
IN
32 31 23
IN
F17 PE_WAKE# Int K9 PE1_RX0_P J9 PE1_RX0_N H9 PE1_RX1_P G9 PE1_RX1_N F9 PE1_RX2_P E9 PE1_RX2_N H7 PE1_RX3_P G7 PE1_RX3_N
Int PU PU (S5)
OUT
9 26
89 31 89 31
IN IN IN IN IN IN
9 9

9 9
31 89 31 89
89 36
36 89 36 89
89 36
89 32 7 89 32 7
32 89 32 89
TP_PCIE_PE4_D2RP TP_PCIE_PE4_D2RN =PP1V05_S0_MCP_PEX_DVDD0 57 mA (A01, DVDD0 & 1)
Minimum 1.025V for Gen2 support
T17 W19 U17 V19 W16 W17 W18 U16
+DVDD0_PEX1 +DVDD0_PEX2 +DVDD0_PEX3 +DVDD0_PEX4 +DVDD0_PEX5 +DVDD0_PEX6 +DVDD0_PEX7 +DVDD0_PEX8
=PP1V05_S0_MCP_PEX_DVDD1
T19 +DVDD1_PEX1 U19 +DVDD1_PEX2
+AVDD0_PEX1 +AVDD0_PEX2 +AVDD0_PEX3 +AVDD0_PEX4 +AVDD0_PEX5 +AVDD0_PEX6 +AVDD0_PEX7 +AVDD0_PEX8 +AVDD0_PEX9 +AVDD0_PEX10 +AVDD0_PEX11 +AVDD0_PEX12 +AVDD0_PEX13
Y12 AA12 AB12 M12 P12 R12 N12 T12 U12 AC12 AD12 V12 W12
24
PP1V05_S0_MCP_PLL_PEX 84 mA (A01) MCP_PEX_CLK_COMP NO STUFF
T16 +V_PLL_PEX +AVDD1_PEX1 M13 +AVDD1_PEX2 N13 +AVDD1_PEX3 P13
=PP1V05_S0_MCP_PEX_AVDD1
89
A11 PEX_CLK_COMP
MCP PCIe Interfaces

R1710
2.37K
1% 1/16W MF-LF 2 402
If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX. If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.

PLACEMENT_NOTE=Place within 12.7mm of U1400
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
17
96
=PEG_D2R_P<0> =PEG_D2R_N<0> =PEG_D2R_P<1> =PEG_D2R_N<1> =PEG_D2R_P<2> =PEG_D2R_N<2> =PEG_D2R_P<3> =PEG_D2R_N<3> =PEG_D2R_P<4> =PEG_D2R_N<4> =PEG_D2R_P<5> =PEG_D2R_N<5> =PEG_D2R_P<6> =PEG_D2R_N<6> =PEG_D2R_P<7> =PEG_D2R_N<7> =PEG_D2R_P<8> =PEG_D2R_N<8> =PEG_D2R_P<9> =PEG_D2R_N<9> =PEG_D2R_P<10> =PEG_D2R_N<10> =PEG_D2R_P<11> =PEG_D2R_N<11> =PEG_D2R_P<12> =PEG_D2R_N<12> =PEG_D2R_P<13> =PEG_D2R_N<13> =PEG_D2R_P<14> =PEG_D2R_N<14> =PEG_D2R_P<15> =PEG_D2R_N<15>
F7 E7 D7 C7 E6 F6 E5 F5 E4 E3 C3 D3 G5 H5 J7 J6 J5 J4 L11 L10 L9 L8 L7 L6 N11 N10 N9 P9 N7 N6 N5 N4
PE0_RX0_P PE0_RX0_N PE0_RX1_P PE0_RX1_N PE0_RX2_P PE0_RX2_N PE0_RX3_P PE0_RX3_N PE0_RX4_P PE0_RX4_N PE0_RX5_P PE0_RX5_N PE0_RX6_P PE0_RX6_N PE0_RX7_P PE0_RX7_N PE0_RX8_P PE0_RX8_N PE0_RX9_P PE0_RX9_N PE0_RX10_P PE0_RX10_N PE0_RX11_P PE0_RX11_N PE0_RX12_P PE0_RX12_N PE0_RX13_P PE0_RX13_N PE0_RX14_P PE0_RX14_N PE0_RX15_P PE0_RX15_N
PE0_TX0_P PE0_TX0_N PE0_TX1_P PE0_TX1_N PE0_TX2_P PE0_TX2_N PE0_TX3_P PE0_TX3_N PE0_TX4_P PE0_TX4_N PE0_TX5_P PE0_TX5_N PE0_TX6_P PE0_TX6_N PE0_TX7_P PE0_TX7_N PE0_TX8_P PE0_TX8_N PE0_TX9_P PE0_TX9_N PE0_TX10_P PE0_TX10_N PE0_TX11_P PE0_TX11_N PE0_TX12_P PE0_TX12_N PE0_TX13_P PE0_TX13_N PE0_TX14_P PE0_TX14_N PE0_TX15_P PE0_TX15_N
C5 D4 C4 B4 A4 A3 B3 B2 C1 D1 D2 E1 E2 F2 F3 F4 G3 H4 H3 H2 H1 J1 J2 J3 K2 K3 L4 L3 M4 M3 M2 M1
=PEG_R2D_C_P<0> =PEG_R2D_C_N<0> =PEG_R2D_C_P<1> =PEG_R2D_C_N<1> =PEG_R2D_C_P<2> =PEG_R2D_C_N<2> =PEG_R2D_C_P<3> =PEG_R2D_C_N<3> =PEG_R2D_C_P<4> =PEG_R2D_C_N<4> =PEG_R2D_C_P<5> =PEG_R2D_C_N<5> =PEG_R2D_C_P<6> =PEG_R2D_C_N<6> =PEG_R2D_C_P<7> =PEG_R2D_C_N<7> =PEG_R2D_C_P<8> =PEG_R2D_C_N<8> =PEG_R2D_C_P<9> =PEG_R2D_C_N<9> =PEG_R2D_C_P<10> =PEG_R2D_C_N<10> =PEG_R2D_C_P<11> =PEG_R2D_C_N<11> =PEG_R2D_C_P<12> =PEG_R2D_C_N<12> =PEG_R2D_C_P<13> =PEG_R2D_C_N<13> =PEG_R2D_C_P<14> =PEG_R2D_C_N<14> =PEG_R2D_C_P<15> =PEG_R2D_C_N<15>
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9
OMIT
U1400
MCP79-TOPO-B
BGA (6 OF 11)
+3.3V_DUAL_RMGT1 J24 +3.3V_DUAL_RMGT2 K24
=PP3V3_ENET_MCP_RMGT 8 18 24 83 mA (A01) =PP1V05_ENET_MCP_RMGT 8 24 131 mA (A01)
D
91 33 91 33 91 33 91 33
LAN
D
Network Interface Select
Interface ENET_TXD<0>
+V_DUAL_RMGT1 U23 +V_DUAL_RMGT2 V23 MII_VREF E28 RGMII_TXD0 RGMII_TXD1 RGMII_TXD2 RGMII_TXD3 B24 C24 C25 D25
IN IN IN IN IN IN IN IN IN
ENET_RXD<0> ENET_RXD<1> ENET_RXD<2> ENET_RXD<3> ENET_CLK125M_RXCLK ENET_RX_CTRL =MCP_MII_RXER =MCP_MII_COL =MCP_MII_CRS TP_ENET_INTR_L
C23 B23 E24 A24
RGMII_RXD0 RGMII_RXD1 RGMII_RXD2 RGMII_RXD3
MCP_MII_VREF ENET_TXD<0> ENET_TXD<1> ENET_TXD<2> ENET_TXD<3> ENET_CLK125M_TXCLK ENET_TX_CTRL ENET_MDC ENET_MDIO TP_ENET_PWRDWN_L MCP_CLK25M_BUF0_R ENET_RESET_L
IN OUT OUT OUT OUT OUT OUT OUT BI
24
33 91 33 91 33 91 33 91
91 33 91 33
A23 RGMII_RXC/MII_RXCLK C22 RGMII_RXCTL/MII_RXDV F23 MII_RXER/GPIO_36 B26 MII_COL/GPIO_20/MSMB_DATA B22 MII_CRS/GPIO_21/MSMB_CLK J22 RGMII_INTR/GPIO_35
RGMII MII
1 0
24 18 8
9 9
RGMII_TXCTL/MII_TXEN C26
33 91
R18101
49.9
1% 1/16W MF-LF 402 2
24
RGMII_MDC D21 RGMII_MDIO C21

RGMII_PWRDWN/GPIO_37 G23
33 91 33 91
PP1V05_ENET_MCP_PLL_MAC 5 mA (A01) MCP_MII_COMP_VDD MCP_MII_COMP_GND
NOTE: All Apple products set strap to MII, RGMII products will enable feature via software. This avoids a leakage issue since MCP79 requires a S5 pull-up. =PP3V3_S0_MCP_GPIO
8 19 21
T23 +V_DUAL_MACPLL BUF_25MHZ E23

OUT
34 91
91 91
C27 MII_COMP_VDD B27 MII_COMP_GND
MII_RESET# J23
OUT
33 91
R18111
49.9
1% 1/16W MF-LF 402 2
25 25
TP_MCP_RGB_DAC_RSET TP_MCP_RGB_DAC_VREF
C39 RGB_DAC_RSET B38 RGB_DAC_VREF
+V_RGB_DAC J32 +V_TV_DAC K32 DDC_CLK0 B31 DDC_DATA0 A31
PP3V3_S0_MCP_DAC 25 103 mA 206 mA (A01) 103 mA MCP_DDC_CLK0 MCP_DDC_DATA0 TP_MCP_RGB_RED TP_MCP_RGB_GREEN TP_MCP_RGB_BLUE TP_MCP_RGB_HSYNC TP_MCP_RGB_VSYNC CRT_IG_R_C_PR CRT_IG_G_Y_Y CRT_IG_B_COMP_PB CRT_IG_HSYNC CRT_IG_VSYNC LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N LVDS_IG_A_DATA_P<0> LVDS_IG_A_DATA_N<0> LVDS_IG_A_DATA_P<1> LVDS_IG_A_DATA_N<1> LVDS_IG_A_DATA_P<2> LVDS_IG_A_DATA_N<2> LVDS_IG_A_DATA_P<3> LVDS_IG_A_DATA_N<3> LVDS_IG_B_CLK_P LVDS_IG_B_CLK_N LVDS_IG_B_DATA_P<0> LVDS_IG_B_DATA_N<0> LVDS_IG_B_DATA_P<1> LVDS_IG_B_DATA_N<1> LVDS_IG_B_DATA_P<2> LVDS_IG_B_DATA_N<2> LVDS_IG_B_DATA_P<3> LVDS_IG_B_DATA_N<3> LVDS_IG_DDC_CLK LVDS_IG_DDC_DATA =MCP_HDMI_DDC_CLK =MCP_HDMI_DDC_DATA MCP_IFPAB_RSET MCP_IFPAB_VPROBE
1
R18601
100K
5% 1/16W MF-LF 402 2
R1861
100K
5% 1/16W MF-LF 2 402
C
89 25 89 25
RGB ONLY
OUT OUT
MCP_TV_DAC_RSET MCP_TV_DAC_VREF
E36 TV_DAC_RSET A35 TV_DAC_VREF
RGB_DAC_RED B39 RGB_DAC_GREEN A39 RGB_DAC_BLUE B40 RGB_DAC_HSYNC A40 RGB_DAC_VSYNC A41 A36 B36 C36
RGB DAC Disable:

25 25 25
Okay to float all RGB_DAC signals. DDC_CLK0/DDC_DATA0 pull-ups still required.
25 25
20 8
=PP3V3_S5_MCP_GPIO
R1820
47K
25 25
IN OUT
MCP_CLK27M_XTALIN MCP_CLK27M_XTALOUT
C38 XTALIN_TV D38 XTALOUT_TV
TV C Y Comp
/ / / /
Component Pr TV_DAC_RED Y TV_DAC_GREEN Pb TV_DAC_BLUE
TV DAC Disable:
OUT OUT OUT OUT OUT
25 89 25 89 25 89
5% 1/16W MF-LF 402 2

44
TV_DAC_HSYNC/GPIO_44 D36 TV_DAC_VSYNC/GPIO_45 C37
Okay to float all TV_DAC signals. Okay to float XTALIN_TV and XTALOUT_TV. DDC_CLK0/DDC_DATA0 pull-ups still required.
25 89 25 89
BI
80
IN
LPCPLUS_GPIO DP_IG_CA_DET LVDS_IG_BKL_PWM LVDS_IG_BKL_ON LVDS_IG_PANEL_PWR =MCP_HDMI_TXC_P =MCP_HDMI_TXC_N =MCP_HDMI_TXD_P<0> =MCP_HDMI_TXD_N<0> =MCP_HDMI_TXD_P<1> =MCP_HDMI_TXD_N<1> =MCP_HDMI_TXD_P<2> =MCP_HDMI_TXD_N<2> DP_IG_AUX_CH_P DP_IG_AUX_CH_N =DVI_HPD_GMUX_INT (See below) =MCP_HDMI_HPD =PP3V3R1V8_S0_MCP_IFP_VDD 190 mA (A01, 1.8V) PP3V3_S0_MCP_VPLL 16 mA (A01) 8 mA 8 mA (See below)
E16 GPIO_6/FERR*/IGPU_GPIO_6 B15 GPIO_7/NFERR*/IGPU_GPIO_7 G39 LCD_BKL_CTL/GPIO_57 E37 LCD_BKL_ON/GPIO_59 F40 LCD_PANEL_PWR/GPIO_58 D35 HDMI_TXC_P/ML0_LANE3_P E35 HDMI_TXC_N/ML0_LANE3_N G35 F35 F33 G33 J33 H33 HDMI_TXD0_P/ML0_LANE2_P HDMI_TXD0_N/ML0_LANE2_N HDMI_TXD1_P/ML0_LANE1_P HDMI_TXD1_N/ML0_LANE1_N HDMI_TXD2_P/ML0_LANE0_P HDMI_TXD2_N/ML0_LANE0_N
IFPA_TXC_P B35 IFPA_TXC_N C35 IFPA_TXD0_P IFPA_TXD0_N IFPA_TXD1_P IFPA_TXD1_N IFPA_TXD2_P IFPA_TXD2_N IFPA_TXD3_P IFPA_TXD3_N B32 A32 D32 C32 D33 C33 B34 C34
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
83 89 83 89
83 89 83 89 83 89 83 89 83 89 83 89 9 89 9 89
OUT OUT OUT
Interface Mode MCP Signal =MCP_HDMI_TXC_P/N =MCP_HDMI_TXD_P/N<0> =MCP_HDMI_TXD_P/N<1> =MCP_HDMI_TXD_P/N<2> =MCP_HDMI_DDC_CLK =MCP_HDMI_DDC_DATA =MCP_HDMI_HPD DP_IG_AUX_CH_P/N TMDS/HDMI TMDS_IG_TXC_P/N TMDS_IG_TXD_P/N<0> TMDS_IG_TXD_P/N<1> TMDS_IG_TXD_P/N<2> TMDS_IG_DDC_CLK TMDS_IG_DDC_DATA TMDS_IG_HPD TP_DP_IG_AUX_CHP/N DisplayPort DP_IG_ML_P/N<3> DP_IG_ML_P/N<2> DP_IG_ML_P/N<1> DP_IG_ML_P/N<0> DP_IG_DDC_CLK DP_IG_DDC_DATA DP_IG_HPD DP_IG_AUX_CH_P/N
9 9
9 9
OUT OUT OUT OUT OUT OUT OUT OUT
9 9 9 9 9 9
WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

IFPB_TXC_P L31 IFPB_TXC_N K31 IFPB_TXD4_P IFPB_TXD4_N IFPB_TXD5_P IFPB_TXD5_N IFPB_TXD6_P IFPB_TXD6_N IFPB_TXD7_P IFPB_TXD7_N J29 H29 L29 K29 L30 K30 N30 M30
9 89 9 89
83 89 83 89 83 89 83 89 83 89 83 89 9 89 9 89
NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used. NOTE: 20K pull-down required on DP_HPD_DET. NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used. NOTE: HDMI port requires level-shifting. IFP interface can be used to provide HDMI or dual-channel TMDS without level-shifters. LVDS: Power +VDD_IFPx at 1.8V Dual-channel TMDS: Power +VDD_IFPx at 3.3V
89 80 89 80
OUT OUT
D43 DP_AUX_CH0_P C43 DP_AUX_CH0_N C31 HPLUG_DET2/GPIO_22 F31 HPLUG_DET3
9 9
IN IN
25 8
M27 +VDD_IFPA M26 +VDD_IFPB M28 +V_PLL_IFPAB M29 +V_PLL_HDMI T25 +VDD_HDMI J31 HDMI_RSET J30 HDMI_VPROBE
25
DDC_CLK2/GPIO_23 C30 DDC_DATA2/GPIO_24 B30 DDC_CLK3 D31 DDC_DATA3 E31 IFPAB_RSET E32 IFPAB_VPROBE G31
OUT BI
80 80
OUT BI
9 9
25 8
89 25 89 25
OUT OUT
=PP1V05_S0_MCP_HDMI_VDD 95 mA (A01) MCP_HDMI_RSET MCP_HDMI_VPROBE
OUT OUT
25 89 25 89
R1850
10K
GPIOs 57-59 (if LCD panel is used): In MCP79 these pins have undocumented internal pull-ups (~10K to 3.3V S0). To ensure pins are low by default, pull-downs (1K or stronger) must be used.
5% 1/16W MF-LF 2 402
MCP Ethernet & Graphics

=DVI_HPD_GMUX_INT: Alias to DVI_HPD for systems using IFP for DVI. Alias to GMUX_INT for systems with GMUX. Alias to HPLUG_DET2 for other systems. Pull-down (20k) required in all cases.
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
18
96
RGMII_TXC/MII_TXCLK D24
33 91
FLAT PANEL
DACS
6
OMIT
1
=PP3V3_S0_MCP_GPIO
2 5% 1/16W MF-LF 402 1/16W 1/16W 1/16W 1/16W MF-LF MF-LF MF-LF MF-LF 402 402 402 402 2 2 2 2
U1400
MCP79-TOPO-B
BGA (7 OF 11)
90 19 90 19 19 59 9 19 19
21 18 8
MCP_RS232_SOUT_L PCI_REQ0_L PCI_REQ1_L CRTMUX_SEL_TV_L MCP_RS232_SIN_L
R1989 R1990 R1991 R1992 R1994
8.2K 8.2K 8.2K 8.2K 8.2K
1 1 1 1 1
OUT OUT IN
PCI_REQ0_L PCI_REQ1_L CRTMUX_SEL_TV_L AUD_IPHS_SWITCH_EN MCP_RS232_SIN_L MCP_DEBUG<0> MCP_DEBUG<1> MCP_DEBUG<2> MCP_DEBUG<3> MCP_DEBUG<4> MCP_DEBUG<5> MCP_DEBUG<6> MCP_DEBUG<7> TP_PCI_AD<8> TP_PCI_AD<9> TP_PCI_AD<10> TP_PCI_AD<11> TP_PCI_AD<12> TP_PCI_AD<13> TP_PCI_AD<14> TP_PCI_AD<15> TP_PCI_AD<16> TP_PCI_AD<17> TP_PCI_AD<18> TP_PCI_AD<19> TP_PCI_AD<20> TP_PCI_AD<21> TP_PCI_AD<22> TP_PCI_AD<23> TP_PCI_AD<24> TP_PCI_AD<25> TP_PCI_AD<26> TP_PCI_AD<27> TP_PCI_AD<28> TP_PCI_AD<29> TP_PCI_AD<30> TP_PCI_AD<31> TP_PCI_INTW_L TP_PCI_INTX_L TP_PCI_INTY_L TP_PCI_INTZ_L TP_PCI_TRDY_L
T2 V9 T3 U9 T4 AC3 AE10 AC4 AE11 AB3 AC6 AB2 AC7 AC8 AA2 AC9 AC10 AC11 AA1 AA5 Y5 W3 W6 W4 W7 V3 W8 V2 W9 U3 W11 U2 U5 U1 U6 T5 U7 P2 N3 N2 N1
PCI_REQ0# PCI_REQ1#/FANRPM2 PCI_REQ2#/GPIO_40/RS232_DSR# PCI_REQ3#/GPIO_38/RS232_CTS# PCI_REQ4#/GPIO_52/RS232_SIN# PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3 PCI_AD4 PCI_AD5 PCI_AD6 PCI_AD7 PCI_AD8 PCI_AD9 PCI_AD10 PCI_AD11 PCI_AD12 PCI_AD13 PCI_AD14 PCI_AD15 PCI_AD16 PCI_AD17 PCI_AD18 PCI_AD19 PCI_AD20 PCI_AD21 PCI_AD22 PCI_AD23 PCI_AD24 PCI_AD25 PCI_AD26 PCI_AD27 PCI_AD28 PCI_AD29 PCI_AD30 PCI_AD31 PCI_INTW# PCI_INTX# PCI_INTY# PCI_INTZ#
PCI_GNT0# PCI_GNT1#/FANCTL2 PCI_GNT2#/GPIO_41/RS232_DTR# PCI_GNT3#/GPIO_39/RS232_RTS# PCI_GNT4#/GPIO_53/RS232_SOUT# PCI_CBE0# PCI_CBE1# PCI_CBE2# PCI_CBE3# PCI_DEVSEL# PCI_FRAME# PCI_IRDY# PCI_PAR PCI_PERR#/GPIO_43/RS232_DCD# PCI_SERR# PCI_STOP#
R3 U10 R4 U11 P3 AA3 AA6 AA11 W10 AA9 Y4 AA10 Y1 AB9 AA7 Y2
TP_PCI_GNT0_L TP_PCI_GNT1_L GMUX_JTAG_TMS GMUX_JTAG_TDI MCP_RS232_SOUT_L TP_PCI_C_BE_L<0> TP_PCI_C_BE_L<1> TP_PCI_C_BE_L<2> TP_PCI_C_BE_L<3> TP_PCI_DEVSEL_L TP_PCI_FRAME_L TP_PCI_IRDY_L TP_PCI_PAR TP_PCI_PERR_L TP_PCI_SERR_L TP_PCI_STOP_L PM_LATRIGGER_L
90 19 90 19
OUT OUT OUT
9 19 9 19 19
5% 5% 5% 5%
90 13 90 13 90 13 90 13 90 13 90 13 90 13 90 13
BI BI BI BI BI BI BI BI
PCI_PME#/GPIO_30 T1
OUT
13 23
Int PU (S5)
PCI_RESET0# R10 PCI_RESET1# R11
MEM_VTT_EN_R TP_PCI_RESET1_L
OUT
26
PCI_CLK0 R6 PCI_CLK1 R7 PCI_CLK2 R8
90
TP_PCI_CLK0 TP_PCI_CLK1 PCI_CLK33M_MCP_R

1
R1910
22
5% 1/16W MF-LF 2 402
PCI_CLKIN R9
90
PCI_CLK33M_MCP
PLACEMENT_NOTE=Place close to pin R8
LPC_FRAME# AD4 LPC_PWRDWN#/GPIO_54/EXT_NMI# AE12
44
LPC_FRAME_R_L LPC_PWRDWN_L LPC_RESET_L LPC_AD_R<0> LPC_AD_R<1> LPC_AD_R<2> LPC_AD_R<3> LPC_CLK33M_SMC_R
R1960
22
2 5% 1/16W MF-LF 402
LPC_FRAME_L
OUT OUT OUT
42 44 83 90 42 44
Y3 PCI_TRDY# AD11 PCI_CLKRUN#/GPIO_42 AE2 LPC_DRQ1#/GPIO_19 Int AE1 LPC_DRQ0# Int PU AE6 LPC_SERIRQ Int PU
LPC
LPC_RESET0# AE5 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 AD3 AD2 AD1 AD5
26 83 90
44 42
IN
PM_CLKRUN_L FW_PME_L TP_LPC_DRQ0_L LPC_SERIRQ
36
IN
PU
R1950 R1951 R1952 R1953
22 22 22 22
1 1 1 1
2 2 2 2
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF
402 402 402 402
LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3>
BI BI BI BI
42 44 83 90 42 44 83 90 42 44 83 90 42 44 83 90
44 42
BI
LPC_CLK0 AE9
1
OUT
26 90
U24 U26 U39 U4 U8 V16 V17 V18 V20 V22 V24 V26 V27 V28 V33 V37 V4 V40 V7 W20 W22 W24 W36 W40 W43 Y16 Y17 Y18 Y19 Y20 Y22 Y24 Y25
GND65 GND66 GND67 GND68 GND69 GND70 GND71 GND72 GND73 GND74 GND75 GND76 GND77 GND78 GND79 GND80 GND81 GND82 GND83 GND84 GND85 GND86 GND87 GND88 GND89 GND90 GND91 GND92 GND93 GND94 GND95 GND96 GND97
GND98 GND99 GND100 GND101 GND102 GND103 GND104 GND105 GND106 GND107 GND108 GND109 GND110 GND111 GND112 GND113 GND114 GND115 GND116 GND117 GND118 GND119 GND120 GND121 GND122 GND123 GND124 GND125 GND126 GND127 GND128 GND129 GND130
Y26 Y27 AB18 H34 AB20 AB21 AB23 AB24 AB25 AB26 AB27 AB28 AB34 AB37 AB4 AB40 AC22 AC36 AC40 AB33 AC5 AD16 AD17 AD18 AD19 AD20 AD24 AD25 AD26 AD27 AD28 AD33 AD34
R1961
10K
5% 1/16W MF-LF 2 402
Strap for Boot ROM Selection (See HDA_SDOUT)
MCP PCI & LPC


D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
19
96
GND
PCI
5
OMIT
4
U1400
MCP79-TOPO-B
BGA (8 OF 11)
89 39 89 39
OUT OUT
SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N SATA_HDD_D2R_N SATA_HDD_D2R_P
AJ7 SATA_A0_TX_P AJ6 SATA_A0_TX_N AJ5 SATA_A0_RX_N AJ4 SATA_A0_RX_P
USB0_P C29 USB0_N D29 USB1_P C28 USB1_N D28 USB2_P A28 USB2_N B28
89 39 89 39
IN IN
D
89 39 89 39
OUT OUT
SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N SATA_ODD_D2R_N SATA_ODD_D2R_P
AJ11 SATA_A1_TX_P AJ10 SATA_A1_TX_N AJ9 SATA_A1_RX_N AK9 SATA_A1_RX_P
USB3_P F29 USB3_N G29 USB4_P K27 USB4_N L27 USB5_P J26 USB5_N J27 USB6_P F27 USB6_N G27
89 39 89 39
IN IN
BI BI
31 90 31 90
SATA USB
TP_SATA_C_D2RN TP_SATA_C_D2RP
AJ2 SATA_B0_RX_N AJ1 SATA_B0_RX_P
USB7_P D27 USB7_N E27 USB8_P K25 USB8_N L25 USB9_P H25 USB9_N J25 USB10_P F25 USB10_N G25
BI BI
40 90 40 90
TP_SATA_D_R2D_CP TP_SATA_D_R2D_CN TP_SATA_D_D2RN TP_SATA_D_D2RP
AM4 SATA_B1_TX_P AL3 SATA_B1_TX_N AL4 SATA_B1_RX_N AK3 SATA_B1_RX_P
BI BI
32 90 32 90
=PP3V3_S5_MCP_GPIO
8 18
BI BI
9 90 9 90
R2051
8.2K
R2053
8.2K
TP_USB_10P TP_USB_10N TP_USB_11P TP_USB_11N
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
TP_SATA_E_R2D_CP TP_SATA_E_R2D_CN TP_SATA_E_D2RN TP_SATA_E_D2RP
AN1 SATA_C0_TX_P AM1 SATA_C0_TX_N AM2 SATA_C0_RX_N AM3 SATA_C0_RX_P
USB11_P K23 USB11_N L23
R20501
8.2K
5% 1/16W MF-LF 402 2
R20521
8.2K
5% 1/16W MF-LF 402 2
C
USB_EXTA_OC_L USB_EXTB_OC_L USB_EXTC_OC_L EXCARD_OC_L
IN IN IN IN
32 43 40 40
TP_SATA_F_R2D_CP TP_SATA_F_R2D_CN TP_SATA_F_D2RN TP_SATA_F_D2RP
AP3 SATA_C1_TX_P AP2 SATA_C1_TX_N AN3 SATA_C1_RX_N AN2 SATA_C1_RX_P
USB_OC0#/GPIO_25 USB_OC1#/GPIO_26 USB_OC2#/GPIO_27/MGPIO USB_OC3#/GPIO_28/MGPIO
L21 K21 J21 H21
+V_PLL_USB L28
PP3V3_S0_MCP_PLL_USB 19 mA (A01)
90
24
USB_RBIAS_GND A27
MCP_USB_RBIAS_GND
TP_MCP_SATALED_L
24
R20601
E12 SATA_LED# AE16 +V_PLL_SATA GND131 GND132 GND133 GND134 GND135 GND136 GND137 GND138 GND139 GND140 GND141 GND142 GND143 GND144 GND145 GND146 GND147 GND148 GND149 GND150 GND151 GND152 GND153 GND154 GND155 GND156 GND157 GND158 GND159 GND160 AD35 AD37 AD38 AE22 AE24 AE39 AE4 AD6 AF16 AF17 AF18 AF20 AF22 AF26 AF27 AF28 AF33 AF34 AF37 AF40 AG18 AG20 AG22 AG26 AG36 AG40 AH18 AH20 AH22 AH24
806
1% 1/16W MF-LF 402 2
PP1V05_S0_MCP_PLL_SATA 84 mA (A01) =PP1V05_S0_MCP_SATA_DVDD0 43 mA (A01, DVDD0 & 1)

9
AF19 AG16 AG17 AG19
+DVDD0_SATA1 +DVDD0_SATA2 +DVDD0_SATA3 +DVDD0_SATA4
=PP1V05_S0_MCP_SATA_DVDD1
AH17 +DVDD1_SATA1 AH19 +DVDD1_SATA2
B
8
=PP1V05_S0_MCP_SATA_AVDD0 127 mA (A01, AVDD0 & 1)
AJ12 AN11 AK12 AK13 AL12 AM11 AM12 AN12 AL13 AN14 AL14 AM13 AM14
+AVDD0_SATA1 +AVDD0_SATA2 +AVDD0_SATA3 +AVDD0_SATA4 +AVDD0_SATA5 +AVDD0_SATA6 +AVDD0_SATA7 +AVDD0_SATA8 +AVDD0_SATA9 +AVDD1_SATA1 +AVDD1_SATA2 +AVDD1_SATA3 +AVDD1_SATA4
=PP1V05_S0_MCP_SATA_AVDD1
89
MCP_SATA_TERMP
AE3 SATA_TERMP
R2010
2.49K If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA. If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.
1% 1/16W MF-LF 2 402
MCP SATA & USB


D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
20
96
TP_SATA_C_R2D_CP TP_SATA_C_R2D_CN
AK2 SATA_B0_TX_P AJ3 SATA_B0_TX_N
External A USB_EXTA_P USB_EXTA_N AirPort (PCIe Mini-Card) USB_MINI_P USB_MINI_N External D USB_EXTD_P USB_EXTD_N Camera USB_CAMERA_P USB_CAMERA_N IR USB_IR_P USB_IR_N Geyser Trackpad/Keyboard USB_TPAD_P USB_TPAD_N Bluetooth USB_BT_P USB_BT_N External B USB_EXTB_P USB_EXTB_N ExpressCard USB_EXCARD_P USB_EXCARD_N External C USB_EXTC_P USB_EXTC_N
BI BI
40 90 40 90
BI BI
9 90 9 90
BI BI
9 90 9 90
BI BI
31 90 31 90
BI BI
41 90 41 90
BI BI
50 90 50 90
OMIT
U1400
MCP79-TOPO-B
BGA (9 OF 11) +V_DUAL_HDA1 J16 +V_DUAL_HDA2 K16
1
=PP3V3R1V5_S0_MCP_HDA 8 21 24 7 mA (A01)
R2160
8.2K
D
90 54
HDA
5% 1/16W MF-LF 2 402
R2170
HDA_SDOUT_R
1
D
HDA_SDOUT
OUT
54 90
IN
HDA_SDIN0
G15 HDA_SDATA_IN0
HDA_SDATA_OUT F15
22
90 21
Int PD TP_MLB_RAM_SIZE
J14 HDA_SDATA_IN1/GPIO_2/PS2_KB_CLK
R2171
HDA_BITCLK E15
90 21
HDA_BIT_CLK_R
22
5% 1/16W MF-LF 402
BIOS Boot Select

HDA_BIT_CLK
OUT
9 90
I/F LPC PCI SPI0 SPI1
HDA_SDOUT 0 0 1 1
LPC_FRAME# 0 1 0 1
Int PD =PP3V3R1V5_S0_MCP_HDA
1
5% 1/16W MF-LF 402
R2172
1
24 21 8
TP_MLB_RAM_VENDOR (MXM_OK for MXM systems)
J15 HDA_SDATA_IN2/GPIO_3/PS2_KB_DATA
HDA_RESET# K15
90 21
HDA_RST_R_L
22
HDA_RST_L
OUT
54 90
Int PD
R2110
49.9
HDA_SYNC L15
90 21
R2173
HDA_SYNC_R
1
22
HDA_SYNC
1% 1/16W MF-LF 2 402

90
OUT
54 90
5% 1/16W MF-LF 402
MCP_HDA_PULLDN_COMP
A15 HDA_PULLDN_COMP
HDA_DOCK_EN#/GPIO_4/PS2_MS_CLK K17 HDA_DOCK_RST#/GPIO_5/PS2_MS_DATA L17 SLP_S3# G17 SLP_RMGT# J17 SLP_S5# H17
MCP_GPIO_4 AUD_I2C_INT_L PM_SLP_S3_L PM_SLP_RMGT_L PM_SLP_S4_L MCP_THMDIODE_P MCP_THMDIODE_N MCP_VID<0> MCP_VID<1> MCP_VID<2> MCP_SPKR SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA AP_PWR_EN MEM_EVENT_L ODD_PWR_EN_L SMC_IG_THROTTLE_L ARB_DETECT MCP_CPUVDD_EN SPI_CS0_R_L SPI_CLK_R SPI_MISO SPI_MOSI_R PM_CLK32K_SUSCLK_R TP_MCP_BUF_SIO_CLK MCP_TEST_MODE_EN
1
SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L

21
IN
21 59
24
PP1V05_S0_MCP_PLL_NV 37 mA (A01) 20 mA 17 mA =SPI_CS1_R_L_USE_MLB SMC_ADAPTER_EN TP_SB_A20GATE TP_MCP_KBDRSTIN_L SMC_WAKE_SCI_L SMC_RUNTIME_SCI_L SM_INTRUDER_L
AE18 +V_PLL_NV_H AE17 +V_PLL_SP_SPREF
OUT OUT OUT
7 34 37 42 44 68 81 83 9 40 42 43 68
R1961 and R2160 selects SPI0 ROM by default, LPC+ debug card pulls LPC_FRAME# high for SPI1 ROM override. NOTE: MCP79 does not support FWH, only LPC ROMs. So Apple designs will not use LPC for BootROM override. =PP3V3_S0_MCP BOOT_MODE_SAFE
1
8 22 24
26 22
PP3V3_G3_RTC
44 9 43 42 37 34
OUT IN
L24 GPIO_1/PWRDN_OK/SPI_CS1 L26 GPIO_12/SUS_STAT#/ACCLMTR K13 L13 C19 C18 A20GATE Int PU KBRDRSTIN# Int PU SIO_PME# Int PU (S5) EXT_SMI/GPIO_32# Int PU
THERM_DIODE_P B11 THERM_DIODE_N C11
OUT OUT
48 95 48 95
R21201
R2121
49.9K
42 23 42 23
NOTE: MCP79 rev A01 does not support SPI1 option. Rev B01 will.
49.9K
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 2 402
IN IN
(S5)
MCP_VID0/GPIO_13 L20 MCP_VID1/GPIO_14 M20 MCP_VID2/GPIO_15 M21
OUT OUT OUT
21 65 21 65 21 65
R2180
10K
5% 1/16W MF-LF 2 402 OUT 1

9
BUF_SIO_CLK Frequency
Frequency 24 MHz 14.31818 MHz HDA_SYNC 1 0
B20 INTRUDER# M25 LID# M24 LLB#
SPKR C13
23 42 23
IN
TP_MCP_LID_L PM_BATLOW_L PM_DPRSLPVR PM_PWRBTN_L PM_SYSRST_DEBOUNCE_L RTC_RST_L
Int PU (S5) Int PU (S5)
BOOT_MODE_USER
SMB_CLK0 SMB_DATA0 SMB_CLK1/MSMB_CLK SMB_DATA1/MSMB_DATA SMB_ALERT#/GPIO_64 L19 K19 G21 F21 M23
OUT BI OUT BI OUT
7 13 45 90 7 13 45 90 45 90 45 90 21 31 34
R2181
10K USER mode: Normal SAFE mode: For ROMSIP recovery Connects to SMC for automatic recovery.
87 62
IN
M22 CPU_DPRSLPVR C16 PWRBTN# D16 RSTBTN# C20 RTC_RST# D20 PWRGD_SB E20 PS_PWRGD C17 CPU_VLD E19 F19 J19 J18 G19 JTAG_TDI Int JTAG_TDO JTAG_TMS Int JTAG_TRST# JTAG_TCK
MISC
5% 1/16W MF-LF 2 402
42 23 26 23
IN IN
Int PU (S5) Int PU
SPI Frequency Select

Frequency SPI_DO SPI_CLK 31 MHz 42 MHz 25 MHz 1 MHz 0 0 1 1 0 1 0 1
(MGPIO2) (MGPIO3)
42 26
IN IN
PM_RSMRST_L MCP_PS_PWRGD MCP_CPU_VLD JTAG_MCP_TDI JTAG_MCP_TDO JTAG_MCP_TMS JTAG_MCP_TRST_L JTAG_MCP_TCK MCP_CLK25M_XTALIN MCP_CLK25M_XTALOUT RTC_CLK32K_XTALIN RTC_CLK32K_XTALOUT
FANRPM0/GPIO_60 FANCTL0/GPIO_61 FANRPM1/GPIO_63 FANCTL1/GPIO_62
B12 A12 D12 C12
IN OUT IN
21
21 28 29 42 39 21 43
26
IN
CPUVDD_EN D17
OUT
26
23 13 6 6 23 13 6 13 6 13 6
IN OUT IN IN IN
PU PU
SPI_CS0/GPIO_10 SPI_CLK/GPIO_11 SPI_DI/GPIO_8 SPI_DO/GPIO_9
C14 D13 C15 B14
OUT OUT IN OUT
44 90 44 90 44 90 44 90
NOTE: Straps not provided on this page.
B
26 26
IN OUT
A16 XTALIN B16 XTALOUT A19 XTALIN_RTC B19 XTALOUT_RTC

1
SUS_CLK/GPIO_34 B18 BUF_SIO_CLK AE7 TEST_MODE_EN K22 PKG_TEST L22
B
OUT
26 90
26 26
IN OUT
R21501
10K
5% 1/16W MF-LF 402 2
R2163
10K
R2190
1K
R2151
100K
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
1% 1/16W MF-LF 2 402
=PP3V3_S0_MCP_GPIO
8 18 19
HDA Output Caps

For EMI Reduction on HDA interface HDA_SDOUT_R HDA_BIT_CLK_R HDA_RST_R_L HDA_SYNC_R
21 90 21 90 21 90 21 90
=PP3V3_S3_MCP_GPIO
1
R2140
10K
R2141
10K
R2142
10K
R2143
10K
R2154
100K
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 1 402

21 21 59 21 28 29 42 21 43
MCP_GPIO_4 AUD_I2C_INT_L MEM_EVENT_L SMC_IG_THROTTLE_L ARB_DETECT

1
AP_PWR_EN
21 31 34
MCP HDA & MISC

MCP_VID<0> MCP_VID<1> MCP_VID<2>
1
21 65 21 65 21 65
C2170
10PF
C2172
10PF
1
21
SYNC_MASTER=T18_MLB
5% 50V CERM 2 402
5% 50V CERM 2 402

R2147
100K
R2155
22K
R2156
22K
R2157
22K
C2171
10PF
C2173
10PF
5% 50V 2 CERM 402
5% 50V 2 CERM 402
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
21
96
5% 1/16W MF-LF 402
8
OMIT
7
U1400
MCP79-TOPO-B
BGA (11 OF 11) AH26 AH33 AH34 AH37 AH38 AJ39 AJ8 AK10 AK33 AK34 AK37 AK4 AK40 AL36 AL40 AL5 AM10 AM16 AM18 AM20 AM22 AM24 AM26 AM30 AM34 AM35 AM37 AM38 AM5 AM6 AM7 AM9 AP26 AN28 AN30 AN39 AN4 Y7 AP10 AU26 AP14 AU14 AP28 AP32 AP34 AP36 AP37 AP4 AP40 AP7 AW23 AR28 AR32 AR40 AT10 AR12 AT13 AT29 AT33 AT6 AT7 AT9 AY21 AY22 L12 AU12 AU28 AP33 AU32 AR30 AU36 AU38 AU4 G28 F20 AV28 AV32 AV36 AV4 AV7 AW11 G20 AR43 AW43 AY10 AV12 AY30 AY33 AY34 AY37 AY38 AY41 GND161 GND162 GND163 GND164 GND165 GND166 GND167 GND168 GND169 GND170 GND171 GND172 GND173 GND174 GND175 GND176 GND177 GND178 GND179 GND180 GND181 GND182 GND183 GND184 GND185 GND186 GND187 GND188 GND189 GND190 GND191 GND192 GND193 GND194 GND195 GND196 GND197 GND198 GND199 GND200 GND201 GND202 GND203 GND204 GND205 GND206 GND207 GND208 GND209 GND210 GND211 GND212 GND213 GND214 GND215 GND216 GND217 GND218 GND219 GND220 GND221 GND222 GND223 GND224 GND225 GND226 GND227 GND228 GND229 GND230 GND231 GND232 GND233 GND234 GND235 GND236 GND237 GND238 GND239 GND240 GND241 GND242 GND243 GND244 GND245 GND246 GND247 GND248 GND249 GND250 GND251 GND252 GND253 GND254 GND255 GND256 GND257 GND258 GND259 GND260 GND261 GND262 GND263 GND264 GND265 GND266 GND267 GND268 GND269 GND270 GND271 GND272 GND273 GND274 GND275 GND276 GND277 GND278 GND279 GND280 GND281 GND282 GND283 GND284 GND285 GND286 GND287 GND288 GND289 GND290 GND291 GND292 GND293 GND294 GND295 GND296 GND297 GND298 GND299 GND300 GND301 GND302 GND303 GND304 GND305 GND306 GND307 GND308 GND309 GND310 GND311 GND312 GND313 GND314 GND315 GND316 GND317 GND318 GND319 GND320 GND321 GND322 GND323 GND324 GND325 GND326 GND327 GND328 GND329 GND330 GND331 GND332 GND333 GND334 GND335 GND336 GND337 GND338 GND339 GND340 GND341 GND342 GND343 AV40 BA1 BA4 AW31 AY6 L35 BC33 BC37 BC41 AY14 BC5 C2 D10 D14 D15 D18 D19 D22 D23 D26 D30 D37 D6 E13 E17 E21 E25 E29 E33 F12 F16 F32 F8 G10 G12 G14 G16 BC12 G22 G24 AW20 G34 G4 G43 G6 G8 H11 H15 AW35 H23 AN8 G40 J12 J8 K10 K12 K18 K26 K37 K4 K40 K8 AU1 L40 L43 L5 M10 M34 M35 M37 Y28 Y33 Y34 Y35 Y37 Y38 AB17 AB16 AN26 AD7 M11 AA4 AB19 AY13 P11 Y6 T11 V11 Y11 AH16 T22
5
OMIT
4
U1400
MCP79-TOPO-B
46 24 8
=PPVCORE_S0_MCP 23065 mA (A01, 1.2V) 16996 mA (A01, 1.0V)
BGA (10 OF 11) AA25 AC23 U25 AH12 AG10 AG5 Y21 Y23 AA16 AA26 AA27 AA28 AC16 AC17 AC18 AC19 AC20 AC21 AA17 AC24 AC25 AC26 AC27 AC28 AD21 AD23 W27 V25 AA18 AE19 AE21 AE23 AE25 AE26 AE27 AE28 AF10 AF11 AA19 AF2 AF21 AF23 AF25 AF3 AF4 AF7 AH23 AF9 AA20 AG11 AG12 AG21 AG23 AG25 AG3 AG4 AA21 AG6 AG7 AG8 AG9 AH1 AH10 AH11 W26 AH2 AA23 W28 AH25 AH21 AH3 AH4 AH5 AH6 AH7 AH9 AA24 W21 W23 W25 AF12 +VDD_CORE1 +VDD_CORE2 +VDD_CORE3 +VDD_CORE4 +VDD_CORE5 +VDD_CORE6 +VDD_CORE7 +VDD_CORE8 +VDD_CORE9 +VDD_CORE10 +VDD_CORE11 +VDD_CORE12 +VDD_CORE13 +VDD_CORE14 +VDD_CORE15 +VDD_CORE16 +VDD_CORE17 +VDD_CORE18 +VDD_CORE19 +VDD_CORE20 +VDD_CORE21 +VDD_CORE22 +VDD_CORE23 +VDD_CORE24 +VDD_CORE25 +VDD_CORE26 +VDD_CORE27 +VDD_CORE28 +VDD_CORE29 +VDD_CORE30 +VDD_CORE31 +VDD_CORE32 +VDD_CORE33 +VDD_CORE34 +VDD_CORE35 +VDD_CORE36 +VDD_CORE37 +VDD_CORE38 +VDD_CORE39 +VDD_CORE40 +VDD_CORE41 +VDD_CORE42 +VDD_CORE43 +VDD_CORE44 +VDD_CORE45 +VDD_CORE46 +VDD_CORE47 +VDD_CORE48 +VDD_CORE49 +VDD_CORE50 +VDD_CORE51 +VDD_CORE52 +VDD_CORE53 +VDD_CORE54 +VDD_CORE55 +VDD_CORE56 +VDD_CORE57 +VDD_CORE58 +VDD_CORE59 +VDD_CORE60 +VDD_CORE61 +VDD_CORE62 +VDD_CORE63 +VDD_CORE64 +VDD_CORE65 +VDD_CORE66 +VDD_CORE67 +VDD_CORE68 +VDD_CORE69 +VDD_CORE70 +VDD_CORE71 +VDD_CORE72 +VDD_CORE73 +VDD_CORE74 +VDD_CORE75 +VDD_CORE76 +VDD_CORE77 +VDD_CORE78 +VDD_CORE79 +VDD_CORE80 +VDD_CORE81 +VTT_CPU1 +VTT_CPU2 +VTT_CPU3 +VTT_CPU4 +VTT_CPU5 +VTT_CPU6 +VTT_CPU7 +VTT_CPU8 +VTT_CPU9 +VTT_CPU10 +VTT_CPU11 +VTT_CPU12 +VTT_CPU13 +VTT_CPU14 +VTT_CPU15 +VTT_CPU16 +VTT_CPU17 +VTT_CPU18 +VTT_CPU19 +VTT_CPU20 +VTT_CPU21 +VTT_CPU22 +VTT_CPU23 +VTT_CPU24 +VTT_CPU25 +VTT_CPU26 +VTT_CPU27 +VTT_CPU28 +VTT_CPU29 +VTT_CPU30 +VTT_CPU31 +VTT_CPU32 +VTT_CPU33 +VTT_CPU34 +VTT_CPU35 +VTT_CPU36 +VTT_CPU37 +VTT_CPU38 +VTT_CPU39 +VTT_CPU40 +VTT_CPU41 +VTT_CPU42 +VTT_CPU43 +VTT_CPU44 +VTT_CPU45 +VTT_CPU46 +VTT_CPU47 +VTT_CPU48 +VTT_CPU49 +VTT_CPU50 +VTT_CPU51 +VTT_CPU52 R32 AC32 E40 J36 N32 T32 U32 V32 W32 P31 AF32 AE32 AH32 AJ32 AK31 AK32 AD32 AL31 AB32 B41 B42 C40 C41 C42 D39 D40 D41 E38 E39 F37 F38 F39 G36 G37 G38 H35 H37 J34 J35 K33 K34 K35 L32 L33 L34 M31 M32 M33 N31 P32 Y32 AA32
=PP1V05_S0_MCP_FSB 8 9 14 24 1139 mA 1182 mA (A01)
+VTT_CPUCLK AG32
43 mA
=PP3V3_S0_MCP
+3.3V_1 +3.3V_2 +3.3V_3 +3.3V_4 +3.3V_5 +3.3V_6 +3.3V_7 +3.3V_8 AD10 AE8 AB10 AD9 Y10 AB11 AA8 Y9
8 21 24
450 mA (A01)
+3.3V_DUAL1 +3.3V_DUAL2 +3.3V_DUAL3 +3.3V_DUAL4 +3.3V_DUAL_USB1 +3.3V_DUAL_USB2 +3.3V_DUAL_USB3 +3.3V_DUAL_USB4
G18 H19 J20 K20 G26 H27 J28 K28
=PP3V3_S5_MCP 16 mA
8 24
266 mA (A01)
250 mA
26 21
PP3V3_G3_RTC 10 uA (G3) 80 uA (S0)
A20 +VBAT
+VDD_AUXC1 T21 +VDD_AUXC2 U21 +VDD_AUXC3 V21
=PP1V05_S5_MCP_VDD_AUXC 8 24 105 mA (A01)
MCP Power & Ground


D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
22
96
GND
POWER
3.3V Interface Pull-ups

These internal pull-ups are missing in Revs A01 & A01P.
44 8
=PP3V3_S5_MCP_A01
19 13
OUT
PM_LATRIGGER_L PCIE_WAKE_L JTAG_MCP_TDI JTAG_MCP_TMS PM_SYSRST_DEBOUNCE_L TP_MCP_LID_L MCP_LID_L

MAKE_BASE=TRUE
32 31 17
OUT
21 13 6
OUT
21 13 6
OUT
26 21
OUT
21
OUT
MCP_A01&MCP_A01P&MCP_A01Q R2400 10K 1 2 5% 1/16W MF-LF MCP_A01&MCP_A01P&MCP_A01Q R2401 10K 1 2 5% 1/16W MF-LF MCP_A01&MCP_A01P&MCP_A01Q R2402 10K 1 2 5% 1/16W MF-LF MCP_A01&MCP_A01P&MCP_A01Q R2403 10K 1 2 5% 1/16W MF-LF MCP_A01&MCP_A01P&MCP_A01Q R2404 10K 1 2 5% 1/16W MF-LF MCP_A01&MCP_A01P&MCP_A01Q R2405 10K 1 2
5%
402 402 402 402 402
1/16W MF-LF 402
42 21
OUT
SMC_WAKE_SCI_L SMC_RUNTIME_SCI_L PM_PWRBTN_L PM_BATLOW_L
42 21
OUT
42 21
OUT
42 21
OUT
MCP_A01&MCP_A01P&MCP_A01Q R2410 10K 1 2 5% 1/16W MF-LF MCP_A01&MCP_A01P&MCP_A01Q R2411 10K 1 2 5% 1/16W MF-LF MCP_A01&MCP_A01P&MCP_A01Q R2412 10K 1 2 5% 1/16W MF-LF MCP_A01&MCP_A01P&MCP_A01Q R2413 10K 1 2
5%
402 402 402
1/16W MF-LF 402
MCP79 A01 Silicon Support
SYNC_MASTER=T18_MLB

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
23
96
8
MCP Core Power
46 22 8
=PPVCORE_S0_MCP 23065 mA (A01, 1.2V) 16996 mA (A01, 1.0V)
NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF) Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)
(No IG vs. EG data)
C2500 1
4.7UF
20% 4V X5R 2 402
C2501 1
4.7UF
20% 4V X5R 2 402
C2502 1
4.7UF
20% 4V X5R 2 402
C2503 1
4.7UF
20% 4V X5R 2 402
C2504
1UF
C2505
1UF
C2506
1UF
C2507
1UF
C2508
0.1UF
C2509
0.1UF
C2510
0.1UF
C2511
0.1UF
C2512
0.1UF
C2513
0.1UF
10% 2 10V X5R 402-1
10% 2 10V X5R 402-1
10% 2 10V X5R 402-1
10% 2 10V X5R 402-1
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 10V 2 CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
D
8
MCP PCIE (DVDD) Power =PP1V05_S0_MCP_PEX_DVDD 57 mA (A01)

8
MCP SATA (DVDD) Power =PP1V05_S0_MCP_SATA_DVDD 43 mA (A01)

8
=PP1V05_S0_MCP_AVDD_UF 333 mA (A01)
30-OHM-5A
1 0603 2
L2570
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF) Apple: 5x 2.2uF 0402 (11 uF) PP1V05_S0_MCP_PEX_AVDD 8 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM 206 mA (A01)
VOLTAGE=1.05V 1
C2515
4.7UF
C2516
1UF
C2517
1UF
C2518
0.1uF
C2519
0.1uF
C2520
4.7UF
C2521
0.1uF
C2570
2.2UF
C2571
2.2UF
C2572
2.2UF
C2573
2.2UF
C2574
2.2UF
20% 4V X5R 2 402
10% 2 10V X5R 402-1
10% 2 10V X5R 402-1
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 4V X5R 2 402
20% 2 10V CERM 402
20% 2 6.3V CERM 402-LF
20% 2 6.3V CERM 402-LF
20% 2 6.3V CERM 402-LF
20% 2 6.3V CERM 402-LF
20% 2 6.3V CERM 402-LF
MCP 1.05V AUX Power

22 8
MCP 1.05V RMGT Power

18 8
=PP1V05_S5_MCP_VDD_AUXC 105 mA (A01)

1
=PP1V05_ENET_MCP_RMGT 131 mA (A01)
30-OHM-5A
1 0603 2
L2575
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF) Apple: 2x 2.2uF 0402 (4.4 uF) PP1V05_S0_MCP_SATA_AVDD 8 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM 127 mA (A01)
VOLTAGE=1.05V 1
C2525
0.1uF
C2526
0.1uF
C2528
4.7uF
C2529
0.1uF
C2575
2.2UF
C2576
2.2UF
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 4V X5R 2 402
20% 2 10V CERM 402
20% 2 6.3V CERM 402-LF
20% 2 6.3V CERM 402-LF
MCP FSB (VTT) Power

22 14 9 8
=PP1V05_S0_MCP_FSB 1182 mA (A01)
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF) Apple: 7x 2.2uF 0402 (15.4 uF)
8
=PP1V05_S0_MCP_PLL_UF 562 mA (A01)
R2580
1
0.2
C2530
2.2UF
C2531
2.2UF
C2532
2.2UF
C2533
2.2UF
C2534
2.2UF
C2535
2.2UF
C2536
2.2UF
1% 1/6W MF 402-HF
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V 1
PP1V05_S0_MCP_PLL_FSB 14 270 mA (A01)
C2580 1
4.7UF
20% 4V X5R 2 402
C2581
2.2UF
20% 2 6.3V CERM 402-LF
20% 2 6.3V CERM 402-LF
20% 2 6.3V CERM 402-LF
20% 2 6.3V CERM 402-LF
20% 2 6.3V CERM 402-LF
20% 2 6.3V CERM 402-LF
20% 2 6.3V CERM 402-LF
20% 2 6.3V CERM 402-LF
MCP Memory Power

16 8
=PP1V8R1V5_S0_MCP_MEM 4771 mA (A01, DDR3)
30-OHM-1.7A
1 0402 2
L2582
PP1V05_S0_MCP_PLL_PEX 17 84 mA (A01)
C2540 1
4.7UF
20% 4V X5R 2 402
C2541
0.1UF
C2542
0.1UF
C2543
0.1UF
C2544
0.1UF
C2545
0.1UF
C2546
0.1UF
C2547
0.1UF
C2548
0.1UF
C2549
0.1UF
C2582 1
4.7UF
20% 4V X5R 2 402
C2583
0.1UF
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
MCP 3.3V Power

22 21 8
=PP3V3_S0_MCP 450 mA (A01)
NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF) Apple: 4x 2.2uF 0402 (8.8 uF)
8
=PP3V3_S0_MCP_PLL_UF 19 mA (A01)
30-OHM-1.7A
1 0402 2
L2555
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF) PP3V3_S0_MCP_PLL_USB 20 MIN_LINE_WIDTH=0.4 MM 19 mA (A01) MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V 1
30-OHM-1.7A
1 0402 2
L2584
PP1V05_S0_MCP_PLL_SATA 20 84 mA (A01)
C2550
2.2UF
C2551
2.2UF
C2552
2.2UF
C2553
2.2UF
C2555
2.2UF
C2584 1
4.7UF
20% 4V X5R 2 402
C2585
0.1UF
B
MCP 3.3V AUX/USB Power
22 8
20% 2 6.3V CERM 402-LF
20% 2 6.3V CERM 402-LF
20% 2 6.3V CERM 402-LF
20% 2 6.3V CERM 402-LF
20% 2 6.3V CERM 402-LF
20% 2 10V CERM 402
B
30-OHM-1.7A
1 0402 2
=PP3V3_S5_MCP 266 mA (A01)
24 18 8
MCP 3.3V Ethernet Power =PP3V3_ENET_MCP_RMGT 83 mA (A01)
1
L2586
PP1V05_S0_MCP_PLL_CORE 16 87 mA (A01)
C2560
2.2UF
C2564
2.2UF
C2586 1
4.7UF
20% 4V X5R 2 402
C2587
0.1UF
20% 2 6.3V CERM 402-LF
20% 2 6.3V CERM 402-LF
20% 2 10V CERM 402
MCP 3.3V/1.5V HDA Power

21 8
=PP3V3R1V5_S0_MCP_HDA 7 mA (A01)
1
30-OHM-1.7A
1 0402 2
L2588
PP1V05_S0_MCP_PLL_NV 21 37 mA (A01)
C2562
2.2UF
C2588 1
20% 2 6.3V CERM 402-LF
MCP79 Ethernet VRef

24 18 8
4.7UF
C2589
0.1UF
C2590
0.1UF
20% 4V X5R 2 402
20% 2 10V CERM 402
20% 2 10V CERM 402
R25911
1.47K
MCP Standard Decoupling

A
8
=PP1V05_ENET_MCP_PLL_MAC 5 mA (A01)
30-OHM-1.7A
1 0402 2
L2595
1% 1/16W MF-LF 402 2
PP1V05_ENET_MCP_PLL_MAC 18 5 mA (A01)
MCP_MII_VREF
OUT
18
C2595 1
4.7UF
20% 4V X5R 2 402
C2596
0.1UF
R25901
1.47K
1% 1/16W MF-LF 402 2
C2591
0.1UF
20% 2 10V CERM 402
20% 10V 2 CERM 402
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
24
96
WF: Checklist says 0-ohm resistor placeholder for ferrite bead. NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF)
18 8
NO STUFF
8
=PP3V3R1V8_S0_MCP_IFP_VDD 190 mA (A01, 1.8V)

1
=PP3V3_S0_MCP_DAC_UF 206 mA (A01)
30-OHM-1.7A
1 0402 2
L2650
C2610
2.2UF
NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF) Apple: 2x 2.2uF 0402 (4.4 uF) PP3V3_S0_MCP_DAC 18 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM 206 mA (A01) VOLTAGE=3.3V NO STUFF
1
20% 2 6.3V CERM 402-LF
C2650
2.2UF
R2651
0
20% 2 6.3V CERM 402-LF
5% 1/16W MF-LF 2 402
18 8
C2615 1
4.7UF
20% 4V X5R 2 402
C2616
2.2UF
20% 6.3V 402-LF
2 CERM
18
TP_MCP_RGB_RED TP_MCP_RGB_GREEN TP_MCP_RGB_BLUE TP_MCP_RGB_HSYNC TP_MCP_RGB_VSYNC CRT_IG_R_C_PR CRT_IG_G_Y_Y CRT_IG_B_COMP_PB CRT_IG_HSYNC CRT_IG_VSYNC TP_MCP_RGB_DAC_RSET TP_MCP_RGB_DAC_VREF MCP_TV_DAC_RSET MCP_TV_DAC_VREF MCP_CLK27M_XTALIN MCP_CLK27M_XTALOUT
NC_MCP_RGB_RED
MAKE_BASE=TRUE
18
NC_MCP_RGB_GREEN
MAKE_BASE=TRUE
18
NC_MCP_RGB_BLUE
MAKE_BASE=TRUE
18
NC_MCP_RGB_HSYNC MAKE_BASE=TRUE NC_MCP_RGB_VSYNC

MAKE_BASE=TRUE
89 18 89 18
MCP_HDMI_RSET MCP_HDMI_VPROBE NO STUFF
89 18 89 18
C2620 1
0.1UF
20% 10V CERM 2 402
R2620
1K
MCP_IFPAB_RSET MCP_IFPAB_VPROBE NO STUFF
18
NO STUFF
1
1% 1/16W MF-LF 2 402
C2630 1
0.1UF
20% 10V CERM 2 402
R2630
1K
89 18
NC_CRT_IG_R_C_PR MAKE_BASE=TRUE NC_CRT_IG_G_Y_Y

MAKE_BASE=TRUE
89 18
1% 1/16W MF-LF 2 402
89 18
NC_CRT_IG_B_COMP_PB MAKE_BASE=TRUE NC_CRT_IG_HSYNC MAKE_BASE=TRUE NC_CRT_IG_VSYNC MAKE_BASE=TRUE NC_MCP_RGB_DAC_RSET MAKE_BASE=TRUE NC_MCP_RGB_DAC_VREF MAKE_BASE=TRUE NC_MCP_TV_DAC_RSET MAKE_BASE=TRUE NC_MCP_TV_DAC_VREF MAKE_BASE=TRUE NC_MCP_CLK27M_XTALIN MAKE_BASE=TRUE NC_MCP_CLK27M_XTALOUT MAKE_BASE=TRUE
89 18
89 18
=PP3V3_S0_MCP_VPLL_UF 16 mA (A01)
WF: Checklist says 0-ohm resistor placeholder for ferrite bead. NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) L2640 Apple: ??? 30-OHM-1.7A PP3V3_S0_MCP_VPLL 18 MIN_LINE_WIDTH=0.4 MM 1 2 MIN_NECK_WIDTH=0.2 MM 16 mA (A01)
0402
18
18
89 18
VOLTAGE=3.3V
C2640 1
4.7UF
20% 6.3V 2 CERM 603
C2641
0.1uF
89 18
20% 2 10V CERM 402
18
18
HDCP ROM
WF: Open question on which packge option(s) nVidia can support.
8
=PP3V3_S0_HDCPROM
C2690 1
0.1UF
20% 10V CERM 2 402
R26901
OMIT VCC
8
U2695 AT24C08
1 A0 2 A1 3 A2 SOIC
5% 1/16W MF-LF 402 2
10K
SDA SCL WP
5 6
=I2C_HDCPROM_SDA =I2C_HDCPROM_SCL HDCPROM_WP
BI IN
45 45
GND
4
MCP Graphics Support
SYNC_MASTER=AMASON_M98_MLB

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
25
96
Current numbers from email Xiaowei Lin provided 11/12/2007 3:22pm (no official document number).
=PP1V05_S0_MCP_HDMI_VDD 95 mA (A01)
RTC Power Sources

8
=PP3V3_S5_RTC_D
VIN 1
Platform Reset Connections

LPC Reset (Unbuffered)
R2881
90 83 19
U2801
MIC5232-2.8YD5
TSOT-23-5
IN
LPC_RESET_L
33
DEBUG_RESET_L
OUT
44
D
C2802
1UF
10% 10V X5R 402 2 1
EN
VOUT
PP3V3_G3_RTC
1
21 22
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

4
5% 1/16W MF-LF 402
R2883
1
D
42
33
NC GND 2
R2800
100
SMC_LRESET_L
OUT
R2801
10
C28011
10% 6.3V 2 CERM 402
5% 1/16W MF-LF 402 2
1UF
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 402
PP3V3_G3_SUPERCAP
1
C2800
0.08F
RTC_DISCHARGE_R
NO STUFF
5% 1/10W MF-LF 603
R2892
17 9
IN
PCIE_RESET_L
FW_RESET_L
OUT
36
21
IN
RTC_CLK32K_XTALOUT
RTC Crystal
R2810
1
R2890 C2810
12pF
2 5% 50V CERM 402 1 1
5% 1/16W MF-LF 402
GMUX_PCIE_RESET_L
MAKE_BASE=TRUE
5% 1/16W MF-LF 402
=GMUX_PCIE_RESET_L
OUT
83
RTC_CLK32K_XTALOUT_R CRITICAL
4
NO STUFF
R2811
10M
5% 1/16W MF-LF 402
R2891
1
PCA9557D_RESET_L
OUT
27
C
21
5% 1/16W MF-LF 402 2

OUT
Y2810
7X1.5X1.4-SM
32.768K
R2893 C2811
12pF
2 5% 50V CERM 402 1 1
1
5% 1/16W MF-LF 402
BKLT_PLT_RST_L
OUT
85
RTC_CLK32K_XTALIN
5% 1/16W MF-LF 402
R2894
1
MINI_RESET_L
OUT
31
MCP 25MHz Crystal

21
C2815
12pF
2 5% 50V CERM 402
19
R2895
1
5% 1/16W MF-LF 402
IN
MCP_CLK25M_XTALOUT
EXCARD_RESET_L
OUT
32
R2815
1
5% 1/16W MF-LF 402
MCP_CLK25M_XTALOUT_R
3
NO STUFF
R2870
IN
R2816
1M
5% 1/16W MF-LF 402 2

21
SM-3.2X2.5MM
25.0000M
Y2815
2 4
5% 1/16W MF-LF 402
CRITICAL
MEM_VTT_EN_R
33
MEM_VTT_EN
OUT
NC NC
C2816
12pF
2
90 19
5% 1/16W MF-LF 402
OUT
MCP_CLK25M_XTALIN
R2825
IN
LPC_CLK33M_SMC_R
PLACEMENT_NOTE=Place close to U1400 1
33
LPC_CLK33M_SMC
OUT
42 90
5% 50V CERM 402
MCP S0 PWRGD & CPU_VLD

8
5% 1/16W MF-LF 402
R2826
1
33
LPC_CLK33M_LPCPLUS
OUT
44 90
R2827
=PP3V3_S5_MCPPWRGD MCPSEQ_SMC
1 1
C2850
0.1UF
2 LPC_CLK33M_GMUX 5% 1/16W MF-LF 402 PLACEMENT_NOTE=Place close to U1400
33
5% 1/16W MF-LF 402
OUT
83
20% 2 10V CERM 402
R2829
90 21
IN
PM_CLK32K_SUSCLK_R
1 PLACEMENT_NOTE=Place close to U1400
22
PM_CLK32K_SUSCLK
OUT
42 90
MCPSEQ_SMC
68 42
IN
ALL_SYS_PWRGD VR_PWRGOOD_DELAY
TC7SZ08AFEAPE SOT665
R2853
1
Y U2850 B
S0_AND_IMVP_PGOOD
5% 1/16W MF-LF 402
MCP_PS_PWRGD
OUT
21
62
IN
MCPSEQ_SMC
5% 1/16W MF-LF 402
MCPSEQ_MIX
R2852
1
MCPSEQ_MIX
R2851
1
5% 1/16W MF-LF 402
MCP_CPU_VLD MCPSEQ_SMC
OUT
21
5% 1/16W MF-LF 402

21
Reset Button
42
R2850
1
IN
PM_SYSRST_L XDP
IN
MCP_CPUVDD_EN
5% 1/16W MF-LF 402
R2896
13 10
IN
XDP_DBRESET_L
R2899
1
10K pull-up to 3.3V S0 inside MCP PM_SYSRST_DEBOUNCE_L NO STUFF

1 OUT
21 23
33
SB Misc
MCPSEQ_SMC represents MCP79 MLB power sequencing connections, but results in MCP79 ROMSIP sequence happening after CPU powers up. MCPSEQ_MIX is cross between MLB and internal power sequencing, which results in earlier ROMSIP and MCP FSB I/O interface initialization. SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion). NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.
5% 1/16W MF-LF 402
OMIT
R28971
0
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 402
C2899
1UF

10% 2 10V X5R 402
SILK_PART=FP SYS RESET
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
26
96
R2802
1.0M 1
2% 2 3.3V XHHG SM
PCIE Reset (Unbuffered)
7
MEM A VREF DQ DAC channel Min DAC code Max DAC code Max sink I Max source I Nominal Vref Min Vref Max Vref Vref Stepping (per DAC LSB) A 0x00 0x87 -3.75 mA 5 mA 0.75 V 0.375 V 1.250 V 6.5 mV
6
MEM A VREF CA B 0x00 0x87 -3.75 mA 5 mA 0.75 V 0.375 V 1.250 V 6.5 mV MEM B VREF DQ A 0x00 0x87 -3.75 mA 5 mA 0.75 V 0.375 V 1.250 V 6.5 mV
5
MEM B VREF CA B 0x00 0x87 -3.75 mA 5 mA 0.75 V 0.375 V 1.250 V 6.5 mV CPU FSB VREF C 0x00 0x55 -0.91 mA 0.52 mA 0.70 V 0.091 V 1.044 V 11.2 mV
4
FRAME BUFFER VREF D 0x00 0xFF -59.04 mA 51.15 mA 1.248 V 1.042 V 1.426 V 1.5 mV
Page Notes
Power aliases required by this page: - =PP3V3_S3_VREFMRGN - =PP3V3_S5_VREFMRGN - =PPVTT_S3_DDR_BUF Signal aliases required by this page: - =I2C_VREFDACS_SCL - =I2C_VREFDACS_SDA - =I2C_PCA9557D_SCL - =I2C_PCA9557D_SDA
SO-DIMM A and SO-DIMM B Vref settings should be margined separately (i.e. not simultaneously) due to current limitation of TPS51116 regulator.
=PPVTT_S3_DDR_BUF
64 8
BOM options provided by this page: VREFMRGN NO_VREFMRGN
10mA max load
D
R2903
1 VREFMRGN
200
VREFMRGN
1
B1 A2
U2902
MAX4253
VREFMRGN_DQ_SODIMMA_BUF A4
1% 1/16W MF-LF 402
PP0V75_S3_MEM_VREFDQ_A
28
C2903
0.1UF
B4
27
VREFMRGN_DQ_SODIMMA_EN
C2900
2.2UF
C2901
0.1UF
B1 C2
VREFMRGN
20% 2 6.3V CERM 402-LF
VREFMRGN
20% 2 10V CERM 402
R2901
100K
R2905
1 VREFMRGN
VREFMRGN
200
U2902
MAX4253
C4
5% 1/16W MF-LF 402
1% 1/16W MF-LF 402
PP0V75_S3_MEM_VREFDQ_B
29
VREFMRGN
6 SCL 7 SDA 9 A0 8 U2900 VDD 1 MSOP VOUTA
C3 VREFMRGN_DQ_SODIMM VREFMRGN_CA_SODIMM VREFMRGN_CPUFSB VREFMRGN_FRAMEBUF
UCSP C1 VREFMRGN
V+
R2906
VREFMRGN_DQ_SODIMMB_BUF 1
VREFMRGN
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm
100
VB4
27
VREFMRGN_DQ_SODIMMB_EN
45
IN BI
=I2C_VREFDACS_SCL =I2C_VREFDACS_SDA
1% 1/16W MF-LF 402
Place close to J3200.1

VREFMRGN
DAC5574
45
VOUTB 2 VOUTC 4 VOUTD 5
R2902
100K
R2909
VREFMRGN 1
200
ADDR=0x98(WR)/0x99(RD)
10 A1
5% 1/16W MF-LF 402
VREFMRGN
GND 3
1
B1 A2
U2903
MAX4253
VREFMRGN_CA_SODIMMA_BUF A4
1% 1/16W MF-LF 402
PP0V75_S3_MEM_VREFCA_A
28
C2904
0.1UF
20% 10V 2 CERM 402
UCSP A1 VREFMRGN A3
V+
R2910
1
VREFMRGN
100
VB4
27
VREFMRGN_CA_SODIMMA_EN
1% 1/16W MF-LF 402

VREFMRGN
R2907
100K
B1 C2
R2911
1 VREFMRGN
200
U2903
MAX4253
C4
5% 1/16W MF-LF 402
1% 1/16W MF-LF 402
PP0V75_S3_MEM_VREFCA_B
29
UCSP C1 VREFMRGN C3
V+
R2912
VREFMRGN_CA_SODIMMB_BUF 1
VREFMRGN
100
VB4
27
VREFMRGN_CA_SODIMMB_EN
1% 1/16W MF-LF 402
R2908
100K VREFMRGN
1 B1 A2
U2904
MAX4253
UCSP A1 A4
5% 1/16W MF-LF 402
VREFMRGN
R2916
1
VREFMRGN
49.9 2
1% 1/16W MF-LF 402
GPU_FB_A_VREF_DIV
OUT
C2905
0.1UF
Place close to U8400, U8450
V+
20% 2 10V CERM 402
VREFMRGN A3
VREFMRGN_FRAMEBUF_BUF
VB4
27
VREFMRGN_FRAMEBUF_EN
R2917
1
VREFMRGN
B
B1
49.9 2
1% 1/16W MF-LF 402
GPU_FB_B_VREF_DIV
OUT
R2915
100K
Place close to U8500, U8550
VREFMRGN
16 1
C2
U2904
MAX4253
UCSP C1 C4
5% 1/16W MF-LF 402
VREFMRGN
C2902
0.1UF
VREFMRGN
C3
V+
R2914
VREFMRGN_CPUFSB_BUF 1
VREFMRGN
100
VREFMRGN
CPU_GTLREF
OUT
10 87
20% 2 10V CERM 402
VCC
U2901
PCA9557
QFN 3
VB4
27
VREFMRGN_CPUFSB_EN
1% 1/16W MF-LF 402
Place close to U1000.AD26
ADDR=0x30(WR)/0x31(RD)
A0 A1 5 A2
4
45 45
IN BI
=I2C_PCA9557D_SCL =I2C_PCA9557D_SDA
1 2
SCL SDA
THRM
P0 P1 P2 P3 P4 P5 P6 P7
NC
7 9 10 11 12 13 14
VREFMRGN_CPUFSB_EN
27
VREFMRGN_CA_SODIMMA_EN
27
100K
5% 1/16W MF-LF 402 1
R2913
27
VREFMRGN
VREFMRGN_DQ_SODIMMA_EN VREFMRGN_CA_SODIMMB_EN
27
VREFMRGN_DQ_SODIMMB_EN
27
VREFMRGN_FRAMEBUF_EN
27
NC
PCA9557D_RESET_L IN
26
RESET* 15 GND
8
PAD
17
FSB/DDR3/FRAMEBUF Vref Margining
A
Required zero ohm resistors when no VREF margining circuit stuffed
SYNC_MASTER=DDR

PART NUMBER 116S0004 116S0004 116S0004 116S0004
QTY 1 1 1 1
DESCRIPTION
RES,MTL FILM,0,5%,0402,SM,LF RES,MTL FILM,0,5%,0402,SM,LF RES,MTL FILM,0,5%,0402,SM,LF RES,MTL FILM,0,5%,0402,SM,LF
REFERENCE DES R2903 R2905 R2909 R2911
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
BOM OPTION NO_VREFMRGN NO_VREFMRGN NO_VREFMRGN NO_VREFMRGN
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
27
96
=PP3V3_S3_VREFMRGN
20% 10V 2 CERM 402
UCSP A1 VREFMRGN A3
V+
R2904
1
VREFMRGN
100
V-
1% 1/16W MF-LF 402
8
Page Notes
Power aliases required by this page: - =PP1V5_S0_MEM_A - =PP1V5_S3_MEM_A - =PP0V75_S0_MEM_VTT_A - =PPSPD_S0_MEM_A (2.5 - 3.3V) Signal aliases required by this page: - =I2C_SODIMMA_SCL - =I2C_SODIMMA_SDA
7
8
6
=PP1V5_S0_MEM_A =PP1V5_S3_MEM_A
DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)

1
C3110
0.1UF
C3111
0.1UF
C3112
0.1UF
C3113
0.1UF
C3114
0.1UF
C3115
0.1UF
C3116
0.1UF
C3117
0.1UF
C3118
0.1UF
C3119
0.1UF
C3120
0.1UF
C3121
0.1UF
C3122
0.1UF
C3123
0.1UF
20% 2 10V CERM 402 1
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 10V 2 CERM 402
20% 2 10V CERM 402
20% 10V 2 CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
C3100
10UF
C3101
10UF
PP0V75_S3_MEM_VREFDQ_A
BOM options provided by this page: (NONE)
20% 2 6.3V X5R 603
20% 2 6.3V X5R 603
27
D
1
C3130
2.2UF
20% 6.3V CERM 402-LF
C3131
0.1UF
20% 10V CERM 402
88 15
IN
MEM_A_CKE<0>
75 77
88 15
IN
MEM_A_BA<2> MEM_A_A<12> MEM_A_A<9> MEM_A_A<8> MEM_A_A<5> MEM_A_A<3> MEM_A_A<1> MEM_A_CLK_P<0> MEM_A_CLK_N<0> MEM_A_A<10> MEM_A_BA<0> MEM_A_WE_L MEM_A_CAS_L MEM_A_A<13> MEM_A_CS_L<1>
79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127
88 15 88 15
IN IN
88 15 88 15
IN IN
88 15 88 15
IN IN
88 15
IN IN
88 15
88 15 88 15
IN IN
88 15 88 15
IN IN
88 15 88 15
IN IN
88 15 88 15
BI BI
MEM_A_DQ<33> MEM_A_DQ<32> MEM_A_DQS_N<4> MEM_A_DQS_P<4> MEM_A_DQ<34> MEM_A_DQ<35> MEM_A_DQ<44> MEM_A_DQ<41> MEM_A_DM<5> MEM_A_DQ<45> MEM_A_DQ<42> MEM_A_DQ<52> MEM_A_DQ<51> MEM_A_DQS_N<6> MEM_A_DQS_P<6> MEM_A_DQ<55> MEM_A_DQ<54> MEM_A_DQ<61> MEM_A_DQ<60> MEM_A_DM<7> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_SA<0>
129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203
88 15 88 15
BI BI
88 15 88 15
BI BI
88 15 88 15
BI BI
88 15
IN
88 15 88 15
BI BI
88 15 88 15
BI BI
88 15 88 15
BI BI
88 15 88 15
BI BI
88 15 88 15
BI BI
88 15
IN
88 15 88 15
BI BI
=PPSPD_S0_MEM_A MEM_A_SA<1>
CKE0 CKE1 VDD VDD NC A15 BA2 A14 F-RT-THB VDD VDD A12/BC* A11 A9 A7 VDD VDD A8 A6 A5 A4 VDD VDD A3 A2 A0 A1 VDD VDD CK0 CK1 CK0* CK1* VDD VDD A10/AP BA1 BA0 RAS* VDD VDD WE* S0* CAS* ODT0 VDD VDD A13 ODT1 S1* NC VDD VDD TEST VREFCA VSS VSS DQ32 DQ36 DQ33 DQ37 VSS VSS DQS4* DM4 DQS4 VSS VSS DQ38 DQ34 DQ39 DQ35 VSS VSS DQ44 DQ40 DQ45 DQ41 VSS VSS DQS5* DM5 DQS5 VSS VSS DQ42 DQ46 DQ43 DQ47 VSS VSS DQ48 DQ52 DQ49 DQ53 VSS VSS DQS6* DM6 DQS6 VSS VSS DQ54 DQ50 DQ55 DQ51 VSS VSS DQ60 DQ56 DQ61 DQ57 VSS VSS DQS7* DM7 DQS7 VSS VSS DQ58 DQ62 DQ63 DQ59 VSS VSS SA0 EVENT* VDDSPD SDA SA1 SCL VTT VTT
MEM_A_CKE<1> MEM_A_A<15> MEM_A_A<14> MEM_A_A<11> MEM_A_A<7> MEM_A_A<6> MEM_A_A<4> MEM_A_A<2> MEM_A_A<0> MEM_A_CLK_P<1> MEM_A_CLK_N<1> MEM_A_BA<1> MEM_A_RAS_L MEM_A_CS_L<0> MEM_A_ODT<0> MEM_A_ODT<1>
IN
15 88
88 15 88 15
BI BI
J3100
DDR3-SODIMM-DUAL-M97-3
(SYMBOL 2 OF 2)
76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204
MEM_A_DQ<0> MEM_A_DQ<1> MEM_A_DM<0> MEM_A_DQ<3> MEM_A_DQ<2> MEM_A_DQ<9> MEM_A_DQ<13> MEM_A_DQS_N<1> MEM_A_DQS_P<1> MEM_A_DQ<11> MEM_A_DQ<14> MEM_A_DQ<16> MEM_A_DQ<18> MEM_A_DQS_N<2> MEM_A_DQS_P<2> MEM_A_DQ<23> MEM_A_DQ<19> MEM_A_DQ<24> MEM_A_DQ<30> MEM_A_DM<3> MEM_A_DQ<27> MEM_A_DQ<25>
BI
15 88
IN IN
9 15 88 88 15
7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
IN
J3100
DDR3-SODIMM-DUAL-M97-3
(SYMBOL 1 OF 2)
MEM_A_DQS_N<0> MEM_A_DQS_P<0> MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8> MEM_A_DQ<12> MEM_A_DM<1> MEM_RESET_L MEM_A_DQ<15> MEM_A_DQ<10> MEM_A_DQ<21> MEM_A_DQ<20> MEM_A_DM<2> MEM_A_DQ<17> MEM_A_DQ<22> MEM_A_DQ<29> MEM_A_DQ<28> MEM_A_DQS_N<3> MEM_A_DQS_P<3> MEM_A_DQ<26> MEM_A_DQ<31>
BI BI
15 88 15 88
IN IN
15 88 15 88
88 15 88 15
BI BI
BI BI
15 88 15 88
IN IN
15 88 15 88
88 15 88 15
BI BI
BI BI
15 88 15 88
IN IN
15 88 15 88
88 15 88 15
BI BI
IN IN
15 88 29 30
IN IN
15 88 15 88
88 15 88 15
BI BI
BI BI
15 88 15 88
IN IN
15 88 15 88
88 15 88 15
BI BI
BI BI
15 88 15 88
IN IN
15 88 15 88
88 15 88 15
BI BI
IN
15 88
BI BI
15 88 15 88
IN
15 88
88 15 88 15
BI BI
BI BI
15 88 15 88
88 15 88 15
BI BI
MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DM<4> MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<47> MEM_A_DQ<40> MEM_A_DQS_N<5> MEM_A_DQS_P<5> MEM_A_DQ<46> MEM_A_DQ<43> MEM_A_DQ<48> MEM_A_DQ<53> MEM_A_DM<6> MEM_A_DQ<50> MEM_A_DQ<49> MEM_A_DQ<57> MEM_A_DQ<56> MEM_A_DQS_N<7> MEM_A_DQS_P<7> MEM_A_DQ<62> MEM_A_DQ<63> MEM_EVENT_L =I2C_SODIMMA_SDA =I2C_SODIMMA_SCL
BI BI
15 88 15 88 88 15
BI BI
15 88 15 88
IN
IN
15 88
88 15 88 15
BI BI
BI BI
15 88 15 88
BI BI
15 88 15 88
KEY
BI BI
15 88 15 88
516-0196
BI BI
15 88 15 88
BI BI
15 88 15 88
BI BI
15 88 15 88
IN
15 88
BI BI
15 88 15 88
PP0V75_S3_MEM_VREFCA_A
27
BI BI
15 88 15 88
C3135
2.2UF
20% 6.3V CERM 402-LF
C3136
0.1UF
20% 10V CERM 402
BI BI
15 88 15 88
BI BI
15 88 15 88
OUT
21 29 42
BI IN
45 45
"Factory" (top) slot

=PP0V75_S0_MEM_VTT_A
8
1 1
A
2
C3140
2.2UF
20% 6.3V CERM 402-LF 2
R3140
10K
5% 1/16W MF-LF 402
R3141
10K
5% 1/16W MF-LF 402
DDR3 SO-DIMM Connector A

SYNC_MASTER=DDR SYNC_DATE=07/22/2008
516-0196
SPD ADDR=0xA0(WR)/0xA1(RD)

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
28
96
73
KEY
74
3 5
VREFDQ VSS VSS DQ4 DQ0 DQ5 CRITICAL DQ1 VSS VSS DQS0* DM0 DQS0 F-RT-THB VSS VSS DQ2 DQ6 DQ3 DQ7 VSS VSS DQ8 DQ12 DQ9 DQ13 VSS VSS DQS1* DM1 DQS1 RESET* VSS VSS DQ10 DQ14 DQ11 DQ15 VSS VSS DQ16 DQ20 DQ17 DQ21 VSS VSS DQS2* DM2 DQS2 VSS DQ22 VSS DQ18 DQ23 DQ19 VSS DQ28 VSS DQ24 DQ29 DQ25 VSS DQS3* VSS DM3 DQS3 VSS VSS DQ26 DQ30 DQ27 DQ31 VSS VSS
2 4 6
MEM_A_DQ<4> MEM_A_DQ<5>
BI
15 88
8
Page Notes
Power aliases required by this page: - =PP1V5_S0_MEM_B - =PP1V5_S3_MEM_B - =PP0V75_S0_MEM_VTT_B - =PPSPD_S0_MEM_B (2.5 - 3.3V) Signal aliases required by this page: - =I2C_SODIMMB_SCL - =I2C_SODIMMB_SDA
7
8
6
=PP1V5_S0_MEM_B =PP1V5_S3_MEM_B
DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)

1
C3210
0.1UF
C3211
0.1UF
C3212
0.1UF
C3213
0.1UF
C3214
0.1UF
C3215
0.1UF
C3216
0.1UF
C3217
0.1UF
C3218
0.1UF
C3219
0.1UF
C3220
0.1UF
C3221
0.1UF
C3222
0.1UF
C3223
0.1UF
20% 2 10V CERM 402 1
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 10V 2 CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
C3200
10UF
C3201
10UF
PP0V75_S3_MEM_VREFDQ_B
20% 2 6.3V X5R 603
20% 2 6.3V X5R 603
27
D
1
C3230
2.2UF
20% 6.3V CERM 402-LF
C3231
0.1UF
20% 10V CERM 402
88 15
IN
MEM_B_CKE<0>
75 77
88 15
IN
MEM_B_BA<2> MEM_B_A<12> MEM_B_A<9> MEM_B_A<8> MEM_B_A<5> MEM_B_A<3> MEM_B_A<1> MEM_B_CLK_P<0> MEM_B_CLK_N<0> MEM_B_A<10> MEM_B_BA<0> MEM_B_WE_L MEM_B_CAS_L MEM_B_A<13> MEM_B_CS_L<1>
79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127
88 15 88 15
IN IN
88 15 88 15
IN IN
88 15 88 15
IN IN
88 15
IN IN
88 15
88 15 88 15
IN IN
88 15 88 15
IN IN
88 15 88 15
IN IN
88 15 88 15
BI BI
MEM_B_DQ<32> MEM_B_DQ<37> MEM_B_DQS_N<4> MEM_B_DQS_P<4> MEM_B_DQ<34> MEM_B_DQ<35> MEM_B_DQ<41> MEM_B_DQ<40> MEM_B_DM<5> MEM_B_DQ<43> MEM_B_DQ<42> MEM_B_DQ<55> MEM_B_DQ<49> MEM_B_DQS_N<6> MEM_B_DQS_P<6> MEM_B_DQ<52> MEM_B_DQ<51> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DM<7> MEM_B_DQ<63> MEM_B_DQ<59> MEM_B_SA<0>
129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203
88 15 88 15
BI BI
88 15 88 15
BI BI
88 15 88 15
BI BI
88 15
IN
88 15 88 15
BI BI
88 15 88 15
BI BI
88 15 88 15
BI BI
88 15 88 15
BI BI
88 15 88 15
BI BI
R3240
10K
5% 1/16W MF-LF 402
88 15
IN
88 15 88 15
BI BI
=PPSPD_S0_MEM_B MEM_B_SA<1>
CKE0 CKE1 VDD VDD NC A15 BA2 A14 VDD F-RT-BGA3 VDD A12/BC* A11 A9 A7 VDD VDD A8 A6 A5 A4 VDD VDD A3 A2 A1 A0 VDD VDD CK0 CK1 CK0* CK1* VDD VDD A10/AP BA1 BA0 RAS* VDD VDD WE* S0* CAS* ODT0 VDD VDD A13 ODT1 S1* NC VDD VDD TEST VREFCA VSS VSS DQ32 DQ36 DQ33 DQ37 VSS VSS DQS4* DM4 DQS4 VSS VSS DQ38 DQ39 DQ34 DQ35 VSS DQ44 VSS DQ40 DQ45 DQ41 VSS VSS DQS5* DM5 DQS5 VSS VSS DQ42 DQ46 DQ43 DQ47 VSS VSS DQ48 DQ52 DQ49 DQ53 VSS VSS DQS6* DM6 DQS6 VSS VSS DQ54 DQ50 DQ55 DQ51 VSS VSS DQ60 DQ56 DQ61 DQ57 VSS DQS7* VSS DM7 DQS7 VSS VSS DQ58 DQ62 DQ59 DQ63 VSS VSS SA0 EVENT* VDDSPD SDA SA1 SCL VTT VTT
MEM_B_CKE<1> MEM_B_A<15> MEM_B_A<14> MEM_B_A<11> MEM_B_A<7> MEM_B_A<6> MEM_B_A<4> MEM_B_A<2> MEM_B_A<0> MEM_B_CLK_P<1> MEM_B_CLK_N<1> MEM_B_BA<1> MEM_B_RAS_L MEM_B_CS_L<0> MEM_B_ODT<0> MEM_B_ODT<1>
IN
15 88
88 15 88 15
BI BI
76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 206 208 210 212
MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DM<0> MEM_B_DQ<2> MEM_B_DQ<3> MEM_B_DQ<28> MEM_B_DQ<24> MEM_B_DQS_N<3> MEM_B_DQS_P<3> MEM_B_DQ<31> MEM_B_DQ<30> MEM_B_DQ<9> MEM_B_DQ<8> MEM_B_DQS_N<1> MEM_B_DQS_P<1> MEM_B_DQ<15> MEM_B_DQ<10> MEM_B_DQ<21> MEM_B_DQ<17> MEM_B_DM<2> MEM_B_DQ<18> MEM_B_DQ<22>
BI
15 88
IN IN
9 15 88 88 15
7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72
J3200
DDR3-SODIMM
(2 OF 2)
IN
J3200
DDR3-SODIMM
(1 OF 2)
MEM_B_DQS_N<0> MEM_B_DQS_P<0> MEM_B_DQ<6> MEM_B_DQ<7> MEM_B_DQ<29> MEM_B_DQ<25> MEM_B_DM<3> MEM_RESET_L MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<13> MEM_B_DQ<12> MEM_B_DM<1> MEM_B_DQ<14> MEM_B_DQ<11> MEM_B_DQ<20> MEM_B_DQ<16> MEM_B_DQS_N<2> MEM_B_DQS_P<2> MEM_B_DQ<19> MEM_B_DQ<23>
BI BI
15 88 15 88
IN IN
15 88 15 88
88 15 88 15
BI BI
BI BI
15 88 15 88
IN IN
15 88 15 88
88 15 88 15
BI BI
BI BI
15 88 15 88
IN IN
15 88 15 88
88 15 88 15
BI BI
IN IN
15 88 28 30
IN IN
15 88 15 88
88 15 88 15
BI BI
BI BI
15 88 15 88
IN IN
15 88 15 88
88 15 88 15
BI BI
BI BI
15 88 15 88
IN IN
15 88 15 88
88 15 88 15
BI BI
IN
15 88
BI BI
15 88 15 88
IN
15 88
88 15 88 15
BI BI
BI BI
15 88 15 88
88 15 88 15
BI BI
MEM_B_DQ<33> MEM_B_DQ<36> MEM_B_DM<4> MEM_B_DQ<38> MEM_B_DQ<39> MEM_B_DQ<44> MEM_B_DQ<45> MEM_B_DQS_N<5> MEM_B_DQS_P<5> MEM_B_DQ<47> MEM_B_DQ<46> MEM_B_DQ<48> MEM_B_DQ<54> MEM_B_DM<6> MEM_B_DQ<53> MEM_B_DQ<50> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQS_N<7> MEM_B_DQS_P<7> MEM_B_DQ<58> MEM_B_DQ<62> MEM_EVENT_L =I2C_SODIMMB_SDA =I2C_SODIMMB_SCL
BI BI
15 88 15 88 88 15
BI BI
15 88 15 88
IN
IN
15 88
88 15 88 15
BI BI
BI BI
15 88 15 88
BI BI
15 88 15 88
KEY
BI BI
15 88 15 88
516s0704
BI BI
15 88 15 88
BI BI
15 88 15 88
BI BI
15 88 15 88
IN
15 88
BI BI
15 88 15 88
PP0V75_S3_MEM_VREFCA_B
27
BI BI
15 88 15 88
C3235
2.2UF
20% 6.3V CERM 402-LF
C3236
0.1UF
20% 10V CERM 402
BI BI
15 88 15 88
BI BI
15 88 15 88
OUT
21 28 42
BI IN
45 45
"Expansion" (bottom) slot

=PP0V75_S0_MEM_VTT_B
8
1 1
A
2
C3240
2.2UF
20% 6.3V CERM 402-LF 2
R3241
10K
5% 1/16W MF-LF 402
205 207 209 211
MTG PINS
DDR3 SO-DIMM Connector B

SYNC_MASTER=DDR SYNC_DATE=07/22/2008
MTG MTG MTG MTG
PIN PIN PIN PIN
MTG PIN
MTG PIN
MTG PIN MTG PIN

516s0704
SPD ADDR=0xA2(WR)/0xA3(RD)
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
29
96
73
KEY
74
3 5
VREFDQ VSS VSS DQ4 DQ0 DQ5 CRITICAL DQ1 VSS VSS DQS0* DM0 DQS0 F-RT-BGA3 VSS VSS DQ2 DQ6 DQ3 DQ7 VSS VSS DQ8 DQ12 DQ9 DQ13 VSS VSS DQS1* DM1 DQS1 RESET* VSS VSS DQ14 DQ10 DQ15 DQ11 VSS VSS DQ20 DQ16 DQ17 DQ21 VSS VSS DQS2* DM2 DQS2 VSS DQ22 VSS DQ23 DQ18 DQ19 VSS DQ28 VSS DQ24 DQ29 DQ25 VSS DQS3* VSS DM3 DQS3 VSS VSS DQ26 DQ30 DQ27 DQ31 VSS VSS
2 4 6
MEM_B_DQ<4> MEM_B_DQ<5>
BI
15 88
DDR3 RESET Support

MCP79 cannot control this signal directly since it must be high in sleep and MCP MEM rails are not powered in sleep. =PP1V5_S3_MEMRESET 3.3V input must be stable before before 1.5V starts to rise to avoid glitch on MEM_RESET_L. MEMRESET_HW
1
8
R3310
1K
=PP3V3_S5_MEMRESET
C
MEMRESET_HW
R3305
20K
5% 1/16W MF-LF 2 402
R33001
10K
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 2 402
6 2
MEMRESET_HW
MEM_RESET_L MEMRESET_MCP
1
C
OUT
28 29
MEM_RESET MEMRESET_HW
3
Q3305
MMDT3904-X-G
SOT-363-LF 1
R3309
0
5% 1/16W MF-LF 2 402
MEM_RESET_RC_L MEMRESET_HW
Q3305
MMDT3904-X-G
SOT-363-LF 4
R33011
20K
5% 1/16W MF-LF 402 2
MEMRESET_HW
1
C3300
0.1UF
20% 10V 2 CERM 402
16
IN
MCP_MEM_RESET_L
DDR3 Support
SYNC_MASTER=T18_MLB

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
30
96
8
17
7
OUT
PCIE_MINI_PRSNT_L
3
Q3401
SSM6N15FEAPE
SOT563
G 5
AP_PWR_EN
IN
21 34
D
17
5V S3 WLAN FET
OUT
MINI_CLKREQ_L
6
MOSFET CHANNEL
D
FDC606P P-TYPE 26 mOhm @4.5V 0.8 A (EDP)
Q3401
SSM6N15FEAPE
SOT563
RDS(ON) LOADING
G 2
CRITICAL 518S0610
PLACEMENT_NOTE=Place close to J3401.
20347-325E-12
F-RT-SM
31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 32
J3401
C3431 1 2
1
10%
1000 mA peak 750 mA nominal max

IN IN
17 89 17 89
0402-LF
0.1uF
2 0.1uF
16V X5R 402
10%
16V X5R 402
PCIE_MINI_R2D_C_P PCIE_MINI_R2D_C_N
PP5V_WLAN
31
C3430
MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V 1
PP5V_WLAN_F
1 2 5 6
FERR-120-OHM-1.5A
MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V
L3404
FDC606P_G SOT-6
=PP5V_S3_WLAN
0.033UF
D S
Q3450
4
C3422
0.1uF
C3421 1
0.1uF
20% 10V CERM 2 402
C3420
10UF
C3451 1
10% 16V 2 X5R 402
R3451
10K
MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V
PCIE_MINI_D2R_P PCIE_MINI_D2R_N
95 89 95 89
OUT OUT
17 89 17 89
PCIE_MINI_R2D_P PCIE_MINI_R2D_N
L3401 90-OHM-100MA
DLP11S SYM_VER-1 4 3 2 1
AIRPORT
PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N
IN
17 89
20% 10V CERM 2 402
20% 10V 2 X5R 805
C3450
0.1UF
1 10% 16V X5R 402 2
R3450
1
5% 1/16W MF-LF 2 402
P5VWLAN_SS
100K 2
5% 1/16W MF-LF 402
PM_WLAN_EN_L
IN
34
PLACEMENT_NOTE=Place close to J3401. PLACEMENT_NOTE=Place close to Q3450. PLACEMENT_NOTE=Place close to Q3450.

IN
17 89
95 95
PCIE_CLK100M_MINI_CONN_P PCIE_CLK100M_MINI_CONN_N MINI_CLKREQ_Q_L PCIE_WAKE_L

OUT
17 23 32
NC NC
PP5V_S3_BTCAMERA_F I2C_ALS_SDA BI I2C_ALS_SCL IN

45 45 95 95
275 mA peak 206 mA nominal max 2

L3405
1 0402-LF
USB_CAMERA_CONN_P USB_CAMERA_CONN_N
95 95
CONN_USB2_BT_P CONN_USB2_BT_N
L3402 90-OHM
DLP0NS SYM_VER-1 4 1 3 2
ALS CAMERA
USB_CAMERA_P USB_CAMERA_N
FERR-120-OHM-1.5A
=PP5V_S3_BTCAMERA MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V
C3452 1 0.1uF
20% 10V CERM 402
2
OUT
20 90
OUT
20 90
L3403 90-OHM
DLP0NS SYM_VER-1 4 1 3 2
BLUETOOTH
USB_BT_P USB_BT_N
BI
20 90
BI
20 90
PP5V_WLAN_F =PP3V3_S3_WLAN
8
31
R3453
33K
TC7SZ08AFEAPE 5 SOT665
MINI_RESET_CONN_L
74LVC1G17DRL SOT-553 WLAN_SMIT_BUF 4

3
U3402
5 2
NC
5% 1/16W MF-LF 2 402
Y U3401 1 B
WLAN_SMIT_RC
1
NC
MINI_RESET_L
C3453 1
10% 6.3V 2 CERM 402
R3454
62K
Right Clutch Connector

SYNC_MASTER=YITE_M98_MLB SYNC_DATE=07/02/2008
IN
26
1UF
5% 1/16W MF-LF 2 402

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
31
96
D
L3502 90-OHM
DLP0NS
SYM_VER-1
EXPRESSCARD/34 FLEX CONNECTOR

CRITICAL
J3500
3
90 20
BI
USB_EXCARD_N USB_EXCARD_P
USB2_EXCARD_CONN_N 7 USB2_EXCARD_CONN_P 7
32 95
502250-8727
F-RT-SM
28
PLACEMENT_NOTE=Place close to J3500
32 8
=PP3V3_S3_EXCARD
1
L3503 90-OHM-100MA
C3530 1 C3531
0.1uF
20% 2 6.3V X5R 603
95 89 32 7 89 17 7
DLP11S SYM_VER-1
OUT
PCIE_EXCARD_R2D_N PCIE_EXCARD_D2R_P PCIE_CLK100M_EXCARD_CONN_N EXCARD_CLKREQ_CONN_L PP3V3_S0_EXCARD_SWITCH PP3V3_S3_EXCARD_SWITCH PP1V5_S0_EXCARD_SWITCH =SMBUS_EXCARD_SDA EXCARD_CPUSB_L USB2_EXCARD_CONN_N
20% 2 10V CERM 402
10uF
89 17
IN
PCIE_CLK100M_EXCARD_N PCIE_CLK100M_EXCARD_P
4 1
3 2
PCIE_CLK100M_EXCARD_CONN_N PCIE_CLK100M_EXCARD_CONN_P
7 32 95
95 32 7 32 7 32 7
89 17
IN
7 32 95 32 7 32 7

32 8
=PP1V5_S0_EXCARD
1

89 17 89 17
45
BI
C3534 1 C3535
0.1uF
20% 6.3V 2 X5R 603
20% 10V 2 CERM 402
10uF
IN IN
PCIE_EXCARD_R2D_C_N PCIE_EXCARD_R2D_C_P
C3571 1 2
1
10%
0.1uF
2 0.1uF 10%
16V X5R 402
16V X5R 402
PCIE_EXCARD_R2D_N PCIE_EXCARD_R2D_P
7 32 89 95 7 32 89 95
32 7 95 32 7
2 4 6 8 10 12 14 16 18 20 22 NC 24 26
1 3 5 7 9 11 13 15 17 19 21 23 25 27
29
PCIE_EXCARD_R2D_P
7 32 89 95
PCIE_EXCARD_D2R_N OUT 7 17 89 PCIE_CLK100M_EXCARD_CONN_P 7 32 95 EXCARD_CPPE_L 7 32 PP3V3_S0_EXCARD_SWITCH 7 32 PLT_RESET_SWITCH_L 7 32 PCIE_WAKE_L OUT 17 23 31 PP1V5_S0_EXCARD_SWITCH 7 32 =SMBUS_EXCARD_SCL BI 45
NC
USB2_EXCARD_CONN_P 7
32 95
C3570
32 7
EXCARD_CPPE_L
R3501
01 MF-LF 402
5% 1/16W
PCIE_EXCARD_PRSNT_L
17
OUTPUT DECOUPLING
PP3V3_S3_EXCARD_SWITCH
VOLTAGE=3.3V
MIN_LINE_WIDTH=.3mm MIN_NECK_WIDTH=0.2mm 7 32
C3500 1 C3503
0.1uF
20% 2 6.3V X5R 603
CRITICAL =PP3V3_S3_EXCARD TPS2231

17 2 12 QFN AUXOUT VIN3P3 VOUT3P3 VIN1P5 VOUT1P5
AUXIN SHDN* STBY* SYSRST* OC* NC0 NC1 NC2 NC3 NC4 THRML_PAD RCLKEN PERST* CPPE* CPUSB*
U3500
20% 2 10V CERM 402 15 3 11 8 10 9
10uF
CRITICAL
J3501
503219-0221
M-ST-SM 24 23
7 32
32 8 32 8 32
=PP3V3_S0_EXCARD 8 =PP1V5_S0_EXCARD SMC_EXCARD_PWR_EN TP_EXCARD_STBY_L EXCARD_RESET_L EXCARD_OC_L
VOLTAGE=3.3V
MIN_LINE_WIDTH=.6mm MIN_NECK_WIDTH=0.2mm
1
42
IN
R3500
01 MF-LF 402
5% 1/16W
EXCARD_SHDN_L_R
26 43 20
IN IN
20 1 6 19
C3501 C3504
1
10% 2 16V X5R 402
0.1uF
20% 2 6.3V X5R 603
10uF
OUT
FC_CLKREQ_L PCIE_CLK100M_FC_P PCIE_CLK100M_FC_N
1 3
2 4 6 8 10 12 14 16 18 20 22
95 9
IN IN
5 7 9
VENICE
95 9 7 32 95 9
B
NC NC NC NC
95 9
NC 4 NC 5 NC 13 NC 14 NC 16
18 EXCARD_RCLKEN
32
VOLTAGE=1.5V
MIN_LINE_WIDTH=.6mm MIN_NECK_WIDTH=0.2mm
IN IN
PCIE_FC_R2D_C_P PCIE_FC_R2D_C_N 1
10%
C3573 1 2
2 0.1uF
16V X5R 402 10%
=PP3V3_FC_CON
0.1uF
95 95
16V X5R 402
PCIE_FC_R2D_P PCIE_FC_R2D_N
OUT OUT
11 13 15
C3502 C3505
1
21
GND 7
10% 2 16V X5R 402
0.1uF
20% 2 6.3V X5R 603
10uF
C3572 VENICE PLACEMENT_NOTE=Place close to J3501.
=PP1V5_FC_CON FC_PRSNT_L FC_RESET_L
95 9 95 9
PCIE_FC_D2R_P PCIE_FC_D2R_N
17 19 21
OUT OUT
9 9
PLT_RESET_SWITCH_L 7 EXCARD_CPPE_L 7 EXCARD_CPUSB_L 7
32 32 32
25 26
VENICE
Venice Connector
32 8
=PP3V3_S3_EXCARD
32 8
=PP3V3_S0_EXCARD
32 7
EXCARD_CPUSB_L EXCARD_CPPE_L
5 1
74HC1G00GWDG
SC70-5 4
R35611
100K SMC_EXCARD_CP
OUT
42 43
ExpressCard Connector
32
32 7
U3551
3
1% 1/16W MF-LF 402 2
EXCARD_RCLKEN
5 1
74HC1G00GWDG
SC70-5 4
SYNC_MASTER=YITE_M98_MLB
OUT
17
EXCARD_CLKREQ_CONN
U3560
3
EXCARD_CLKREQ_L

C3550 1
0.1uF
20% 10V CERM 2 402
32 7
A2
U3561 SN74LVC1G04YZPR
C2 BGA C1
EXCARD_CLKREQ_CONN_L
B1
C3560 1
0.1uF
20% 10V CERM 2 402
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
32
96
INPUT DECOUPLING
90 20
BI
32 95
D
=PP3V3_ENET_PHY (43mA typ - 1000base-T) (19mA typ - Energy Detect) WF: Marvell numbers, update for Realtek
8
C3710 1 C3711 1
0.1UF
10% 16V 2 X5R 402
=PP1V05_ENET_PHY 8 (221mA typ - 1000base-T) ( 7mA typ - Energy Detect) WF: Marvell numbers, update for Realtek
0.1UF
10% 16V 2 X5R 402
CRITICAL FERR-120-OHM-1.5A
0402-LF
L3715
2
C3700
0.1UF
C3701
0.1UF
C3702
0.1UF PP1V05_ENET_PHYAVDD
CRITICAL
L3705
FERR-120-OHM-1.5A
0402-LF 2
10% 2 16V X5R 402
10% 16V 2 X5R 402
10% 16V 2 X5R 402
0.1UF PP3V3_ENET_PHYAVDD
10% 16V X5R 2 402
0.1UF
10% 16V 2 X5R 402
0.1UF
10% 16V X5R 2 402
C3705
0.1UF
C3706
0.1UF =PP3V3_ENET_PHY_VDDREG
9
10% 2 16V X5R 402
10% 2 16V X5R 402
If internal switcher is used, must place 1x 22uF & 1x 0.1uF caps within 5mm of U3700 pins 44 & 45. NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.
6 41 15 21 37 44 45 28 36 10 40
R37501
4.7K
5% 1/16W MF-LF 402 2
R3751
4.7K
5% 1/16W MF-LF
R37521
4.7K
5% 1/16W MF-LF 402 2
NO STUFF
AVDD33
DVDD33
VDDREG
DVDD12
AVDD12
FB12
R37201
Alias to =PP3V3_ENET_PHY for internal switcher. Alias to GND for external 1.05V supply.
9
5% 1/16W MF-LF 402 2
10K
R3725
4.7K
5% 1/16W MF-LF
2 402
=RTL8211_REGOUT 9 If internal switcher is used, must place inductor within 5mm of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor. If internal switcher is not used, VDDREG and REGOUT can float.
2 402
IN
=RTL8211_ENSWREG
39
ENSWREG
U3700
RTL8211CLGR
TQFP
OMIT
REGOUT
48
R3796
91 18
IN
ENET_CLK125M_TXCLK
1 22 2
5% 1/16W 402 MF-LF
ENET_CLK125M_TXCLK_R
91 18 91 18 91 18 91 18
22
TXC
RXC
19
91
ENET_CLK125M_RXCLK_R ENET_RXD_R<0> ENET_RXD_R<1> ENET_RXD_R<2> ENET_RXD_R<3> ENET_RXCTL_R
R3790 R3791 R3792 R3793 R3794 R3795
22 22 22 22 22 22
2 5% 1/16W MF-LF 402
ENET_CLK125M_RXCLK ENET_RXD<0> ENET_RXD<1> ENET_RXD<2> ENET_RXD<3> ENET_RX_CTRL

5% 1/16W MF-LF 402
OUT
18 91
IN IN IN IN
PLACE R3796 CLOSE TO U1400, PIN D24
ENET_TXD<0> ENET_TXD<1> ENET_TXD<2> ENET_TXD<3> ENET_TX_CTRL
23 24 25 26
TXD[0] TXD[1] TXD[2] TXD[3]
RGMII/MII
RXD[0] RXD[1]/TXDLY RXD[2]/AN0 RXD[3]/AN1
14 16 17 18
91 91 91 91
1 1 1 1
2 2 2 2
5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF
402 402 402 402
OUT OUT OUT OUT
18 91 18 91 18 91 18 91
91 18
IN
27
TXCTL
RXCTL
13
OUT
18 91
91 18 91 18
IN BI
ENET_MDC ENET_MDIO
30 31
MDC MDIO
MANAGEMENT
MDI+[0] MDI-[0] MDI+[1] MDI-[1] MDI+[2] MDI-[2]
1 2 4 5 8 9 11 12
ENET_MDI_P<0> ENET_MDI_N<0> ENET_MDI_P<1> ENET_MDI_N<1> ENET_MDI_P<2> ENET_MDI_N<2> ENET_MDI_P<3> ENET_MDI_N<3> RTL8211_PHYAD0 RTL8211_PHYAD1 RTL8211_RXDLY
35 91 35 91
R3724
91 18
35 91 35 91
IN
ENET_RESET_L
2 1
RTL8211_PHYRST_L
29
PHYRSTB*
RESET MEDIA DEPENDENT
5% 1/16W MF-LF 402
35 91 35 91
C3725
0.1UF RTL8211_RSET
46 RSET REFERENCE
ENET_RESET_L is not asserted when WOL is active. Hence, RC (R3725 and C3725) are made NOSTUFF.
NO STUFF
20% 2 10V CERM 402
MDI+[3] MDI-[3]
35 91 35 91
TP_RTL8211_CLK125
32
CLK125 CLOCK LED0/PHYAD0 LED1/PHYAD1 LED2/RXDLY 34 35 38
R37301
2.49K
1% 1/16W MF-LF 402 2
91 34
IN
RTL8211_CLK25M_CKXTAL1 TP_RTL8211_CKXTAL2
42 43
CKXTAL1 CKXTAL2
LED GND 7 20 33 47
C3790
10PF
R37551 R37561
4.7K
5% 1/16W MF-LF 402 2
4.7K
R3757
4.7K
5% 1/16W MF-LF
5% 50V CERM 2 402
5% 1/16W MF-LF 402 2
2 402
Reserved for EMI per RealTek request.
Ethernet PHY (RTL8211CL)
SYNC_MASTER=SUMA_M98_MLB

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
Configuration Settings:
PHYAD AN[1:0] RXDLY TXDLY = = = = 01 11 0 0 (PHY Address 00001) (Full auto-negotiation) (RXCLK transitions with data) (No TXCLK Delay)
APPLE INC.
SIZE
DRAWING NUMBER
REV.
D
SCALE NONE
051-7546
SHT OF
A.0.0
33
96
C3714 1
C3715 1 C3716 1
MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V
3.3V ENET FET

@ 2.5V Vgs: Rds(on) = 90mOhm max I(max) = 1.7A (85C)
8
CRITICAL
Q3810
NTR4101P
SOT-23-HF
=PP3V3_S5_P3V3ENETFET
2
=PP3V3_ENET_FET
S D 3
1
R38001
10K
5% 1/16W MF-LF 402 2
C3811
0.033UF
1
R3810
P3V3ENET_EN_L
1
10% 2 16V X5R 402
C3810
0.01UF
2 1 10% 16V CERM 402
100K 2
5% 1/16W MF-LF 402
P3V3ENET_SS
Q3801
SSM6N15FEAPE
SOT563
D 3
5
9
S 4
IN
=P3V3ENET_EN
MOBILE: Recommend aliasing PM_SLP_RMGT_L and =P3V3ENET_EN. Nets separated on ARB for alternate power options.
WLAN Enable Generation

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0")) NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.
C
Q3805
SSM6N15FEAPE
SOT563
PM_WLAN_EN_L OUT 31 Pull-up is with power FET.

D 6
8
1.05V ENET FET

=PP1V05_ENET_P1V05ENETFET 1.8V Vgs
2
31 21
S 1
C3840 1
AC_OR_S0_L 0.1UF
6
IN
AP_PWR_EN
Q3805
SSM6N15FEAPE
SOT563
D 3
Q3801
SSM6N15FEAPE
SOT563
=PP3V3_S5_P1V05ENETFET
R3840
1
20% 10V CERM 2 402 1
CRITICAL
100K 2
5% 1/16W MF-LF 402
Q3840
G S
P1V05ENET_SS
SI2312BDS
SOT23 2
R38421
5
43 42 37 21
Q3841
SSM6N15FEAPE
SOT563
S 4
G 2
69.8K
1% 1/16W MF-LF 402 2
=PP1V05_ENET_FET
IN
SMC_ADAPTER_EN
R3841
83 81 68 44 42 37 21 7
IN
PM_SLP_S3_L
P1V05ENET_EN_L
10K
S 1
C3841
0.01UF
Q3841
SSM6N15FEAPE
SOT563
D 3
1% 1/16W MF-LF 402
10% 2 16V CERM 402
P1V05ENET_EN_L_RC
S 4
IN
=P1V05ENET_EN
Non-ARB: Recommend aliasing PM_SLP_RMGT_L and =P1V05ENET_EN. Nets separated on ARB for alternate power options.
RTL8211 25MHz Clock

A
NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered. Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.
Ethernet & AirPort Support

SYNC_MASTER=SUMA_M98_MLB SYNC_DATE=07/01/2008
R3895
91 18
IN
MCP_CLK25M_BUF0_R
22
RTL8211_CLK25M_CKXTAL1
OUT
33 91
5% 1/16W MF-LF 402 PLACEMENT_NOTE=Place close to U1400
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
34
96
Page Notes
Power aliases required by this page: (NONE) Signal aliases required by this page: (NONE) BOM options provided by this page: (NONE)
Place one of 0.1uf cap close to each centertap pin of transformer
ENETCONN_CTAP
1
C3900
0.1UF
10% 16V X5R 402
C3902
0.1UF
10% 16V X5R 402
C3904
0.1UF
10% 16V 402
C3906
0.1UF
10% 16V 402
2 X5R
2 X5R
CRITICAL
91 33
BI
ENET_MDI_P<0> ENET_MDI_N<0>
1 2 3
T3900 SM
95
12
ENETCONN_P<0> ENETCONN_N<0> ENET_CTAP0
91 33
BI
95 11
CRITICAL
10
TX
J3900
F-RT-TH
9 10
RJ45-M97-2
C
91 33
TLA-6T213HF
4 9 8 7
RX
95
ENET_CTAP1 ENETCONN_N<1> ENETCONN_P<1>
BI
ENET_MDI_N<1> ENET_MDI_P<1>
5 6
1 2
91 33
BI
95
3 4 5
CRITICAL
6 7
95 12
91 33
BI
1 2 3
T3901 SM
ENETCONN_N<2> ENETCONN_P<2> ENET_CTAP2
91 33
BI
95
11 10
11 12
TX
TLA-6T213HF
4 9 8 7
RX
95
514-0596
ENET_CTAP3 ENETCONN_N<3> ENETCONN_P<3>
91 33
BI
5 6
91 33
BI
95
Transformers should be mirrored on opposite sides of the board
R39001 R39011
5% 1/16W MF-LF 402 2
75
5% 1/16W MF-LF 402 2
75
R3902
75
R3903
75 CRITICAL
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
C3908
1000PF
1 2 10% 2KV CERM 1206
ENET_BOB_SMITH_CAP
Ethernet Connector
SYNC_MASTER=SUMA_M98_MLB

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
35
96
4
7 mA I/O
2
=PP3V3_FW_FWPHY 138 mA
8 36 38
C4120 1
10% 6.3V 2 CERM 402
1UF
C4121 1 C4122 1
10% 6.3V 2 CERM 402
1UF
10% 6.3V 2 CERM 402
1UF
C4123 1 C4124 1
10% 6.3V 2 CERM 402
1UF
10% 6.3V 2 CERM 402
1UF
D
10% 6.3V 2 CERM 402
120-OHM-0.3A-EMI 114 mA FireWire PHY PP3V3_FW_FWPHY_VDDA 1 2
L4130
0402-LF
C4130 1 C4131 1
1UF
10% 6.3V 2 CERM 402
C4132 1
10% 6.3V 2 CERM 402
1UF
1UF
=PP1V0_FW_FWPHY 135 mA
120-OHM-0.3A-EMI 1 2 PP1V0_FW_FWPHY_AVDD
0402-LF MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.0V
L4110
25 mA PCIe SerDes
1
17 mA PCIe SerDes
120-OHM-0.3A-EMI 1 2 PP3V3_FW_FWPHY_VP25
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V 0402-LF
L4135
C4110
1UF
C4111
1UF
C4135 1
10% 6.3V 2 CERM 402
10% 2 6.3V CERM 402
10% 2 6.3V CERM 402
1UF
C4136 1
10% 6.3V 2 CERM 402
1UF
110 mA Digital Core

1
0 mA VReg PWR
C4100
1UF
C4101
1UF
C4102
1UF
C4103
1UF
C4104
1UF
C4105
1UF
C4106
1UF
C4141 1
0.1UF
20% 10V CERM 2 402
C4140
1UF
10% 2 6.3V CERM 402
10% 2 6.3V CERM 402
10% 2 6.3V CERM 402
10% 2 6.3V CERM 402
10% 2 6.3V CERM 402
10% 2 6.3V CERM 402
10% 2 6.3V CERM 402
10% 2 6.3V CERM 402
C
A1 B1 B12 C13 E2 E10 H2 H12 K2 L1 M12 N3 N11 C1 C12 F1 G12 J1 L3 L11 M2 A12 D5 D6 D8 L5 L10 K12 L6 L9
PLACEMENT_NOTE=Place C4170 close to U1400 PLACEMENT_NOTE=Place C4171 close to U1400
C4170 1 C4171 1
PCIE_RXD0N PCIE_RXD0P PCIE_TXD0N PCIE_TXD0P N8 N7 N5 N6
89 89 89 89
0.1UF 0.1UF
VDD10
VDD33
VDDH
VP
VP25
VREG_PWR
NC NC NC
38 38 38
B13 ATBUSB A13 ATBUSH A11 ATBUSN F12 DS0 E12 DS1 E13 DS2 B8 A8 B5 A5 B3 A3 B9 A9 B6 A6 B4 A4
OMIT CRITICAL
U4100
FW643
BGA PCI EXPRESS PHY
IN IN IN BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
=FW_PHY_DS0 =FW_PHY_DS1 =FW_PHY_DS2 FW_P0_TPA_N FW_P0_TPA_P FW_P1_TPA_N FW_P1_TPA_P FW_P2_TPA_N FW_P2_TPA_P FW_P0_TPB_N FW_P0_TPB_P FW_P1_TPB_N FW_P1_TPB_P FW_P2_TPB_N FW_P2_TPB_P FW_P0_TPBIAS FW_P1_TPBIAS FW_P2_TPBIAS FW643_R0 FW643_TPCPS TP_FW643_NAND_TREE FW643_REXT FW_CLK24P576M_XO_R FW_CLK24P576M_XI
(IPD) NT-19 (IPD) NT-20 (IPD) NT-21
PCIE_FW_R2D_N PCIE_FW_R2D_P PCIE_FW_D2R_C_N PCIE_FW_D2R_C_P PCIE_CLK100M_FW_N PCIE_CLK100M_FW_P TP_FW643_TCK TP_FW643_TDI TP_FW643_TDO TP_FW643_TMS FW643_TRST_L
IN IN
17 89 17 89
10% 16V 2 X5R 402 10% 16V 2 X5R 402
PCIE_FW_R2D_C_N PCIE_FW_R2D_C_P
IN
17 89
IN
17 89
C4175 1 C4176 1
REFCLKN N9 REFCLKP N10
10% 16V PCIE_FW_D2R_N 2 OUT 17 89 X5R 402 10% 16V PCIE_FW_D2R_P 2 OUT 17 89 0.1UF X5R 402 PLACEMENT_NOTE=Place C4175 close to U4000 PLACEMENT_NOTE=Place C4176 close to U4000
0.1UF
92 38 92 38 92 38 92 38 38 38 92 38 92 38 92 38 92 38
38
=PPVP_FW_PHY_CPS
38 38
TPA0N TPA0P TPA1N TPA1P TPA2N TPA2P TPB0N TPB0P TPB1N TPB1P TPB2N TPB2P
TEST CONTROLLER 1394 PHY
NT-4 (IPU) TCK NT-3 (IPU) TDI (IPU) TDO NT-1 (IPU) TMS NT-2 (IPU) TRST*
M4 N2 M1 M3 N1
=PP3V3_FW_FWPHY FW643_LDO
8 36 38
R41651
OUT
19
R4166
10K
B
C4150
22PF
2
1
R41601
390K
5% 1/16W MF-LF 402 2
38 38 38
B7 TPBIAS0 C3 TPBIAS1 A2 TPBIAS2 B11 R0 B10 TPCPS K1 L8 F13 G13 M13 N13 J2 L13 D12 D1 A10 H13 K13 NAND_TREE REXT XO XI NT-9
WAKE* FIXME!!! - TYPO IN SYMBOL REGCTL REGCLT POWER MANAGEMENT VAUX_DETECT NT-12 (IPD) VAUX_DISABLE NT-13 (OD) CLKREQN
NT-10 (IPD)
C2 D13 E1 D2 L2
FW_PME_L FW643_REGCTL FW643_VAUX_DETECT TP_FW643_VAUX_ENABLE FW_CLKREQ_L
5% 1/16W MF-LF 402 2
10K
5% 1/16W MF-LF 2 402
OUT
17
R4164
10K
R4150
FW_CLK24P576M_XO CRITICAL
NC
1
NT-OUT NOTE: NT-xx notes show NAND tree order.
SCIF
412
NT-16 (IPD) SCIFCLK NT-14 (IPD) SCIFDAIN NT-17 SCIFDOUT NT-15 (IPD) SCIFMC
G2 G1 H1 F2
TP_FW643_SCIFCLK TP_FW643_SCIFDAIN TP_FW643_SCIFDOUT TP_FW643_SCIFMC
5% 1/16W MF-LF 2 402
5% 50V CERM 402
Y4150
24.576MHZ
SM-3.2X2.5MM
1% 1/16W MF-LF 402
C4151 NC
22PF
2 5% 50V CERM 402 1
R41611
2.94K
1% 1/16W MF-LF 402 2
R4170
191
1% 1/16W MF-LF 2 402
TP_FW643_SE TP_FW643_SM TP_FW643_MODE_A TP_FW643_CE TP_FW643_FW620_L TP_FW643_JASI_EN TP_FW643_AVREG TP_FW643_VBUF FW643_PU_RST_L TP_FW643_OCR10_CTL
NC
SE (IPD) SM (IPD) MODE_A (IPD) NT-18 CE (IPD) FW620* (IPU) JASI_EN (IPD) NT-11 AVREG VBUF FW_RESET* (IPU) NT-8
SERIAL EEPROM CONTROLLER
NT-7 NT-6
SCL SDA
N12 M11
FW643_SCL TP_FW643_SDA
MISCELLANEOUS CHIP RESET
NT-5
PERST*
N4
FW_RESET_L
1
IN
26
R4163
10K
R41621
470K
5% 1/16W MF-LF 402 2
C4162
0.33UF
J12 OCR_CTL_V10 J13 OCR_CTL_V12
(Reserved)
VSS VREG_VSS L12
B2 D4 D7 D9 D10 E4 E5 E9 F4 F6 F7 F8 F10 G4 G6 G7 G8 G10 H4 H6 H7 H8 H10 J4 J5 J9 J10 K4 K5 K7 K8 K9 L7 K6 K10
10% 2 6.3V CERM-X5R 402
5% 1/16W MF-LF 2 402
FireWire LLC/PHY (FW643)

SYNC_MASTER=SENSOR SYNC_DATE=08/14/2008

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
36
96
2 4 3
Page Notes
Power aliases required by this page: - =PPBUS_S5_FWPWRSW (system supply for bus power) - =PP3V3_FW_LATEVG_ACTIVE - =PPVP_FW_SUMNODE (power passthru summation node) Signal aliases required by this page: (NONE) BOM options provided by this page: - FW_PORT_FAULT_PU
FireWire Port Power Switch

CRITICAL
Q4260
NDS9407
8
OMIT CRITICAL
CRITICAL
D4260
PWRDI5 2
=PPBUS_S5_FWPWRSW
3 2 1
SOI-HF 8 7 6 5 4
F4260
1.5A-24V PPBUS_FW_FWPWRSW_F
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V 1 2
=PPBUS_S5_FW_FET
3
PPBUS_FW_FWPWRSW_D
1
1812L15024HF
R4260
470K
C4260 1
0.01uF
20% 16V CERM 2 402
PDS540XF
5% 1/16W MF-LF 2 402
FWPWR_EN_L_DIV
1
5% 1/16W MF-LF 2 402
330K
FWPWR_EN_L Enables port power when machine is running or on AC. Q4261 D SSM6N15FEAPE
SOT563 6
Q4261
SSM6N15FEAPE
SOT563
D 3
2
43 42 34 21
IN IN
SMC_ADAPTER_EN PM_SLP_S3_L
S 1
S 4
83 81 68 44 42 34 21 7
FW_PORTPWR_EN_FET
Q4262
SSM3K15FV
SOD-VESM-HF
D 3
S 2
37
FW_PORTPWR_EN
Late-VG Event Detection

8 38
=PP3V3_FW_LATEVG_ACTIVE PP2V4_FW_LATEVG
R42111
5% 1/16W MF-LF 402 2
R4212
10K
2 V+
C4210
0.1UF
R4219
2.0M
10K
1% 1/16W MF-LF 2 402
20% 2 10V CERM 402 4
P2V4_FWLATEVG_RC
U4210
SM-HF 1
5% 1/16W MF-LF 2 402
LMC7211
LATEVG_EVENT_L
D4219
SOD-123 2 1 1
FW_PORTPWR_EN
37
FWLATEGV_3V_REF
V5
MBR0540XXH
C4219
0.33UF
C4211 1
100pF
5% 50V CERM 2 402
R4213
80.6K
1% 1/16W MF-LF 2 402
10% 2 10V CERM-X5R 603
R4210
1
200K 2
1% 1/16W MF-LF 402
FWLATEVG_3V_REF Hysteresis: 2.95V when port power is on 2.81V on late Vg event and port power is off
FireWire Port Power
A
PART NUMBER
740S0080
SYNC_MASTER=SENSOR

QTY
1
DESCRIPTION
LITTLEFUSE, 1.5A RESETTABLE 24V
REFERENCE DES
F4260
CRITICAL
CRITICAL
BOM OPTION
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
37
96
R4261
5
=PP3V3_FW_FWPHY
Page Notes
Power aliases required by this page: - =PPVP_FW_PORT1 - =PP3V3_FW_LATEVG
38 36 8
R43821 R43801
1% 1/16W MF-LF 402 2
10K
- =GND_CHASSIS_FW_PORT1 - =GND_CHASSIS_FW_EMI_R
1% 1/16W MF-LF 402 2
10K
Signal aliases required by this page: (NONE) NOTE: This page is expected to contain the necessary aliases to map the FireWire TPA/TPB pairs to their appropriate connectors and/or to properly terminate unused signals. BOM options provided by this page: (NONE) NOTE: FireWire TPA/TPB pairs are NOT constrained on this page. It is assumed that FireWire PHY page will provide the appropriate constraints to apply to entire TPA/TPB XNets. 1394b implementation based on Apple FireWire Design Guide (FWDG 0.6, 5/14/03)
FireWire PHY Config Straps

Configures PHY for: - 1-port Portable Power Class (0) - Port "1" Bilingual (1394B)
FWPHY_DS0
MAKE_BASE=TRUE
=FW_PHY_DS0 =FW_PHY_DS2 =FW_PHY_DS1
36
FWPHY_DS2
MAKE_BASE=TRUE
36
FWPHY_DS1
MAKE_BASE=TRUE
36
R43811
1% 1/16W MF-LF 402 2
10K
36 36 92 36 92 36 36 36
FW_P0_TPBIAS FW_P2_TPBIAS FW_P0_TPA_N FW_P0_TPA_P FW_P2_TPA_N FW_P2_TPA_P FW_P0_TPB_N FW_P0_TPB_P FW_P2_TPB_N FW_P2_TPB_P
NC_FW0_TPBIAS MAKE_BASE=TRUE NC_FW2_TPBIAS MAKE_BASE=TRUE NC_FW0_TPAN MAKE_BASE=TRUE NC_FW0_TPAP MAKE_BASE=TRUE NC_FW2_TPAN MAKE_BASE=TRUE NC_FW2_TPAP MAKE_BASE=TRUE NC_FW0_TPBN NC_FW0_TPBP NC_FW2_TPBN NC_FW2_TPBP
MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE
92 36
Termination
Place close to FireWire PHY
36
92 36 36 36
FW_P1_TPBIAS
Q4300
(SYM-VER2)
SOT-363
TI PHYs require 1uF even though FW spec calls out 0.33uF

1
C4360
0.33UF
4
8
C
Cable Power
D
10% 2 6.3V CERM-X5R 402
=PPVP_FW_PHY_CPS_FET
R43111
470K
5% 1/16W MF-LF 402 2
PPVP_FW_CPS MAKE_BASE=TRUE MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=12.6V
=PPVP_FW_PHY_CPS
36
CRITICAL
8
=PPVP_FW_PORT1
"Snapback" & "Late VG" Protection

38 37
FERR-250-OHM Note: Trace PPVP_FW_PORT1 must handle up to 5A 1 2 PPVP_FW_PORT1_F

SM 1
L4310
PP2V4_FW_LATEVG
C4314
0.01UF
DP4310
CPS_EN_L_DIV BAV99DW-X-G
C4311 1
1
SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY 1
R43121
330K
5% 1/16W MF-LF 402 2
0.01uF
SOT-363 5
10% 2 50V X7R 402
R4360
56.2
R4361
56.2
10% 50V 2 X7R 402 4
PORT 1
BILINGUAL
CRITICAL
1% 1/16W MF-LF 2 402

92 36
1% 1/16W MF-LF 402 2
DP4310
CPS_EN_L BAV99DW-X-G
C4310
FW_PORT1_TPA_P
MAKE_BASE=TRUE
FW_P1_TPA_P FW_P1_TPA_N FW_P1_TPB_P FW_P1_TPB_N

SIGNAL_MODEL=EMPTY 1 SIGNAL_MODEL=EMPTY 1
0.01uF
38
SOT-363 2
92 36
FW_PORT1_TPA_N
MAKE_BASE=TRUE
38
10% 50V 2 X7R 402
6 1
1
92 36
FW_PORT1_TPB_P
MAKE_BASE=TRUE
Q4300
38 38 36 8 38
1394B-M97
F-RT-TH1
TPB-
J4310
=PP3V3_FW_FWPHY
G S
1
BSS8402DW
SOT-363
(SYM-VER1)
38
FW_PORT1_TPB_N (FW_PORT1_BREF) FW_PORT1_TPB_P
92 36
FW_PORT1_TPB_N
MAKE_BASE=TRUE
9 2 8
38
TPB+
R4362
56.2
R4363
56.2
NC7 (GND_FW_PORT1_VG)
38
1% 1/16W MF-LF 2 402
1% 1/16W MF-LF 402 2
6 3
FW_PORT1_TPA_N FW_PORT1_AREF FW_PORT1_TPA_P
5 4
38
TPBTPB<R> VP TPB+ VP NC NC VG TPA- TPAVG TPA<R> TPA(R) TPA+ TPA+
TPB(R)
OUTPUT
B
INPUT
FW_PORT1_TPB_C
1 1 C4364 R4364 4.99K 5% 2 25V CERM 402
DP4311
BAV99DW-X-G
SOT-363 2
10
C4319 1 DP4311
6
11 12 13 14 15
CABLE OUTER SHLD
220pF
0.1uF
1% 1/16W MF-LF 402 2
C4312 1
0.01uF
10% 50V 2 X7R 402 1
BAV99DW-X-G
SOT-363 5 1
10% 50V 2 X7R 603-1
CHASSIS GND
C4313 1
0.01uF
10% 50V 2 X7R 402 4
R4319
1M
5% 1/16W MF-LF 2 402
AREF needs to be isolated from all local grounds per 1394b spec When a bilingual device is connected to a beta-only device, there is no DC path between them (to avoid ground offset issue) BREF should be hard-connected to logic ground for speed signaling and connection
514S0605
PLACEMENT_NOTE=Place C4319 close to connector pin 5.
Late-VG Protection Power

A
8
FireWire Ports
=PP3V3_FW_LATEVG
R4390
1
332
PP2V4_FW_LATEVG
MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=2.4V 3
37 38

1% 1/16W MF-LF 402
PP2V4_FWLATEVG needs to be biased to at least 2.1V for FW signal integrity and should be biased to 2.4V for margin R4390 should be 390 Ohms max for a 3.3V rail
ESD and late-VG rail CRITICAL for snap-back diodes D4390 (Common to all ports) MMBZ5227BLT1H
SOT23
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
38
96
BSS8402DW
ODD Power Control

CRITICAL
Q4590
FDC606P_G
6 2 5
8
=PP5V_S0_ODD
4
SOT-6
PP5V_SW_ODD
D
NOTE: 3.3V must be S0 if 5V is S3 or S5 to ensure the drive is unpowered in S3/S5.
39 8
MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V
100K
5% 1/16W MF-LF 402
=PP3V3_S0_ODD
R4595
ODD_PWR_EN_LS5V_L
1
10% 10V 2 CERM 402
0.068UF
R4596
100K 2
5% 1/16W MF-LF 402
C4595
C4596
0.01UF
1 2 10% 16V CERM 402
R4597
100K
5% 1/16W MF-LF 402
ODD_PWR_SS
Q4596
SSM6N15FEAPE
SOT563
D 6
ODD_PWR_EN
2
Q4596
SSM6N15FEAPE
SOT563
D 3
S 1
5
21
S 4
IN
ODD_PWR_EN_L
SATA ODD Port

FL4520 90-OHM-100MA
DLP11S CRITICAL 3
SYM_VER-1
C
PLACEMENT_NOTE=PLACE C4520 CLOSE TO MCP79 PLACEMENT_NOTE=PLACE C4521 NEXT TO C4520
1 2
95
SATA_ODD_R2D_UF_P
C4521 C4520
CERM 402
SATA_ODD_R2D_C_P
IN
20 89
0.01UF
CRITICAL 55560-0168
M-ST-SM-LF 2 4
39 8
10% 16V CERM 402 2
J4500
1 3 5 7 9
95
SATA_ODD_R2D_UF_N
SATA_ODD_R2D_C_N
IN
20 89
0.01UF
PLACEMENT_NOTE=Place FL4520 close to J4500
89 7 89 7
10% 16V
=PP3V3_S0_ODD
6 8 10
SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_D2R_C_N SATA_ODD_D2R_C_P
89 7 89 7
R45901
5% 1/16W MF-LF 402 2
12 14 16
11 13 15
33K
PLACEMENT_NOTE=PLACE C4526 CLOSE TO J4500 PLACEMENT_NOTE=PLACE C4525 NEXT TO C4526
90-OHM-100MA DLP11S
SYM_VER-1
FL4525
CRITICAL 3 SATA_ODD_D2R_N OUT
20 89
C4526 1
0.01UF
95
SATA_ODD_D2R_UF_N
CERM 402
10% 16V 2
95
516S0617
42 7
C4525 1
0.01UF
SATA_ODD_D2R_UF_P
402
SATA_ODD_D2R_P
OUT
20 89
OUT
SMC_ODD_DETECT
10% 16V CERM
Indicates disc presence
PLACEMENT_NOTE=Place FL4525 close to J4500
B
CRITICAL
B
C4501
0.1UF
CRITICAL
C4502
0.1UF
PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501 PLACEMENT_NOTE=PLACE C4502 CLOSE TO J4501
20374020E31
F-ST-SM 21
J4501
20% 2 10V CERM 402
FERR-70-OHM-4A
1 2 3 4 5 6 7 8 9 10 11 12 13 14
89 CRITICAL
L4500
0603
20% 2 10V CERM 402
SATA HDD Port

2
PP5V_S0_HDD_FLT
=PP5V_S0_HDD
PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501
FL4501 90-OHM-100MA
DLP11S
SYM_VER-1
PLACEMENT_NOTE=Place C4510 close to MCP79 PLACEMENT_NOTE=Place C4511 next to C4510

4
95
NC NC
89
SATA_HDD_R2D_UF_P
C4510 1
0.01UF
SATA_HDD_R2D_C_P
402
IN
20 89
10% 16V CERM 2
SATA_HDD_R2D_P
2 1
95
NC
89
SATA_HDD_R2D_UF_N
C4511 1
0.01UF
90-OHM-100MA DLP11S
SYM_VER-1
SATA_HDD_R2D_C_N
402
IN
20 89
SATA_HDD_R2D_N PLACEMENT_NOTE=Place FL4501 close to J4501 SATA_HDD_D2R_C_N SATA_HDD_D2R_C_P
10% 16V CERM
FL4502
CRITICAL
NC
89
C4515 1
0.01UF
95
SATA_HDD_D2R_UF_N
SATA_HDD_D2R_N
OUT
20 89
10% 16V CERM 402 2

95
SATA Connectors
SYNC_MASTER=CHANG_M98_MLB SYNC_DATE=07/01/2008
15 16 17 18 19 20
NC NC
C4516 1
0.01UF
SATA_HDD_D2R_UF_P
SATA_HDD_D2R_P
OUT
20 89
10% 16V CERM 402
PLACEMENT_NOTE=PLACE FL4502 CLOSE TO J4501

PLACEMENT_NOTE=Place C4515 next to C4516 PLACEMENT_NOTE=Place C4516 close to J4501
22
518S0654
APPLE INC.
D
SCALE NONE
051-7546
SHT OF
A.0.0
39
96
Port Power Switch

CRITICAL
Left USB Port A

CRITICAL FERR-220-OHM-2.5A 1 2 PP5V_S3_RTUSB_A_F
0603
Q4690
L4605
C
68 43 42 21
=PP5V_S3_RTUSB
20
TPS2064DGN
2 OUT IN OC1* OUT2 6 OUT1 7
PP5V_S3_RTUSB_A_ILIM
PM_SLP_S4_L 1
USB_EXTA_OC_L USB_EXTB_OC_L
8 3
MSOP
R4690
5.1K USB_PWR_EN
20
OUT
5% 1/16W MF-LF 2 402
EN1 5 OC2* 4 EN2
PP5V_S3_RTUSB_B_ILIM
C4605
0.01uF
C
CRITICAL
J4600
USB
6
20% 16V CERM 2 402

4
CRITICAL
DLP11S
SYM_VER-1
L4600 90-OHM-100MA
3
95
F-RT-TH-M97-3 5
GND TPAD
1 9
CRITICAL
CRITICAL
1 2
1
95
USB2_EXTA_MUXED_N
95
USB2_LT1_N USB2_LT1_P
2 5 3 4
C4690 C4692
0.47UF
1
10UF
C4691
0.1UF
1 2
C4695 1
10UF
20% 6.3V 2 X5R 603
NC IO NC IO
10% 10V 2 X5R 402
20% 6.3V 2 X5R 603
20% 2 10V CERM 402
C4696 C4617 10UF

100UF
C4616
100UF USB2_EXTA_MUXED_P
1 2
95
20% 2 6.3V POLY-TANT CASE-B2-SM
20% 6.3V X5R 603
3 4
7 8
6 VBUS 1 GND
514-0606
D4600
RCLAMP0502N
SLP1210N6
CRITICAL We can add protection to 5V if we want, but leaving NC for now L4615 FERR-220-OHM-2.5A Place L4600 and L4605 at connector pin 1 2 PP5V_S3_RTUSB_B_F CRITICAL
0603
C4615
0.01uF
20% 402
B
CRITICAL
2 16V CERM
USB/SMC Debug Mux

SMC_DEBUG_YES
8
J4610
USB
6
F-RT-TH-M97-3 5
CRITICAL
90-OHM-100MA DLP11S
SYM_VER-1
=PP3V42_G3H_SMCUSBMUX SMC_DEBUG_YES
SIGNAL_MODEL=USB_MUX 1 9
L4610
95
1 3
95
C4650 1
0.1UF
44 43 42 44 43 42
R4650
10K
90 20
BI
USB_EXTB_N USB_EXTB_P
USB_LT2_N USB_LT2_P
2 3 4
IN OUT
SMC_RX_L SMC_TX_L USB_EXTA_P USB_EXTA_N
20% 10V CERM 2 402
VCC
5 M+ 4 M7 D+ 6 DY+ 1 Y- 2
5% 1/16W MF-LF 2 402
90 20
BI
2 7
PI3USB102ZLE
90 20 90 20
BI BI
TQFN
6 VBUS 1 GND
CRITICAL
SEL 10 GND 3
OE*
USB_DEBUGPRT_EN_L SEL=0 Choose SMC SEL=1 Choose USB
IN
42
D4610
RCLAMP0502N
SLP1210N6
NC IO NC IO
U4650
2 5 3 4
CRITICAL
External USB Connectors

SYNC_MASTER=AMASON_M98_MLB SYNC_DATE=07/02/2008
SMC_DEBUG_NO
R4651
1
Left USB Port B

SMC_DEBUG_NO

5% 1/16W MF-LF 402
R4652
1
5% 1/16W MF-LF 402
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
40
96
41 8 =PP5V_S3_IR
D
1
C4801
0.1UF
10% 16V X7R-CERM 402
VCC
CY7C63803-LQXC
QFN
90 20 90 20
BI BI
USB_IR_P DIFFERENTIAL_PAIR=USB2_IR USB_IR_N DIFFERENTIAL_PAIR=USB2_IR IR_VREF_FILTER
C4803
1UF
10% 10V X5R 402-1
12 13 15 16 17 18 19
P1.0/D+ P1.1/DP1.2/VREG P1.3/SSEL P1.4/SCLK P1.5/SMOSI P1.6/SMISO
P0.0 P0.1 INT0/P0.2 INT1/P0.3 INT2/P0.4 TIO0/P0.5 TIO1/P0.6
7 6 5 4 3 2 1
R4800
100
IR_RX_OUT_RC
1 5% 1/16W MF-LF 402 1 2
IR_RX_OUT
IN
41
8 9 10 20 21 NC 22 23 24
CRITICAL OMIT
P/N 338S0633
2
C4804
0.001UF
10% 50V CERM 402
C
THRML PAD 25 VSS 11
B
FF18-6A-R11AD-B-3H
F-RT-SM
B
J4800
1 2 3 4 5 6
R4805
1
1/16W
10
5% MF-LF
PLACE PLACE PLACE PLACE
R4805 R4806 R4807 R4808
NEAR NEAR NEAR NEAR
J4800 J4800 J4800 J4800
2
402
=PP3V42_G3H_LIDSWITCH
CRITICAL
PP3V42_G3H_LIDSWITCH_R PP5V_S3_IR_R
R4806
1
1/16W 5% MF-LF
10
2
402
=PP5V_S3_IR
8 41
R4807
1
SMC_LID_R SYS_LED_ANODE_R
100
5% MF-LF
2
402
R4808
1
1/16W 5% MF-LF
1/16W
4.7
2
402
SMC_LID 42 SYS_LED_ANODE 43 IR_RX_OUT

41
43 50
518S0692
1
C4805
0.1UF
10% 16V X7R-CERM 402
C4806
0.1UF
10% 16V X7R-CERM 402
C4807
0.001UF
10% 50V CERM 402
C4808
0.001UF
10% 50V CERM 402
PLACE C4805 NEAR J4800 PLACE C4806 NEAR J4800 PLACE C4807 NEAR J4800 PLACE C4808 NEAR J4800
Front Flex Support
SYNC_MASTER=CHANG_M98_MLB

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
41
96
U4800
14
NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating, those designated as inputs require pull-ups.
43 7 52 43 8
PP3V3_S5_AVREF_SMC =PP3V3_S5_SMC
D
C4902 1
22UF
1
D
C4903
0.1UF
1
C4904
0.1UF
C4905
0.1UF
C4906
0.1UF PLACEMENT_NOTE=Place C4907 close to U4900 pin F1
32 43 68 26 68
OUT OUT IN IN
SMC_EXCARD_PWR_EN SMC_RSTGATE_L ALL_SYS_PWRGD RSMRST_PWRGD PM_RSMRST_L IMVP_VR_ON PM_PWRBTN_L ESTARLDO_EN

NC NC NC NC NC NC
U4900
B12 A13 A12 B13 D11 C13 C12 D10 D13 E11 D12 F11 E13 E12 F13 E10 A9 D9 C8 B7 A8 D8 D7 D6 P10 P11 P12 P13 P14 P15 P16 P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34 P35 P36 P37 P40 P41 P42 P43 P44 P45 P46 P47 P50 P51 P52
20% 6.3V 2 CERM 805
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
HS82117
LGA-HF (1 OF 3)
OMIT
21 62 23 21
OUT OUT OUT OUT
NC
C4920 1
0.1UF
20% 10V CERM 2 402
SMC_PROCHOT_3_3_L SMC_BIL_BUTTON_L SMC_CPU_ISENSE SMC_CPU_VSENSE SMC_GPU_ISENSE SMC_GPU_VSENSE SMC_DCIN_ISENSE SMC_PBUS_VSENSE SMC_BATT_ISENSE SMC_NB_MISC_ISENSE SMC_WAKE_SCI_L
IN IN IN IN IN IN IN IN IN IN OUT
43 43
AVCC
VCC
VCL AVREF NC
10% 6.3V CERM-X5R 2 402
43
43
SMC_P24 SMC_P26
43
P70 P71 P72 P73 P74 P75 P76 P77 P80 P81 P82 P83 P84 P85 P86 P90 P91 P92 P93 P94 P95 P96 P97
N10 M11 L10 N11 N12 M13 N13 L12 A7 B6 C7 D5 A6 B5 C6 J4 G3 H2 G1 H4 G4 F4 F1
46 46 47 46 46 46 46
PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15 PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15
HS82117
LGA-HF (3 OF 3)
U4900
OMIT
R49091
E5 NC 5% 1/16W MF-LF 402 2
10K
R4901
10K
5% 1/16W MF-LF 2 402
44 43
IN
43
SMC_RESET_L SMC_XTAL SMC_EXTAL
D3 A3 A2
RES* XTAL EXTAL
MD1 MD2
D1 H1
SMC_MD1 SMC_KBC_MDE
IN
44
43 43 21 23
NMI
E3
SMC_NMI
IN
44
90 83 44 19 90 83 44 19 90 83 44 19
BI BI BI BI IN IN IN BI
90 83 44 19 90 83 44 19 26 90 26 44 19
43 45 52
BI OUT
SMC_P41 SMB_MGMT_DATA SMS_ONOFF_L
NC
(OC)
NC NC
76 51
OUT OUT OUT IN BI
SMC_GFX_THROTTLE_L SMC_SYS_KBDLED SMC_TX_L SMC_RX_L SMB_0_S0_CLK
D4 A5 B4 A1 C2 B2 C1 C3 G2 F3 E4
SMC_ONOFF_L SMC_BC_ACOK SMC_BS_ALRT_L PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L PM_CLK32K_SUSCLK (OC) SMB_0_S0_DATA
IN IN IN IN IN IN IN BI
43 50 43 60 43 60 7 21 34 37 44 68 81 83 21 40 43 68 43 26 90 45
D2 L3 F10 B11 C5
LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_FRAME_L SMC_LRESET_L LPC_CLK33M_SMC LPC_SERIRQ
PM_CLKRUN_L LPC_PWRDWN_L SMC_TX_L SMC_RX_L (OC) SMB_MGMT_CLK
NC
OUT IN OUT IN BI
19 44 19 44 40 42 43 44 40 42 43 44 45
ETRST AVSS VSS
H3 L9 1
SMC_TRST_L NO STUFF
IN
44
R4902
10K
R4998
10K
R4903
0
XW4900 SM
2 1
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
NOTE: P94 and P95 are shorted, P95 could be spare.
GND_SMC_AVSS
43 46 47
44 43 42 40 44 43 42 40 45
(OC)
(DEBUG_SW_1) (DEBUG_SW_2)
26 40 29 28 21
OUT OUT BI
B
60 43 23 21
BI OUT
SMC_PA0 SMC_PA1 PM_SYSRST_L USB_DEBUGPRT_EN_L MEM_EVENT_L SMC_PA5 43 SYS_ONEWIRE PM_BATLOW_L

43 43
U4900
(OC) (OC) (OC) (OC) (OC) (OC)
NC
N3 N1 M3 M2 N2 L1 K3 L2 B8 C9 B9 A10 C10 B10 C11 A11 G11 G13 F12 H13 G10 G12 H11 J13 M10 N9 K10 L8 M9 N8 K9 L7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
HS82117
LGA-HF (2 OF 3)
OMIT
PE0 PE1 PE2 PE3 PE4 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 PH0 PH1 PH2 PH3 PH4 PH5
K1 J3 K2 J1 K4 K5 N5 M6 L5 M5 N4 L4 M4 M8 N7 K8 K7 K6 N6 M7 L6 E2 F2 J2 A4 B3 C4
SMC_CASE_OPEN SMC_TCK SMC_TDI SMC_TDO SMC_TMS

NC
IN IN IN OUT IN
43 43 44 43 44 43 44 43 44
B
43 41 43 50 9
SMC_SYS_LED SMC_LID
NC NC NC NC NC
OUT IN
23 21 39 7
OUT IN
43 32
IN
SMC_RUNTIME_SCI_L SMC_ODD_DETECT SMC_PB3 (See below) 43 SMC_EXCARD_CP SMC_EXCARD_OC_L SMC_GFX_OVERTEMP_L SMC_FAN_0_CTL SMC_FAN_1_CTL SMC_FAN_2_CTL SMC_FAN_3_CTL SMC_FAN_0_TACH SMC_FAN_1_TACH SMC_FAN_2_TACH SMC_FAN_3_TACH SMS_X_AXIS SMS_Y_AXIS SMS_Z_AXIS SMC_ANALOG_ID SMC_NB_CORE_ISENSE SMC_NB_DDR_ISENSE ALS_LEFT ALS_RIGHT
NC
SMC_MCP_SAFE_MODE
OUT
43 76
IN IN OUT OUT OUT OUT IN IN IN IN IN IN IN IN IN IN IN IN
49 49 43 43 49 49 43 43
(OC) (OC) (OC) (OC) (OC) (OC)
=SMC_SMS_INT SMB_BSA_DATA SMB_BSA_CLK SMB_A_S3_DATA SMB_A_S3_CLK SMB_B_S0_DATA SMB_B_S0_CLK SMC_PROCHOT SMC_THRMTRIP SMC_PH2 ALS_GAIN
IN BI BI BI BI BI BI OUT OUT
43
43 45 45 45 45 45 45
NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.
43 43
52 52 52 43 43
OUT
43
NC NC
SMC
43 43 43

SMC_PB3: SMC_IG_THROTTLE_L for MG systems. Otherwise, TP/NC okay (was ISENSE_CAL_EN)
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
42
96
P60 P61 P62 P63 P64 P65 P66 P67
L13 K12 K11 J12 K13 J10 J11 H12
SMC_PM_G2_EN
NC NC NC
OUT
68
R4999
1
SMC_VCL PP3V3_S5_SMC_AVCC
M12 B1 M1 H10 L11 E1 MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=3.3V
4.7
SMC_ADAPTER_EN
OUT
21 34 37 43
5% 1/16W MF-LF 402
C4907 1
0.47UF
7
SMC Reset "Button" / Brownout Detect
6
42 42
5
SMC_FAN_2_CTL SMC_FAN_2_TACH SMC_FAN_3_CTL SMC_FAN_3_TACH NC_SMC_FAN_2_CTL
MAKE_BASE=TRUE
4
NC_SMC_FAN_2_TACH
MAKE_BASE=TRUE
2
SMC FSB to 3.3V Level Shifting
43 8
52 43 42 8
=PP3V3_S5_SMC
42
NC_SMC_FAN_3_CTL
MAKE_BASE=TRUE
=PP3V3_S0_SMC
1
42
NC_SMC_FAN_3_TACH
MAKE_BASE=TRUE
R5060
470
5% 1/16W MF-LF 402
C5000
0.1uF
20% 10V CERM 402
R5000
1K
5% 1/16W MF-LF 402
42
=PP1V05_S0_SMC_LS
1
U5000
NCP303LSN
SOT23-5-HF 5
2
R5061
3.3K
5% 1/16W MF-LF 402
TO SMC
OUT
42
ESTARLDO_EN
NC_ESTARLDO_EN
MAKE_BASE=TRUE
SMC_PROCHOT_3_3_L
3 5
D
SILK_PART=SMC_RST
SMC_MANUAL_RST_L OMIT
1
NC
CD NC GND
3
OUT IN
1 2
SMC_RESET_L OUT
42 44
R5001
0
5% 1/10W MF-LF 603
C5001
0.01UF
10% 16V CERM 402
CRITICAL
60 43 42
SMC_BC_ACOK
MAKE_BASE=TRUE
=CHGR_ACOK
CPU_PROCHOT_BUF
61 46
Q5060
BC847BV-X-F SOT563-HF
4
Q5032
SSM6N15FEAPE
SOT563
D 3
42
ALS_LEFT ALS_RIGHT SMC_NB_CORE_ISENSE SMC_NB_DDR_ISENSE SMC_NB_MISC_ISENSE SMC_ANALOG_ID
SMC_MCP_VSENSE
MAKE_BASE=TRUE
TO CPU
87 62 14 10
R5062
CPU_PROCHOT_L
3.3K
1 5% 1/16W MF-LF 402 2
42
SMC_CPU_HI_ISENSE
MAKE_BASE=TRUE
46
BI
CPU_PROCHOT_L_R
Q5060
BC847BV-X-F SOT563-HF
1
42 52 43 42 8
SMC_MCP_CORE_ISENSE
MAKE_BASE=TRUE
47
=PP3V3_S5_SMC
5
S 4
42
6
47
Q5059
SSM6N15FEAPE
SOT563
50
SMC_TPAD_RST_L
SN74LVC1G02
SOT553-5 4 SMC_TPAD_RST
42
MAKE_BASE=TRUE
SMC_CPU_FSB_ISENSE
MAKE_BASE=TRUE
47
50 43 42
SMC_ONOFF_L
02 3
42
SMC_GPU_1V8_ISENSE
MAKE_BASE=TRUE
47
G 2
SMC_PROCHOT
IN
42
42
SMC_P24 SMC_P26 SMC_P41 ALS_GAIN SMC_PB3 SMC_RSTGATE_L
TP_SMC_P24
MAKE_BASE=TRUE
87 14 10
OUT
PM_THRMTRIP_L
42
SMC_BMON_MUX_SEL
MAKE_BASE=TRUE
46
42
TP_SMC_P41
MAKE_BASE=TRUE
Q5059
SSM6N15FEAPE
SOT563
42
NC_ALS_GAIN
MAKE_BASE=TRUE
42
SMC_IG_THROTTLE_L
MAKE_BASE=TRUE
21
G 5
SMC_THRMTRIP
IN
42
C
42
42
TP_SMC_RSTGATE_L
MAKE_BASE=TRUE
C
52 43 42 8
R5095
OUT
=PP3V3_S5_SMC
SMC_EXCARD_OC_L
0
5% 1/16W MF-LF 402
EXCARD_OC_L
IN
20 32
42 42
SMC_PA0 SMC_PA1
R5091 R5092
100K 100K
1 1
2 2
5% 5%
1/16W 1/16W
MF-LF MF-LF
402 402
SMC AVREF Supply

CRITICAL
52
SMS_INT_L
MAKE_BASE=TRUE
=SMC_SMS_INT
42 50 43 42
VR5020
8
50 42 41
=PPVIN_S5_SMCVREF
1
REF3333
SOT23-3
PP3V3_S5_AVREF_SMC
2 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V 1
7 42
42
IN GND
3
OUT
SMC Crystal Circuit

C5010
15pF
2 5% 50V CERM 402 SMC_ONOFF_L OMIT
1
42
44 42 40 44 42 40
SMC_ONOFF_L SMC_LID SMC_PH2 SMC_TX_L SMC_RX_L
R5070 R5071 R5072 R5073 R5074 R5075 R5076 R5077 R5078 R5079 R5080 R5081 R5087
10K 100K 10K 10K 100K
1 1 1 1 1
2 2 2 2 2
5% 5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF MF-LF
402 402 402 402 402
C5026
0.01UF
10% 16V CERM 402
ONEWIRE_PU
2 1
SMC_XTAL
Debug Power "Button"
60 42 60 42
C5020
0.47UF
10% 6.3V CERM-X5R 402
C5025
10uF
20% 6.3V X5R 603
R5010
1
44 42 44 42 44 42
SMC_XTAL_R
GND_SMC_AVSS
TABLE_ALT_HEAD
5% 1/16W MF-LF 402

42 46 47
OUT
42 43 50
44 42 43 42 60 43 42
PART NUMBER
ALTERNATE FOR PART NUMBER

353S1278
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_ITEM
CRITICAL 20.00MHZ
5X3.2-SM
42
Y5010
R5015
0
SYS_ONEWIRE SMC_BS_ALRT_L SMC_TMS SMC_TDO SMC_TDI SMC_TCK SMC_BIL_BUTTON_L SMC_BC_ACOK
2.0K 100K 10K 10K 10K 10K 10K 470K
1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2
5% 5% 5% 5% 5% 5% 5% 5%
1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W 1/16W
MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF MF-LF
402 402 402 402 402 402 402 402
353S1381
ALL
Intersil ISL60002-33
C5011
2
SILK_PART=PWR_BTN
B
System (Sleep) LED Circuit
15pF
1 2 5% 50V CERM 402
5% 1/10W MF-LF 2 603
Place R5015,R5001 on bottom side
SMC_EXTAL
8 7
PP3V42_G3H
42 37 34 21 42
=PP5V_S3_SYSLED
1
SMC_ADAPTER_EN SMC_CASE_OPEN SMC_EXCARD_CP PM_SLP_S5_L PM_SLP_S4_L
R5085 R5086 R5088 R5090
10K 10K 10K 100K
1 1
5%
2
1/16W 1/16W
MF-LF MF-LF
402 402
5%
C5050
0.1UF
R5051
10K
42 32
R5031
523
R5030
20
5%
42 68 42 40 21
1/16W
MF-LF
402
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 2 402
10% 2 16V X5R 402
5% 1/16W MF-LF 2 402
5%
1/16W
MF-LF
402
SYS_LED_ILIM
43 42
74LVC1G17DRL
U5050
SOT-553 4
SMC_BIL_BUTTON_DB_L
2
60 43 8
=PP3V3_S0_SMC
SMC_BIL_BUTTON_L
SYS_LED_L_VDIV
1 3
Q5030
2SA2154MFV-YAE
SOD
NC
42
SMC_PA5
R5089
10K
5%
1
1/16W MF-LF 402
NC
R50321
1.47K
C5051
0.01UF
1% 1/16W MF-LF 402 2
SYS_LED_ANODE
OUT
41
10% 25V 2 X7R 402
SMC Support
SYS_LED_L

D 6
Q5032
SSM6N15FEAPE
SOT563
42
IN
SMC_SYS_LED
2 G
S 1
SIZE DRAWING NUMBER REV.
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
43
96
U5001
SMC_MCP_DDR_ISENSE
LPC+SPI Connector
CRITICAL LPCPLUS
55909-0374
44 8
J5100
D
90 83 42 19 90 83 42 19 44 44 90 83 42 19 42 19 43 42
=PP3V3_S5_LPCPLUS =PP5V_S0_LPCPLUS
BI BI
M-ST-SM 31 32
D
LPC_CLK33M_LPCPLUS LPC_AD<2> LPC_AD<3> SPIROM_USE_MLB SPI_ALT_CLK SPI_ALT_CS_L LPC_SERIRQ LPC_PWRDWN_L SMC_TDI SMC_TCK SMC_RESET_L SMC_NMI SMC_RX_L LPCPLUS_GPIO
IN BI BI
26 90 19 42 83 90 19 42 83 90
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30
LPC_AD<0> LPC_AD<1> SPI_ALT_MOSI SPI_ALT_MISO LPC_FRAME_L PM_CLKRUN_L SMC_TMS DEBUG_RESET_L SMC_TDO SMC_TRST_L SMC_MD1 SMC_TX_L
3 5 7
IN OUT IN OUT OUT IN OUT
9 11 13 15 17 19 21 23 25 27 29
OUT IN IN BI IN OUT OUT OUT OUT OUT OUT
44 44 44 19 42 19 42 42 43 42 43 42 43 42 40 42 43 18
Alternate SPI ROM Support

MUX SEL CONTROLLED BY FRANKCARD SWITCH ONCE CS1 IS SUPPORTED IN MCP
44 8 53 44 8
42 42 43 42 40
IN OUT IN
33
34
=PP3V3_S5_LPCPLUS
1
=PP3V3_S5_ROM
LPCPLUS
C5114
0.1UF
20% 402
R51901
SPI_CLK_R
90 44 21
5% 1/16W MF-LF 402 2

IN
10K
LPCPLUS
1 Y+ 2 Y-
2 10V CERM
516S0573
OUT OUT
44 44 8 44 8
MCP79 Internal SPI MUX Support

NOT SUPPORTED IN REV A01 OR B01 MCP79 SILICON =PP3V3_S0_LPCPLUS =PP3V3_S5_LPCPLUS
VCC
90 44 21
IN
C
R51911
5% 1/16W MF-LF 402 2
SPI_MOSI_R
U5110
TQFN
M+ 5 M- 4 D+ 7 D- 6
SPI_ALT_CLK SPI_ALT_MOSI SPI_CLK_MUX SPI_MOSI_MUX
PI3USB102ZLE
OUT OUT
44 53 44 53
10K
CRITICAL
44
MCP SPI Override Options

MCP79 REV A01 REQUIRES EXTERNAL MUX, REV B01 STILL DOES NOT SUPPORT INTERNAL MUX
44
R5140
100K
MCP_CS1_YES
2 3
C
LPC_FRAME_PU
SPIROM_USE_MLB
10 SEL GND 3
OE* 8
5% 1/16W MF-LF 402 2
SPIROM_USE_MLB
Q5140
SSM3J16FV
SOD-VESM-HF
MCP_CS1_YES 1 R5141
470
5% 1/16W MF-LF 402 2
SEL HIGH OUTPUTS TO D (ON BOARD ROM) SEL LOW OUTPUTS TO M (FRANKCARD ROM)
8 44
MCP_CS1_NO
=PP3V3_S5_LPCPLUS
1
LPCPLUS
From Frank Card
R5142
1
LPC_FRAME_R_L
OUT
19
C5124
0.1UF SPI_ALT_MISO
IN
44
LPCPLUS SPI_MISO SPI_CS0_R_L

1 Y+ 2 Y-
20% 2 10V CERM 402

M+ 5 M- 4
5% PLACEMENT_NOTE=Place near J5100 1/16W MF-LF 402
SPI_CS1_R_L_USE_MLB
MAKE_BASE=TRUE
=SPI_CS1_R_L_USE_MLB
BI
9 21
VCC
90 44 21 90 21
OUT IN
PI3USB102ZLE
TQFN
D+ 7 D- 6 SPI_MLB_CS_L_MUX
U5120
1 SPI_ALT_CS_L_MUX
1/16W
MCP_CS1_NO Pull-up on debug card 0 2 R5127 SPI_ALT_CS_L

5% MF-LF 402
OUT
44
MCP_CS1_YES
R5147
1
To Frank Card
PLACEMENT_NOTE=PLACE NEXT TO U5120
SPI_MISO_MUX
IN
44 53
CRITICAL
10 SEL GND 3 OE* 8
MCP_CS1_NO 0 2 R5126 1
1/16W 5% MF-LF 402
5% 1/16W MF-LF 402

53
SPI_MLB_CS_L MCP_CS1_NO
OUT
R5144
20K
=PP3V3_S5_ROM
8 44 53
MCP_CS1_YES&LPCPLUS_NOT
R5146
1
5% 1/16W MF-LF 402 2
SPI Frequency Clamp

ENSURES MCP79 SPI_DO OR SPI_CLK INPUT IS LOW WHEN STRAP IS LATCHED.NOT NEEDED FOR B01 OR LATER. NO STUFF Keep very short MCP_FORCE_SPI_DO_L
23 8
5% 1/16W MF-LF 402
PLACEMENT_NOTE=PLACE NEXT TO U1400
R5161
1
SPI_MOSI SPI_CLK
OUT
53 90
SPI MUX BYPASS

LPCPLUS_NOT R5156
53 44
=PP3V3_S5_MCP_A01 MCP_A01&MCP_A01Q
MCP_A01&MCP_A01Q
Q5160
SSM6N15FEAPE
SOT563
D 6
5% 1/16W MF-LF 402
OUT
53 90
R51631
100K
5% 1/16W MF-LF 402 2
MCP_A01&MCP_A01Q
R5162
2
S 1
OUT
SPI_CLK_MUX
0
5% 1/16W MF-LF 402
SPI_CLK_R
IN
21 44 90
MCP_SPI_FORCE MCP_A01&MCP_A01Q
LPCPLUS_NOT R5157
1
5% 1/16W MF-LF 402
53 44
OUT
SPI_MOSI_MUX
0
5% 1/16W MF-LF 402
Q5160
SPI_MOSI_R
IN
21 44 90
D 3
LPCPLUS_NOT R5158
53 44
SLP_S3# nVidia recommendation, SSM6N15FEAPE SOT563 not compatible with button-mashing. MCP_A01&MCP_A01Q
IN
SPI_MISO_MUX
0
5% 1/16W MF-LF 402
SPI_MISO
OUT
21 44 90 83 81 68 42 37 34 21 7
R5160
IN
PM_SLP_S3_L
S 4
MCP_SPI_FORCE_L
LPC+SPI Debug Connector

SYNC_MASTER=CHANG_M98_MLB SYNC_DATE=07/01/2008
5% 1/16W MF-LF 402

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
44
96
S G
MCP79 SMBus "0" Connections

8
SMC "0" SMBus Connections

8
SMC "A" SMBus Connections

NOTE: SMC RMT bus remains powered and may be active in S3 state
8
=PP3V3_S0_SMBUS_MCP_0
=PP3V3_GPU_SMBUS_SMC_0_S0
=PP3V3_S3_SMBUS_SMC_A_S3
MCP79
U2300 (MASTER)
R5200
4.7K
5% 1/16W MF-LF 402
R5201
4.7K
5% 1/16W MF-LF 402
SO-DIMM "A"
J3100 (Write: 0xA0 Read: 0xA1) =I2C_SODIMMA_SCL =I2C_SODIMMA_SDA
28 42
SMC
U4900 (MASTER) SMB_0_S0_CLK SMB_0_S0_DATA
93
R5250
4.7K
5% 1/16W MF-LF 402
R5251
4.7K
5% 1/16W MF-LF 402
GPU Temp (Ext)

EMC1043-1: U5550 (Write: 0x98 Read: 0x99) =SMBUS_GPUTHMSNS_SCL =SMBUS_GPUTHMSNS_SDA
48 42
SMC
U4900 (MASTER) SMB_A_S3_CLK SMB_A_S3_DATA
R52701
2.2K
5% 1/16W MF-LF 402 2
R5271
2.2K
TRACKPAD
J5800 (Write: 0x90 Read: 0x91) =I2C_TPAD_SCL =I2C_TPAD_SDA
51
5% 1/16W MF-LF 2 402
90 21 13 7
SMBUS_MCP_0_CLK
MAKE_BASE=TRUE
SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA
SMBUS_SMC_A_S3_SCL
MAKE_BASE=TRUE
MAKE_BASE=TRUE
28 42 93 48 42
90 21 13 7
SMBUS_MCP_0_DATA
MAKE_BASE=TRUE
SMBUS_SMC_A_S3_SDA
MAKE_BASE=TRUE
51
MAKE_BASE=TRUE
SO-DIMM "B"
J3200 (Write: 0xA2 Read: 0xA3) =I2C_SODIMMB_SCL =I2C_SODIMMB_SDA
29
GPU Temp (Int)

G96: U8000 (Write: 0x9E Read: 0x9F) =GPU_I2CS_SCL =GPU_I2CS_SDA
77
ALS
J3401 (Write: 0x72 Read: 0x73) I2C_ALS_SCL I2C_ALS_SDA
31
29
77
31
ExpressCard Slot
J3500
SMC "Battery A" SMBus Connections

8
MCP Temp
EMC1043-1: U5500 (Write: 0x98 Read: 0x99) =SMBUS_MCPTHMSNS_SCL
48
=PP3V42_G3H_SMBUS_SMC_BSA
=SMBUS_EXCARD_SCL =SMBUS_EXCARD_SDA
32
32
SMC
U4900 (MASTER)
42
R52801
1.6K
5% 1/16W MF-LF 402 2
93
R5281
1.6K
Battery
J6955 (See Table) =SMBUS_BATT_SCL =SMBUS_BATT_SDA
60
=SMBUS_MCPTHMSNS_SDA
48
5% 1/16W MF-LF 2 402
SMB_BSA_CLK SMB_BSA_DATA
SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA
MAKE_BASE=TRUE
42
93
60
MAKE_BASE=TRUE
SMC "B" SMBus Connections

8
Battery Charger
=PP3V3_S0_SMBUS_SMC_B_S0
Battery
ISL6258A - U7000 (Write: 0x12 Read: 0x13)
MCP79 SMBus "1" Connections

8
Battery Manager - (Write: 0x16 Read: 0x17) Battery LED Driver - (Write: 0x36 Read: 0x37) Battery Temp - (Write: 0x90 Read: 0x91)
SMC
=SMBUS_CHGR_SCL =SMBUS_CHGR_SDA
61
R5260 1
3.3K
5% 1/16W MF-LF 402 2
93
R5261
3.3K
CPU Temp
EMC1043-1: U5570 (Write: 0x98 Read: 0x99) =I2C_CPUTHMSNS_SCL =I2C_CPUTHMSNS_SDA
48
U4900 (MASTER)
42
61
5% 1/16W MF-LF 2 402
=PP3V3_S0_SMBUS_MCP_1
SMB_B_S0_CLK SMB_B_S0_DATA
SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA
MAKE_BASE=TRUE
42 93 48
MCP79
U2300 (MASTER?)
90 21
R5230
2.0K
R5231
2.0K
HDCP ROM
U2690 or U2695 (Write: 0xA0-0xAE, Read: 0xA1-0xAF) =I2C_HDCPROM_SCL =I2C_HDCPROM_SDA
SMC "Management" SMBus Connections

The bus formerly known as "Battery B"
8
MAKE_BASE=TRUE
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 2 402
=PP3V3_S3_SMBUS_SMC_MGMT
Battery Charger Temp

TMP102: U5540 (Write: 0x92 Read: 0x93)
SMBUS_MCP_1_CLK
MAKE_BASE=TRUE
25
90 21
SMBUS_MCP_1_DATA
MAKE_BASE=TRUE
SMC
25
R5290
4.7K
R5291
4.7K
Vref DACs
U2900 (Write: 0x98 Read: 0x99) =I2C_VREFDACS_SCL =I2C_VREFDACS_SDA
27
=SMBUS_TMPSNSR_SCL =SMBUS_TMPSNSR_SDA
48
U4900 (MASTER)
5% 1/16W MF-LF 402 2

93
5% 1/16W MF-LF 2 402
48
Mikey
42
SMB_MGMT_CLK SMB_MGMT_DATA
SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA
MAKE_BASE=TRUE
42 93 27
U6860 (WRITE: 0X72 READ: 0X73) =I2C_MIKEY_SCL =I2C_MIKEY_SDA

59
MAKE_BASE=TRUE
B
Margin Control
U2901 (Write: 0x30 Read: 0x31) =I2C_PCA9557D_SCL =I2C_PCA9557D_SDA
27
59
27
SMS
U5930 (Write: 0x70 Read: 0x71) =I2C_SMS_SCL =I2C_SMS_SDA
52
52
M98 SMBus Connections
SYNC_MASTER=DDR

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
45
96
8
12 11 8
7
CPU Voltage Sense / Filter
XW5309
SM 1 2
6
R5309
5
Q5315
4
PBUS Voltage Sense & Filter
=PPVCORE_S0_CPU
CPUVSENSE_IN
4.53K
1% 1/16W MF-LF 402
SMC_CPU_VSENSE
1
OUT
42
FDG6332CG
SC70-6
8 7
Place short near U1000 center
C5309
0.22UF
20% 6.3V X5R 402
PPBUS_G3H
4
P-CHN S D
3
PPBUS_G3H_VSENSE
R5315
42 43 46 47
G
5
R5385 1
27.4K
1% 1/16W MF-LF 402
GND_SMC_AVSS Place RC close to SMC
100K
5% 1/16W MF-LF 402
D
78 8
GPU Voltage Sense / Filter

=PPVCORE_GPU_REG
Rthevanin = 4573 ohms SMC_PBUS_VSENSE

OUT
42
PBUSVSENS_EN_DIV
XW5359
SM 1 2
R5359
GPUVSENSE_IN
4.53K
1 1% 1/16W MF-LF 402 2
SMC_GPU_VSENSE
1
OUT
42
R5316 1
100K
5% 1/16W MF-LF 402
R5386 1
5.49K
1% 1/16W MF-LF 402
C5385
0.22UF
20% 6.3V X5R 402
Place short near U8000 center
C5359
0.22UF
20% 6.3V X5R 402
2 2
PBUSVSENS_EN_L
42 43 46 47

6
42 43 46 47
Place RC close to SMC
D N-CHN
MCP Voltage Sense / Filter

68 24 22 8
Q5315
FDG6332CG
SC70-6
=PBUSVSENS_EN
G S
1
=PPVCORE_S0_MCP
XW5399 SM
R5399
1
Enables PBUS VSense divider when high.
1 2 MCPVSENSE_IN PLACEMENT_NOTE=Place near U1400 center
4.53K2
1% 1/16W MF-LF 402
SMC_MCP_VSENSE
1
OUT
43
C5399
0.22UF
20% 6.3V 2 X5R 402
42 43 46 47
C
BMON Current Sense - Entire circuit must be near SMC (U4900)
8
=PP3V42_G3H_BMON_ISNS BMON_ENG BMON_ENG

1 C5318
BMON_ENG
1 C5369
U5313
BMON_INA_OUT BMON_ENG 2 CHGR_BMON 3
B0 A GND 0
61
0.1uF 6 5 4 BMON_AMUX_OUT BMON_ENG

1 14.53K 2
1% 1/16W MF-LF 402
0.1uF
20% 402
NC7SB3157P6XG SC70 SEL B1

1 VCC
2 10V CERM
20% 402
SMC_BMON_MUX_SEL
IN
43
REGULATOR SIDE: CHGR_CSO_R_P CHGR_CSO_R_N LOAD SIDE:
2 10V CERM
V+
U5303
95 61
DCIN Current Sense Filter

R5391
SMC_BATT_ISENSEOUT
1 C5390
42
OUT
5 4
INA213
ININ+
SC70 OUT 6
REF
IN
95 61
IN
1 BMON_PROD
VER 1
R5380
61
R5371
100K
0.22UF
20% 6.3V X5R 402
IN
CHGR_AMON
4.53K
1 1% 1/16W MF-LF 402 2
SMC_DCIN_ISENSE
1
OUT
42
GND
R5330
2
Monitors battery discharge current from battery to PBUS INA213 has gain of 50V/V
5% 1/16W MF-LF 402
5% 1/16W MF-LF 2402
C5380
0.22UF
20% 6.3V X5R 402
GND_SMC_AVSS 42
43 46 47
GND_SMC_AVSS
B
42 43 46 47
CPU VCore High Side Current Sensor

8
=PP3V42_G3H_CPUCOREISNS
1
C5388
0.1UF
20% 10V CERM 402
62
CPU VCore Load Side Current Sense / Filter

OUT
=PPVIN_S5_CPU_IMVP_ISNS
R5331
IN
V+
IMVP6_IMON
6.19K
1% 1/16W MF-LF 402
SMC_CPU_ISENSE
1
1
U5388
R5388
0.001
1% 0.5W MF 1206
OUT
42
1 3
95
ISNS_CPU_N ISNS_CPU_P
5 IN4 IN+
INA210
SC70
R5335
6
OUT
CPUVCORE_HISIDE_IOUT
4.53K
1 1% 1/16W MF-LF 402 2
SMC_CPU_HI_ISENSE
1
OUT
43
R5332
17.4K
C5330
0.22UF
20% 6.3V X5R 402
A
8
95
REF 1
C5335
0.22UF
20% 6.3V X5R 402
2 4
1% 1/16W MF-LF 402 2
Current & Voltage Sensing

SYNC_MASTER=SENSOR
42 43 46 47
GND
IN
GND_SMC_AVSS

=PPVIN_S5_CPU_IMVP_ISNS_R
42 43 46 47
Consider INA211 (GAIN 500 version) since I=4.93 Amps across R5388
APPLE INC.
SIZE
DRAWING NUMBER
REV.
D
SCALE NONE
051-7546
SHT OF
A.0.0
46
96
GND_SMC_AVSS
8
=PP3V3_S0_MCPCOREISNS
7
MCP VCore Current Sense
3
GPU VCore Current Sense
C5420
0.1UF
20% 10V CERM 402
NC
V+
MCP VCore Current Sense Filter

78
R5493
IN
U5410
95
GPU VCore Current Sense Filter

U5420
95 65
GFXIMVP6_IMON1
4.53K
1% 1/16W MF-LF 402
GPUISENS_P
8 3
OPA2333DRBG4
DFN 1
MCPCOREISNS_N MCPCOREISNS_P
5 IN4 IN+
INA213
SC70
R5470
6
R5475
GPUVCORE_IOUT
1
OUT
MCPCORE_IOUT
4.53K
1 1% 1/16W MF-LF 402 2
V+ VTHRM
4.53K
1% 1/16W MF-LF 402
SMC_MCP_CORE_ISENSE
1
SMC_GPU_ISENSE
1
OUT
43
OUT
42
95 65
REF 1
C5470
0.22UF
20% 6.3V X5R 402
R5491
1
C5475
0.22UF
20% 6.3V X5R 402
10K
1% 1/16W MF-LF 402
95
GPUISENS_N
GND
2
NC
NC
GND_SMC_AVSS
GND_SMC_AVSS
42 43 46 47
42 43 46 47
R5498
1
10K
1% 1/16W MF-LF 402
New Gain: 2x can sense current up to 16.6 Amps
MCP MEM VDD Current Sense

8
C5498
470PF
1 2 10% 50V CERM 402
=PP3V3_S0_MCPDDRISNS
1
C5440
0.1UF
20% 10V CERM 402
IN
=PPMCPDDR_ISNS_R R5444
MCP MEM VDD Current Sense Filter

U5440
8
95
R5445 1
0.002
3 95
DDRISNS_P
3.65K
1% 1/16W MF-LF 402
OPA2333DRBG4
DFN
DDRISNS_R_P
R5440
MCPDDR_IOUT
1
GPU VCore Current Sense and GPU 1.8V Current Sense share dual package opamp U5410
43
V+ VTHRM
4.53K
1% 1/16W MF-LF 402
C
8
1% 1/4W MF 1206 2 4
95
SMC_MCP_DDR_ISENSE
1
OUT
R5443 DDRISNS_N
1
3.65K
1% 1/16W MF-LF 402
C5490
0.22UF
20% 6.3V X5R 402
95
DDRISNS_R_N
9
2
OUT
=PPMCPDDR_ISNS
C
42 43 46 47
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
1
GND_SMC_AVSS
C5442 1
470PF
10% 50V CERM 2 402
R5442
1M
R5441
1
1M
1% 1/16W MF-LF 402
1% 1/16W MF-LF 2 402
SIGNAL_MODEL=EMPTY Gain: 274x
GPU 1.8V Current Sense

=PP3V3_S0_GPU1V8ISNS
1
C5441
470PF
1 2 10% 50V CERM 402
8
C5410
0.1UF
20% 10V CERM 402
SIGNAL_MODEL=EMPTY
2
IN
=PP1V8_S0GPU_ISNS_R R5415
U5410
8
95
GPU 1.8V Current Sense Filter

OPA2333s for proto are placeholders for OPA2330
R5413
0.002
1 3
95
P1V8GPU_P
3.65K
1% 1/16W MF-LF 402
OPA2333DRBG4
DFN 7
P1V8GPUISNS_R_P
R5465
P1V8_S0GPU_IOUT
1
V+ VTHRM
4.53K
1% 1/16W MF-LF 402
1% 1/4W MF 1206 2 4
95 8
SMC_GPU_1V8_ISENSE
1
OUT
43
R5414 P1V8GPU_N
1
3.65K
1% 1/16W MF-LF 402
C5465
0.22UF
20% 6.3V X5R 402
95
P1V8GPUISNS_R_N
9
2
OUT
=PP1V8_S0GPU_ISNS
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY
1
GND_SMC_AVSS
1M
42 43 46 47
C5412 1
R5412
1M
R5411
1 2
1% 1/16W MF-LF 402
MCP MEM VDD Current Sense and CPU FSB 1.05V Current Sense share dual package opamp U5440
470PF
SIGNAL_MODEL=EMPTY
10% 50V CERM 2 402
1% 1/16W MF-LF 2 402
C5411
470PF
1 2 10% 50V CERM 402
SIGNAL_MODEL=EMPTY
CPU FSB 1.05V Current Sense
Gain: 274x
NC R5431
95 66
1.05V CPU Current Sense Filter
U5440
OPA2333DRBG4
DFN
1V05CPU_P
3.65K
1% 1/16W MF-LF 402
8
95
1V05CPUISNS_R_P
R5495 CPU1V05_S0_IOUT
4.53K
1 1% 1/16W MF-LF 402 2
V+ VTHRM
SMC_CPU_FSB_ISENSE
1
OUT
43
R5436
95 66
1V05CPU_N
3.65K
1% 1/16W MF-LF 402
C5435
0.22UF
20% 6.3V X5R 402
95
1V05CPUISNS_R_N
NC
1 1
NC
Current Sensing
SYNC_MASTER=SENSOR
42 43 46 47
SIGNAL_MODEL=EMPTY
SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY
C5472
470PF
R5437
1M
R5432
1

1M
1% 1/16W MF-LF 402
10% 50V CERM 2 402
1% 1/16W MF-LF 2 402
SIGNAL_MODEL=EMPTY
C5432
470PF
1 2 10% 50V CERM 402
Gain: 274x
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
47
96
CPU Proximity/CPU Die/Right Fin Stack

R5570
8
Battery Charger Proximity

8
=PP3V3_S0_CPUTHMSNS
47
=PP3V3_S0_BATTCHARGERTMPSNSR
PP3V3_S0_CPUTHMSNS_R
MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V 1 VDD 1
5% 1/16W MF-LF 402
2 CERM 402
C5570 0.1uF R55711 20% 10V

5% 1/16W MF-LF 402 2
TEMP SENSOR HAS ADDRESS WRITE:0X92, READ: 0X93
R5572
10K
10K
95 10
BI
CPU_THERMD_P
SIGNAL_MODEL=EMPTY
U5570
EMC1403-1
1 2 DP1 3 DN1 4 DP2 5 DN2 GND 6 DFN THERM* 7 ALERT* 8
5% 1/16W MF-LF 2 402

45 =SMBUS_TMPSNSR_SDA 45 =SMBUS_TMPSNSR_SCL
5 V+
U5540
HPA00330AI
SOT563
Detect CPU Die Temperature
D
4 3
C5580
0.0022UF CPU_THERMD_N
CPUTHMSNS_THM_L CPUTHMSNS_ALERT_L =I2C_CPUTHMSNS_SDA =I2C_CPUTHMSNS_SCL

BI BI
45
6 1
SDA SCL GND
ADD0 ALERT
10% 50V CERM 2 402
CRITICAL
SMDATA 9 SMCLK 10
95 10
BI
45
C5540
0.1uF
20% 10V CERM 402
THRM_PAD 11
Placement note: Placement note:

Place U5570 under CPU and close to left fin stack Place U5540 near battery charger circuit
SIGNAL_MODEL=EMPTY
Detect Right Fin Stack Temperature
BC846BMXXH SOT732-3
Q5501
2
C5590 1
1
0.0022uF
95
10% 50V CERM 2 402
CPUTHMSNS_D2_N
Placement note:
Place Q5501 on bottom side close to right fin stack
MCP Proximity/MCP Die/Right Heat Pipe

C
8
R5500
=PP3V3_S3_REMTHMSNS
1
C
1
47
PP3V3_S3_REMTHMSNS_R
5% 1/16W MF-LF 402

95 21
BI
MCP_THMDIODE_P
SIGNAL_MODEL=EMPTY
1 VDD
1
C5500 0.1uF 20% R55011 2 10V CERM

1 402
R5502
10K
5% 1/16W MF-LF
Note: EMC1403 can perform Beta Compensation for External Diode 1 only
Detect MCP Die Temperature
0.0022uF
C5511
U5500
EMC1403-1
2 DP1 3 DN1 4 DP2 5 DN2 DFN THERM* 7 ALERT* 8
5% 1/16W MF-LF 402 2
10K
2 402
10% 50V CERM 2 402
REMTHMSNS_THM_L REMTHMSNS_ALERT_L =SMBUS_MCPTHMSNS_SDA =SMBUS_MCPTHMSNS_SCL

BI BI
45
J5502
78171-0002
M-RT-SM 3
95 21
BI
95
MCP_THMDIODE_N MCPTHMSNS_D_P
SIGNAL_MODEL=EMPTY
CRITICAL
SMDATA 9
Detect Right Heat Pipe Temperature

1
518S0519
C5521
0.0022uF
GND 6
SMCLK 10 THRM_PAD 11
45
4
95
10% 50V CERM 2 402
MCPTHMSNS_D_N
Placement note:
Place U5500 near MCP
Placement note:
Keep 2 caps as close to IC pins as possible
GPU Proximity/GPU Die/Left Heat Pipe

R5550
8
=PP3V3_S0_GPUTHMSNS
47
PP3V3_S0_GPUTHMSNS_R
MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V 1
5% 1/16W MF-LF 402

95 76
BI
GPU_TDIODE_P
SIGNAL_MODEL=EMPTY
1 VDD
1
20% 2 10V CERM 402
C5550 0.1uF R55511

5% 1/16W MF-LF 402 2
10K
R5552
10K
5% 1/16W MF-LF
Detect GPU Die Temperature
C5551
0.0022uF
U5550
EMC1403-1
2 DP1 3 DN1 4 DP2 DFN THERM* 7 ALERT* 8
2 402
10% 50V CERM 2 402
GPUTHMSNS_THM_L GPUTHMSNS_ALERT_L =SMBUS_GPUTHMSNS_SDA =SMBUS_GPUTHMSNS_SCL

BI BI
45
95 76
BI
GPU_TDIODE_N
95
GPUTHMSNS_D_P
SIGNAL_MODEL=EMPTY
CRITICAL
SMDATA 9
Detect Left Heat Pipe Temperature
5 DN2
1
A
Placement note:
BC846BMXXH SOT732-3
Place on top side under left heat pipe near CPU
Q5503
2
C5552
0.0022uF
GND 6
SMCLK 10 THRM_PAD 11
45
Thermal Sensors
10% 50V CERM 2 402
95
GPUTHMSNS_D_N
Placement note:
Place U5550 near GPU
Placement note:
Keep 2 caps as close to IC pins as possible
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
48
96
95
CPUTHMSNS_D2_P
C
8 7 8
Left Fan
=PP5V_S0_FAN_LT =PP3V3_S0_FAN_LT CRITICAL
8 8
Right Fan
=PP5V_S0_FAN_RT =PP3V3_S0_FAN_RT CRITICAL
1
C
J5660
5 1 2 3 4 6
R5650
47K
78171-0004 M-RT-SM
5 1 2 3 4 6
J5650
R5660
47K
78171-0004 M-RT-SM
R5655
42
5% 1/16W MF-LF 402 2

7
OUT
SMC_FAN_0_TACH
47K
R5665
42
5% 1/16W MF-LF 402 2

7
FAN_LT_TACH
OUT
SMC_FAN_1_TACH
47K
FAN_RT_TACH
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
R56511
100K
5% 1/16W MF-LF 402 2
42
R56611
100K
5% 1/16W MF-LF 402 2
42
5
G
Q5660
2N7002DW-X-G
D
2
G
IN
SMC_FAN_0_CTL
4 S
SOT-363 3 7
518S0369
IN
Q5660
2N7002DW-X-G
SOT-363
D 6
7
518S0369
FAN_LT_PWM
SMC_FAN_1_CTL
1 S
FAN_RT_PWM
Fan Connectors
SYNC_MASTER=M87_MLB

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
49
96
PSOC USB CONTROLLER

TMP102
IC
KEYBOARD CONNECTOR
PIN NAME CURRENT V+ VDD VOUT VDD 10UA 80UA 60MA 60MA 8MA 14MA R_SNS 2.55 KOHM MAX MAX (TYP) (MAX) 10 OHM 0.2 OHM 1.5 OHM V_SNS 0.0255 V 0.204 V 0.6 V 0.012 V 0.012 V 0.021 V 0.0188 V POWER 0.255E-6 16.32E-6 36E-3 0.72E-3 96E-6 294E-6 W W W W W W
J5713
APN 518S0637
50
3V3 LDO
NC
32 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
USB INTERFACES TO MLB TRACKPAD PICK BUTTONS SPI HOST TO Z2 KEYBOARD SCANNER
PSOC
IN
=PP3V3_S3_TPAD
D
51 7 50 51 7 50 50
PP3V3_S3_PSOC WS_KBD23 7 50 WS_KBD22 7 50 WS_KBD21 7 50 WS_KBD20 7 50 WS_KBD19 7 50 WS_KBD18 7 50 PICKB_L BUTTON_DISABLE Z2_HOST_INTN WS_LEFT_SHIFT_KEY WS_LEFT_OPTION_KEY
50
18V BOOSTER
VIN
50 7
4MA (MAX)
4.7 OHM
75.2E-6 W
50 7 50 7 50 7 50 7 50 7 50 7
56 55 54 53 52 51 50 49 48 47 46 45 44 43
PSOC PROGRAMMING CONNECTOR

TEST POINTS ARE FOR ON BOARD PROGRAMMING
TPAD_DEBUG
APN 518S0430
50 7 50 7 50 7
J5702
FH19C-4S-0.5SH25
F-RT-SM1
50
R5714
WS_KBD15_C 1
470
1% 1/16W MF-LF 402
50 7 50 7 50 7 50 7 7
50 51 7 51 7
51 7 51 7 51 7 51 7 51 7 51 7 51 7 51 7 51 7
15 P1_7 16 P1_5 17 P1_3 18 P1_1 19 VSS 20 D+ 21 D22 VDD 23 P7_7 24 P7_0 25 P1_0 26 P1_2 27 P1_4 28 P1_6
51 7
WS_CONTROL_KEY Z2_KEY_ACT_L Z2_BOOT_CFG1 TP_P4_5 Z2_DEBUG3 Z2_RESET PSOC_MISO PSOC_F_CS_L PSOC_MOSI PSOC_SCLK Z2_MISO Z2_CS_L Z2_MOSI Z2_SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14
P2_3 P2_1 P4_7 P4_5 P4_3 P4_1 P3_7 P3_5 P3_3 P3_1 P5_7 P5_5 P5_3 P5_1
CRITICAL
CY8C24794
MLF
(SYM-VER2)
U5701
APN 337S2983 OMIT
P2_2 P2_0 P4_6 P4_4 P4_2 P4_0 P3_6 P3_4 P3_2 P3_0 P5_6 P5_4 P5_2 P5_0 THRML PAD
42 41 40 39 38 37 36 35 34 33 32 31 30 29 57
WS_KBD17 7 50 WS_KBD16N 50 WS_KBD15_C 50 WS_KBD14 7 50 WS_KBD13 7 50 WS_KBD12 7 50 WS_KBD11 7 50 WS_KBD10 7 50 WS_KBD9 7 50 WS_KBD8 7 50 WS_KBD7 7 50 WS_KBD1 7 50 WS_KBD2 7 50 WS_KBD3 7 50
NC
50 8
5 1 2 3 4
=PP3V3_S3_TPAD
WS_KBD15_CAP 7 WS_KBD16_NUM
50 7 50 50 50 50
50
ISSP_SCLK_P1_1 ISSP_SDATA_P1_0
ISSP CLOCK ISSP DATA

50
R5715
WS_KBD16N
1
50
10K
NC
1% 1/16W MF-LF 402
R5710
1
1K
5% 1/16W MF-LF 402
50 50
43 42
OUT
SMC_ONOFF_L
1
WS_KBD17 7 WS_KBD18 7 WS_KBD19 7 WS_KBD20 7 WS_KBD21 7 WS_KBD22 7 WS_KBD23 7 WS_KBD_ONOFF_L

=PP3V42_G3H_TPAD
WS_LEFT_SHIFT_KBD WS_LEFT_OPTION_KBD WS_CONTROL_KBD
50 8 50 7 50 7 50 7
C5710
0.1UF
TP_PSOC_SCL
WS_KBD4 7 WS_KBD5 7 WS_KBD6 7
ISOLATION CIRCUIT
50 50 50 8 50
20% 2 10V CERM 402

PLACEMENT_NOTE=NEAR J5713
NC
31 F-RT-SM
=PP3V42_G3H_TPAD
C5725
0.1UF
FF14-30A-R11B-B-3H
TP_PSOC_SDA
ISSP_SDATA_P1_0 50 ISSP SDATA/I2C SDA

50 8
=PP3V3_S3_TPAD WS_LEFT_SHIFT_KBD
2 1
5 TC7SZ08AFEAPE
A
SOT665
CRITICAL
20% 10V CERM 402
SMC_MANUAL_RESET LOGIC
WS_LEFT_SHIFT_KEY 50
50 8
TP_PSOC_P1_3
Z2_CLKIN
7 51 50 7
U5725 Y
B
=PP3V42_G3H_TPAD
1 2
C5758
0.1UF 10%
16V X7R-CERM 402
3
50
ISSP_SCLK_P1_1 ISSP SCLK/I2C SCL
TP_P7_7
50 8
=PP3V42_G3H_TPAD
CRITICAL
APN 311S0406
5 TC7SZ08AFEAPE
DIFFERENTIAL_PAIR=USB2_TPAD
90 20
R5701
1
CRITICAL
5
USB_TPAD_P
24 2
5%
50 8
=PP3V3_S3_TPAD
2 1
SOT665
USB_TPAD_R_P
1/16W MF-LF 402
PP3V3_S3_PSOC
DIFFERENTIAL_PAIR=USB2_TPAD NET_SPACING_TYPE=USB NET_PHYSICAL_TYPE=USB_90D
50
50 7
WS_LEFT_OPTION_KBD
U5726 Y
B
WS_LEFT_OPTION_KEY 50
50 7 50 7 50 7
WS_LEFT_SHIFT_KBD WS_LEFT_OPTION_KBD WS_CONTROL_KBD
1 3 6
SN74LVC1G10
SC70
Y
A B C
U5703
2
43
SMC_TPAD_RST_L
TO MLB CONNECTOR
90 20
R5702
24 2 1
1/16W MF-LF 402
USB_TPAD_N
USB_TPAD_R_N
DIFFERENTIAL_PAIR=USB2_TPAD NET_SPACING_TYPE=USB NET_PHYSICAL_TYPE=USB_90D
DIFFERENTIAL_PAIR=USB2_TPAD
5%
=PP3V42_G3H_TPAD
50 8
R5769
33K
5%
R5770
33K
5%
R5771
33K
50 8
=PP3V3_S3_TPAD WS_CONTROL_KBD
2 1
CRITICAL 5 TC7SZ08AFEAPE
A
SOT665
1/16W MF-LF 2 402
1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
U5727 Y
B
WS_CONTROL_KEY 50
50 7
U5701 CHIP DECOUPLING PLACE C5701, C5702 & C5703

CLOSE TO U5701 VDD PIN 22
PLACE C5704, C5705 & C5706

CLOSE TO U5701 VDD PIN 49
TPAD BUTTONS DISABLE

R5704
1
50
PP3V3_S3_PSOC
1 2
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM
1.5 2 =PP3V3_S3_TPAD 8 50
50
C5701
4.7UF
20% 6.3V X5R 603
1 2
C5702
100PF
5% 50V CERM 402
1 2
C5703
0.1UF
10% 16V X7R-CERM 402
1 2
C5704
100PF
5% 50V CERM 402
1 2
C5705
0.1UF
10% 16V X7R-CERM 402
1 2
C5706
4.7UF
20% 6.3V X5R 603
5% 1/16W MF-LF 402
BUTTON_DISABLE PLACE THESE COMPONENTS CLOSE TO J5800 THIS ASSUMES THERES A PP3V42_G3H PULL UP ON MLB
Q5701
SSM3K15FV
SOD-VESM-HF
D 3
WELLSPRING 1
THE TPAD BUTTONS WILL BE DISABLE WHEN THE LID IS CLOSED LID OPEN => SMC_LID_LC ~ 3.42V LID CLOSE => SMC_LID_LC < 0.50V
A
1 G SMC_LID
43 42 41
S 2
IN
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
50
96
WS_KBD1 WS_KBD2 WS_KBD3 WS_KBD4 WS_KBD5 WS_KBD6 WS_KBD7 WS_KBD8 WS_KBD9 WS_KBD10 WS_KBD11 WS_KBD12 WS_KBD13 WS_KBD14
P2_5 P2_7 P0_1 P0_3 P0_5 P0_7 VSS VDD P0_6 P0_4 P0_2 P0_0 P2_6 P2_4
BOOSTER +18.5VDC FOR SENSORS

BOOSTER DESIGN CONSIDERATION: - POWER CONSUMPTION - DROOP LINE REGULATION - RIPPLE TO MEET ERS - 100-300 KHZ CLEAN SPECTRUM - STARTUP TIME LESS THAN 2MS - R5812,R5813,C5818 MODIFIED
D
PP5V_S3_TPAD_F 51
APN 152S0504
CRITICAL
L5801
3.3UH-870MA
IPD FLEX CONNECTOR

R5806
PP18V5_S3_SW
1
D5802
SOD-323
R5805
PLACEMENT_NOTE=under L5800 on top side
5% 1/16W MF-LF 402
INPUT_SW
0.50MM 0.20MM
BOOST_SW
MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM SWITCH_NODE=TRUE
0
5% 1/16W MF-LF
402
PP18V5_S3
7 51
R5800 0
1 2 5% 1/10W MF-LF 603
VLF3010AT-SM-HF
APN 516S0689
CRITICAL
B0520WSXG
APN 371S0313
1
1
MIN_LINE_WIDTH=0.50MM PP5V_S3_BOOSTER MIN_NECK_WIDTH=0.20MM
39PF
2 5% 50V CERM 402
1M
APN 353S1401 NO STUFF

CRITICAL PLACEMENT_NOTE=NEAR J5800
8
1% 1/16W MF-LF 2 402
55560-0227
VIN
=PP5V_S3_TPAD
1 C5800 0.1UF 2
20% 10V CERM 402
L5800
0.01H-0.3A-80V SM-HF
SYM_VER-1
1 3
51
L DO
U5805
QFN
1 C5819
FB
4 5 8
1
BOOST_FB
2
1UF
10% 25V X5R 603-1
VOLTAGE=3V3 MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM
TPS61045
CTRL
Z2_BOOST_EN
7 51
1 2
4 3
PP5V_S3_TPAD_F
TPAD_GND_F
VOLTAGE=0V MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM
CRITICAL
PGND SW GND THRML
R5813
71.5K
1%
1/16W MF-LF
7 51
PLACEMENT_NOTE=NEAR J5800
1 C5816 0.1UF 2
10% 16V X7R-CERM 402
1 2
2.2UF
10% 16V X5R 603
C5817
PAD
R5811
100K
1% 1/16W MF-LF 402
51 7
TPAD_GND_F 50 7 Z2_CS_L 50 7 Z2_DEBUG3 50 7 Z2_MOSI 50 7 Z2_MISO 50 7 Z2_SCLK 51 7 Z2_BOOST_EN 50 7 Z2_HOST_INTN Z2_BOOT_CFG1 50 7 Z2_CLKIN 50 7
51 7 51 7
0.50MM 0.20MM
M-ST-SM
2 402
PP3V3_S3_LDO
0.50MM 0.20MM
2 4 6 8 10 12 14 16 18 20 22
1 3 5 7 9 11 13 15 17 19 21
Z2_KEY_ACT_L 7 50 Z2_RESET 7 50 PSOC_F_CS_L 7 50 PICKB_L 7 50 PSOC_MISO 7 50 PSOC_MOSI 7 50 PSOC_SCLK 7 50

=I2C_TPAD_SDA
0.20MM
45
=I2C_TPAD_SCL 45 PP18V5_S3 7 51 0.50MM
R5801 0
1 2 5% 1/10W MF-LF 603
PLACEMENT_NOTE=under L5800 on top side
TPAD_GND_F
3V3 LDO FOR IPD

R5873 10
2 1% 1/16W MF-LF 402
51 7
51
PP5V_S3_TPAD_F 1
PP5V_S3_VR
PP3V3_S3_LDO
R5836
0.2 2
CRITICAL APN 353S1364

2
1 2
C5853
2.2UF 10%
16V
VDD
1 2
VR5802
MM3243DRRE
C5838
0.1UF
10%
16V X7R-CERM 402
1 2
C5854
4.7UF
20% 6.3V X5R 603
MLF 1 CE
X5R 603
VOUT GND
4
PP3V3_S3_LDO_R
B
51 7
TPAD_GND_F
Keyboard LED Driver

8
=PP3V3_S0_TPAD
=PP5V_S0_KBDLED
CRITICAL
L5850 R5853
470K
5% 1/16W MF-LF 402 2
42
To detect Keyboard backlight, SMC will tristate SMC_SYS_KBDLED: LOW = keyboard backlight present HIGH= keyboard backlight not present
IN
10UH-0.58A-0.35OHM 1 2 KBDLED_SW MIN_LINE_WIDTH=0.3 MM 1098AS-SM MIN_NECK_WIDTH=0.25 MM
CRITICAL
C5850 1
1UF 10% 10V 2 X5R 402-1
6 CTRL
SWITCH_NODE=TRUE
FF18-4A-R11AD-B-3H
F-RT-SM
51
J5815
1 2
J5815 pin 1 is grounded on keyboard backlight flex
VIN SW 3 LED 5
7
SMC_KDBLED_PRESENT_L
SMC_SYS_KBDLED NO STUFF
KBDLED_ANODE
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM
BOM OPTION: KBDLED_YES

CRITICAL
U5850
LT3491
DFN
R5855
10
1%
APN 518S0612
WELLSPRING 2
SYNC_MASTER=PWRSQNC SYNC_DATE=05/12/2008
R5853 ALWAYS PRESENT
R58541
5% 1/16W MF-LF 402 2
R58521
10K 5% 1/16W MF-LF 402 2
1/16W
MF-LF
4.7K
2 402
CAP 4 THRML GND 2
KBD BACKLIGHT CONNECTOR

1
KBDLED_CAP
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM
PAD
7
C5855
1UF
10% 35V X5R 603
SMC_KDBLED_PRESENT_L 51
APPLE INC.
D
SCALE NONE
051-7546
SHT OF
A.0.0
51
96
C5818
R5812
J5800
1/6W MF 402-HF
1%
Digital SMS
Pull-up required if SMS_INT_L not used.
52 8
=PP3V3_S3_SMS
ENG_DIGSMS
1
VDD VDDIO SCK U5930 SDO SDI INT CSB GND
ENG_DIGSMS
43 42 8
=PP3V3_S5_SMC
1
R5932 10K
5% 1/16W MF-LF
PROD_DIGSMS
45
=I2C_SMS_SCL =I2C_SMS_SDA
6 7
273141043 NC
LGA CRITICAL
11NC 12NC 1 NC 10NC
10% 16V CERM-X5R 402
10% 16V X5R 402
+Y +X +Z (up) Front of system
2402
43
45
8 4 5
OUT
SMS_INT_L
1
RESERVED
5% 1/16W MF-LF 2402
R5931 10K
ENG_DIGSMS
ENG_DIGSMS
Circle indicates pin 1 location when placed in correct orientation
Stuff R5931 AND NoStuff R5932 to use U5930 NoStuff R5931 AND Stuff R5932 if U5930 is not used
Analog SMS
R5921 PULLS UP SMS_PWRDN TO TURN OFF SMS WHEN PIN IS NOT BEING DRIVEN BY SMC
52 8
=PP3V3_S3_SMS
1
14
C5922
0.1UF 10%
402
C5926
10UF 20%
603
B
42
Desired orientation when placed on board top-side:
R59211
5% 1/16W MF-LF 4022
IN
10K
VDD
2 16V X5R
2 4V X5R
AP344ALH
1 5 2 SMS_SELFTEST 15 NC 4
1
U5920
LGA
+Y 12 SMS_X_AXIS 10 SMS_Y_AXIS 8 SMS_Z_AXIS

OUT OUT OUT
42
FS PD ST RES RES NC NC NC GND
VOUTX
SMS_ONOFF_L
SMS_PWRDN
MAKE_BASE=TRUE
CRITICAL
VOUTY VOUTZ
+X
42
Front of system
+Z (up)
42
R5922 NC
10K
5% 1/16W MF-LF 2 402
3 NC 6 NC 9
NC NC NC
11 NC 13 NC 16 NC
C5923
402
C5924
402
C5925
402
Circle indicates pin 1 location when placed in correct orientation
0.01UF 10% 2 16V CERM
0.01UF 10% 2 16V CERM
0.01UF 10% 2 16V CERM
Sudden Motion Sensor (SMS)
SYNC_MASTER=SENSOR

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
52
96
C5931 0.022UF
C5932 0.1UF
Desired orientation when placed on board top-side:
44 8
=PP3V3_S5_ROM NO STUFF
R61901 R61001
C
44
R6150
IN
5% 1/16W MF-LF 402 2
10K
3.3K
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 2 402

90 44
3.3K
0.1UF
VCC
20% 10V CERM 2 402

6 SCLK
U6100
32MBIT
SOP SI/SIO0 5 MX25L3205DM2I-12G
90 44
R6101
C6100 1
CRITICAL
SPI_CLK_MUX SPI_MLB_CS_L
R6152
SPI_MOSI
1
C
SPI_MOSI_MUX
IN
44
SPI_CLK
PLACEMENT_NOTE=PLACE CLOSE TO U6100

44
IN
5% 1/16W MF-LF 402
1 CE*
OMIT
SO/SIO1 2
90
R6105
SPI_MISO_R NO STUFF
1
SPI_WP_L SPI_HOLD_L
3 WP*/ACC
7 HOLD*
5% 1/16W MF-LF 402
SPI_MISO_MUX
OUT
44
1
GND 4
R6191
10K
5% 1/16W MF-LF 402
5% 1/16W MF-LF 2 402
MCP79 SPI Frequency Select

Frequency SPI_MOSI 0 0 1 1 SPI_CLK 0 1 0 1
31 MHz 42 MHz 25 MHz 1 MHz
25MHz is selected with R5190 and R5191 Any of the 4 frequencies can be selected with R6190, R6191, R5190 and R5191
SPI ROM
SYNC_MASTER=CHANG_M98_MLB

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
53
96
5
AUDIO CODEC
APPLE P/N 353S1527
XW6203 SM
54
R6208
1
4V6_REG_SENSE
MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM VOLTAGE=4.6V
PP4V6_AUDIO_ANALOG
54 55 59
59 58 54 8
FERR-220-OHM 2 =PP3V3_S0_AUDIO 1
0402
L6201
5% 1/16W MF-LF 402 MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V 1 MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.20MM
CODEC_DVDD
1
AVDD_ADC_DAC CRITICAL
D
1
R6251
20K
C6200
4.7UF
C6201
AVDD1 25 AVDD2 38
5% 1/16W MF-LF 402 2

9 90 21 90 21
20% 4V X5R 2 402
10% 2 50V CERM 402
0.001UF
C6203
10% 50V 2 CERM 402
0.001UF
C6204 1
20% 6.3V 2 TANT CASE-AL1
DVDD 1 DVDD_IO 9
C6206
100UF
10% 50V 2 CERM 402
0.001UF
C6207
20% 2 50V CERM 402
0.001UF GND_AUDIO_CODEC
54 55 56 57 59
IN IN IN
HDA_BITCLK HDA_SYNC HDA_SDOUT
R6203
SPDIFO 48 47 13 34 39 41 16 17 30 33 14 15 31 NO_TEST 28 21 22 29 NO_TEST 32 NO_TEST 43 NO_TEST 44 NO_TEST 45 NO_TEST 46 NO_TEST 27 40 37
90 21
OUT
HDA_SDIN0
5% 1/16W MF-LF 402

56
CODEC_SDATA_IN
SDATA_OUT SDATA_IN
CRITICAL
U6200
ALC885-VB3-GR
LQFP
SENSE_A SENSE_B PORT-A-L PORT-A-R PORT-F-L PORT-F-R PORT-F-VREFO
R6250
1
AUD_SPDIF_IN AUD_SENSE_A AUD_SENSE_B AUD_BI_PORT_A_L AUD_BI_PORT_A_R AUD_BI_PORT_F_L AUD_BI_PORT_F_R AUD_VREF_PORT_F AUD_VREF_PORT_A AUD_BI_PORT_E_L AUD_BI_PORT_E_R
IN IN IN
58 59 59
OUT IN
AUD_GPIO_0 AUD_GPIO_1
33
AUD_GPIO_0_R
NC_AUD_BI_PORT_C_L
57
5% 1/16W MF-LF 402
2 3
GPIO0/DMIC-CLK GPIO1/DMIC-L PORT-C-L PORT-C-R PORT-D-L PORT-D-R CD-L CD-GND CD-R
REV B3
IN IN IN IN OUT OUT IN IN
55 55
OUT OUT OUT
AUD_BI_PORT_C_R AUD_BI_PORT_D_L AUD_BI_PORT_D_R NC_BAL_IN_L NC_BAL_IN_COM NC_BAL_IN_R
NO_TEST 23 24
35 36
59 59 59 55 59 59
56 56
PORT-A-VREFO/DCVOL PORT-E-L PORT-E-R PORT-E-VREFO PORT-B-VREFO PORT-B-L PORT-B-R PORT-C-VREFO PORT-B-VREFO2 PORT-G-L
C
HDA_RST_L
NO_TEST 18 NO_TEST 19 NO_TEST 20
NC_AUD_VREF_PORT_E AUD_VREF_PORT_B AUD_BI_PORT_B_L AUD_BI_PORT_B_R NC_AUD_VREF_PORT_C NC_AUD_VREF_PORT_B2 NC_AUD_BI_PORT_G_L NC_AUD_BI_PORT_G_R NC_AUD_BI_PORT_H_L NC_AUD_BI_PORT_H_R
1
OUT OUT OUT
57 57 57
BEEP
90 21
12
BEEP
IN
11
RESET*
PORT-G-R PORT-H-L
R6205
100K
PORT-H-R
C6220
26 AVSS1 42 AVSS2
7 DVSS
5% 1/16W MF-LF 2 402
10% 2 16V X5R 402
0.1UF
VREF JDREF NC
AUD_CODEC_VREF AUD_CODEC_JDREF NC_VRP

NO_TEST 1
R6207
100K
R6206
20.0K CRITICAL
C6222
0.001UF
5% 1/16W MF-LF 2 402
2 SM 1
59 57 56 55 54
1% 1/16W MF-LF 2 402
C6221
3.3UF
10% 2 50V CERM 402
XW6201
10% 16V 2 TANT SMA-HF
GND_AUDIO_CODEC
MIN_LINE_WIDTH=0.30 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V
AUDIO 4.6V REGULATOR

APPLE P/N 353S1897
C6211
0.015UF 1 4V6_REG_BP 2 CRITICAL
10% 16V X7R 402
FERR-220-OHM
56 9
L6200
0402
U6201
MAX8902A
3 1 EN IN BP GND THRML PAD 9 TDFN SELA SELB OUT OUTS 4 5 8 6
PP5V_S3_AUDIO
AUD_4V6_REG_IN
PP4V6_AUDIO_ANALOG
54 55 59
R6220
59 58 54 8
=PP3V3_S0_AUDIO
1K
AUD_REG_SHDN_L CRITICAL
4V6_REG_SENSE
54
5% 1/16W MF-LF 402 1
C6210
0.1UF
R6221
10K
C6208 1
20% 16V TANT-POLY 2 2012-LLP
C6209
0.001UF
CRITICAL
1
10% 2 16V X5R 402
5% 1/16W MF-LF 2 402
10UF
C6205
100UF
C6212
0.1UF
10% 16V 402
10% 2 50V CERM 402
20% 2 6.3V TANT CASE-AL1
2 X5R
AUDIO:CODEC
SYNC_MASTER=AUDIO SYNC_DATE=07/09/2008
XW6200 SM
1 2
GND_AUDIO_CODEC
54 55 56 57 59

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
54
96
R6204
22
6 10 5
BCLK SYNC
AUD_SPDIF_O
33
AUD_SPDIF_OUT
OUT
58
SPDIFI/EAPD/MIDI-I/DMIC-R
5% 1/16W MF-LF 402
Pseudo-Diff Line-In Filter GAIN = -5.4DB AV = 0.52 FC = 1.8 HZ

FERR-220-OHM
59 54
L6300
0402
MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.20MM PP4V6_AUDIO_LINE_IN CRITICAL
PP4V6_AUDIO_ANALOG
C6310 10UF
58
R6310
1
IN
AUD_LI_INL
AUD_LI_INL_C
25.5K 2
1% 1/16W MF-LF 402
R6312
AUD_LI_INL_R
1
13.3K 2
1% 1/16W MF-LF 402
20% 16V TANT-POLY 2012-LLP
C6312
2.2UF
1
10% 16V X5R 603
AUD_PORTA_L
AUD_BI_PORT_A_L
OUT
54
R6302
27.4K
CRITICAL
CRITICAL 0.001UF
1% 1/16W MF-LF 402 2
C6301 1
2.2UF
20% 6.3V 2 CERM 402-LF
C6300 1
10% 50V CERM 2 402
CRITICAL 10 MAX4253EUB V+
U6300
7
V-
UMAX-HF 9 6
CRITICAL
C
IN
59
AUD_LIFILT_SHUTDOWN_L CRITICAL
58
IN
AUD_LI_GND
C6311 10UF
2 1
R6311
1
AUD_LIFILT_LT_R
25.5K 2
1% 1/16W MF-LF 402
R6313
AUD_LIFILT_LT
1
13.3K 2
1% 1/16W MF-LF 402
R6301
1
10
R6300
AUD_CODEC_INREF
1 165 2
1% 1/16W MF-LF 402
AUD_VREF_PORT_A
IN
54
5% 1/16W MF-LF 402
C6320 10UF
2 1
R6320
1
AUD_LIFILT_RT_R
25.5K 2
1% 1/16W MF-LF 402
R6322
AUD_LIFILT_RT
1
13.3K 2
1% 1/16W MF-LF 402
CRITICAL
CRITICAL
1
59 57 56 55 54
GND_AUDIO_CODEC
C6303 1
0.001UF
10% 50V CERM 2 402
C6302
100UF
20% CASE-AL1
CRITICAL
4 3
V-
2 6.3V TANT
GND_AUDIO_CODEC
5 1
54 55 56 57 59
R63031
27.4K
U6300
2
V+
B
58
1% 1/16W MF-LF 402 2
10
MAX4253EUB CRITICAL AUD_PORTA_R
UMAX-HF
C6322
2.2UF
1
10% 16V X5R 603
AUD_BI_PORT_A_R
OUT
54
CRITICAL
C6321 10UF
IN
R6321
1
AUD_LI_INR
AUD_LI_INR_C
25.5K 2
1% 1/16W MF-LF 402
R6323
AUD_LI_INR_R
1
13.3K 2
1% 1/16W MF-LF 402
CRITICAL
AUDIO: LINE IN
A
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
55
96
Headphone Amplifier (MAX9724A) APN:353S1637

D
54 9
PP5V_S3_AUDIO
FERR-120-OHM-1.5A 1 2 PP5V_AUDIO_HPAMP_PVDD_F
0402 VOLTAGE=5V MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 mm
L6500
D
1
CRITICAL
C6501
C6500 1
20% 16V TANT-POLY 2 2012-LLP
10UF
10% 50V 2 CERM 402
0.001UF AUD_HPAMP_OUTL_R
12
56 56
IN IN
AUD_HPAMP_INL_M AUD_HPAMP_INR_M
6 INL 8 INR
CRITICAL
U6500
MAX9724A
TQFN
OUTL 11 OUTR 10 C1P 1 C1N 3
AUD_PORTD_L
FERR-1000-OHM
54
L6501
0402
5 SHDN* 13 THRM PAD 7 SGND 2 PGND 9 SVSS
MAX9724_C1P CRITICAL
5% 1/16W MF-LF 402
R6523
1
OUT
58
AUD_PORTD_R
OUT
58
4 PVSS
IN
AUD_GPIO_0
AUD_HPAMP_MUTE_L
C6504 1
1UF MAX9724_C1N
MIN_LINE_WIDTH=0.20 mm MIN_NECK_WIDTH=0.10 mm 10% 10V X5R 2 402
5% 1/16W MF-LF 402
AUD_HPAMP_OUTR_R
56
R65001
5% 1/16W MF-LF 402 2
10K
MAX9724_PVSS CRITICAL
1
R65141
2.21K
1% 1/16W MF-LF 402 2
R6524
2.21K
C6503
1UF CRITICAL
C
59 57 55 54
XW6500 SM
1 2
10% 2 10V X5R 402
C6502 1
10% 16V X5R-CERM 2 0805
1% 1/16W MF-LF 2 402
GND_AUDIO_HPAMP_PGND
10UF
GND_AUDIO_CODEC
XW6501 SM
1 2
AUD_LO_GND
IN
58
1st Order DAC Filter

HP:3.52 HZ LP:34 KHZ VOLTAGE GAIN:1.53
B
CRITICAL
B
C6510
3.3UF
54
R6510
AUD_CODEC_OUTL_C
1
IN
AUD_BI_PORT_D_L
13.7K 2
1% 1/16W MF-LF 402
R6511
1
21K
AUD_HPAMP_OUTL_R
56
10% 16V TANT SMA-HF
1% 1/16W MF-LF 402
CRITICAL
C6511
220PF
2 1 5% 25V CERM 402
56
AUD_HPAMP_INL_M
CRITICAL
C6521
220PF
2 1 5% 25V CERM 402
56
AUD_HPAMP_INR_M CRITICAL
C6520
3.3UF
54
R6520
AUD_CODEC_OUTR_C
1
IN
AUD_BI_PORT_D_R
13.7K 2
1% 1/16W MF-LF 402
R6521
1
21K
AUD_HPAMP_OUTR_R
56
AUDIO: HEADPHONE AMP

10% 16V TANT SMA-HF
1% 1/16W MF-LF 402

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
56
96
VDD
R6513
56
2X MONO SPEAKER AMPLIFIERS (LM48310) APN: 353S1901 GAIN = 12DB 79Hz < FC (L&R) < 93Hz 53Hz < FC (SUB) < 62Hz
D
57 9
D
PP5V_S3_AUDIO_AMP
PLACE C6611/C6612 CLOSE TO PVDD PIN
CRITICAL
CRITICAL
1
CRITICAL
1
C6612 1
20% 6.3V TANT-POLY 2 CASE-A4
C6611
47UF
10% 2 50V CERM 402
0.001UF
9 PVDD 3 VDD
C6610
1UF
SPEAKER CHECKPOINTS
10% 2 10V X5R 402-1
CRITICAL FERR-1000-OHM AUD_BI_PORT_B_L

54
C6613
0.1UF
1 2 10% 16V X7R-CERM 402
LM48310
IN
1 0402
AUD_SPKRAMP_INL_L
LM48310L_PIN LM48310L_NIN
1 IN_P 2 IN_N 4 SD*
LLP
OUTA 10 OUTB 7
SPKRAMP_L_P_OUT SPKRAMP_L_N_OUT U6610_SOUT
MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM
57 95 95 57 57 95
R6610
2
SPKRAMP_L_P_OUT
0
5% 1/16W MF-LF 402
SPKRCONN_L_P_OUT
OUT
7 58 95
54
IN
FERR-1000-OHM 2 AUD_VREF_PORT_B 1
0402
L6601
SYNC_OUT 6 5 SYNC_IN THRML PAD 11
PLACE CLOSE TO U6610 PIN6

1
R6601
100K
CRITICAL
1
CRITICAL
GND 8
C6614
0.1UF
R6602
33
95 57
R6611
2
SPKRAMP_L_N_OUT
0
5% 1/16W MF-LF 402
SPKRCONN_L_N_OUT
5% 1/16W MF-LF 402 2
10% 2 16V X7R-CERM 402
5% 1/16W MF-LF 2 402
OUT
7 58 95
59 57 56 55 54
GND_AUDIO_CODEC
SPKRAMP_SYNC1 57
57
AUD_SPKRAMP_SHUTDOWN_L
C
PLACE C6621/C6622 CLOSE TO PVDD PIN MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM
57 9
PP5V_S3_AUDIO_AMP CRITICAL CRITICAL

1
R6620
2
CRITICAL
1
95 57
SPKRAMP_R_P_OUT
0
5% 1/16W MF-LF 402
SPKRCONN_R_P_OUT
OUT
7 58 95
C6622 1
CRITICAL FERR-1000-OHM
54
C6621
0.001UF
9 PVDD 3 VDD
C6620
1UF
95 57
20% 6.3V TANT-POLY 2 CASE-A4
47UF
10% 2 50V CERM 402
10% 2 10V X5R 402-1
R6621
2
SPKRAMP_R_N_OUT
0
5% 1/16W MF-LF 402
SPKRCONN_R_N_OUT
L6620
0402
C6623
0.1UF AUD_SPKRAMP_INR_L
1 2 10% 16V X7R-CERM 402
U6620
LM48310
OUT
7 58 95
IN
AUD_BI_PORT_B_R
LM48310R_PIN LM48310R_NIN
1 IN_P 2 IN_N 4 SD*
LLP
OUTA 10 OUTB 7
SPKRAMP_R_P_OUT SPKRAMP_R_N_OUT NOSTUFF
57 95 57 95
57
AUD_SPKRAMP_SHUTDOWN_L CRITICAL
1
R6603
1
CRITICAL
GND 8
C6624
0.1UF
5% 1/16W MF-LF 402
10% 2 16V X7R-CERM 402

59 57 56 55 54
SPKRAMP_SYNC1 57 U6620_SOUT
GND_AUDIO_CODEC
R6604
1
33
R6630
2
SPKRAMP_SYNC2 57
95 57
SPKRAMP_S_P_OUT
0
5% 1/16W MF-LF 402
SPKRCONN_S_P_OUT
B
OUT
7 58 95
5% 1/16W MF-LF 402
PLACE CLOSE TO U6620 PIN6

95 57
R6631
2
SPKRAMP_S_N_OUT
0
5% 1/16W MF-LF 402
SPKRCONN_S_N_OUT
PLACE C6631/C6632 CLOSE TO PVDD PIN

57 9
OUT
7 58 95
PP5V_S3_AUDIO_AMP CRITICAL CRITICAL

1
CRITICAL
1
C6632 1
CRITICAL FERR-1000-OHM
54
C6631
0.001UF
9 PVDD 3 VDD
C6630
1UF
20% 6.3V 2 TANT CASE-AL1
100UF
10% 2 50V CERM 402
10% 2 10V X5R 402-1
L6630
0402
C6633
0.15UF AUD_SPKRAMP_INS_L
1 10% 10V X5R 402 2
U6630
LM48310
IN
AUD_BI_PORT_C_R
LM48310S_PIN LM48310S_NIN
1 IN_P 2 IN_N 4 SD*
LLP
OUTA 10 OUTB 7
SPKRAMP_S_P_OUT SPKRAMP_S_N_OUT NOSTUFF
57 95 57 95
57
AUD_SPKRAMP_SHUTDOWN_L CRITICAL
1
R6605
1
CRITICAL
GND 8
C6634
0.15UF
5% 1/16W MF-LF 402
AUDIO:SPEAKER AMP
A
59 57 56 55 54
10% 10V 2 X5R 402
GND_AUDIO_CODEC
SPKRAMP_SYNC2 57

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
57
96
L6610
U6610
AUDIO JACK 1 LO/HP JACK, SPDIF TX

D
R6713
AUD_CONNJ1_SLEEVE2
59 58 54 8
AUD_SPDIF_OUT
IN
54
MIC CONNECTOR
CRITICAL
D
J6780
78171-0003
M-RT-SM 4
FERR-1000-OHM AUD_CONNJ1_SLEEVE2_F
1 0402 2
L6703 L6702
0402
HS_MIC_HI
OUT
59
APN: 518S0520
59 7
=PP3V3_S0_AUDIO AUD_CONNJ1_SLEEVE
1
5% 1/16W MF-LF 402
FERR-1000-OHM
1 2
APN: 514-0607
J6700
F-RT-TH3
6 5 2 1 3 4
R6711
0
2
OUT OUT OUT
HS_MIC_LO
OUT
59
59 7 59 7
AUD_CONNJ1_SLEEVE_F
CRITICAL AUD_CONNJ1_RING
1
FERR-220-OHM-2.5A
1 2 0603
AUDIO-JACK-TRANS-M97
R6714
0
2
AUD_LO_GND
OUT
56
AUD_CONNJ1_RING_F
R6715
AUD_CONNJ1_TIPDET
1
5% 1/16W MF-LF 402
CRITICAL FERR-220-OHM AUD_CONNJ1_TIPDET_F

1 0402 2
L6704
AUD_PORTD_R
BI
56
AUDIO
A - VIN B - VCC C - GND
7 8 9
R6716
AUD_CONNJ1_TIP
1
5% 1/16W MF-LF 402
CRITICAL FERR-220-OHM AUD_CONNJ1_TIP_F

1 0402 2
L6706
AUD_PORTD_L
BI
56
5% 1/16W MF-LF 402
OPERATING VOLTAGE 3.3
R6710
1
POF
10
AUD_CONNJ1_SLEEVEDET
11 12 13
1
R6700
AUD_CONNJ1_SLEEVEDET_F CRITICAL
2 1
10K
AUD_J1_SLEEVEDET_R
OUT
59
SHELL
SHIELD PINS
5% 1/16W MF-LF 402
C6700
0.1UF
C6701
2.2UF
CRITICAL
DZ6702
6.8V-100PF
402
CRITICAL 6.8V-100PF
402
5% 1/16W MF-LF 402 2 1 0402 1 1
10% 16V 2 X5R 402
20% 6.3V 2 CERM 402-LF
DZ6705
6.8V-100PF
402
DZ6704
FERR-1000-OHM
2
L6705
SPEAKER CONNECTOR
AUD_J1_TIPDET_R
OUT
59
CRITICAL
1 2
CRITICAL
CRITICAL
DZ6706
6.8V-100PF
402
DZ6703
6.8V-100PF
402
J6781
C6705
100PF
95 57 7
APN: 518S0519
IN IN
78171-0002
M-RT-SM 3
5% 2 50V CERM 402
GND_CHASSIS_AUDIO_JACK
58
95 57 7
SPKRCONN_L_P_OUT SPKRCONN_L_N_OUT
1 2
RETURN FOR HF NOISE APN: 518S0521

R6701
58 59 58 54 8
CRITICAL
J6782
78171-0004
M-RT-SM 5
95 57 7 95 57 7 95 57 7
IN IN IN IN
=PP3V3_S0_AUDIO
APN: 514-0608
J6750
F-RT-TH3
5 2 1 3 4
R6749
AUD_J2_OPT_OUT
1
5% 1/16W MF-LF 402
10
AUD_SPDIF_IN
OUT
54
95 57 7
SPKRCONN_S_P_OUT SPKRCONN_S_N_OUT SPKRCONN_R_P_OUT SPKRCONN_R_N_OUT NOSTUFF CRITICAL
1 2 3 4
CRITICAL
5% 1/16W MF-LF 402
NOSTUFF CRITICAL
1
R6761
1
FERR-220-OHM AUD_CONNJ2_SLEEVE_F
1 0402 2
L6751
C6783 1
NOSTUFF CRITICAL 100PF 5% 50V NOSTUFF CERM CRITICAL 402
1 2
C6784
100PF
5% 402
AUDIO-RCVR-M97
AUD_CONNJ2_SLEEVE
2 50V CERM
AUD_CONNJ2_TIPDET
5% 1/16W MF-LF 402
R6762
1
C6781 1
100PF
5% 50V CERM 2 402 2
C6782
100PF
5% 50V 402
AUD_CONNJ2_TIPDET_F
1
R6764
AUD_CONNJ2_RING
1
5% 1/16W MF-LF 402
FERR-1000-OHM AUD_LI_INR
BI
55
L6754
0402
2 CERM
AUDIO
A - VDD B - GND C - VOUT
6 7 8
AUD_CONNJ2_RING_F AUD_CONNJ2_TIP_F
1
5% 1/16W MF-LF 402
FERR-1000-OHM
2 0402
L6756
R6766
1
AUD_LI_INL
BI
55
OPERATING VOLTAGE 3.3
AUD_CONNJ2_TIP
POF
9
SHELL
SHIELD PINS
10 11 12
R6768
AUD_CONNJ2_SLEEVEDET
1
1
5% 1/16W MF-LF 402
FERR-220-OHM
1 2 0402
L6758
AUD_J2_COM
XW6701 SM
1 2
AUD_LI_GND
55
AUD_CONNJ2_SLEEVEDET_F CRITICAL CRITICAL

2
C6750
0.1UF
5% 1/16W MF-LF 402
10% 2 16V X5R 402
DZ6753
6.8V-100PF
402
DZ6755
6.8V-100PF
402
FERR-1000-OHM
1 0402 2
L6752
AUD_J2_TIPDET_R
OUT
59
AUDIO: JACKS
CRITICAL
CRITICAL
1 1
DZ6752
6.8V-100PF
402 1
DZ6754
402
C6756
100PF

6.8V-100PF
5% 2 50V CERM 402
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

58
AUDIO JACK 2 LINE IN JACK, SPDIF RX

APPLE INC.
SIZE
DRAWING NUMBER
REV.
D
SCALE NONE
051-7546
SHT OF
A.0.0
58
96
5% 1/10W MF-LF 603
CRITICAL
BI_MIC_LO BI_MIC_SHIELD BI_MIC_HI
1 2 3
L6701
4
NOSTUFF FERR-1000-OHM
59 55 54
3
L6881
0402
2
PORT E (HEADSET MIC)
PP4V6_AUDIO_ANALOG
VOLTAGE=4.6V MIN_LINE_WIDTH=0.10 mm MIN_NECK_WIDTH=0.10 mm
MIKEY FERR-1000-OHM
CODEC OUTPUT SIGNAL PATHS

FUNCTION HP/LINE OUT SATELLITES SUB SPDIF OUT VOLUME 0X0C (12) 0X0D (13) 0X0F (15) N/A CONVERTER 0X02 (2) 0X03 (3) 0X05 (05) 0X06 (6) MIXER(OUTPUT) 0X0C (12) 0X0D (13) 0X0F (15) PIN COMPLEX MUTE CONTROL 0X14 (20,D) GPIO_0 0X18 (24,B) VREF_B (100%) 0X1A (26,C) VREF_B (100%) 0x1E (SPDIF OUT) N/A DET ASSIGNMENT 0X14 (20,D) N/A N/A 0X16 (22,G)
59 58 54 8
L6880
0402
=PP3V3_S0_AUDIO =I2C_MIKEY_SCL MIKEY 0 2
PP3V3_S0_HS_RX
R6890
1
45
IN
CODEC INPUT SIGNAL PATHS

FUNCTION LINE IN SPDIF IN BUILT-IN MIC HEADSET MIC MIXER(INPUT) 0X23 (35) N/A 0X24 (36) 0X24 (36) CONVERTER 0X08 (8) 0X0A (10) 0X07 (7) 0X07 (7) PIN COMPLEX 0X15 (21,A) 0x1F (SPDIF IN) 0X19 (25,F) 0X1B (27,E) VREF VREF_A (50%) N/A VREF_F (100%) MIKEY DET ASSIGNMENT 0X15 (21,A) N/A N/A MIKEY
45
BI
=I2C_MIKEY_SDA
MIKEY 0 2
R6891
1 5% 1/16W 402 MF-LF
C6880
10UF
A2
5% 1/16W 402 MF-LF
CRITICAL MIKEY 1
6.3V 20% 2 603 X5R
MIKEY
D
HS_MIC_BIAS HS_SW_DET HS_RX_BP
AVDD
U6880 CD3272A2
WCSP9
21
OUT
AUD_I2C_INT_L
MIKEY 0 2
R6892
1
HS_SCL HS_SDA HS_INT_L HS_RST_L
B3 A3 C3 B2
SCL SDA INT*
MICBIAS DETECT BYPASS
B1 A1 C1
R6893
19 9
5% 1/16W 402 MF-LF 2
MIKEY CRITICAL
1
C6882
4.7UF
20% TANT 603-HF
IN
AUD_IPHS_SWITCH_EN
MIKEY
C2
5% 1/16W 402 MF-LF
R68801
100K
5% 1/16W MF-LF 402 2
MIKEY
PORT D DETECT (Line-out)

54
PORT G DETECT(SPDIF DELEGATE)
HS_INT_L PULLUP ON MCP PAGE
C6881
0.01UF 16V
MIKEY 1 MIKEY MIKEY

1
GND_AUDIO_CODEC
54 55 56 57 59
OUT OUT
59
AUD_SENSE_B AUD_SENSE_A PP3V3_S0_AUDIO_F

1
59 57 56 55 54
10% 402 CERM 2
R6881
10K
R6882
2.2K
59 54
GND_AUDIO_CODEC MIKEY CRITICAL
R6806
5.11K
R6805
10K
1% 1/16W MF-LF 402 2
5% 1/16W MF-LF 2 402
R6801
220K
AUD_OUTJACK_INSERT_L
5% 1/16W MF-LF 2 402
1% 1/16W MF-LF 2 402
AUD_PORTD_DET_L NC
1% 1/16W MF-LF 2 402
C6883
0.1UF
1 10% 25V X5R 402 2
AUD_PORTG_DET_L NC
54
Q6800
SSM6N15FEAPE
SOT563 2
D 3
OUT
AUD_BI_PORT_E_L
MAKE_BASE=TRUE
HS_MIC_HI OMIT
1
IN
58
Q6801
SSM6N15FEAPE
SOT563
D 3
Q6801
SSM6N15FEAPE
SOT563
D 6
54
R6802
OUT
AUD_BI_PORT_E_R
R6883
100K
OMIT
58
IN
AUD_J1_TIPDET_R
47K
AUD_J1_DET_RC
5 G 1
5% 1/16W MF-LF 402
S 4
5 G
C6801
0.1UF
S 4
2 G
S 1
XW6880 SM
59 57 56 55 54
5% 1/16W MF-LF 2 402
C6884
15PF
OMIT
C6885
50V 5% 402 CERM 2
2 10% 50V CERM 402
0.001UF HS_MIC_LO
C
IN
58
GND_AUDIO_CODEC
2 20% 10V CERM 402

59 57 56 55 54
GND_AUDIO_CODEC
R6803
59
TABLE_5_HEAD
PP3V3_S0_AUDIO_F
1
100K 2
5% 1/16W MF-LF 402
PART#
QTY 1 1 1 1 1 1
DESCRIPTION 100K 5% 0402 RESISTOR 15PF 5% 0402 CAPACITOR 100PF 10% 0402 CAPACITOR 0 OHMS 5% 0402 RESISTOR 0 OHMS 5% 0402 RESISTOR 0 OHMS 5% 0402 RESISTOR
REFERENCE DESIGNATOR(S) R6883 C6884 C6885 R6883 C6884 C6885
BOM OPTION
TABLE_5_ITEM
AUD_J1_SLEEVEDET_INV
116S0114 131S1513 MIKEY MIKEY
R6861
220K
TABLE_5_ITEM
59 58
IN
AUD_J1_SLEEVEDET_R
5% 1/16W MF-LF 2 402
Q6800
SOT563
D 6
59 58
AUD_J1_SLEEVEDET_R
132S0045 116S0004 MIKEY NOMIKEY
TABLE_5_ITEM
SSM6N15FEAPE
TABLE_5_ITEM
TABLE_5_ITEM
C6802
0.01UF
2 G
116S0004
NOMIKEY
TABLE_5_ITEM
S 1
116S0004 NOMIKEY
59 57 56 55 54
GND_AUDIO_CODEC
10% 2 16V CERM 402
LINE_IN AMP SHUTDOWN CONTROL

59 55 54
PP4V6_AUDIO_ANALOG
PORT F (BUILT-IN MIC) PORT A DETECT (Line-in)

1 1
R6815
100K
54
59 54
OUT
AUD_SENSE_A
R6814
100K
R6855
IN
B
59
PP3V3_S0_AUDIO_F
1
R6813
39.2K
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
AUD_VREF_PORT_F
2.2K 2
5% 1/16W MF-LF 402
R6850
BI_MIC_BIAS CRITICAL
1
2.2K 2
5% 1/16W MF-LF 402
C6853
10UF
20% TANT-POLY 2012-LLP
AUD_LIFILT_SHUTDOWN_L
OUT
55
B
FERR-1000-OHM
R6811
270K
1% 1/16W MF-LF 402 2
2 16V
59 57 56 55 54
Q6803
AUD_INJACK_INSERT_L
D 6
GND_AUDIO_CODEC CRITICAL
5% 1/16W MF-LF 2 402
NC
D 3
SSM6N15FEAPE
SOT563
54
C6850
0.1UF
1 10% 25V X5R 402 2
L6850
0402
Q6802
SSM3K15FV
SOD-VESM-HF
D 3
Q6803
SSM6N15FEAPE
SOT563
OUT
AUD_BI_PORT_F_L
MAKE_BASE=TRUE
BI_MIC_HI_F
1
BI_MIC_HI
IN
7 58
2 G
R6812
58
AUD_LIN_SHUTDOWN
S 4
S 1
54
IN
AUD_J2_TIPDET_R
47K
OUT
AUD_BI_PORT_F_R
R6852
100K
AUD_J2_DET_RC
1 1 G
5% 1/16W MF-LF 402
C6811
0.1UF 10V
S 2
5 G
XW6850 SM
59 57 56 55 54
5% 1/16W MF-LF 2 402
C6852
15PF 50V
C6851
0.001UF
1
5% 402 CERM 2
10% 2 CERM 50V 402
FERR-1000-OHM
2
L6851
0402
2 20% 402 CERM

59 57 56 55 54
GND_AUDIO_CODEC
BI_MIC_LO_F
BI_MIC_LO
IN
7 58
GND_AUDIO_CODEC GND_CHASSIS_AUDIO_MIC
1
XW6851 SM
1 2
BI_MIC_SHIELD
IN
7 58
R6851
0
5% 1/16W MF-LF 2 402
PLACE L6800/C6800 CLOSE TO Q6800/01/02
FERR-1000-OHM
59 58 54 8
L6800
0402
AUDIO: JACK TRANSLATORS

=PP3V3_S0_AUDIO
2
1
PP3V3_S0_AUDIO_F 59

C6800
0.1UF
10V 2 20% 402 CERM

59 57 56 55 54
GND_AUDIO_CODEC
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
59
96
ENABLE GND
2 6.3V
MagSafe DC Power Jack

CRITICAL CRITICAL
J6900
78048-0573
M-RT-SM
F6905
6AMP-24V PP18V5_DCIN_FUSE
MIN_LINE_WIDTH=1mm MIN_NECK_WIDTH=0.20mm VOLTAGE=18.5V 1 1 2 1206-1
Q6910 restricts system load to 10K-70K window until adapter detects system and enables 16.5V output. CRITICAL Q6910
=PP18V5_DCIN_CONN
8 60
PWR PWR GND GND SIG
1 2 3 4 5
C6905
0.01UF
20% PLACEMENT_NOTE=Place near L6900 2 50V CERM 603
1-Wire OverVoltage Protection

PP18V5_DCIN_ONEWIRE
MIN_LINE_WIDTH=0.25mm MIN_NECK_WIDTH=0.20mm VOLTAGE=18.5V
6
BSS84V
SOT-563
Vgs(max) = 20V
D S
1
C6915 1
SC-75
R6917
270K
G
2
R69111
470K
5% 1/16W MF-LF 402 2
RCLAMP2402B
D6900
CRITICAL
100K
5% 1/16W MF-LF 402 2
R69151
270K CRITICAL ONEWIRE_DCIN_DIV
1 V+ 3 V2 5
ONEWIRE_EN CRITICAL Q6915

SOT563
U6915
LM397
5% 1/16W MF-LF 402 2
R69181
270K
5% 1/16W MF-LF 402 2
ONEWIRE_PWR_EN_L_DIV Vgs = 11.750V @ 20V DCIN Vgs = 7.63V @ 13V DCIN R69121 330K
5% 1/16W MF-LF 402 2
ADAPTER_SENSE
<Rb> <Vth> R69141 ONEWIRE_ESD

100K
5% 1/16W MF-LF 402 2
SOT23-5-HF 4 ONEWIRE_OVERVOLT
SSM6N15FEAPE
R69161
270K
5% 1/16W MF-LF 402 2
ONEWIRE_PWR_EN_L
5
C6917
0.001UF
6
10% 2 50V CERM 402
Q6915
SSM6N15FEAPE
SOT563
R6910
SMC_BC_ACOK_RC
1 1
The chassis ground will otherwise float and can send transients onto ADAPTER_SENSE when AC is connected.
1K
Vth = Vdcin * (Rb / (Ra + Rb)) Vth = Vdcin / 2

1
R6920
24.3K
Voltage divider from DCIN ensures Q6901 Vgs is met when SYS_ONEWIRE is high or low. Q6920 used as bilateral switch to ensure SYS_ONEWIRE doesnt drive unpowered U6990 CRITICAL
SMC_BC_ACOK
IN
42 43
0.001UF CRITICAL
C6910
5% 1/16W MF-LF 402
10% 50V CERM 2 402
G 5
SOT563
1% 1/16W MF-LF 2 402
Q6920
SSM6N15FEAPE
2
Q6920
SSM6N15FEAPE
SOT563
SYS_ONEWIRE_BILAT
1
SYS_ONEWIRE
3.425V "G3Hot" Supply

R6905
60 8
Supply needs to guarantee 3.31V delivered to SMC VRef generator HN2D01JEAPE

SOT665
=PP18V5_DCIN_CONN
47
D6905
5% 1/8W MF-LF 805
PPDCIN_S5_P3V42G3H
8
PPVIN_G3H_P3V42G3H
3 4
P3V42G3H_BOOST
3 VIN 6 BOOST
=PPVBAT_G3H_P3V42G3H
NC
2
NC
C6990
10UF
10% 25V X5R 805
C6994
0.22UF
20% 6.3V X5R 402
U6990
LT3470ETS8
1 NC 2 TSOT23-8 SHDN* CRITICAL NC FB GND 4 8
SW BIAS 5 7
CRITICAL
2
1 CDPH4D19FHF-SM
L6995
33UH
2
=PP3V42_G3H_REG
BI
42 43
B
CRITICAL
P3V42G3H_SW
MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE
Vout = 3.425 200mA max output

1
BAT-M98
F-RT-SM 10
J6950
Battery Connector
FERR-50-OHM
C6995
22pF
5% 50V CERM 402
<Ra> R6995
348K
(Switcher limit)
L6950
SM-LF
1% 1/16W MF-LF 2 402
1 2 3 4 5 6 7
PPVBAT_G3H_CONN_F
PPVBAT_G3H_CONN
C6999
22UF
20% 6.3V X5R-CERM 603
61
P3V42G3H_FB
1
=SMBUS_BATT_SCL =SMBUS_BATT_SDA SMC_BS_ALRT_L

1
45 60 45 60 42 43
<Rb> R6996
200K
1% 1/16W MF-LF 402
CRITICAL 1
C6950
D6950
RCLAMP2402B
SC-75
CRITICAL
11
10% 2 50V CERM 402
0.001UF
3
J6955
78171-0005
M-RT-SM
Vout = 1.25V * (1 + Ra / Rb)
6 1 2 3 4 5
516S0698
GND_BATT_CHGND
=PP3V42_G3H_BATT =SMBUS_BATT_SDA =SMBUS_BATT_SCL SMC_BIL_BUTTON_DB_L
BI BI
45 60 45 60
OUT
43
DC-In & Battery Connectors

A
518S0588
C6954
0.001UF
10% 50V CERM 402
C6953
47PF
5% 50V CERM 402
C6952
47PF
5% 50V CERM 402
C6955
0.001UF
10% 50V CERM 402

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
60
96
<Ra> R69131
0.1UF
10% 25V 2 X5R 402
If ADAPTER_SENSE > Vth then turn off FET
5% 1/16W MF-LF 402 2
8
8
7
FROM ADAPTER
=PPDCIN_S5_CHGR
6
Inrush Limiter
2
Reverse-Current Protection
PPDCIN_S5_CHGR_R
D7005
1SS418
R7060
470K
C7060 1
0.1UF CRITICAL CRITICAL SOI SOI HAT1128R01HAT1128R01
1 2 6 7 3
R70651
100K
5% 1/16W MF-LF 402 2
5% SOD-723-HF 1/16W 1 MF-LF 2 402
10% 25V X5R 2 402

4
1 2
=PP3V42_G3H_CHGR
8 61
PPDCIN_S5_INRUSH
4 S
G 5
AMON_CLAMP
1 S
G 2
PP5V1_CHGR_VDD 61
(CHGR_AGATE) (CHGR_DCIN)
NOSTUFF
TO SYSTEM
=PPBUS_G3H
8
D7040
1 2
R7021
1
SIGNAL_MODEL=EMPTY
10
2
95
SOD-723-HF
1SS418
C7020
61 8
=PP3V42_G3H_CHGR
61
R7001
PP5V1_CHGR_VDD
1
10% 2 16V CERM 402
0.047UF
1
5% 1/16W MF-LF 402
CRITICAL CHGR_CSI_R_P CHGR_CSI_R_N

4 2 3 1
R7020
0.02
0.5% 1W MF 0612
CRITICAL
F7040
8AMP-24V
1206 2
R7022
10
2 5% 1/16W MF-LF 402
95
4.7
PP5V1_CHGR_VDDP
ACIN pin threshold is 3.2V, +/- 50mV Divider sets ACIN threshold at 13.07V
C7002 1
1UF
10% 10V 2 X5R 402
30mA max load
5% 1/16W MF-LF 402
PPDCIN_S5_FET_CHGR
CRITICAL
1
CRITICAL
1
C7001 1
1UF
20 10% 10V 2 X5R 402
C7022 1
0.1UF
10% 25V 2 X5R 402
C7021
0.1UF
5
C7030
22UF
C7031
22UF
10% 2 25V X5R 402
Input impedance of ~40K meets sparkitecture requirements
R7010
30.1K
1
45 45
IN BI
ISL6258A
1% 1/16W MF-LF 402 2
=SMBUS_CHGR_SCL =SMBUS_CHGR_SDA
NC
VDD VDDP 12 VHST CRITICAL AGATE 1 11 SCL CSIP 28 QFN 10 SDA CSIN 27
19
20% 2 25V POLY-TANT CASE-D2-SM
20% 25V 2 POLY-TANT CASE-D2-SM
U7000
93 93
CHGR_AGATE CHGR_CSI_P CHGR_CSI_N CHGR_BGATE CHGR_DCIN CHGR_BOOT CHGR_UGATE CHGR_PHASE CHGR_LGATE TP_CHGR_TRKL CHGR_AMON CHGR_BMON =CHGR_ACOK
1
CRITICAL
4
Q7030
RJK0305DPB
LFPAK-HF
C7032
1UF
C7033
1UF
C7034
1000PF
VREF = 3.2V, < 300uA CHGR_ACIN CHGR_ICOMP CHGR_VCOMP CHGR_VNEG CHGR_CSO_P CHGR_CSO_N
SIGNAL_MODEL=EMPTY 1
4 VREF 3 ACIN 5 ICOMP 7 VCOMP 8 VNEG 18 CSOP 17 CSON THRM_PAD
BGATE 16 DCIN 2 BOOT 25 UGATE 24 PHASE 23 21 13 9 15 14
C7035
0.1UF
1 2 3
10% 2 25V X5R 603-1
10% 2 25V X5R 603-1
10% 2 25V X7R 402
10% 2 25V X5R 402
CRITICAL
3
L7030
4.7UH-10.2A
2
R70111
9.31K
1% 1/16W MF-LF 402 2 1
OMIT
PPVBAT_G3H_CHGR_REG
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=12.6V CRITICAL
R7015
56.2K
93 93
1% 1/16W MF-LF 2 402
C7050
0.1uF
26 6 AGND
CHGR_VCOMP_R
22 PGND
LGATE (OD) TRKL* 20V/V AMON 32V/V BMON (OD) ACOK

OUT OUT OUT
46 61 46 43
FDA1254F-SM
C7040 1
CRITICAL
C7041
1000PF CRITICAL HAT1127H
LFPAK-SM 3 2
CRITICAL
4
Q7035
RJK0305DPB
LFPAK-HF
29
10% 50V CERM 2 402
PPVBAT_G3H_FET
R7016
3.01K
XW7000 SM
1 2
1% 1/16W MF-LF 402 2
Max Current = 8.5A (L7030 limit) f = 400 kHz
C7055 1
10% 25V X5R 2 603-1
1UF
10% 16V CERM 2 402
0.01uF
C7057 1
1 2 3
2 4
1 3
PPVBAT_G3H_CHGR_R
1 2 3
C7015 1
0.001UF
10% 2 16V X5R 402
R7050
0.01
0.5% 1W MF 0612
22UF
10% 2 25V X7R 402
CRITICAL
152S0542
HAT1127H LFPAK-SM
Q7055
Q7056
60
B
PPVBAT_G3H_CONN
R7056
5% MF-LF 402 1/16W
C7058
BATT_POS_GATE
2 1
1M
C7056
0.1UF
16V 2 X5R 402
0.1UF 10%
R7051
1
CHGR_VNEG_R
1
10
95 46
CHGR_CSO_R_P CHGR_CSO_R_N
10% 2 16V X5R 402
R7057
5% MF-LF 402 1/16W
C7016
470PF (CHGR_CSO_P) (CHGR_CSO_N) (PPVBAT_G3H_CHGR_R)
5% 1/16W MF-LF 402
R7052
1
10
330K
95 46
10% 2 50V CERM 402
5% 1/16W MF-LF 402
60 9
GND_BATT_CHGND
C7042
0.033UF
C7000 1
1UF
10% 10V 2 X5R 402
C7011
0.01UF
C7005 1
0.1UF
10% 25V X5R 2 402
C7026
0.001UF
10% 16V 2 X5R 402
10% 2 16V CERM 402
10% 2 50V CERM 402
GND_CHGR_AGND
PBus Supply & Battery Charger

A
M99 1. 2. 3. 4. 5. differences from last sync on 12/02/07 to T18 MLB: L7030 changed from T18 MLB inductor to 152S0542. Added Q7056, C7058,R7055,R7056.. U7000 Thermal Pad is now connected to GND, not through XW. Q7060 and Q7065 changed to 376S0667. Q7055 and Q7056 changed to 376S0666.

PART NUMBER
353S1811 353S1832
QTY
1 1
DESCRIPTION
IC,ISL6258,BAT CHARGER,28P,4X4,QFN,L IC,ISL6258A,BAT CHARGER,4X4MM,QFN28
REFERENCE DES
U7000 U7000
CRITICAL
CRITICAL CRITICAL
BOM OPTION
ISL6258 ISL6258A 2S Battery Default 3S Battery Default
APPLE INC.
D
SCALE NONE
051-7546
SHT OF
A.0.0
61
96
5% 1/16W MF-LF 2 402
330K
D
5 6 7 8
R7061
Q7060
Q7065
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm 1
CHGR_AGATE_DIV
CHGR_SGATE_DIV
MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm 1
1
C7070
0.1uF
R70701
57.6K
1% 1/16W MF-LF 402 2
R7074
1M
R7066
62K
5% 1/16W MF-LF 402 2
U7070
TL331
10% 16V 2 X5R 402 5 1
5% 1/16W MF-LF 2 402
CHGR_SGATE
SOT23-5 4
VCC GND
2 3
CHGR_AMON 46 61 R7075 clamps CHGR_AMON when charger is not powered to counter TL331 bias current. SGATE_P0V1_VREF
3 D 1
Q7074
SSM6N15FEAPE
SOT563 6 D
R7071
1.82K
Q7074
SSM6N15FEAPE
SOT563
1% 1/16W MF-LF 402 2
8
8
7
R7120
1
4
CRITICAL
3
These caps are for Q7100
CRITICAL
1
2
CRITICAL
1
These caps are for Q7102
=PPVIN_S5_CPU_IMVP
10
PPVIN_S5_IMVP6_VIN
C7108 1
1000PF
C7117 1
22UF
C7109
1UF
5
C7155 1
22UF
C7152 1
1000PF
10% 25V 2 X7R 402
C7153 1
22UF
C7154
1UF
1% 1/16W MF-LF 402

8
C7196
0.1UF
=PP5V_S0_CPU_IMVP
10% 16V 2 X5R 402
10% 25V 2 X7R 402
10% 2 25V X5R 603-1
10% 2 25V X5R 603-1
CRITICAL
R7112
1
10
PP5V_S0_IMVP6_VDD
D
8
1% 1/16W MF-LF 402
C7126
1UF
R7121
=PP3V3_S0_IMVP
1
10
10% 10V 2 X5R 402
PP3V3_S0_IMVP6_3V3
1
DPRSLPVR DPRSTP* 0 1 1 0 1 0 1 0
C7135
4.7UF
20% 6.3V 2 X5R-CERM 402
PSI* Operation Mode 1 2-Phase CCM 0 1-Phase CCM 1 1-Phase DCM 0 1-Phase DCM
5
Q7100
RJK0305DPB
LFPAK-HF
D
CRITICAL =PPVCORE_S0_CPU_REG
8
1 2 3
0.36UH-30A-1.05MOHM (IMVP6_PHASE1)
1 PCMC104T-SM 2
L7100
44A MAX CURRENT
13 12 11 10 8 6
=PP1V05_S0_CPU
1% 1/16W MF-LF 402
XW7103 SM
CRITICAL
1
62
XW7104 SM
2
62
C7156 1
1000PF
10% 25V X7R 2 402
R7199
68
C7130
0.1uF
R7197
10K
LFPAK-HF
R7119
87 21
R7104
1
IN
PM_DPRSLPVR
499
20
22
31
87 43 14 10
OUT
CPU_PROCHOT_L
1% 1/16W MF-LF 402
R7198
1
VIN
87 9 87 9 87 9 87 9 87 9 87 9
VDD
PVCC BOOT1
36
62 62
1 2 3
IN IN IN IN IN IN IN
LAYOUT NOTE: Place R7126 in hot spot of reg circuit.

1
40 39 38 37
ISL9504BCRZ
5% 1/16W MF-LF 402
(IMVP6_NTC)
CRITICAL
87 9
IMVP6_VID<6> IMVP6_VID<5> IMVP6_VID<4> IMVP6_VID<3> IMVP6_VID<2> IMVP6_VID<1> IMVP6_VID<0> CPU_DPRSTP_L IMVP_DPRSLPVR CPU_PSI_L IMVP6_IMON
43 42 41
VID6 VID5 VID4 VID3 VID2 VID1 VID0
U7100
QFN
BOOT2 26
35
IMVP6_BOOT1 IMVP6_BOOT2 IMVP6_UGATE1 IMVP6_PHASE1 IMVP6_LGATE1 (GND)
C7127
0.22UF
C7115
0.22UF
20% 603 1
R7100
1
C7103
0.22UF
1 2 10% 10V CERM 402
5% 1/16W MF-LF 2 402
20% 25V 2 X5R 603
10K
2 25V X5R
UGATE1
62
1% 1/16W MF-LF 402
PHASE1 34 LGATE1 32 PGND1

33
62
R7101
3.65K
62
R7126
470K
402
C7110 1
0.01uF
2 10% 16V CERM 2 402
87 14 10 9
IN
87
46 45 2 3
DPRSTP* DPRSLPVR PSI* IMON
1% 1/10W MF-LF 2 603
ISEN1 24
27
62
IMVP6_ISEN1 IMVP6_UGATE2 IMVP6_PHASE2 IMVP6_LGATE2 (GND)

5
(IMVP6_ISEN1)
10 46
IN OUT
(PGD_IN) (ISL9504A)
UGATE2
62
IMVP6_NTC_R
48
9 62 26
PHASE2 28 3V3 CLK_EN* VR_ON PGOOD VR_TT* ISEN2 NTC VSUM SOFT OCSET RBIAS
19 8 23
62
R71271
4.02K
OUT IN OUT
C7105
0.015UF
1 1
R7108
147K
1% 1/16W MF-LF 402 2
10% 16V X7R 2 402
1% 1/16W MF-LF 2 402
62
VR_PWRGD_CLKEN_L IMVP_VR_ON_R VR_PWRGOOD_DELAY IMVP6_VR_TT_L IMVP6_NTC (GND_IMVP6_SGND) IMVP6_SOFT IMVP6_RBIAS (GND_IMVP6_SGND) IMVP6_VDIFF IMVP6_FB2 IMVP6_FB IMVP6_COMP IMVP6_VW
47 44 1 5 6
LGATE2 30 PGND2 29
62
62
IMVP6_ISEN2 IMVP6_VSUM IMVP6_OCSET IMVP6_VO IMVP6_DROOP IMVP6_DFB

4
Q7102
LFPAK-HF
CRITICAL
7 4
RJK0305DPB CRITICAL
1 2 3
62
62
VO 18 DROOP
16
OUT OUT
62 62
NO STUFF
62
13
VDIFF DFB
17
62
R7117
1
C7116 1
0.001uF
10% 50V CERM 2 402 5
C7106
0.001UF
R7113
1K
62 62 62 62
12 11 10 9
3.92K2
1% 1/16W MF-LF 402
0.36UH-30A-1.05MOHM (IMVP6_PHASE2)
1 PCMC104T-SM 2
L7101
FB2 FB COMP VW VSEN 14 RTN

15
10% 50V 2 CERM 402
IMVP6_VDIFF_RC
1% 1/16W MF-LF 402 2
C7131
0.01UF
GND
21
R7118
1K
C7129
180pF
R7116
13.3K
4
XW7101 SM Q7103
LFPAK-HF
XW7102 SM
2
62
C7157 1
1000PF
10% 25V 2 X7R 402
25
NC TPAD
49
R7111
255
R7109
1K GND_IMVP6_SGND
10% 16V CERM 2 402
1% 1/16W MF-LF 2 402
5% 2 50V CERM 402
1% 1/16W MF-LF 2 402
CRITICAL
62
IMVP6_VSUM2
IMVP6_VO2
RJK0328DPB
1
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 2 402
SIGNAL_MODEL=EMPTY
(IMVP6_VO)
1
R7107
1
(IMVP6_FB)
C7134
0.068UF
10% 402
R7115
11K
R7130
2.61K
1 2 3
C7114
470PF
C7113 1
220PF
10% 50V X7R-CERM 2 402
2 10V CERM
1% 1/16W MF-LF 2 402
1% 1/16W MF-LF 402 2
R7105
1
C7104
0.22UF
1 2 10% 10V CERM 402
5% 1/16W MF-LF 2 402
10K
10% 2 50V CERM 402
IMVP6_VO_R
1
1% 1/16W MF-LF 402
IMVP6_COMP_RC
(IMVP6_VW)
CRITICAL
1
R7106
3.65K
R71141
97.6K
1% 1/16W MF-LF 402 2
0.001UF
C7107
R7110
6.81K
C7128 1
10% 6.3V CERM-X5R 2 402
R7131
10KOHM-5%
0603-LF 2
0.22UF
1% 1/10W MF-LF 2 603
10% 50V CERM 2 402
1% 1/16W MF-LF 2 402
(IMVP6_ISEN2) (IMVP6_VSUM)
(IMVP6_COMP)
Place R7131 Between L7100,L7101 and CPU
(IMVP6_VO)
R7122
87 62
IMVP6_VSEN_P
CPU_VCCSENSE_P
IN
11 87
87 62
IMVP6_VSEN_N NO STUFF
5% 1/16W MF-LF 402
R7123
1
CPU_VCCSENSE_N
IN
11 87
C7121 R7160
42
C7133
0.01uF
C7132
0.01uF
0.22UF IMVP_VR_ON_R
62
5% 1/16W MF-LF 402
IMVP_VR_ON
XW7100 SM
1 2
20% 6.3V 2 X5R 402
10% 16V CERM 2 402
10% 2 16V CERM 402
62
IMVP6_OCSET IMVP6_VO IMVP6_DROOP IMVP6_DFB IMVP6_SOFT IMVP6_RBIAS IMVP6_VDIFF IMVP6_FB2 IMVP6_FB IMVP6_COMP IMVP6_VW
5% 1/16W MF-LF 402
IMVP6 CPU VCore Regulator

MIN_LINE_WIDTH=0.25 MM MIN_LINE_WIDTH=0.25 MIN_LINE_WIDTH=0.25 MIN_LINE_WIDTH=0.25 MIN_LINE_WIDTH=0.25 MIN_LINE_WIDTH=0.25 MIN_LINE_WIDTH=0.25 MIN_LINE_WIDTH=0.25 MIN_LINE_WIDTH=0.25 MIN_LINE_WIDTH=0.25 MIN_LINE_WIDTH=0.25 MM MM MM MM MM MM MM MM MM MM
MIN_NECK_WIDTH=0.20 MM MIN_NECK_WIDTH=0.20 MIN_NECK_WIDTH=0.20 MIN_NECK_WIDTH=0.20 MIN_NECK_WIDTH=0.20 MIN_NECK_WIDTH=0.20 MIN_NECK_WIDTH=0.20 MIN_NECK_WIDTH=0.20 MIN_NECK_WIDTH=0.20 MIN_NECK_WIDTH=0.20 MIN_NECK_WIDTH=0.20 MM MM MM MM MM MM MM MM MM MM

62 62 62 62 62 62 62 62 62 62
62 62 62 62 62 62 62 87 62
IMVP6_PHASE1 IMVP6_BOOT1 IMVP6_UGATE1 IMVP6_LGATE1 IMVP6_ISEN1 IMVP6_VSUM1 IMVP6_VO1 IMVP6_VSEN_P
MIN_LINE_WIDTH=1.5 MM MIN_LINE_WIDTH=0.25 MM MIN_LINE_WIDTH=0.5 MM MIN_LINE_WIDTH=0.5 MM MIN_LINE_WIDTH=0.25 MM MIN_LINE_WIDTH=0.25 MM MIN_LINE_WIDTH=0.25 MM MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM
62 62 62 62 62 62 62
I849
87 62
IMVP6_PHASE2 IMVP6_BOOT2 IMVP6_UGATE2 IMVP6_LGATE2 IMVP6_ISEN2 IMVP6_VSUM2 IMVP6_VO2 IMVP6_VSEN_N
MIN_LINE_WIDTH=1.5 MM MIN_LINE_WIDTH=0.25 MM MIN_LINE_WIDTH=0.5 MM MIN_LINE_WIDTH=0.5 MM MIN_LINE_WIDTH=0.25 MM MIN_LINE_WIDTH=0.25 MM MIN_LINE_WIDTH=0.25 MM MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.2 MM MIN_NECK_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM
D
APPLE INC.
I848
051-7546
SHT NONE OF
A.0.0
SCALE
62
96
5% 1/16W MF-LF 2 402
10% 16V 2 X5R 402
5% 1/16W MF-LF 2 402
Q7101
RJK0328DPB
IMVP6_VSUM1
IMVP6_VO1
=PPVIN_S5_P5VP3V3
CRITICAL
R7264
CRITICAL
2
1
C7280
P3V3S5_VBST_R
22UF
20% 25V POLY-TANT CASE-D2-SM
C7240
22UF
20% 25V POLY-TANT CASE-D2-SM
C7241
1UF
10% 25V X5R 603-1
P5VP3V3_VREG5 P5VP3V3_VREG3
5% 1/16W MF-LF 402
C7281
1UF
10% 25V X5R 603-1
R7224
2 P5VS5_VBST_R
P5VP3V3_VREF
5
1
16
CRITICAL
C7224
0.1UF
10% 50V X7R 603-1
5% 1/16W MF-LF 402
C7200
1UF
10% 25V X5R 603-1
C7203
10UF
20% 6.3V X5R 603
C7205
10UF
20% 6.3V X5R 603
C7264
0.1UF
10% 50V X7R 603-1
CRITICAL
2
f=365KHz
Q7220
RJK0305DPB
8
=PP5V_S3_REG
LFPAK-HF
VIN 14 SKIPSEL 4 TONSEL
VREF VREG3 8 VREG5 17
C7201
0.22UF
10% 10V CERM 402
Q7260
FDMS9600S
MLP
1 9 4 3 2
f=460KHz
=PP3V3_S5_REG
8
Vout = 5.0V 6A max output (Q7220 limit)

1
CRITICAL
P5VS5_VBST 3 2 1
2
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
22 VBST1
U7201 QFN
Vout = 3.3V
CRITICAL
VBST2 9 DRVH2 10 LL2 11 DRVL2 12 VO2 7 VFB2 5 ENTRIP2 6 VCLK 18
P3V3S5_VBST P3V3S5_DRVH
GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm
L7220
2.2UH-14A
IHLP2525CZ-SM1
P5VS5_DRVH
GATE_NODE=TRUE
21 DRVH1 TPS51125 20 LL1 19 DRVL1 24 VO1 2 VFB1 1 ENTRIP1
L7260
4.7UH-5.5A Q1
10 1 IHLP2525CZ
1
5.5A max output (L7260 limit)

2
P5VS5_LL
SWITCH_NODE=TRUE
P3V3S5_LL
SWITCH_NODE=TRUE
CRITICAL
SW
8
C7252
330UF
C7250
10UF
20% 10V X5R 805
NO STUFF 1
P5VS5_DRVL
GATE_NODE=TRUE
P3V3S5_DRVL
GATE_NODE=TRUE
NO STUFF 1
CRITICAL
R7262
10
R7222
10
C7290
10UF
20% 6.3V X5R 603
C7292
150UF
20% 6.3V 2 POLY-TANT CASE-D3L-SM1
CRITICAL
(P5VS5_VO1)
P5VS5_VFB P5VS5_ENTRIP
(P3V3S5_V02)
P3V3S5_VFB P3V3S5_ENTRIP
5% 1/16W MF-LF 402 2
Q7225
RJK0301DPB
LFPAK-HF P5VS5_RC
Q2
5% 1/16W MF-LF 402 2
P3V3S5_RC NO STUFF1
7 6 5
NO STUFF1
C7222
100PF
5% 50V CERM 402
C7262
100PF
5% 50V CERM 402
3 2 1
2
PGOOD 23
R7200
75K 15 25
1% 1/16W MF-LF 402
XW7220
SM 1
EN0 13 GND THRM_PAD

1
NO STUFF
XW7260
SM 1
C7208
220PF
5% 25V CERM 402
R7206
75K
1% 1/16W MF-LF 402
PLACEMENT_NOTE=Place XW7260 next to L7260.
PLACEMENT_NOTE=Place XW7220 next to L7220.
PP5V_S5_REG_XW
PATH=I623 1
PLACEMENT_NOTE=Place XW7200 next to U7200 pin 15.
PP3V3_S5_REG_XW PATH=I621 1
R7220
15K GND_P5VP3V3_SGND
XW7200
SM 1 2
R7260
6.49K
1% 1/16W MF-LF
5% 1/16W MF-LF 2 402
2 402
B
1
R7221
10K
1% 1/16W MF-LF
68
R7261
10K
1% 1/16W MF-LF
One master PGOOD for both 5V and 3V3

OUT
P5V3V3_PGOOD
2 402
2 402
Q7210
SSM6N15FEAPE
SOT563
68 8
D 6
=PP3V42_G3H_PWRCTL
2
1
S 1
R7210
10K
5% 1/16W MF-LF 402
Q7211
SSM6N15FEAPE
SOT563
D 3
2
TABLE_ALT_HEAD
P5VS3_EN_L
S 4
PART NUMBER
ALTERNATE FOR PART NUMBER

376S0668 376S0669
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_ITEM
Q7210
SSM6N15FEAPE
SOT563
D 3
P3V3S5_EN_L
376S0651 376S0652
ALL ALL
FET FDM8678S alternate to Si7108

TABLE_ALT_ITEM
FET FDM8676 alternate to Si7110

TABLE_ALT_ITEM
68
152S0778
152S0693
ALL
4.7uH inductor Cyntec a;ternate to MagLayers
S 4
68
=P5VS3_EN
M99 1. 2. 3. 4.
differences from last sync on 11/01/07 to M88 MLB: L7260 changed from M88 MLB inductors to 152S0693. Q7220 changed to 372S0512. Q7225 changed to 376S0511. U7200 changed to 353S2087. Added R7200, R7220,R7221, R7260,R7261, C7201.
5V / 3.3V Power Supply


SIZE
DRAWING NUMBER
REV.
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
63
96
=PPVIN_S0_DDRREG_LDO
C7355
10UF
=PPVIN_S3_DDRREG CRITICAL CRITICAL

1
20% 2 6.3V X5R 603

8
C7330 1
22UF
C7331 1
22UF
C7332
1UF
C7333
1000PF
=PP5V_S3_DDRREG
R7305
1
4.7
PP5V_S3_DDRREG_V5FILT
10% 2 25V X5R 603-1
10% 2 25V X7R 402
5% 1/16W MF-LF 402
15
14
4.7UF
20% 6.3V 2 CERM 603
1UF
10% 10V 2 X5R 402
23
C7300
C7305
CRITICAL DDRREG_VDDQSNS (DDRREG_DRVH)

4
Q7330
RJK0305DPB
LFPAK-HF
V5IN 6 COMP
V5FILT
VLDOIN VDDQSNS 8
R73101
1% 1/16W MF-LF 402 2
C
69 9 68 68
10K
CRITICAL
IN IN OUT
CRITICAL
=DDRVTT_EN =DDRREG_EN DDRREG_PGOOD 10mA max load Vout = VDDQSNS/2
10 S3 VTT Enable 11 S5 VDDQ/VTTREF Enable 13 PGOOD VDDQ PGOOD
MODE 4 VBST 22 DRVH 21 LL 20 DRVL 19
C7325
0.1UF (DDRREG_VBST)
1 2
1 2 3
1.0UH-13A-5.6MOHM
1 PCMB065T-SM 2
L7330
C
CRITICAL
1
U7300
QFN
DDRREG_VBST DDRREG_DRVH
GATE_NODE=TRUE
27 8
=PPVTT_S3_DDR_BUF =PPVTT_S0_DDR_LDO
MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.2 mm
TPS51116
5 VTTREF 24 VTT SYM (2 OF 2)
10% 50V X7R 603-1
C7340
330UF
DDRREG_LL
SWITCH_NODE=TRUE
(DDRREG_LL)
XW7360Vout SM
1 2
= VTTREF
2 VTTSNS
CRITICAL
4
DDRREG_DRVL
GATE_NODE=TRUE
(DDRREG_DRVL)
Q7335
RJK0301DPB
LFPAK-HF
20% 2 2.5V POLY-TANT CASE-C2-SM
=PPDDR_S3_REG 8 Vout = 1.50V or 1.80V 15A max output (Q7335 limit) f = 400 kHz
DDRREG_VTTSNS
NC NC
CRITICAL
C7341 1
20% 2.5V POLY-TANT 2 CASE-C2-SM
C7345
10UF
CS 16 VDDQSET 9 THRM_PAD GND 25 3 PGND CS_GND
DDRREG_CS DDRREG_FB
1 2 3 PLACEMENT_NOTE=Place next to Q7335
330UF
C7346
1000PF
CRITICAL
CRITICAL
1
C7360
22UF
C7361
22UF
7 NC0 12 NC1 VTTGND 1
20% 2 6.3V X5R 603
10% 2 25V X7R 402
XW7345 SM
PLACEMENT_NOTE=Place next to C7345
1
18
17
20% 6.3V X5R-CERM 2 603
20% 2 6.3V X5R-CERM 603
XW7335 SM
1 2
DDRREG_CSGND
(DDRREG_CSGND)
NO STUFF
C7320 1
100PF
5% 50V CERM 2 402
R7320
15.0K
(DDRREG_VDDQSNS)
1% 1/16W MF-LF 2 402
0.033UF
C7350 1
10% 16V 2 X5R 402
XW7300 SM
1
(DDRREG_FB)
<Ra>
R7321
15.0K
Vout = 0.75V * (1 + Ra / Rb)
B
GND_DDRREG_SGND
1% 1/16W MF-LF 2 402
<Rb>
1.5V DDR3 Supply
SYNC_MASTER=M99_MLB

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
64
96
=PPVIN_S0_P5VRTS0_MCPCORE CRITICAL
C7510 1
20% 25V POLY-TANT 2 CASE-D2-SM
C7511
1UF Q7510
22UF
D
G
4
10% 2 25V CRITICAL X5R 603-1

SI7110DN
PWRPK-1212-8-HF
S
3 2 1
(P5VRTS0_UGATE)
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM GATE_NODE=TRUE
5
CRITICAL
R75001
5% 1/16W MF-LF 402 2
C7501 1
10% 10V 2 X5R 402-1
C7563
1000PF
5
4.7
1UF
C7560 1
C7561
1UF
CRITICAL
Q7511
SI7108DN
PWRPK-1212-8-HF

G
4
CRITICAL (MCPCORES0_UGATE) 4
(P5VRTS0_LGATE)
PVIN_P5VRTS0_MCPCORE
PP3V3_S0_MCP_VREF
Q7560
RJK0305DPB
LFPAK-HF
19
S
3 2 1
C7500 1
3 10% 25V 2 X5R 805 6 17 15 16 18 10 14 9 11 12 29 4 20 2 5
C7504 1
PVCC VCC VREF3 LDO LDOREFIN VIN BOOT1 CRITICAL BOOT2 UGATE1 UGATE2 PHASE1 ISL6236 PHASE2 LGATE2 LGATE1 QFN OUT1 OUT2 EN1 EN2 BYP FB1 REFIN2 ILIM1 ILIM2 SKIP* EN_LDO REF SECFB POK1 TON POK2 7 8 24 26 25 23 30 27 32 31 1 13 28 10% 10V 2 X5R 402-1
C7503 1
Max load 100mA PP5V_S0_MCPREG_LDO VOLTAGE=5V (SGND) MCPCORES0_BOOT MCPCORES0_UGATE MCPCORES0_PHASE MCPCORES0_LGATE (=PPMCPCORE_S0_REG) MCPCORES0_REFIN MCPCORES0_ILIM PP2V_S0_MCPREG_REF
VOLTAGE=2V 10% 10V 2 X5R 402-1
C7502
4.7UF
10UF
1UF
1UF
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE
(P5VRTS0_BOOT)
1
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM CRITICAL

8
20% 2 6.3V X5R-CERM 402
C7514
0.22UF P5VRTS0_BOOT P5VRTS0_UGATE P5VRTS0_PHASE P5VRTS0_LGATE (=P5V_RTS0_EN)
C7564 1
5% 10V CERM-X7R 2 603
1 2 3
0.22UF
CRITICAL 0.6UH-30A-1.5MOHM
1 MPL104-SM 2 PPMCPCORE_ISENSE
R5425
0.001
1% 1W MF 1206
=PP5V_RT_REG
1
L7510
2.2UH-14A
2 IHLP2525CZ-SM1
Vout = 5.03V 5A max output (Q7510 limit?) f = 400 kHz

CRITICAL
10% 2 16V X7R 603
L7560
Vout = See below

=PPMCPCORE_S0_REG
8
U7500
(P5VRTS0_PHASE)
(MCPCORES0_PHASE)
MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM SWITCH_NODE=TRUE 5
1 3
2 4
(=PP5V_RTS0_REG)
1
95 47
C7516
10UF
20% 10V X5R 805
CRITICAL
4 (MCPCORES0_LGATE) MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM GATE_NODE=TRUE
MCPCOREISNS_P MCPCOREISNS_N 95 47
C7566
10UF
XW7516 SM
1 PLACEMENT_NOTE=Place next to C7516
P5V_RTS0_FB P5V_RTS0_ILIM
Q7565
RJK0328DPB
LFPAK-HF 1
20% 4V X5R 2 603
Max Current: 25A? (Q7560 Limit) f = 300 kHz

CRITICAL
1
C7565
330UF
CRITICAL
1
C7515
330UF
C7567
10UF
C7568
330UF
P5VRTS0_VSNS NO STUFF 1
20% 6.3V 2 POLY-TANT CASE-D3L-SM1
Max load 50uA
MCP_PROD
R7520
61.9K
NO STUFF
C7520 1
100PF
5% 50V CERM 2 402
R75701
48.7K
1 2 3
20% 2 4V X5R 603
THRM_PAD GND 33 21
PGND 22
1% 1/16W MF-LF 2 402
<Ra>
R7521
0
<Ra>
MCP_PROD MCP_PROD
1
0.1% 1/16W MF 402 2
C7569
1000PF
10% 402
2 25V X7R
MCP_PROD
1
MCP_PROD
1
R7514
100K
XW7500 SM
1 2
C7530
0.1UF
R75641
100K
1% 1/16W MF-LF 402 2
R75711
54.9K
5% 1/16W MF-LF 2 402
<Rb>
1% 1/16W MF-LF 2 402
20% 2 10V CERM 402
GND_MCPREG_SGND
<Rb>
0.1% 1/16W MF 402 2
1 C7590 R7580 475K
R7581
237K
R7582
110K
0.01UF
10% 16V 2 CERM 402
0.1% 1/16W MF 2 402
<Rc>
D 3
<Rd>
0.1% 1/16W MF 2 402
0.1% 1/16W MF 2 402
<Re>
MCP_VID2_L
MCP_VID0_L
MCP_VID1_L
Vout = 0.7V * (1 + Ra / Rb)

68 68 68
IN OUT OUT IN
68
=P5V_RTS0_EN MCPCORES0_PGOOD P5V_RTS0_PGOOD =MCPCORES0_EN
Vout = 2.0V * Req / (Ra + Req) Req = Rb || Rc || Rd || Re
Q7580
SSM6N15FEAPE
SOT563
Q7580
SSM6N15FEAPE
SOT563
D 6
Q7582
SSM6N15FEAPE
SOT563
D 3
5 G
S 4
2 G
S 1
5 G
S 4
21 21 21
IN IN IN
MCP_VID<0> MCP_VID<1> MCP_VID<2>
MCP79 Rev A01 requires higher core & analog voltage
PART NUMBER
114S0382 114S0400 114S0482 114S0453 114S0422 114S0373 114S0404
QTY
1 1 1 1 1 1 1 1 1 1
DESCRIPTION
RES,MTL FILM,1/16W,48.7K,1,0402,SMD,LF RES,MTL FILM,1/16W,76.8K,1,0402,SMD,LF RES,MTL FILM,1/16W,523K,1,0402,SMD,LF RES,MTL FILM,1/16W,267K,1,0402,SMD,LF RES,MTL FILM,1/16W,130K,1,0402,SMD,LF RES,MTL FILM,1/16W,40.2K,1,0402,SMD,LF RES,MTL FILM,1/16W,84.5K,1,0402,SMD,LF RES,MTL FILM,1/16W,301K,1,0402,SMD,LF RES,MTL FILM,1/16W,237K,1,0402,SMD,LF RES,MTL FILM,1/16W,100K,1,0402,SMD,LF
REFERENCE DES
R7570 R7571 R7580 R7581 R7582 R7570 R7571 R7580 R7581 R7582
CRITICAL
BOM OPTION
MCP_A01 MCP_A01 MCP_A01 MCP_A01 MCP_A01 MCP_A01Q MCP_A01Q MCP_A01Q MCP_A01Q MCP_A01Q
VID<2:0> 000 001 010 011 100 101 110 111
Rev A01 Voltage +1.224V +1.159V +1.101V +1.049V +0.995V +0.952V +0.913V +0.876V
Production Voltage MCP Target +1.060V +0.994V +0.937V +0.885V +0.830V +0.789V +0.752V +0.719V +1.05V +1.00V +0.95V +0.90V +0.85V +0.80V +0.75V +0.70V
1.05V / MCP Core Regulator

114S0458 114S0447 114S0411

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
65
96
(Internal 10-ohm path from PVCC to VCC) PP5V_S0_MCPREG_VCC
10% 25V 2 X7R 402
22UF
10% 2 25V X5R 603-1
=PPVIN_S0_CPUVTTS0 CRITICAL
C7690 1
C7695
1UF CRITICAL
22UF
10% 2 25V X5R 603-1
Q7660
FDMS9600S
MLP
1
9 4 3 2
=PP5V_S0_CPUVTTS0
R7601
1
CRITICAL PP5V_S0_CPUVTTS0_V5FILT
10 4 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V
R5435
0.002
1% 1/4W MF 1206
200
1% 1/16W MF-LF 402
R7679
1
2.2UH-14A
Q1 8 10 SW 1 2
L7660
=PPCPUVTT_S0_REG
2 4 1
C7601 1
2.2UF
10% 16V 2 X5R 603
C7600
1UF
165K
1% 1/16W MF-LF 402 2
PPCPUFSB_ISNS
IHLP2525CZ-SM1
1 3
C
68
V5FILT
V5DRV
CRITICAL
U7600
TPS51117RGY_QFN14 SYM (2 OF 2)
1 EN_PSV 6 PGOOD 3 VOUT 5 VFB 11 TRIP GND 7 THRM_PAD 15 8 QFN TON 2 VBST 14 DRVH 13 LL 12 DRVL 9 PGND
10% 2 10V X5R 402
C7665
10UF
IN OUT
=CPUVTTS0_EN CPUVTTS0_PGOOD (=PPCPUVTT_S0_REG) CPUVTTS0_VFB CPUVTTS0_TRIP
CPUVTTS0_TON CPUVTTS0_VBST CPUVTTS0_DRVH

GATE_NODE=TRUE
C7680
0.1UF
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
Q2
1
20% 6.3V 2 X5R 603

95 47
1V05CPU_P CRITICAL 1V05CPU_N

2
68
10% 50V X7R 2 603-1
7 6 5
95 47
C7660 1
330UF
CPUVTTS0_LL
SWITCH_NODE=TRUE
XW7665 SM
1
20% 2.0V 2 POLY-TANT B2-SM
CPUVTTS0_DRVL
GATE_NODE=TRUE
CPUVTTS0_VSNS
1
R7670
8.06K
NO STUFF
PLACEMENT_NOTE=Place XW7665 next to C7665
C7670 1
100PF
5% 50V CERM 2 402
R7685
6.34K
1% 1/16W MF-LF 2 402
XW7600 SM
1 2
1% 1/16W MF-LF 2 402
<Ra>
R7671
20.0K
(GND)
1
1% 1/16W MF-LF 2 402
GND_CPUVTTS0_SGND
<Rb>
(CPUVTTS0_VFB) (=PPCPUVTT_S0_REG)
Vout = 0.75V * (1 + Ra / Rb)
CPU VTT Power Supply
A
M99 differences from last sync on 12/03/07 to T18 MLB: 1. Tied THERMAL_PAD to PGND. GND and THERMAL_PAD disconnected.
SYNC_MASTER=M99_MLB

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
66
96
1.8V S0 Switcher / 1.0VFW SWITCHER

S5 power required for output discharge feature
D
8
D
=PP3V3_S3_P1V8S0
C7700
2.2UF
CRITICAL
L7780
2.2UH =PP1V0_FW_REG
2 CPL2512-SM
8
20% 6.3V CERM 2 402-LF
P1V0FW_SW
C7782 1
10PF
VIN 5% 50V CERM 2 402 3
1% 1/16W MF-LF 2 402
187K
U7700 DFN-HF
LTC3547
1 VFB1 8 VFB2
P1V0FW_VFB
1
CRITICAL
SW1 4 SW2 6
<Rb> R7783
280K
20% 2 4V X5R 402
4.7UF
RUN1 2 RUN2 7
CRITICAL
THRML PAD 9
L7700
2.2UH P1V8S0_LX
1 CPL2512-SM 2
1% 1/16W MF-LF 2 402
GND 5
=PP1V8_S0_REG
C7701 1
10PF
5% 50V CERM 2 402
<Ra>
1
C
P1V8S0_VFB =P1V8S0_EN
8
R7700
562K
1
1% 1/16W MF-LF 2 402
Vout = 1.816V 0.3A max output (Switcher limit) f = 1.6 MHz C7705
4.7UF
1.8V S0 Switcher
INPUT RAIL IS 3.3V S0
8
C
=PP3V3_GPU_P1V8S0 C7760
10uF
20% 6.3V X5R 603 2 1
<Rb>
1
68
R7701
280K
IN
20% 4V 2 X5R 402
CRITICAL
=PP3V3_FW_P1V0FW
1% 1/16W MF-LF 2 402
VI
CRITICAL 10UH-0.55A-330MOHM PCAA031B-SM MAX CURRENT = 300MA

P1V8GPU_SW
1 2
U7760
TPS62202
4 3
L7760
Vout = 0.6V * (1 + Ra/Rb)
83 82 68
=P1V8FB_EN
FB EN
SOT23-5
SW 5 GND
2
=PP1V8_GPUIFPX_REG
C7762
10uF
20% 6.3V X5R 603
67 8
=PPVIN_S0_P1V05S5
5
MCP 1.05V AUXC Supply

R7751
P5V_P1V05S5_V5FILT P1V05S5_ISEN P5V_P1V05S5
C7775
1UF
D
10% 2 25V X5R 603-1

4
G
CRITICAL
Q7770
SI7110DN
PWRPK-1212-8-HF
CRITICAL 1.5UH-6.0A
1 2 PCMB053T
2 3
L7770
B
67 8
4.7
=PPVIN_S0_P1V05S5
1
C7752
1UF
5% 1/16W MF-LF 402
C7751
2.2UF
12 PVCC
2 VCC
R77791
1
=PP1V05_S5_MCP
C7750
2.2UF P1V05S5_DRVH
2.43K
1% 1/16W MF-LF 402 2
10% 2 25V X5R 603-1
10% 16V 2 X5R 603 1 VIN 7 FSET 4 3 16 5
ISL6269
QFN UG 14
U7750
10% 2 16V X5R 603
CRITICAL
Q7771
SI7108DN
PWRPK-1212-8-HF
XW7775 SM
1
C7776
4.7UF CRITICAL
GATE_NODE=TRUE
P1V05_S5_FSET
1
G S
20% 2 4V X5R 402
Vout = 1.052V 5A max output (L7770 limit) f = 400 kHz
R7752
38.3K P1V05_S5_COMP
C7770 1
68
C7771 1
330UF
20% 2.0V 2 POLY-TANT B2-SM
IN
=P1V05S5_EN P1V05_S5_PGOOD P1V05S5_VFB
C7753 1
0.01UF
10% 16V CERM 2 402
1% 1/16W MF-LF 2 402
68
OUT
EN FCCM PGOOD COMP
BOOT 13 PHASE 15 ISEN 9 LG 11
P1V05S5_VBST P1V05S5_LL
SWITCH_NODE=TRUE
0.1UF
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
2 3
10% 25V X5R 2 402
P1V05S5_DRVL
GATE_NODE=TRUE MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM 1
6 FB 8 VO THRML PAD 17
P1V05S5_VSNS
PGND 10
R7753 C7755 33PF

49.9K
<Ra> R7780
3.74K
1% 1/16W MF-LF 2 402
5% 50V CERM 2 402
1% 1/16W MF-LF 2 402
P1V05S5_COMP_R
(GND)
2
C7754 1
470PF
<Rb> R7781
4.42K
10% 50V CERM 2 402
XW7750 SM
1
1% 1/16W MF-LF 2 402
Misc Power Supplies

GND_P1V05S5_SGND
(P1V05S5_VFB) (=PP1V05_S5_REG)
Vout = 0.6V * (1 + Ra / Rb)
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
67
96
<Ra> 1 R7782
Vout = 1.001V 300mA max output (Switcher limit) f = 2.25 MHz 1 C7785
8
R7802
68 63 8
7
3.3V 1,05V S5 ENABLE
6
State Run (S0)
5
SMC_PM_G2_ENABLE PM_SLP_S4_L PM_SLP_S3_L
4
1 1 0 0 1 0 0 0
43 42 40 21
3
3.3V,5V S3 ENABLE
IN
1 1 1 0
=PP3V42_G3H_PWRCTL
100K
5% 1/16W MF-LF 402
P3V3S5_EN_L
Sleep (S3)
OUT
63
PM_SLP_S4_L
MAKE_BASE=TRUE
(PM_S4_STATE_L)
1
=P3V3S3_EN
OUT
69
Soft-Off (S5)
NO STUFF
1
R7810
100K
C7802
0.068UF
10% 10V CERM 402
PLACEMENT_NOTE=near U7201
Battery Off (G3Hot)
Q7800
SSM3K15FV
SOD-VESM-HF
42
D 3
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 402
5.1K
5% 1/16W MF-LF 402

IN
SMC_PM_G2_EN
68 63 8
S5 rail PWRGD
=PP3V42_G3H_PWRCTL =PP3V3_S5_PWRCTL
68 8
R7811
R7812
P5VS3_EN
MAKE_BASE=TRUE
=P5VS3_EN
OUT
63
R78581
100K
5% 1/16W MF-LF 402
1 G
S 2
DDRREG_EN
=DDRREG_EN
C7840
1 1 2
R7801
2
2
0.1uF PM_G2_P1V05S5_EN
MAKE_BASE=TRUE 1
NO STUFF
MAKE_BASE=TRUE
OUT
64
5.1K
5% 1/16W MF-LF 402
=P1V05S5_EN
OUT
67
20% 10V CERM 402
R7840 100K
5% 1/16W MF-LF 402
C7810
0.47UF
10% 6.3V CERM-X5R 402
C7812
0.47UF
10% 6.3V CERM-X5R 402
C7801
0.47UF
10% 6.3V CERM-X5R 402
VDD
5
CT
SENSE CT
U7840
SOT23-6
RESET* MR*
1 3
RSMRST_PWRGD P1V05_S5_PGOOD
42
TPS3808G33DBVRG4
0.001UF
20% 50V CERM 402
C7841 1
GND
TPS3808 MR* HAS INTERNAL PULLUP
Other S0 RAILS
S0 ENABLE
68 8
IG EG
PM_ALL_GFX_PGOOD high PM_ALL_GPU_PGOOD
=PP3V3_S0_PWRCTL
(PM_SLP_S3_L)
PM_SLP_S3_L_R
MAKE_BASE=TRUE 2
=P5V_RTS0_EN
OUT OUT OUT
65
R7878
PM_SLP_S3_L
83 81 44 42 37 34 21 7
IN
22K
1 5% 1/16W MF-LF 402 1
33K
5% 1/16W MF-LF 402 1
0
5% 1/16W MF-LF 402 1
10K
5% 1/16W MF-LF 402 1
5% 1/16W MF-LF 402
R7879
100K
PLACEMENT_NOTE=nearU9900 PLACEMENT_NOTE=nearU7951 PLACEMENT_NOTE=nearQ7971 PLACEMENT_NOTE=nearU7500 PLACEMENT_NOTE=nearU9900 PLACEMENT_NOTE=nearU7700 PLACEMENT_NOTE=nearU7600
5% 1/16W MF-LF 402 2

P1V8S0_EN
MAKE_BASE=TRUE
MCPDDR_EN
MAKE_BASE=TRUE
CPUVTTS0_EN
MAKE_BASE=TRUE
MCPCORES0_EN
MAKE_BASE=TRUE
NO STUFF
1
Unused PGOOD signal

TP_DDRREG_PGOOD
MAKE_BASE=TRUE
C7880 C7881
1
C7882
0.47UF
10% 6.3V CERM-X5R 402
C7883
0.47UF
10% 6.3V CERM-X5R 402
1 C7884
0.47UF
0.47UF
2
64
0.47UF
2
10% 6.3V CERM-X5R 402
DDRREG_PGOOD
10% 6.3V CERM-X5R 402
PLACEMENT_NOTE=nearU7500 PLACEMENT_NOTE=nearQ7971 PLACEMENT_NOTE=nearU7951 PLACEMENT_NOTE=nearU9900 PLACEMENT_NOTE=nearQ7600 PLACEMENT_NOTE=nearU7700 PLACEMENT_NOTE=nearU9900
EG_PWRSEQ_HW
1.1V GPU ENABLE Graphic MEM ENABLE

P1V1_GPU_EN_RC
1
R7851
68 8
=PP3V3_S0_PWRCTL
10K
5% 1/16W
EG_PWRSEQ_HW
EG_PWRSEQ_HW
R7852
0
5% 1/16W MF-LF 402
68 8
EG_PWRSEQ_HW R7868
=PP3V3_GPU_PWRCTL
1
R7850
68 8
MF-LF
402
100K
P1V8_S0GPU_EN_RC
2
=PP3V3_S5_PWRCTL
100K
5% 1/16W MF-LF 402
EG_PWRSEQ_HW
Q7850
SSM6N15FEAPE
SOT563
D 3
5% MF-LF 1/16W 402
P1V1_GPU_EN
MAKE_BASE=TRUE 1
C7850
20% 16V CERM 402
NO STUFF
0.022UF
EG_PWRSEQ_HW
Q7861
SSM6N15FEAPE
SOT563
D 3
NO STUFF
S 4
2
C7869
0.022UF
20% 16V CERM 402
EG_PWRSEQ_HW
83
U7870
1
8
IN
EXTGPU_PWR_EN
Q7850
SSM6N15FEAPE
SOT563
D 6
LTC2909
SEL ADJ1 ADJ2 REF GND THRM_PAD
=P1V1GPU_EN OUT
82 83
78
GPUVCORE_PGOOD
R78531
100K
5% 1/16W MF-LF 402 2
GPU_S0_EN_L
MAKE_BASE=TRUE 2
GPUVCORE_EN_RC_L
68
S 1
8
GPUVCORE ENABLE
EG_PWRSEQ_HW R7863
68 8
=PP3V3_GPU_PWRCTL
100K
EG_PWRSEQ_HW R7864
0
1 5% 1/16W MF-LF 402
GPUVCORE_EN_RC
1
GPUVCORE_EN
2 MAKE_BASE=TRUE
=GPUVCORE_EN
OUT
78 83
5% 1/16W 402 MF-LF
=PP3V3_S0_PWRCTL
68 8 68 8
EG_PWRSEQ_HW
Q7861
SSM6N15FEAPE
SOT563
D 6
EG_PWRSEQ_HW 1
C7861
0.01UF
10% 16V CERM 402 PLACEMENT_NOTE=near U8900
R7889
100K
5% 1/16W MF-LF 402 2

68
GPUVCORE_EN_RC_L
S 1
EG_PWRSEQ_HW R7888
82
P1V1GPU_PGOOD
1
5% MF-LF 1/16W 402
100
R78802
R78812
R7882
R7883
R7884
5% 1/16W MF-LF 402
R7885
10K
5% 1/16W MF-LF 402
R7886
5.1K
5% 1/16W MF-LF 402
=P3V3S0_EN =PBUSVSENS_EN
R7892 1
69
10K
5% 1/16W MF-LF 402 2
46
P2V5S0_EN
=P2V5S0_EN =P1V2S0_EN
P1V05S0_EN
68
S0PGOOD_PWROK
=PP3V3_S5_PWRCTL
8 68
MAKE_BASE=TRUE
OUT OUT OUT OUT OUT OUT OUT
86 65
P1V2_S0_EN
MAKE_BASE=TRUE
IN IN IN
MCPCORES0_PGOOD
1
86 66 69
CPUVTTS0_PGOOD P1V8S0_PGOOD P5V_RTS0_PGOOD P5V3V3_PGOOD
R7894 1
0
5% 1/16W MF-LF 402 2
2
C7889
0.1UF
20% 10V CERM 402
=P1V8S0_EN =MCPDDR_EN
=CPUVTTS0_EN
67 65 69 63 66
IN IN
S0_PWR_PGOOD
MAKE_BASE=TRUE
=MCPCORES0_EN
65
5 TC7SZ08AFEAPE
NO STUFF
R7891
NO STUFF
1
68 9
SOT665
4
PM_ALL_GPU_PGOOD 1
0
5% 1/16W MF-LF 402
ALL_GFX_PGOOD_R
U7880Y
B
ALL_SYS_PWRGD
OUT
26 42
C7885
0.47UF
10% 6.3V CERM-X5R 402
C7886
0.47UF
10% 6.3V CERM-X5R 402
10% 6.3V CERM-X5R 402
3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT

place XW0402 if needed to save trace space for pin 7,8
8
EG_PWRSEQ_HW
R7869
0
5% 1/16W MF-LF 402
=PP3V3_S0_VMON
B
C7870 1
0.1uF
20% 10V CERM 402
P1V8_S0GPU_EN
2
MAKE_BASE=TRUE
=P1V8FB_EN
OUT
67 82 83
S 4
G96 GPU requires rails to come up in the following order: 1) 1.1V 2) GPU_3.3V 3) GPUVcore 4) GDDR3 1.8V BOMOPTION: EG
VCC
DFN
TMR RST*
2 4
TIE TMR TO GND TRST = 200MS S0PGOOD_PWROK
=PP1V5_S0_VMON
8 7 NC 6
68
=PP1V05_S0_VMON
LTC2909 THRESHOLD IS 3.136V 1.5V 1.05V COMPARED TO 0.5V
EXT GPU PWRGD Pullup

=PP3V3_S0_PWRCTL
Power Control
SYNC_MASTER=PWRSQNC SYNC_DATE=05/12/2008
R7890 1
100K
5% 1/16W MF-LF 402 2
P3V3GPU_EN
OUT
69 83
82
P1V8FB_PGOOD
PM_ALL_GPU_PGOOD
MAKE_BASE=TRUE
OUT
9 68
SIZE
DRAWING NUMBER
REV.
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
68
96
67
3.3V S3 FET
8
3.3V S0 FET
CRITICAL
Q7910
FDC638P_G
SM
CRITICAL
Q7930
FDC606P_G
SOT-6
=PP3V3_S3_P3V3S3FET
4
6 5
=PP3V3_S3_FET
5 2
=PP3V3_S0_P3V3S0FET
=PP3V3_S0_FET
SSM6N15FEAPE
SOT563
5% 1/16W MF-LF 402
10% 16V X5R 402 2
SSM6N15FEAPE 3
D
68
Q7912
D 6
R7912
10K
C7911
0.033UF
R7932
C7931
0.033UF
10% 16V X5R 402
1 2
3.3V S3 FET
MOSFET CHANNEL FDC638P P-TYPE 48 mOhm @4.5V 0.087 A (EDP)
68
3.3V S0 FET
MOSFET CHANNEL FDC606P P-TYPE 26 mOhm @4.5V 2.9 A (EDP)
Q7912
SOT563
D 3
100K
5% 1/16W MF-LF 402
R7910
P3V3S3_EN_L
1
C7910
0.01UF
R7930
P3V3S0_EN_L
47K
1 5% 1/16W MF-LF 402 2
C7930
0.01UF
47K
5% 1/16W MF-LF 402
RDS(ON) LOADING
RDS(ON) LOADING
2 IN
S 1
P3V3S3_SS
P3V3S0_SS
=P3V3S3_EN
IN
=P3V3S0_EN
S 4
10% 16V CERM 402
10% 16V CERM 402
3.3V GPU FET 1.05V S0 FET

8
CRITICAL
Q7970
FDC606P_G
SOT-6
=PP1V05_S5_P1V05S0FET
CRITICAL
=PP3V3_GPU_P3V3GPUFET
=PP3V3_S0GPU_FET
C
8
5% 1/16W MF-LF 402
APN 376S0651
MOSFET CHANNEL
SI7108DN N-TYPE
=PP5V_S3_P1V05S0FET
220K
P1V05S0_SS
SI7108DN
PWRPK-1212-8-HF
51K
5% 1/16W MF-LF 402
1UF
10% 10V X5R 402 2
R7952
Q7953
1.05V S0 FET
R7972 1
C7971
1 2
3.3V GPU FET

MOSFET CHANNEL FDC606P P-TYPE 26 mOhm @4.5V 1.1 A (EDP) EG
R7970
P3V3GPU_EN_L
1K
1 5% 1/16W MF-LF 402 2
C7970
0.01UF
RDS(ON) LOADING BOM_OPTION
P3V3GPU_SS
RDS(ON)
8
5 mOhm @4.5V 2.1 A (EDP)
=PP3V3_S5_P1V05FET
Q7972
SSM3K15FV
SOD-VESM-HF
G S
LOADING
1 2 3
D 3
10% 16V CERM 402
R79531
10K
5% 1/16W MF-LF 402 2
Q7951
SSM6N15FEAPE
SOT563
D 6
83 68
IN
P3V3GPU_EN
1
=PP1V05_S0_FET
S 1
1
S 2
R7951
P1V05_EN_L
1 5% 1/16W MF-LF 402
2 G
C7953
0.068UF
100K 2
10% 2 10V CERM 402
SSM6N15FEAPE
SOT563
Q7951
5 G
D 3
P1V05_EN_L_RC
S 4
68
IN
P1V05S0_EN
MCP79 DDR FETs

MCP79 DDR pad leakage is high enough that nVidia recommends unpowering during sleep. In order to support unpowering rail, hardware must guarantee MEM_CKE signals are low before rail is turned off, and remains low until after rail turns back on or DIMMs will exit self-refresh prematurely. MEM_VTT_EN output from MCP79 used to enable clamp on VTT rail, which pulls all CKE signals low through VTT termination resistors.
1.5V S0 FET
8
=PP1V8R1V5_S0_MCP_FET
5
1.5V S0 FET
MOSFET SI7108DN N-TYPE 5 mOhm @4.5V 5.4 A (EDP)
8
=PPVTT_S0_VTTCLAMP
R79751
1
C7902
=PP5V_S3_MCPDDRFET
APN 376S0651
CRITICAL
CHANNEL RDS(ON) LOADING
R7901
1
0.1UF 20% 10V CERM 2 402
10 5% 1/16W MF-LF 402 2
90mA max load @ 0.9V 81mW max power
Q7901
4
G S
VTTCLAMP_L =PP5V_S3_VTTCLAMP
10K
5% 1/16W MF-LF 402
MCPDDR_SS
SI7108DN
PWRPK-1212-8-HF
Q7975 R79761
SSM6N15FEAPE SOT563
8
D 6
R7903
Q7971
SSM6N15FEAPE SOT563
D 6
1 2 3
=PP1V8R1V5_S0_FET
100K 5% 1/16W MF-LF 402 2
100K 5% 1/16W MF-LF 402 2
Power FETs
2
S 1
SYNC_MASTER=PWRSQNC
R7971
MCPDDR_EN_L
1
S 1
C7903
Q7975
SSM6N15FEAPE SOT563
VTTCLAMP_EN
D
3

1 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING I TO MAINTAIN THE DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART SIZE DRAWING NUMBER REV.
47K
5% 1/16W MF-LF 402
0.068UF 10% 10V 2 CERM 402
NO STUFF
C7976
Q7971
SSM6N15FEAPE
SOT563
D 3
MCPDDR_EN_L_RC
5
64 9
0.001UF 20% 50V CERM 2 402
S 4
5
68
S 4
IN
=DDRVTT_EN
APPLE INC.
D
SCALE NONE
051-7546
SHT OF
A.0.0
IN
=MCPDDR_EN
69
96
5 6
4
OMIT
3
U8000
NB9P-GS
2
C8055
AL17 AM17
89 89
1
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
Page Notes
Power aliases required by this page: - =PP1V2_GPU_PEX_PLLXVDD - =PP1V2_GPU_PEX_IOVDDQ - =PP1V2_GPU_PEX_IOVDD Signal aliases required by this page: (NONE) BOM options provided by this page: (NONE)
89 9
IN
PEG_R2D_C_P<0> PEG_R2D_C_N<0> PEG_R2D_C_P<1> PEG_R2D_C_N<1> PEG_R2D_C_P<2> PEG_R2D_C_N<2> PEG_R2D_C_P<3> PEG_R2D_C_N<3> PEG_R2D_C_P<4> PEG_R2D_C_N<4> PEG_R2D_C_P<5> PEG_R2D_C_N<5> PEG_R2D_C_P<6> PEG_R2D_C_N<6> PEG_R2D_C_P<7> PEG_R2D_C_N<7> PEG_R2D_C_P<8> PEG_R2D_C_N<8> PEG_R2D_C_P<9> PEG_R2D_C_N<9> PEG_R2D_C_P<10> PEG_R2D_C_N<10> PEG_R2D_C_P<11> PEG_R2D_C_N<11> PEG_R2D_C_P<12> PEG_R2D_C_N<12> PEG_R2D_C_P<13> PEG_R2D_C_N<13> PEG_R2D_C_P<14> PEG_R2D_C_N<14> PEG_R2D_C_P<15> PEG_R2D_C_N<15> PEG_CLK100M_P PEG_CLK100M_N GPU_RESET_L
C8020 C8021 C8022 C8023 C8024 C8025 C8026 C8027 C8028 C8029 C8030 C8031 C8032 C8033 C8034 C8035 C8036 C8037 C8038 C8039 C8040 C8041 C8042 C8043 C8044 C8045 C8046 C8047 C8048 C8049 C8050 C8051
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
1 1
89 9
IN
2 89 10% 16V X5R 40289 2 10% 16V X5R 402 2 89 10% 16V X5R 40289 2 10% 16V X5R 402 2 89 10% 16V X5R 40289 2 10% 16V X5R 402 2 89 10% 16V X5R 40289 2 10% 16V X5R 402 2 89 10% 16V X5R 40289 2 10% 16V X5R 402 2 89 10% 16V X5R 40289 2 10% 16V X5R 402 2 89 10% 16V X5R 40289 2 10% 16V X5R 402 2 89 10% 16V X5R 40289 2 10% 16V X5R 402 2 89 10% 16V X5R 40289 2 10% 16V X5R 402 2 89 10% 16V X5R 40289 2 10% 16V X5R 402 2 89 10% 16V X5R 40289 2 10% 16V X5R 402 2 89 10% 16V X5R 40289 2 10% 16V X5R 402 2 89 10% 16V X5R 40289 2 10% 16V X5R 402 2 89 10% 16V X5R 40289 2 10% 16V X5R 402 2 89 10% 16V X5R 40289 2 10% 16V X5R 402 2 89 10% 16V X5R 40289 2 10% 16V X5R 402
PEG_R2D_P<0> PEG_R2D_N<0>
AP17 AN17
BGA SYMBOL 1 OF 9 PEX_RX0 PEX_TX0 PEX_RX0* PEX_TX0*
1 1
PEG_D2R_C_P<0> PEG_D2R_C_N<0>
C8056 C8057
2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402 2 10% 16V X5R 402
PEG_D2R_P<0> PEG_D2R_N<0> PEG_D2R_P<1> PEG_D2R_N<1> PEG_D2R_P<2> PEG_D2R_N<2> PEG_D2R_P<3> PEG_D2R_N<3> PEG_D2R_P<4> PEG_D2R_N<4> PEG_D2R_P<5> PEG_D2R_N<5> PEG_D2R_P<6> PEG_D2R_N<6> PEG_D2R_P<7> PEG_D2R_N<7> PEG_D2R_P<8> PEG_D2R_N<8> PEG_D2R_P<9> PEG_D2R_N<9> PEG_D2R_P<10> PEG_D2R_N<10> PEG_D2R_P<11> PEG_D2R_N<11> PEG_D2R_P<12> PEG_D2R_N<12> PEG_D2R_P<13> PEG_D2R_N<13> PEG_D2R_P<14> PEG_D2R_N<14> PEG_D2R_P<15> PEG_D2R_N<15>
OUT
9 89
OUT
9 89
1 1
OUT
9 89
89 9
IN
1 1
AN19 AP19
PEX_RX1 PEX_RX1*
PEX_TX1 PEX_TX1*
AM18 AM19
89 89
C8058 C8059
OUT
9 89
89 9
D
8 8 8
IN
1 1
D
OUT
9 89
=PP1V1_GPU_PEX_PLLXVDD =PP1V1_GPU_PEX_IOVDDQ =PP1V1_GPU_PEX_IOVDD
89 9
IN
1 1
AR19 AR20
PEX_RX2 PEX_RX2*
PEX_TX2 PEX_TX2*
AL19 AK19
89 89
C8060 C8061
OUT
9 89
89 9
IN
1 1
OUT
9 89
89 9
IN
1 1
AP20 AN20
PEX_RX3 PEX_RX3*
PEX_TX3 PEX_TX3*
AL20 AM20
89 89
C8062 C8063
OUT
9 89
89 9
IN
1 1
OUT
9 89
89 9
IN
PEX_RX4 PEX_RX4*
PEX_TX4 PEX_TX4*
89 89
C8064 C8065
OUT
9 89
89 9
IN
1 1
OUT
9 89
PEX 1.1V Current = 2A 250mA
89 9
IN
1 1
AR22 AR23
PEX_RX5 PEX_RX5*
PEX_TX5 PEX_TX5*
AL22 AK22
89 89
C8066 C8067
OUT
9 89
89 9
IN
1 1
C8002
1UF
C8001
4.7UF
C8000
22UF
89 9
IN
1 1
AP23 AN23
PEX_RX6 PEX_RX6*
PEX_TX6 PEX_TX6*
AL23 AM23
OUT
9 89
89 89
C8068 C8069
OUT
9 89
NC_GPU_DFM
NO_TEST=TRUE
10% 2 6.3V CERM 402
20% 2 6.3V CERM 603
20% 2 6.3V CERM-X5R 805
89 9
IN
1 1
OMIT
89 9
IN
1 1
AN25 AP25
PEX_RX7 PEX_RX7*
PEX_TX7 PEX_TX7*
AM24 AM25
OUT
9 89
89 89
C8070 C8071
OUT
9 89
C
H32 M7 P6 P7 R7 U7 V6 AB7 AD6 AF6 AG6 AJ5 D35 AK15 AL7 E7 E35 F7 A2
U8000
NB9P-GS
BGA SYMBOL 2 OF 9 PEX_IOVDD1 PEX_IOVDD2 PEX_IOVDD3 PEX_IOVDD4 PEX_IOVDD5 AK16 AK17 AK21 AK24 AK27 1500mA
C8003
1UF
C8004
0.1UF
C8005
0.1UF
89 9
IN
10% 2 6.3V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
1 1
C
OUT
9 89
89 9
IN
1 1
AR25 AR26
PEX_RX8 PEX_RX8*
PEX_TX8 PEX_TX8*
AL25 AK25
89 89
C8072 C8073
OUT
9 89
89 9
IN
1 1
OUT
9 89
89 9
IN
1 1
AP26 AN26
PEX_RX9 PEX_RX9*
PEX_TX9 PEX_TX9*
AL26 AM26
89 89
C8074 C8075
OUT
9 89
89 9
IN
1 NC PEX_IOVDDQ1 PEX_IOVDDQ2 PEX_IOVDDQ3 PEX_IOVDDQ4 PEX_IOVDDQ5 PEX_IOVDDQ6 PEX_IOVDDQ7 PEX_IOVDDQ8 PEX_IOVDDQ9 PEX_IOVDDQ10 PEX_IOVDDQ11 PEX_IOVDDQ12 PEX_IOVDDQ13 PEX_IOVDDQ14 PEX_IOVDDQ15 PEX_IOVDDQ16 PEX_IOVDDQ17 PEX_IOVDDQ18 PEX_IOVDDQ19 PEX_IOVDDQ20 PEX_IOVDDQ21 PEX_IOVDDQ22 PEX_IOVDDQ23 PEX_IOVDDQ24 PEX_IOVDDQ25 AG11 AG12 AG13 AG15 AG16 AG17 AG18 AG22 AG23 AG24 AG25 AG26 AJ14 AJ15 AJ19 AJ21 AJ22 AJ24 AJ25 AJ27 AK18 AK20 AK23 AK26 AL16
C8008
1UF
C8007
4.7UF
C8006
22UF
89 9
1 1
OUT
9 89
10% 2 6.3V CERM 402
20% 2 6.3V CERM 603
20% 2 6.3V CERM-X5R 805
IN
1 1
AN28 AP28
PEX_RX10 PEX_RX10*
PEX_TX10 PEX_TX10*
AM27 AM28
89 89
C8076 C8077
OUT
9 89
89 9
IN
1 1
OUT
9 89
89 9
C8009
1UF
C8010
0.1UF
C8011
0.1UF
89 9 89 9
IN
1 1
AR28 AR29
PEX_RX11 PEX_RX11*
PEX_TX11 PEX_TX11*
AL28 AK28
89 89
C8078 C8079
OUT
9 89
10% 2 6.3V CERM 402
20% 2 10V CERM 402
20% 2 10V CERM 402
IN
1 1
OUT
9 89
IN
1 1
AP29 AN29
PEX_RX12 PEX_RX12*
PEX_TX12 PEX_TX12*
AK29 AL29
89 89
C8080 C8081
OUT
9 89
89 9
180mA
10NH-600MA
1 0603 1 1 2
89 9
L8015
IN
1 1
OUT
9 89
PP1V1_GPU_PEX_PLLVDD_F
IN
1 1
AN31 AP31
PEX_RX13 PEX_RX13*
PEX_TX13 PEX_TX13*
AM29 AM30
89 89
C8082 C8083
OUT
9 89
C8017
0.1UF
C8016 C8015 1
4.7UF 4.7UF
20% 6.3V 2 CERM 603
89 9
IN
20% 2 10V CERM 402
20% 2 6.3V CERM 603
1 1
89 9
IN
1 1
AR31 AR32
PEX_RX14 PEX_RX14*
PEX_TX14 PEX_TX14*
AM31 AM32
OUT
9 89
89 89
C8084 C8085
OUT
9 89
89 9
IN
1 1
89 9
IN
1 1
AR34 AP34
PEX_RX15 PEX_RX15*
PEX_TX15 PEX_TX15*
AN32 AP32
OUT
9 89
89 89
C8086
OUT
9 89
89 9
IN
R8060
AR16 AR17 PEX_REFCLK PEX_REFCLK* PEX_RST* PEX_CLKREQ* PEX_TSTCLK_OUT PEX_TSTCLK_OUT* PEX_TERMP
AJ17
PEX_PLLVDD VDD_SENSE GND_SENSE
AG14
AD20 AD19
89 17 89 17
IN IN
AJ18 AG21
PEX_TSTCLK_P PEX_TSTCLK_N PEX_TERMP_PD
200
GPU_VDD_SENSE GPU_GND_SENSE
78 9 78
IN
R8020
0
5% 1/16W MF-LF 402
R8050
1
GPU_RESET_R_L TP_PEX_CLKREQ_L
AM16
AR13
2.49K 2
1% 1/16W MF-LF 402
1% 1/16W MF-LF 402
PEX_RFU1 PEX_RFU2
AG19 NC AG20
NC
NV G96 PCI-E
SYNC_MASTER=MUXGFX

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
70
96
AN22 AP22
AM21 AM22
8 Page Notes
Power aliases required by this page: - =PPVCORE_GPU - =PP1V8_GPU_FBVDDQ Signal aliases required by this page: (NONE) BOM options provided by this page: (NONE)
8
5
OMIT
4
U8000
NB9P-GS
3
U8000
NB9P-GS
BGA
=PPVCORE_GPU ???A @ ???/???MHz Core/Mem Clk for VDD
C8100
4.7UF
20% 6.3V X5R-CERM 402
C8101
4.7UF
20% 6.3V X5R-CERM 402
C8102
4.7UF
20% 6.3V X5R-CERM 402
C8103
0.47UF
10% 6.3V CERM-X5R 402
C8104
0.47UF
10% 6.3V CERM-X5R 402
C8105
0.47UF
10% 6.3V CERM-X5R 402
C8106
0.47UF
10% 6.3V CERM-X5R 402
C8107
0.47UF
10% 6.3V CERM-X5R 402
C8108
0.47UF
10% 6.3V CERM-X5R 402
C8109
0.47UF
10% 6.3V CERM-X5R 402
C8110
0.47UF
10% 6.3V CERM-X5R 402
C8111
0.47UF
10% 6.3V CERM-X5R 402
C8112
0.47UF
10% 6.3V CERM-X5R 402
C8113
0.1UF
20% 10V CERM 402
C8114
0.1UF
20% 10V CERM 402
C8115
0.1UF
20% 10V CERM 402
C8116
0.1UF
20% 10V CERM 402
C8117
0.1UF
20% 10V CERM 402
VDD
VDD
C8118
0.1UF
20% 10V CERM 402
C8119
0.1UF
20% 10V CERM 402
C8120
0.1UF
20% 10V CERM 402
C8121
0.1UF
20% 10V CERM 402
C8122
0.1UF
20% 10V CERM 402
GND
GND
=PP1V8_GPU_FBVDDQ
Nvidia PRD for GB-128 uses 4x4.7uF, 8x0.47uF, 16x0.1uF ???A @ ???MHz 1.8V GDDR3
C8150
C8151
4.7UF
20% 6.3V CERM 603
B
C8156
0.1UF
20% 10V CERM 402 2 1
4.7UF
20% 6.3V CERM 603 2
OMIT
C8157
0.1UF
20% 10V CERM 402
C8158
0.1UF
20% 10V CERM 402
C8159
0.1UF
20% 10V CERM 402
C8160
0.47UF
10% 6.3V CERM-X5R 402
C8161
0.47UF
10% 6.3V CERM-X5R 402
U8000
NB9P-GS
BGA
B18 J17 U27 AB27 AB29 AC27 AD27 AE27 AJ28 E21 G8 G9 G17 G18 G22 H29 J14 J15 J16 SYMBOL 7 OF 9
J20 J21 J22 J23 J24 J29 N27 P27 R27 T27
C8162
0.1UF
20% 10V CERM 402
C8163
0.1UF
20% 10V CERM 402
C8164
0.1UF
20% 10V CERM 402
C8165
0.1UF
20% 10V CERM 402
C8166
0.47UF
10% 6.3V CERM-X5R 402
C8167
0.47UF
10% 6.3V CERM-X5R 402
C8168
0.47UF
10% 6.3V CERM-X5R 402
C8169
0.47UF
10% 6.3V CERM-X5R 402
C8170
0.47UF
10% 6.3V CERM-X5R 402
C8171
0.47UF
10% 6.3V CERM-X5R 402
FBVDDQ
FBVDDQ
U29 V27 V29 V34 W27 Y27 AA27 AA29 AA31
AB12 AB14 AB16 AB18 AB20 AB22 AB24 AC9 AD2 AD5 AD11 AD13 AD15 AD17 AD21 AD23 AD25 AD31 AD34 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AG2 AG5 AG31 AG34 AK2 AK5 AP33 AK31 AK34 AL6 AL9 AL12 AL15 AL18 AL21 AL24 AL27 AL30 AN2 AN34 AP3 AP6 AP9 AP12 AP15 AP18 AP21 AP24 AP27 AP30
NV G96 Core/FB Power

SYNC_MASTER=MUXGFX SYNC_DATE=07/10/2008

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
71
96
L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 M12 M14 M16 M18 M20 M22 M24 P11 P13 P15 P17 P19 P21 P23 P25 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 T12 T14 T16 T18 T20 T22 T24 V11 V13 V15 V17
BGA
SYMBOL 9 OF 9
V19 V21 V23 V25 W11 W12 W13 W14 W15 W16 W17 W18 W19 AD24 W21 W22 W23 W24 W25 Y12 Y14 Y16 Y18 Y20 Y22 Y24 AB11 AB13 AB15 AB17 AB19 AB21 AB23 AB25 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AD12 AD14 AD16 AD18 AD22 W20
B3 B6 B9 B12 B15 B21 B24 B27 B30 B33 C2 C34 E6 E9 E12 E15 E18 E24 E27 E30 F2 F5 F31 F34 J2 J5 J31 J34 L9 M2 M5 M11 M13 M15 M17 M19 M21 M23 M25 M31 M34 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 N21 N22 N23 N24 N25 P12 P14 P16 P18 P20 P22 P24 R2 R5 R31 R34 T11 T13 T15 T17 T19 T21 T23 T25 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U23 U24 U25 V2 V5 V9 V12 V14 V16
SYMBOL 8 OF 9
V18 V20 V22 V24 V31 Y11 Y13 Y15 Y17 Y19 Y21 Y23 Y25 AA2 AA5 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA34
8 Page Notes
Power aliases required by this page: - =PP1V2_GPU_FBPLLAVDD - =PP1V8_GPU_FBIO Signal aliases required by this page: (NONE) BOM options provided by this page: (NONE)
94 73
OMIT
OMIT
U8000
NB9P-GS
BGA
R30 R32 P31 N30 L31 M32 M30 L30 P33 P34 N35 P35 N34 L33 L32 N33 K31 K30 G30 K32 G32 H30 F30 G31 H33 K35 K33 G34 K34 E33 E34 G33 AG30 AH31 AG32 AF31 AF30 AD30 AC32 AE30 AE32 AF33 AF34 AE35 AE33 AE34 AC35 AB32 AN33 AK32 AL33 AM33 AL31 AK30 AJ30 AH30 AM35 AH33 AH35 AH32 AH34 AM34 AL35 AJ33 SYMBOL 3 OF 9 FBA_D0 FBA_CMD0 FBA_D1 FBA_CMD1 FBA_D2 FBA_CMD2 FBA_D3 FBA_CMD3 FBA_D4 FBA_CMD4 FBA_D5 FBA_CMD5 FBA_D6 FBA_CMD6 FBA_D7 FBA_CMD7 FBA_D8 FBA_CMD8 FBA_D9 FBA_CMD9 FBA_D10 FBA_CMD10 FBA_D11 FBA_CMD11 FBA_D12 FBA_CMD12 FBA_D13 FBA_CMD13 FBA_D14 FBA_CMD14 FBA_D15 FBA_CMD15 FBA_D16 FBA_CMD16 FBA_D17 FBA_CMD17 FBA_D18 FBA_CMD18 FBA_D19 FBA_CMD19 FBA_D20 FBA_CMD20 FBA_D21 FBA_CMD21 FBA_D22 FBA_CMD22 FBA_CMD23 FBA_D23 FBA_D24 FBA_CMD24 FBA_D25 FBA_CMD25 FBA_D26 FBA_CMD26 FBA_D27 FBA_CMD27 FBA_D28 FBA_CMD28 FBA_CMD29 FBA_D29 FBA_CMD30 FBA_D30 FBA_D31 FBA_CLK0 FBA_D32 FBA_CLK0* FBA_D33 FBA_CLK1 FBA_D34 FBA_CLK1* FBA_D35 FBA_D36 FBA_DQM0 FBA_D37 FBA_DQM1 FBA_D38 FBA_DQM2 FBA_D39 FBA_DQM3 FBA_D40 FBA_DQM4 FBA_D41 FBA_DQM5 FBA_D42 FBA_DQM6 FBA_D43 FBA_DQM7 FBA_D44 FBA_D45 FBA_DQS_RN0 FBA_D46 FBA_DQS_RN1 FBA_D47 FBA_DQS_RN2 FBA_D48 FBA_DQS_RN3 FBA_D49 FBA_DQS_RN4 FBA_D50 FBA_DQS_RN5 FBA_D51 FBA_DQS_RN6 FBA_D52 FBA_DQS_RN7 FBA_D53 FBA_D54 FBA_DQS_WP0 FBA_D55 FBA_DQS_WP1 FBA_D56 FBA_DQS_WP2 FBA_D57 FBA_DQS_WP3 FBA_D58 FBA_DQS_WP4 FBA_D59 FBA_DQS_WP5 FBA_D60 FBA_DQS_WP6 FBA_D61 FBA_DQS_WP7 FBA_D62 FBA_D63 FB_DLLAVDD0 FB_PLLAVDD0 FBA_RFU0 FBA_RFU1* FBA_DEBUG FBA_RFU2 FB_CAL_PD_VDDQ FBA_RFU3* FB_CAL_PU_GND FBA_RFU4 FB_CAL_TERM_GND FBA_RFU5* FBA_RFU6 FBA_RFU7* V32 W31 U31 Y32 AB35 AB34 W35 W33 W30 T34 T35 AB31 Y30 Y34 W32 AA30 AA32 Y33 U32 Y31 U34 Y35 W34 V30 U35 U30 U33 AB30 AB33 T33 W29 T32 T31 AC31 AC30
P30 P32 J30 H34 AF32 AF35 AL32 AL34
U8000
NB9P-GS
BGA
FB_A_LMA<4> FB_A_RAS_L FB_A_LMA<5> FB_A_BA<1> FB_A_UMA<2> FB_A_UMA<4> FB_A_UMA<3> FB_A_CS1_L FB_A_CS0_L FB_A_MA<11> FB_A_CAS_L FB_A_WE_L FB_A_BA<0> FB_A_UMA<5> FB_A_MA<12> FB_A_DRAM_RST FB_A_MA<7> FB_A_MA<10> FB_A_CKE FB_A_MA<0> FB_A_MA<9> FB_A_MA<6> FB_A_LMA<2> FB_A_MA<8> FB_A_LMA<3> FB_A_MA<1> FB_A_MA<13> FB_A_BA<2> TP_FBA_CMD28 TP_FBA_CMD29 TP_FBA_CMD30 FB_A_CLK_P<0> FB_A_CLK_N<0> FB_A_CLK_P<1> FB_A_CLK_N<1> FB_A_DQM_L<0> FB_A_DQM_L<1> FB_A_DQM_L<2> FB_A_DQM_L<3> FB_A_DQM_L<4> FB_A_DQM_L<5> FB_A_DQM_L<6> FB_A_DQM_L<7> FB_A_RDQS<0> FB_A_RDQS<1> FB_A_RDQS<2> FB_A_RDQS<3> FB_A_RDQS<4> FB_A_RDQS<5> FB_A_RDQS<6> FB_A_RDQS<7> FB_A_WDQS<0> FB_A_WDQS<1> FB_A_WDQS<2> FB_A_WDQS<3> FB_A_WDQS<4> FB_A_WDQS<5> FB_A_WDQS<6> FB_A_WDQS<7>
73 94 73 94 73 94 73 94 73 94 73 94 73 94 76 73 94 73 94 73 94 73 94 73 94 73 94 73 94 94 74 94 74 94 74 94 74 94 74 94 74 94 74 94 74 94 74 94 74 94 74 94 74 94 74 94 74 94 74
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
OUT OUT OUT
74 94 74 94 74 94
OUT OUT OUT

73 94 73 94
73 94
94 74 94 74
OUT OUT OUT

74 94 74 94
74 94
R8200
10K
5% 1/16W MF-LF 402
94 74 94 74 94 74 94 74 94 74 94 74 94 74 94 74 94 74 94 74 94 74 94 74 94 74 94 74 94 74
R8250
10K
5% 1/16W MF-LF 402
76 76 76 73 94 73 94 73 94 73 94 73 94 73 94 73 94 76 73 94
73 94
76 76 76 74 94 74 94 74 94 74 94 74 94 74 94 74 94 76 74 94
74 94
R8201
10K
5% 1/16W MF-LF 402
R8251
10K
5% 1/16W MF-LF 402
94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73
OUT OUT OUT OUT
73 94 94 74 73 94 94 74 73 94 94 74 73 94 94 74 94 74
E17 D17 D23 E23

F11 D10 D15 A16 D27
FB_B_CLK_P<0> FB_B_CLK_N<0> FB_B_CLK_P<1> FB_B_CLK_N<1> FB_B_DQM_L<0> FB_B_DQM_L<1> FB_B_DQM_L<2> FB_B_DQM_L<3> FB_B_DQM_L<4> FB_B_DQM_L<5> FB_B_DQM_L<6> FB_B_DQM_L<7> FB_B_RDQS<0> FB_B_RDQS<1> FB_B_RDQS<2> FB_B_RDQS<3> FB_B_RDQS<4> FB_B_RDQS<5> FB_B_RDQS<6> FB_B_RDQS<7> FB_B_WDQS<0> FB_B_WDQS<1> FB_B_WDQS<2> FB_B_WDQS<3> FB_B_WDQS<4> FB_B_WDQS<5> FB_B_WDQS<6> FB_B_WDQS<7>
OUT OUT OUT OUT
74 94 74 94 74 94 74 94
73 94 94 74 73 94 94 74 73 94 94 74 73 94 94 74 73 94 94 74 73 94 94 74 73 94 94 74 73 94 94 74 94 74
N32 L35 H31 G35 AD32 AC34 AJ31 AJ35

N31 L34 J32 H35 AE31 AC33 AJ32 AJ34
IN IN IN IN IN IN IN IN
73 94 94 74 73 94 94 74 73 94 94 74 73 94 94 74 73 94 72 8 73 94 73 94 73 94
=PP1V1_GPU_FBPLLAVDD
94 74 94 74 94 74 94 74 94 74 94 74
L8200
FERR-220-OHM
94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73 94 73
PP1V1_GPU_FBPLLAVDD_F
73 94 73 94 73 94 73 94
1 0402 1

1
C8202
0.1UF
20% 10V CERM 402
C8201
0.1UF
20% 10V CERM 402
C8200
1UF
10% 6.3V CERM 402
94 74 94 74 94 74 72 8
2
73 94 73 94
=PP1V8_GPU_FBIO
94 74 94 74
73 94 94 74 73 94
NC R29 NC L29 NC M29 NC AD29 NC AE29 NC AG29 NC AH29 NC
P29
AG27 AF27 T30 K27 L27 M27 FBA_DEBUG FBCAL_PD_VDDQ FBCAL_PU_GND FBCAL_TERM_GND
R8293
60.4
R82901
48.7
1% 1/16W MF-LF 402 2
94 74 94 74
FBC_D36 FBC_D37 FBC_D38 FBC_D39 FBC_D40 FBC_D41 FBC_D42 FBC_D43 FBC_D44 FBC_D45 FBC_D46 FBC_D47 FBC_D48 FBC_D49 FBC_D50 FBC_D51 FBC_D52 FBC_D53 FBC_D54 FBC_D55 FBC_D56 FBC_D57 FBC_D58 FBC_D59 FBC_D60 FBC_D61 FBC_D62 FBC_D63 FBC_RFU0 FBC_RFU1* FBC_RFU2 FBC_RFU3* FBC_RFU4 FBC_RFU5* FBC_RFU6 FBC_RFU7*
FBC_DQM0 FBC_DQM1 FBC_DQM2 FBC_DQM3 FBC_DQM4 FBC_DQM5 FBC_DQM6 FBC_DQM7 FBC_DQS_RN0 FBC_DQS_RN1 FBC_DQS_RN2 FBC_DQS_RN3 FBC_DQS_RN4 FBC_DQS_RN5 FBC_DQS_RN6 FBC_DQS_RN7 FBC_DQS_WP0 FBC_DQS_WP1 FBC_DQS_WP2 FBC_DQS_WP3 FBC_DQS_WP4 FBC_DQS_WP5 FBC_DQS_WP6 FBC_DQS_WP7 FB_DLLAVDD1 FB_PLLAVDD1 FBC_DEBUG FB_VREF
74 94 74 94 74 94 74 94 74 94 74 94 74 94 74 94
D28 D34 A34 D9 B10 E14 B14 F26 A26 D31 A31 E10 A10 D14 C14 E26 B26 D32 A32 J19 J18 G19 J27
IN IN IN IN IN IN IN IN
74 94 74 94 74 94 74 94 74 94 74 94 74 94 74 94
72 8
=PP1V1_GPU_FBPLLAVDD
C8290
0.1UF
20% 10V CERM 402
C8291
0.1UF
20% 10V CERM 402
74 94 74 94 74 94 74 94 72 8 74 94 74 94 74 94 74 94
=PP1V8_GPU_FBIO
R82941
60.4
1% 1/16W MF-LF 402 2
R8295 1
1.07K
1% 1/16W MF-LF 402
1% 1/16W MF-LF 402 2
PLACEMENT_NOTE=Place close to U8000.
R8292
40.2
R8291 1
33.2
1% 1/16W MF-LF 402
PLACEMENT_NOTE=Place close to
1% 1/16W U8000.MF-LF 402
NC G12 NC G14 NC G15 NC G24 NC G25 NC G27 NC G28 NC
G11
FBC_DEBUG
GPU_FB_VREF NO STUFF NO STUFF 1

1
C8296
0.1uF
10% 16V X5R 402
R8297
1.02K
1% 1/16W MF-LF 402
R8296 1
2.49K
1% 1/16W MF-LF 402
PLACEMENT_NOTE=Place close to U8000.

2
GPU_FB_VREF_UNTERM_L NO STUFF
Q8295
SSM6N15FEAPE
SOT563
NV G96 Frame Buffer I/F

A
76 74 73
IN
FB_VREF_UNTERM

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
72
96
FB_A_DQ<0> FB_A_DQ<1> FB_A_DQ<2> FB_A_DQ<3> FB_A_DQ<4> FB_A_DQ<5> FB_A_DQ<6> FB_A_DQ<7> FB_A_DQ<8> FB_A_DQ<9> FB_A_DQ<10> FB_A_DQ<11> FB_A_DQ<12> FB_A_DQ<13> FB_A_DQ<14> FB_A_DQ<15> FB_A_DQ<16> FB_A_DQ<17> FB_A_DQ<18> FB_A_DQ<19> FB_A_DQ<20> FB_A_DQ<21> FB_A_DQ<22> FB_A_DQ<23> FB_A_DQ<24> FB_A_DQ<25> FB_A_DQ<26> FB_A_DQ<27> FB_A_DQ<28> FB_A_DQ<29> FB_A_DQ<30> FB_A_DQ<31> FB_A_DQ<32> FB_A_DQ<33> FB_A_DQ<34> FB_A_DQ<35> FB_A_DQ<36> FB_A_DQ<37> FB_A_DQ<38> FB_A_DQ<39> FB_A_DQ<40> FB_A_DQ<41> FB_A_DQ<42> FB_A_DQ<43> FB_A_DQ<44> FB_A_DQ<45> FB_A_DQ<46> FB_A_DQ<47> FB_A_DQ<48> FB_A_DQ<49> FB_A_DQ<50> FB_A_DQ<51> FB_A_DQ<52> FB_A_DQ<53> FB_A_DQ<54> FB_A_DQ<55> FB_A_DQ<56> FB_A_DQ<57> FB_A_DQ<58> FB_A_DQ<59> FB_A_DQ<60> FB_A_DQ<61> FB_A_DQ<62> FB_A_DQ<63>
BI BI BI BI BI BI BI BI BI BI BI BI
FB_B_DQ<0> FB_B_DQ<1> FB_B_DQ<2> FB_B_DQ<3> FB_B_DQ<4> FB_B_DQ<5> FB_B_DQ<6> FB_B_DQ<7> FB_B_DQ<8> FB_B_DQ<9> FB_B_DQ<10> FB_B_DQ<11> FB_B_DQ<12> FB_B_DQ<13> FB_B_DQ<14> FB_B_DQ<15> FB_B_DQ<16> FB_B_DQ<17> FB_B_DQ<18> FB_B_DQ<19> FB_B_DQ<20> FB_B_DQ<21> FB_B_DQ<22> FB_B_DQ<23> FB_B_DQ<24> FB_B_DQ<25> FB_B_DQ<26> FB_B_DQ<27> FB_B_DQ<28> FB_B_DQ<29> FB_B_DQ<30> FB_B_DQ<31> FB_B_DQ<32> FB_B_DQ<33> FB_B_DQ<34> FB_B_DQ<35> FB_B_DQ<36> FB_B_DQ<37> FB_B_DQ<38> FB_B_DQ<39> FB_B_DQ<40> FB_B_DQ<41> FB_B_DQ<42> FB_B_DQ<43> FB_B_DQ<44> FB_B_DQ<45> FB_B_DQ<46> FB_B_DQ<47> FB_B_DQ<48> FB_B_DQ<49> FB_B_DQ<50> FB_B_DQ<51> FB_B_DQ<52> FB_B_DQ<53> FB_B_DQ<54> FB_B_DQ<55> FB_B_DQ<56> FB_B_DQ<57> FB_B_DQ<58> FB_B_DQ<59> FB_B_DQ<60> FB_B_DQ<61> FB_B_DQ<62> FB_B_DQ<63>
D11 E11 F10 D8 F8 F9 E8 F12 B11 C13 A11 B8 A8 C8 C11 C10 D12 E13 F17 F15 F16 E16 F14 F13 D13 A13 B13 A14 C16 A17 B16 D16 D24 D26 E25 F25 F27 E28 F28 D29 A25 B25 D25 C26 C28 B28 A28 A29 E29 F29 D30 E31 C33 D33 F32 E32 B29 C29 B31 C31 B32 C32 B34 B35
SYMBOL 4 OF 9 FBC_D0 FBC_CMD0 FBC_D1 FBC_CMD1 FBC_D2 FBC_CMD2 FBC_D3 FBC_CMD3 FBC_D4 FBC_CMD4 FBC_D5 FBC_CMD5 FBC_D6 FBC_CMD6 FBC_D7 FBC_CMD7 FBC_CMD8 FBC_D8 FBC_D9 FBC_CMD9 FBC_D10 FBC_CMD10 FBC_CMD11 FBC_D11 FBC_D12 FBC_CMD12 FBC_D13 FBC_CMD13 FBC_D14 FBC_CMD14 FBC_D15 FBC_CMD15 FBC_D16 FBC_CMD16 FBC_D17 FBC_CMD17 FBC_D18 FBC_CMD18 FBC_D19 FBC_CMD19 FBC_D20 FBC_CMD20 FBC_D21 FBC_CMD21 FBC_D22 FBC_CMD22 FBC_D23 FBC_CMD23 FBC_CMD24 FBC_D24 FBC_D25 FBC_CMD25 FBC_D26 FBC_CMD26 FBC_D27 FBC_CMD27 FBC_CMD28 FBC_D28 FBC_D29 FBC_CMD29 FBC_D30 FBC_CMD30 FBC_D31 FBC_CLK0 FBC_D32 FBC_CLK0* FBC_D33 FBC_CLK1 FBC_D34 FBC_CLK1* FBC_D35
C17 B19 D18 F21 A23 D21 B23 E20 G21 F20 F19 F23 A22 C22 B17 F24 C25 E22 C20 B22 A19 D22 D20 E19 D19 F18 C19 F22 C23 B20 A20
FB_B_LMA<4> FB_B_RAS_L FB_B_LMA<5> FB_B_BA<1> FB_B_UMA<2> FB_B_UMA<4> FB_B_UMA<3> FB_B_CS1_L FB_B_CS0_L FB_B_MA<11> FB_B_CAS_L FB_B_WE_L FB_B_BA<0> FB_B_UMA<5> FB_B_MA<12> FB_B_DRAM_RST FB_B_MA<7> FB_B_MA<10> FB_B_CKE FB_B_MA<0> FB_B_MA<9> FB_B_MA<6> FB_B_LMA<2> FB_B_MA<8> FB_B_LMA<3> FB_B_MA<1> FB_B_MA<13> FB_B_BA<2> TP_FBC_CMD28 TP_FBC_CMD29 TP_FBC_CMD30
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
74 94 74 94 74 94 74 94 74 94 74 94 74 94 76 74 94 74 94 74 94 74 94
8
74 73 8
6
OMIT CRITICAL
A2 A11 F1 F12 M1 M12 V2 V11 VDD0 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7
VSS0 A3 VSS1 A10 VSS2 G1 VSS3 G12 VSS4 L1 VSS5 L12 VSS6 V3 VSS7 V10
5
74 73 8
4
=PP1V8_GPU_FB_VDD
3
OMIT CRITICAL
1 Page Notes
Power aliases required by this page: - =PP1V8_S0_FB_VDD - =PP1V8_S0_FB_VREFA Signal aliases required by this page: (NONE) BOM options provided by this page: VRAM4
=PP1V8_GPU_FB_VDD
U8400
BGA (2 OF 2)
U8450
BGA (2 OF 2)
C8400
10UF
20% 6.3V X5R 603
C8401
0.1uF
10% 16V X5R 402
C8402
0.1uF
10% 16V X5R 402
C8403
0.1uF
10% 16V X5R 402
C8404
0.1uF
10% 16V X5R 402
C8450
10UF
20% 6.3V X5R 603
C8451
0.1uF
10% 16V X5R 402
C8452
0.1uF
10% 16V X5R 402
C8453
0.1uF
10% 16V X5R 402
C8454
0.1uF
10% 16V X5R 402
K4J10324QD-HC11
32MX32-900MHZ-MFH
32MX32-900MHZ-MFH
K4J10324QD-HC11
D
1
K1 VDDA0 K12 VDDA1
VSSA0 J1 VSSA1 J12 VSSQ0 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14 VSSQ15 VSSQ16 VSSQ17 VSSQ18 VSSQ19 B1 B4 B9 B12 D1 D4 D9 D12 G2 G11 L2 L11 P1 P4 P9 P12 T1 T4 T9 T12
1
K1 VDDA0 K12 VDDA1
C8410
0.1uF
10% 16V X5R 402
C8415
0.1uF
10% 16V X5R 402
U8400.J1
U8400.J12
Connect to designated pin, then GND

74 73 9 8
=PP1V8_GPU_FB_VDDQ
C8420
10UF
20% 6.3V X5R 603
C8421
0.1uF
10% 16V X5R 402
C8422
0.1uF
10% 16V X5R 402
C8423
0.1uF
10% 16V X5R 402
C8424
0.1uF
10% 16V X5R 402
C8425
0.1uF
10% 16V X5R 402
C8426
0.1uF
10% 16V X5R 402
C8470
10UF
20% 6.3V X5R 603
C8471
0.1uF
10% 16V X5R 402
C8472
0.1uF
10% 16V X5R 402
C8473
0.1uF
10% 16V X5R 402
C8474
0.1uF
10% 16V X5R 402
C8475
0.1uF
10% 16V X5R 402
C8476
0.1uF
10% 16V X5R 402
73 9
73 9
R8430
549
1% 1/16W MF-LF 402
R8433
549
1% 1/16W MF-LF 402
R8480 1
549
1% 1/16W MF-LF 402
R8483 1
549
1% 1/16W MF-LF 402
FB_A0_VREF FB_A2_VREF
C
R8431
1.33K
H1 VREF0 H12 VREF1

1
FB_A1_VREF FB_A3_VREF
H1 VREF0 H12 VREF1

1
R8432
931
C8431
0.01UF
10% 16V CERM 402
R8434
1.33K
R8435
931
C8432
0.01UF
10% 16V CERM 402
R8481
1.33K
R8482
931
C8481
0.01uF
10% 16V CERM 402
R8484
1.33K
R8485
931
C8482
0.01uF
10% 16V CERM 402
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
FB_A2_VREF_UNTERM_L FB_A0_VREF_UNTERM_L FB_A_CLK0_TERM VRAM4 VRAM4

1
FB_A3_VREF_UNTERM_L FB_A1_VREF_UNTERM_L FB_A_CLK1_TERM
VOLTAGE=0.9V
1
Q8400
SSM6N15FEAPE
1
74 73 72 76
Q8400
SSM6N15FEAPE
SOT563
VRAM4
VRAM4
1
VOLTAGE=0.9V
1
Q8450
1
Q8450
SSM6N15FEAPE
SOT563
R8440
1K
5% 1/16W MF-LF 402
R8442
121
1% 1/16W MF-LF 402
R8444
121
1% 1/16W MF-LF 402
R8446
243
1% 1/16W MF-LF 402
C8446
0.01UF
2 1
SOT563
R8490
1K
R8492
121
1% 1/16W MF-LF 402
R8494
121
1% 1/16W MF-LF 402
R8496
243
1% 1/16W MF-LF 402
C8496
0.01UF
10% 16V CERM 402
SSM6N15FEAPE
SOT563
74 73 72 76
2 1
VRAM4
2 1
VRAM4
10% 16V CERM 402
IN
FB_VREF_UNTERM
2
5% 1/16W MF-LF 402
IN
FB_VREF_UNTERM
2
2 1
VRAM4
2 1
VRAM4
2 1
R8443
121
R8445
121
R8447
243
R8493
121
R8495
121
R8497
243
1% 1/16W MF-LF 402 2

94 73 72 94 73 72 94 72 94 72 94 72 94 72
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
OMIT CRITICAL
K9 A0 H11 A1 K10 A2 M9 A3 K4 A4 H2 A5
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
OMIT CRITICAL
K9 A0 H11 A1 K10 A2 M9 A3 K4 A4 H2 A5
IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN
94 73 72 94 73 72 94 73 72 94 73 72 94 73 72 94 73 72 94 73 72 94 73 72
FB_A_MA<0> FB_A_MA<1> FB_A_LMA<2> FB_A_LMA<3> FB_A_LMA<4> FB_A_LMA<5> FB_A_MA<6> FB_A_MA<7> FB_A_MA<8> FB_A_MA<9> FB_A_MA<10> FB_A_MA<11> FB_A_CKE FB_A_MA<12> FB_A_CLK_P<0> FB_A_CLK_N<0> FB_A_CS0_L FB_A_WE_L FB_A_CAS_L FB_A_RAS_L FB_A0_ZQ FB_A0_MF FB_A0_SEN
U8400
BGA (1 OF 2)
DM0 DM1 DM2 DM3 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21
E3 E10 N10 N3 B2 B3 C2 C3 E2 F3 F2 G3 B11 B10 C11 C10 E11 F10 F11 G10 M11 L10 N11 M10 R11 R10
32MX32-900MHZ-MFH
32MX32-900MHZ-MFH
K4J10324QD-HC11
K4J10324QD-HC11
FB_A_DQM_L<3> FB_A_DQM_L<2> FB_A_DQM_L<0> FB_A_DQM_L<1> FB_A_DQ<24> FB_A_DQ<30> FB_A_DQ<29> FB_A_DQ<31> FB_A_DQ<28> FB_A_DQ<27> FB_A_DQ<25> FB_A_DQ<26> FB_A_DQ<20> FB_A_DQ<22> FB_A_DQ<21> FB_A_DQ<23> FB_A_DQ<19> FB_A_DQ<18> FB_A_DQ<16> FB_A_DQ<17> FB_A_DQ<5> FB_A_DQ<4> FB_A_DQ<6> FB_A_DQ<7> FB_A_DQ<2> FB_A_DQ<3> FB_A_DQ<1> FB_A_DQ<0> FB_A_DQ<13> FB_A_DQ<15> FB_A_DQ<14> FB_A_DQ<12> FB_A_DQ<10> FB_A_DQ<9> FB_A_DQ<8> FB_A_DQ<11>
IN IN IN IN BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
72 94 72 94 72 94 72 94
94 73 72 94 73 72 94 72 94 72 94 72
72 94 94 72 72 94 94 73 72 72 94 94 73 72 72 94 94 73 72 72 94 94 73 72 72 94 94 73 72 72 94 94 73 72 72 94 94 73 72 72 94 94 73 72 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 94 72 72 94 94 72 72 94 94 72 72 94 94 72 72 94 72 94 72 94 72 94 72 94 72 94 94 73 72 72 94 94 73 72 72 94 94 73 72 94 72 94 72 94 72 94 72 94 73 72 94 72 94 72 94 73 72 94 73 72 94 73 72 94 73 72
K3 A6 L4 A7 K2 A8/AP M4 A9 K11 A10 L9 A11 H9 CKE
J3 A12/CS1*
J11 J10 F4 H4 F9 H10 A4 A9 V4 V9 CK
FB_A_MA<0> FB_A_MA<1> FB_A_UMA<2> FB_A_UMA<3> FB_A_UMA<4> FB_A_UMA<5> FB_A_MA<6> FB_A_MA<7> FB_A_MA<8> FB_A_MA<9> FB_A_MA<10> FB_A_MA<11> FB_A_CKE FB_A_MA<12> FB_A_CLK_P<1> FB_A_CLK_N<1> FB_A_CS0_L FB_A_WE_L FB_A_CAS_L FB_A_RAS_L FB_A1_ZQ FB_A1_MF FB_A1_SEN
U8450
BGA (1 OF 2)
FB_A_DQM_L<7> FB_A_DQM_L<5> FB_A_DQM_L<6> FB_A_DQM_L<4> FB_A_DQ<59> FB_A_DQ<58> FB_A_DQ<63> FB_A_DQ<60> FB_A_DQ<57> FB_A_DQ<56> FB_A_DQ<61> FB_A_DQ<62> FB_A_DQ<40> FB_A_DQ<47> FB_A_DQ<46> FB_A_DQ<45> FB_A_DQ<42> FB_A_DQ<44> FB_A_DQ<43> FB_A_DQ<41> FB_A_DQ<54> FB_A_DQ<55> FB_A_DQ<53> FB_A_DQ<52> FB_A_DQ<49> FB_A_DQ<51> FB_A_DQ<50> FB_A_DQ<48> FB_A_DQ<36> FB_A_DQ<37> FB_A_DQ<32> FB_A_DQ<38> FB_A_DQ<39> FB_A_DQ<34> FB_A_DQ<33> FB_A_DQ<35>
72 94 72 94 72 94 72 94
72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94
J3 A12/CS1*
J11 J10 F4 H4 F9 H10 A4 A9 V4 V9 CK
94 72 94 72 94 73 72 94 73 72 94 73 72 94 73 72
94 73 72
IN
FB_A_DRAM_RST
CK* CS0* WE* CAS* RAS* ZQ MF SEN RESET
IN
FB_A_DRAM_RST
94 72 94 72 94 72 94 72
OUT FB_A_RDQS<3> OUT FB_A_RDQS<2> OUT FB_A_RDQS<0> OUT FB_A_RDQS<1> IN IN IN IN IN IN IN
D3 RDQS0 D10 RDQS1 P10 RDQS2 P3 RDQS3
OUT FB_A_RDQS<7> OUT FB_A_RDQS<5> OUT FB_A_RDQS<6> OUT FB_A_RDQS<4> IN IN IN IN IN IN IN
DQ22 T11 DQ23 T10 DQ24 M2 DQ25 L3 DQ26 N2 DQ27 M3 DQ28 R2 DQ29 R3 DQ30 T2 DQ31 T3
94 72 94 72
94 72 94 72
FB_A_WDQS<3> FB_A_WDQS<2> FB_A_WDQS<0> FB_A_WDQS<1> FB_A_BA<0> FB_A_BA<1> FB_A_BA<2>
D2 D11 P11 P2
WDQS0 WDQS1 WDQS2 WDQS3 MFHIGH
FB_A_WDQS<7> FB_A_WDQS<5> FB_A_WDQS<6> FB_A_WDQS<4> FB_A_BA<0> FB_A_BA<1> FB_A_BA<2>
D2 D11 P11 P2
GDDR3 Frame Buffer A (Top)

72 94 72 94 72 94 72 94 72 94 72 94
SYNC_MASTER=MUXGFX

94 73 72 94 73 72 94 73 72
G9 BA0 G4 BA1 H3 BA2
NC J2 RFU
NC J2 RFU
R8448 1
243
1% 1/16W MF-LF 402
R8449
100
5% 1/16W MF-LF 402
R8498 1
243
1% 1/16W MF-LF 402 2
R8499
100
SIZE
DRAWING NUMBER
REV.
5% 1/16W MF-LF 402 2
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
73
96
A1 VDDQ0 A12 VDDQ1 C1 VDDQ2 C4 VDDQ3 C9 VDDQ4 C12 VDDQ5 E1 VDDQ6 E4 VDDQ7 E9 VDDQ8 E12 VDDQ9 J4 VDDQ10 J9 VDDQ11 N1 VDDQ12 N4 VDDQ13 N9 VDDQ14 N12 VDDQ15 R1 VDDQ16 R4 VDDQ17 R9 VDDQ18 R12 VDDQ19 V1 VDDQ20 V12 VDDQ21
C8460
0.1uF
10% 16V X5R 402
C8465
0.1uF
10% 16V X5R 402
U8400.J1
U8400.J12

74 73 9 8
=PP1V8_GPU_FB_VDDQ
MFHIGH
MFHIGH
MFHIGH
MFHIGH
8
74 73 8
6
OMIT CRITICAL
5
74 73 8
4
=PP1V8_GPU_FB_VDD
3
OMIT CRITICAL
1 Page Notes
Power aliases required by this page: - =PP1V8_S0_FB_VDD - =PP1V8_S0_FB_VREF_B Signal aliases required by this page: (NONE) BOM options provided by this page: VRAM4
=PP1V8_GPU_FB_VDD
U8500
BGA (2 OF 2)
U8550
BGA (2 OF 2)
C8500
10UF
20% 6.3V X5R 603
C8501
0.1uF
10% 16V X5R 402
C8502
0.1uF
10% 16V X5R 402
C8503
0.1uF
10% 16V X5R 402
C8504
0.1uF
10% 16V X5R 402
C8550
10UF
20% 6.3V X5R 603
C8551
0.1uF
10% 16V X5R 402
C8552
0.1uF
10% 16V X5R 402
C8553
0.1uF
10% 16V X5R 402
C8554
0.1uF
10% 16V X5R 402
K4J10324QD-HC11
32MX32-900MHZ-MFH
32MX32-900MHZ-MFH
K4J10324QD-HC11
D
1
K1 VDDA0 K12 VDDA1
1
K1 VDDA0 K12 VDDA1
C8510
0.1uF
10% 16V X5R 402
C8515
0.1uF
10% 16V X5R 402
U8500.J1
U8500.J12

74 73 9 8
=PP1V8_GPU_FB_VDDQ
C8520
10UF
20% 6.3V X5R 603
C8521
0.1uF
10% 16V X5R 402
C8522
0.1uF
10% 16V X5R 402
C8523
0.1uF
10% 16V X5R 402
C8524
0.1uF
10% 16V X5R 402
C8525
0.1uF
10% 16V X5R 402
C8526
0.1uF
10% 16V X5R 402
C8570
10UF
20% 6.3V X5R 603
C8571
0.1uF
10% 16V X5R 402
C8572
0.1uF
10% 16V X5R 402
C8573
0.1uF
10% 16V X5R 402
C8574
0.1uF
10% 16V X5R 402
C8575
0.1uF
10% 16V X5R 402
C8576
0.1uF
10% 16V X5R 402
74 9
74 9
R8530
549
1% 1/16W MF-LF 402
R8580 1
549
1% 1/16W MF-LF 402
R8533 1
549
2 1% 1/16W MF-LF 402 2
R8583 1
549
2 1% 1/16W MF-LF 402 2
FB_B0_VREF FB_B2_VREF
C
R8531
1.33K
H1 VREF0 H12 VREF1

1
FB_B1_VREF FB_B3_VREF
H1 VREF0 H12 VREF1

1
R8532
931
C8531
0.01uF
10% 16V CERM 402
R8534
1.33K
R8535
931
C8532
0.01uF
10% 16V CERM 402
R8581
1.33K
R8582
931
C8581
0.01uF
10% 16V CERM 402
R8584
1.33K
R8585
931
C8582
0.01uF
10% 16V CERM 402
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
FB_B2_VREF_UNTERM_L FB_B0_VREF_UNTERM_L FB_B_CLK0_TERM VRAM4 VRAM4

1
FB_B3_VREF_UNTERM_L FB_B1_VREF_UNTERM_L FB_B_CLK1_TERM
VOLTAGE=0.9V
1
Q8500
1
Q8500
SSM6N15FEAPE
SOT563
VRAM4
VRAM4
1
VOLTAGE=0.9V
1
Q8550
1
Q8550
SSM6N15FEAPE
SOT563
R8540
1K
5% 1/16W MF-LF 402
R8542
121
1% 1/16W MF-LF 402
R8544
121
1% 1/16W MF-LF 402
R8546
243
1% 1/16W MF-LF 402
C8546
0.01UF
10% 16V CERM 402
SSM6N15FEAPE
SOT563
74 73 72 76
R8590
1K
R8592
121
1% 1/16W MF-LF 402
R8594
121
1% 1/16W MF-LF 402
R8596
243
1% 1/16W MF-LF 402
C8596
0.01UF
10% 16V CERM 402
SSM6N15FEAPE
SOT563
74 73 72 76
IN
FB_VREF_UNTERM
2
2 1
VRAM4
2 1
VRAM4
2 1
5% 1/16W MF-LF 402
IN
FB_VREF_UNTERM
2
2 1
VRAM4
2 1
VRAM4
2 1
R8543
121
R8545
121
R8547
243
R8593
121
R8595
121
R8597
243
1% 1/16W MF-LF 402 2

94 74 72 94 74 72 94 72 94 72 94 72 94 72
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
OMIT CRITICAL
K9 A0 H11 A1 K10 A2 M9 A3 K4 A4 H2 A5
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
OMIT CRITICAL
K9 A0 H11 A1 K10 A2 M9 A3 K4 A4 H2 A5
94 74 72 94 74 72 94 74 72 94 74 72 94 74 72 94 74 72 94 74 72 94 74 72
FB_B_MA<0> FB_B_MA<1> FB_B_LMA<2> FB_B_LMA<3> FB_B_LMA<4> FB_B_LMA<5> FB_B_MA<6> FB_B_MA<7> FB_B_MA<8> FB_B_MA<9> FB_B_MA<10> FB_B_MA<11> FB_B_CKE FB_B_MA<12> FB_B_CLK_P<0> FB_B_CLK_N<0> FB_B_CS0_L FB_B_WE_L FB_B_CAS_L FB_B_RAS_L FB_B0_ZQ FB_B0_MF FB_B0_SEN
U8500
BGA (1 OF 2)
32MX32-900MHZ-MFH
32MX32-900MHZ-MFH
K4J10324QD-HC11
K4J10324QD-HC11
FB_B_DQM_L<1> FB_B_DQM_L<0> FB_B_DQM_L<2> FB_B_DQM_L<3> FB_B_DQ<12> FB_B_DQ<8> FB_B_DQ<11> FB_B_DQ<10> FB_B_DQ<13> FB_B_DQ<15> FB_B_DQ<14> FB_B_DQ<9> FB_B_DQ<6> FB_B_DQ<5> FB_B_DQ<3> FB_B_DQ<4> FB_B_DQ<0> FB_B_DQ<2> FB_B_DQ<1> FB_B_DQ<7> FB_B_DQ<21> FB_B_DQ<16> FB_B_DQ<19> FB_B_DQ<17> FB_B_DQ<20> FB_B_DQ<22> FB_B_DQ<18> FB_B_DQ<23> FB_B_DQ<26> FB_B_DQ<27> FB_B_DQ<31> FB_B_DQ<28> FB_B_DQ<24> FB_B_DQ<25> FB_B_DQ<29> FB_B_DQ<30>
72 94 72 94 72 94 72 94
94 74 72 94 74 72 94 72 94 72 94 72
72 94 94 72 72 94 94 74 72 72 94 94 74 72 72 94 94 74 72 72 94 94 74 72 72 94 94 74 72 72 94 94 74 72 72 94 94 74 72 72 94 94 74 72 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 94 72 72 94 94 72 72 94 94 72 72 94 94 72 72 94 72 94 72 94 72 94 72 94 72 94 94 74 72 72 94 94 74 72 72 94 94 74 72 94 72 94 72 94 72 94 72 94 74 72 94 72 94 72 94 74 72 94 74 72 94 74 72 94 74 72
J3 A12/CS1*
J11 J10 F4 H4 F9 H10 A4 A9 V4 V9 CK
FB_B_MA<0> FB_B_MA<1> FB_B_UMA<2> FB_B_UMA<3> FB_B_UMA<4> FB_B_UMA<5> FB_B_MA<6> FB_B_MA<7> FB_B_MA<8> FB_B_MA<9> FB_B_MA<10> FB_B_MA<11> FB_B_CKE FB_B_MA<12> FB_B_CLK_P<1> FB_B_CLK_N<1> FB_B_CS0_L FB_B_WE_L FB_B_CAS_L FB_B_RAS_L FB_B1_ZQ FB_B1_MF FB_B1_SEN
U8550
BGA (1 OF 2)
FB_B_DQM_L<6> FB_B_DQM_L<5> FB_B_DQM_L<4> FB_B_DQM_L<7> FB_B_DQ<49> FB_B_DQ<50> FB_B_DQ<48> FB_B_DQ<51> FB_B_DQ<53> FB_B_DQ<55> FB_B_DQ<54> FB_B_DQ<52> FB_B_DQ<41> FB_B_DQ<42> FB_B_DQ<40> FB_B_DQ<47> FB_B_DQ<44> FB_B_DQ<45> FB_B_DQ<43> FB_B_DQ<46> FB_B_DQ<34> FB_B_DQ<35> FB_B_DQ<33> FB_B_DQ<32> FB_B_DQ<37> FB_B_DQ<38> FB_B_DQ<39> FB_B_DQ<36> FB_B_DQ<56> FB_B_DQ<57> FB_B_DQ<63> FB_B_DQ<59> FB_B_DQ<58> FB_B_DQ<62> FB_B_DQ<61> FB_B_DQ<60>
72 94 72 94 72 94 72 94
72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94 72 94
J3 A12/CS1*
J11 J10 F4 H4 F9 H10 A4 A9 V4 V9 CK
94 72 94 72 94 74 72 94 74 72 94 74 72 94 74 72
94 74 72
IN
FB_B_DRAM_RST
IN
FB_B_DRAM_RST
94 72 94 72 94 72 94 72
OUT FB_B_RDQS<1> OUT FB_B_RDQS<0>
FB_B_RDQS<2> OUT FB_B_RDQS<3>

OUT IN IN IN IN IN IN IN
OUT FB_B_RDQS<6> OUT FB_B_RDQS<5> OUT FB_B_RDQS<4> OUT FB_B_RDQS<7> IN IN IN IN IN IN IN
94 72 94 72
94 72 94 72
FB_B_WDQS<1> FB_B_WDQS<0> FB_B_WDQS<2> FB_B_WDQS<3> FB_B_BA<0> FB_B_BA<1> FB_B_BA<2>
D2 D11 P11 P2
FB_B_WDQS<6> FB_B_WDQS<5> FB_B_WDQS<4> FB_B_WDQS<7> FB_B_BA<0> FB_B_BA<1> FB_B_BA<2>
D2 D11 P11 P2
GDDR3 Frame Buffer B (Top)

72 94 72 94 72 94 72 94 72 94 72 94
SYNC_MASTER=MUXGFX

94 74 72 94 74 72 94 74 72
NC J2 RFU
NC J2 RFU
R8548 1
243
1% 1/16W MF-LF 402
R8549
100
5% 1/16W MF-LF 402
R8598 1
243
1% 1/16W MF-LF 402
R8599
100
5% 1/16W MF-LF 402
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
74
96
C8560
0.1uF
10% 16V X5R 402
C8565
0.1uF
10% 16V X5R 402
U8500.J1
U8500.J12

74 73 9 8
=PP1V8_GPU_FB_VDDQ
MFHIGH
MFHIGH
MFHIGH
MFHIGH
8 Page Notes
Power aliases required by this page: - =PP3V3_GPU_VDD33 - =PP3V3_GPI_MIO - =PP1V2_GPU_PLLVDD - =PP1V2_GPU_H_PLLVDD - =PP1V2_GPU_VID_PLLVDD Signal aliases required by this page: (NONE)
7
110mA
76 75 8 6
6
=PP3V3_GPU_VDD33
5
OMIT
4
U8000
NB9P-GS
BGA
J9 J10 J11 J12 J13
1 2
C8690
0.022UF
10% 16V CERM-X5R 402
1 2
C8692
0.022UF
10% 16V CERM-X5R 402
1 2
C8694
0.1UF
20% 10V CERM 402
1 2
C8696
0.47UF
10% 6.3V CERM-X5R 402
C8698
402
1UF 10% 2 6.3V CERM
VDD33_1 VDD33_2 VDD33_3 VDD33_4 VDD33_5
SYMBOL 6 OF 9
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23
K1 K2 K3 H3 H2 H1 H4 H5 H6 J7 K4 K5 H7 J4 J6 L1 L2 L4 M4 L7 L5 K6 L6 M6 C7 B7 A7 D7 D6 A5 A4
1
76 75 8 6
C8691
0.022UF
10% 16V CERM-X5R 402
1 2
C8693
0.022UF
10% 16V CERM-X5R 402
1 2
C8695
0.1UF
20% 10V CERM 402
1 2
NC
J25 J26
RFU0 RFU1 RFU0_GND RFU1_GND
C8697
0.47UF
10% 6.3V CERM-X5R 402
NC
=PP3V3_GPU_VDD33 Typically <??mA 2
AK14 K9
C8600
0.47UF
10% 6.3V CERM-X5R 402
C8601
0.47UF
10% 6.3V CERM-X5R 402
C8602
0.47UF
10% 6.3V CERM-X5R 402
76 76 76 76
D4 D3 C4
BI BI BI BI BI BI BI OUT OUT OUT OUT OUT IN
76 76 76 76 76 76 76
R8696
40.2K
R8697
40.2K
GPU_STRAP_REF_3V3_PD GPU_STRAP_REF_MIOB_PD
N9 M9
1% 1/16W MF-LF 2 402
1% 1/16W MF-LF 2 402
STRAP_REF_3V3 STRAP_REF_MIOB (IPD) MIOA_VDDQ_1 MIOA_VDDQ_2 MIOA_VDDQ_3 MIOA_VDDQ_4 MIOB_VDDQ_1 MIOB_VDDQ_2 MIOB_VDDQ_3 MIOB_VDDQ_4 TESTMODE MIOA_VREF MIOB_VREF MIOA_CAL_PD_VDDQ MIOA_CAL_PU_GND MIOB_CAL_PD_VDDQ MIOB_CAL_PU_GND
76 75 8
=PP3V3_GPU_MIO
P9 R9 T9 U9
2
76 75 8
=PP3V3_GPU_MIO
HDA_SDI HDA_SDO HDA_SYNC HDA_BCLK HDA_RST* SPDIF BUFRST*
GPU_HDA_SDI GPU_HDA_SDO GPU_HDA_SYNC GPU_HDA_BCLK GPU_HDA_RST_L GPU_SPDIF TP_GPU_BUFRST_L
76 76 76 76 76
C8610
1UF
C8611
1UF
10% 6.3V CERM 402
76
R8620 1
49.9
1% 1/16W MF-LF 402
R8621
49.9
1% 1/16W MF-LF 402
10% 6.3V CERM 402
OUT
AA9 AB9 W9 Y9
C
6 6 6 6 6
R8616 1
10K
75 75
R8618
10K
5% 1/16W MF-LF 402
GPU_MIOA_PD_VDDQ GPU_MIOB_PD_VDDQ GPU_MIOA_PU_GND GPU_MIOB_PU_GND
5% 1/16W MF-LF 402
GPU_TESTMODE_PD
GPU_MIOA_VREF GPU_MIOB_VREF
AP35 N5 AF1 U5 T5 AA7 AA6
75 75
JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST* MIOA_CLKIN MIOA_CLKOUT MIOA_CLKOUT* MIOA_CTL3 MIOA_DE MIOA_D0 MIOA_D1 MIOA_D2 MIOA_D3 MIOA_D4 MIOA_D5 MIOA_D6 MIOA_D7 MIOA_D8 MIOA_D9 MIOA_D10 MIOA_D11 MIOA_D12 MIOA_D13 MIOA_D14 MIOA_HSYNC MIOA_VSYNC MIOB_CLKIN MIOB_CLKOUT MIOB_CLKOUT* MIOB_CTL3 MIOB_DE MIOB_D0 MIOB_D1 MIOB_D2 MIOB_D3 MIOB_D4 MIOB_D5 MIOB_D6 MIOB_D7 MIOB_D8 MIOB_D9 MIOB_D10 MIOB_D11 MIOB_D12 MIOB_D13 MIOB_D14 MIOB_D15 MIOB_D16 MIOB_D17 MIOB_HSYNC MIOB_VSYNC THERMDP THERMDN PGOOD_OUT*
AP14 AN14 AN16 AR14 AP16 N4 R4 T4 P5 N2 N1 P4 P1 P2 P3 T3 T2 T1 U4 U1 U2 U3 R6 T6 N6 N3 L3 AE1 V4 W4 W3 Y5 Y1 Y2 Y3 AB3 AB2 AB1 AC4 AC1 AC2 AC3 AE3 AE2 U6 W6 Y6 W5 W7 V7 W1 W2 B5 B4 C5
GPU_JTAG_TCK GPU_JTAG_TDI GPU_JTAG_TDO GPU_JTAG_TMS GPU_JTAG_TRST_L GPU_MIOA_CLKIN GPU_MIOA_CLKOUT_P GPU_MIOA_CLKOUT_N GPU_MIOA_CTL3 GPU_MIOA_DE GPU_MIOA_D<0> GPU_MIOA_D<1> GPU_MIOA_D<2> GPU_MIOA_D<3> GPU_MIOA_D<4> GPU_MIOA_D<5> GPU_MIOA_D<6> GPU_MIOA_D<7> GPU_MIOA_D<8> GPU_MIOA_D<9> GPU_MIOA_D<10> GPU_MIOA_D<11> GPU_MIOA_D<12> GPU_MIOA_D<13> GPU_MIOA_D<14> GPU_MIOA_HSYNC GPU_MIOA_VSYNC GPU_MIOB_CLKIN GPU_MIOB_CLKOUT_P GPU_MIOB_CLKOUT_N GPU_MIOB_CTL3 GPU_MIOB_DE GPU_MIOB_D<0> GPU_MIOB_D<1> GPU_MIOB_D<2> GPU_MIOB_D<3> GPU_MIOB_D<4> GPU_MIOB_D<5> GPU_MIOB_D<6> GPU_MIOB_D<7> GPU_MIOB_D<8> GPU_MIOB_D<9> GPU_MIOB_D<10> GPU_MIOB_D<11> GPU_MIOB_D<12> GPU_MIOB_D<13> GPU_MIOB_D<14> GPU_STRAP<0> GPU_STRAP<1> GPU_STRAP<2> GPU_MIOB_HSYNC GPU_MIOB_VSYNC GPU_THERMD_P GPU_THERMD_N TP_GPU_PGOOD_OUT_L
IN IN OUT IN IN IN BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI IN BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI IN OUT OUT
76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76
R8622 1
49.9
1% 1/16W MF-LF 402
R8623
49.9
1% 1/16W MF-LF 402
R8617 1
10K
5% 1/16W MF-LF 402
1 1
C8617
0.1uF
10% 16V X5R 402
R8619
10K
5% 1/16W MF-LF 402
1
1
C8619
0.1uF
10% 16V X5R 402
R8660
10K
5% 1/16W MF-LF 402
75 75
GPU_MIOA_PD_VDDQ GPU_MIOA_PU_GND GPU_MIOB_PD_VDDQ GPU_MIOB_PU_GND
2 2
75 75
AF9
L8630
8
SP_PLLVDD PLLVDD VID_PLLVDD
=PP1V1_GPU_PLLVDD
FERR-220-OHM
1 0402 2
AE9
PP1V1_GPU_PLLVDD_F
65mA
AD9
1 1
C8633
4.7UF
20% 6.3V CERM 603
C8630
4.7UF
20% 6.3V CERM 603
C8631
0.1uF
10% 16V X5R 402
B
L8635
8
=PP1V1_GPU_H_PLLVDD
FERR-220-OHM
1 0402 2
PP1V1_GPU_H_PLLVDD_F
25mA
76 76
IN OUT
GPU_XTALIN GPU_XTALOUT
B1 B2
XTAL_IN XTAL_OUT
76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76
C8637
4.7UF
20% 6.3V CERM 603
C8635
4.7UF
20% 6.3V CERM 603
C8636
0.1uF
10% 16V X5R 402
76
OUT IN
GPU_XTALOUTBUFF GPU_XTALSSIN
D1 D2
XTAL_OUTBUFF XTAL_SSIN
76
L8640
8
=PP1V1_GPU_VID_PLLVDD
FERR-220-OHM
1 0402 2
PP1V1_GPU_VID_PLLVDD_F
50mA
C8643
4.7UF
20% 6.3V CERM 603
C8640
4.7UF
20% 6.3V CERM 603
C8641
0.1uF
10% 16V X5R 402
NV G96 GPIO/MIO/Misc

76 76
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
75
96
GPU_ROM_CS_L GPU_ROM_SCLK GPU_ROM_SI GPU_ROM_SO
C3
ROM_CS* ROM_SCLK ROM_SI ROM_SO
GPU_GPIO_0 GPU_GPIO_1 GPU_GPIO_2 GPU_GPIO_3 GPU_GPIO_4 GPU_GPIO_5 GPU_GPIO_6 GPU_GPIO_7 GPU_GPIO_8 GPU_GPIO_9 GPU_GPIO_10 GPU_GPIO_11 GPU_GPIO_12 GPU_GPIO_13 GPU_GPIO_14 GPU_GPIO_15 GPU_GPIO_16 GPU_GPIO_17 GPU_GPIO_18 GPU_GPIO_19 GPU_GPIO_20 GPU_GPIO_21 GPU_GPIO_22 GPU_GPIO_23
BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI
76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76 76
8
Native Func
75
7
GPIOs
NC_GPU_GPIO_0
MAKE_BASE=TRUE
75
6
Native Func GPU_GPIO_15 GPU_GPIO_16 GPU_GPIO_17 GPU_GPIO_18 GPU_GPIO_19 GPU_GPIO_20 GPU_GPIO_21 GPU_GPIO_22 GPU_GPIO_23 HPDE DVI_MODE0 HDMI_DETECT0 DVI_MODE1 HDMI_DETECT1 HPDD HPDF SWAPRDY_A GP
5
GPIOs
NC_GPU_GPIO_15
MAKE_BASE=TRUE
76 75
4
GPU_XTALOUT
MAKE_BASE=TRUE
94 76
3
Renamed signals
GPU_XTALOUT GPU_XTALIN GPU_XTALSSIN GPU_THERMD_P GPU_THERMD_N
75 76
2
Unused signals
NC_GPU_SPDIF
MAKE_BASE=TRUE
75
1
GPU_SPDIF
NO_TEST=TRUE
75
GPU_GPIO_0 GPU_GPIO_1 GPU_GPIO_2 GPU_GPIO_3 GPU_GPIO_4 GPU_GPIO_5 GPU_GPIO_6 GPU_GPIO_7
GP HPDC LCD0_BL_PWM LCD0_VDD LCD0_BL_EN VID0 VID1 VID2/MEM_VID
GPU_CLK27M
MAKE_BASE=TRUE
NC_CPU_HDA_SDI
GPU_HDA_SDI GPU_HDA_SDO
NO_TEST=TRUE
75
75
DP_EG_HPD
MAKE_BASE=TRUE
IN
80
75
EG_DP_CA_DET
NC_GPU_GPIO_17
MAKE_BASE=TRUE
76
94
GPU_CLK27M_SS
MAKE_BASE=TRUE
75 76
NC_CPU_HDA_SD0
MAKE_BASE=TRUE
75
75
TP_LVDS_EG_BKL_PWM
MAKE_BASE=TRUE
75
95 48
GPU_TDIODE_P
MAKE_BASE=TRUE
75
NC_CPU_HDA_SYNC
GPU_HDA_SYNC GPU_HDA_BCLK
NO_TEST=TRUE
75
75
EG_LCD_PWR_EN
MAKE_BASE=TRUE
76 83
75
NC_GPU_GPIO_18
MAKE_BASE=TRUE
95 48
GPU_TDIODE_N
MAKE_BASE=TRUE
75
NC_CPU_HDA_BCLK
MAKE_BASE=TRUE
75
75
EG_BKLT_EN
MAKE_BASE=TRUE
76 83
75
NC_GPU_GPIO_19
MAKE_BASE=TRUE
NC_CPU_HDA_RST_L
MAKE_BASE=TRUE
80
GPU_HDA_RST_L
NO_TEST=TRUE
75
75
TP_GPU_GSTATE<0>
MAKE_BASE=TRUE
75
NC_GPU_GPIO_20
MAKE_BASE=TRUE
LVDS_EG_DDC_CLK
MAKE_BASE=TRUE
GPU_I2CA_SCL GPU_I2CA_SDA GPU_I2CB_SCL GPU_I2CB_SDA
77
NC_FBA_MA<13>
FB_A_MA<13> FB_B_MA<13>
NO_TEST=TRUE
72
75
TP_GPU_GSTATE<1>
MAKE_BASE=TRUE
75
NC_GPU_GPIO_21
MAKE_BASE=TRUE
80
LVDS_EG_DDC_DATA
MAKE_BASE=TRUE
77
NC_FBB_MA<13>
MAKE_BASE=TRUE
72
75
GPIO7_FBVDD_ALTVO
MAKE_BASE=TRUE
76 82
75
NC_GPU_GPIO_22
MAKE_BASE=TRUE
80 76
DP_EG_DDC_CLK
MAKE_BASE=TRUE
77
NC_FBA_CMD28
TP_FBA_CMD28 TP_FBC_CMD28
NO_TEST=TRUE
72
75
NC_GPU_GPIO_23
80 76
DP_EG_DDC_DATA
MAKE_BASE=TRUE
77
NC_FBC_CMD28
MAKE_BASE=TRUE
72
75
GPU_GPIO_8 GPU_GPIO_9 GPU_GPIO_10 GPU_GPIO_11 GPU_GPIO_12 GPU_GPIO_13 GPU_GPIO_14
THERM FAN_PWM MEM_VREF SLI_SYNC AC_DET PWR_CTL0 PWR_CTL1
SMC_GFX_OVERTEMP_R_L
MAKE_BASE=TRUE
76
Unused I2C Buses

NC_GPU_I2CC_SCL
NC_FBA_CMD29
NO_TEST=TRUE
72
75
SMC_GFX_THROTTLE_R_L
MAKE_BASE=TRUE
76
NC_FBC_CMD29
MAKE_BASE=TRUE
72
75
FB_VREF_UNTERM
MAKE_BASE=TRUE
72 73 74 76
GPU_I2CC_SCL GPU_I2CC_SDA
NO_TEST=TRUE
77
NC_FBA_CMD30
NO_TEST=TRUE
72
75
GPU_VCORE_VID0
MAKE_BASE=TRUE
OUT OUT OUT
78
NC_GPU_I2CC_SDA
MAKE_BASE=TRUE
77
NC_FBC_CMD30
MAKE_BASE=TRUE
72
75
GPU_VCORE_VID1
MAKE_BASE=TRUE
78
NC_GPU_I2CD_SCL
GPU_I2CD_SCL GPU_I2CD_SDA
NO_TEST=TRUE
77
NC_GPU_ROM_CS_L
GPU_ROM_CS_L FB_A_CS1_L
NO_TEST=TRUE
75
75
GPU_VCORE_VID2
MAKE_BASE=TRUE
78
NC_GPU_I2CD_SDA
MAKE_BASE=TRUE
77
NC_FB_A_CS1_L
MAKE_BASE=TRUE
72
75
TP_GPU_VCORE_VID3
MAKE_BASE=TRUE
NC_GPU_I2CE_SCL
GPU_I2CE_SCL GPU_I2CE_SDA
NO_TEST=TRUE
77
NC_FB_B_CS1_L
FB_B_CS1_L
72
Config Straps
Physical Strapping Pin
76 75 8
NC_GPU_I2CE_SDA
MAKE_BASE=TRUE
77
NC_GPU_I2CH_SCL
GPU_I2CH_SDA
NO_TEST=TRUE
77
Strapping Bit 3 XCLK_277 PCI_DEVID[4] RAMCFG[3] PCI_DEVID[3] 3GIO_PADCFG[3] USER[3]
Strapping Bit 2 TVMODE[2] SUB_VENDOR RAMCFG[2] PCI_DEVID[2] 3GIO_PADCFG[2] USER[2]
Strapping Bit 1 TVMODE[1] SLOT_CLK_CFG RAMCFG[1] PCI_DEVID[1] 3GIO_PADCFG[1] USER[1]
Strapping Bit 0 TVMODE[0] PEX_PLLEN_TERM100 RAMCFG[0] PCI_DEVID[0] 3GIO_PADCFG[0] USER[0]
MAKE_BASE=TRUE
NC_GPU_I2CH_SDA
GPU_I2CH_SCL
I2CS ties into SMBus connection page (I2CS requires pullups even if not used)
77
TP_LVDS_EG_B_CLK_P
MAKE_BASE=TRUE
LVDS_EG_B_CLK_P LVDS_EG_B_CLK_N LVDS_EG_A_DATA_P<3>

NO_TEST=TRUE
77
=PP3V3_GPU_MIO
OMIT NO STUFF
ROM_SO ROM_SCLK ROM_SI STRAP 2

2
TP_LVDS_EG_B_CLK_N
MAKE_BASE=TRUE
77
NC_LVDS_EG_A_DATA_P<3>
MAKE_BASE=TRUE
77
R87071
2.0K
5% 1/16W MF-LF 402
R87091
4.99K
1% 1/16W MF-LF 402
R87111
4.99K
1% 1/16W MF-LF 402
NC_LVDS_EG_A_DATA_N<3>
LVDS_EG_A_DATA_N<3> LVDS_EG_B_DATA_P<3>
NO_TEST=TRUE
77
NC_LVDS_EG_B_DATA_P<3>
MAKE_BASE=TRUE
77
C
75 75 75
STRAP 1 STRAP 0
NC_LVDS_EG_B_DATA_N<3>
LVDS_EG_B_DATA_N<3>
77
OUT GPU_ROM_SI IN IN
GPU_ROM_SO GPU_ROM_SCLK OMIT NO STUFF

1
R8708
45.3K
R8710
2.0K
R8712
15.0K
1% 1/16W MF-LF 402 2
5% 1/16W MF-LF 402 2
1% 1/16W MF-LF 402 2
Strap S1/S2 Bit[3:0] PU/PD Rval 0 0000 PD 5k 1 0001 PD 10k 2 0010 PD 15k 3 0011 PD 20k 4 0100 PD 25k 5 0101 PD 30k 6 0110 PD 35k 7 0111 PD 45k
Strap S1/S2 Bit[3:0] PU/PD Rval 8 1000 PU 5k 9 1001 PU 10k A 1010 PU 15k B 1011 PU 20k C 1100 PU 25k D 1101 PU 30k E 1110 PU 35k F 1111 PU 45k
G96 MIOA_DE and MIOA_D<9..0> are used as Debug Port.
NC_GPU_MIOA_CLKOUT_P
GPU_MIOA_CLKOUT_P GPU_MIOA_CLKOUT_N
NO_TEST=TRUE
75
NC_GPU_MIOA_CLKOUT_N
MAKE_BASE=TRUE
75
NC_GPU_MIOA_CTL3
GPU_MIOA_CTL3 GPU_MIOA_DE GPU_MIOA_D<9..0> GPU_MIOA_CLKIN

NO_TEST=TRUE
75
TP_GPU_MIOA_DE
MAKE_BASE=TRUE
75
TP_GPU_MIOA_D<9..0>
MAKE_BASE=TRUE
75
NC_GPU_MIOA_CLKIN
MAKE_BASE=TRUE
75
76 75 8
=PP3V3_GPU_MIO
NO STUFF NO STUFF
NC_GPU_MIOA_D<14..10>
GPU_MIOA_D<14..10> GPU_MIOA_HSYNC
NO_TEST=TRUE
75
R87011
45.3K
1% 1/16W MF-LF 402 2
R87031
10K
1% 1/16W MF-LF 402 2
R87051
10K
1% 1/16W MF-LF 402 2
PART NUMBER
114S0378 114S0361 114S0343
QTY
1 1 1 1 1 1
DESCRIPTION
RES,MTL FILM,1/16W,45.3K,1,0402,SMD,LF
REFERENCE DES
R8708 R8708 R8708 R8708 R8707 R8707
CRITICAL
BOM OPTION
VRAM_512_SAMSUNG VRAM_512_QIMONDA VRAM_256_SAMSUNG VRAM_256_HYNIX VRAM_1024_SAMSUNG VRAM_1024_QIMONDA
NC_GPU_MIOA_HSYNC
MAKE_BASE=TRUE
75
NC_GPU_MIOA_VSYNC
GPU_MIOA_VSYNC GPU_MIOB_CLKIN
NO_TEST=TRUE
75
G96 HDCP ROM APN is 341S2272, blank device is 335S0574.
NC_GPU_MIOB_CLKIN
MAKE_BASE=TRUE
75
NC_GPU_MIOB_CLKOUT_P
GPU_MIOB_CLKOUT_P GPU_MIOB_CLKOUT_N
NO_TEST=TRUE
75
75
BI BI BI
GPU_STRAP<0> 114S0331 GPU_STRAP<1> 114S0378 GPU_STRAP<2> 114S0361 NO STUFF

RES,MTL FILM,1/16W,30.1K,1,0402,SMD,LF RES,MTL FILM,1/16W,45.3K,1,0402,SMD,LF RES,MTL FILM,1/16W,15.0K,1,0402,SMD,LF
75
GPU 27MHz Crystal

R8783 C8780
12pF
1 2 5% 50V CERM 402 GPU_CLK27M 1 1
NC_GPU_MIOB_CLKOUT_N
MAKE_BASE=TRUE
75
NC_GPU_MIOB_CTL3
GPU_MIOB_CTL3 GPU_MIOB_DE
NO_TEST=TRUE NO_TEST=TRUE
75
75
NC_GPU_MIOB_DE
MAKE_BASE=TRUE
75
R8702
2.0K
R8704
10K
1% 1/16W MF-LF 402
R8706
45.3K
1% 1/16W MF-LF 402
1
79 8 7
NC_GPU_MIOB_D<14..0>
MAKE_BASE=TRUE
GPU_MIOB_D<14..0> GPU_MIOB_VSYNC
75
5% 1/16W MF-LF 402 2
=PP3V3_S0_DDC_LCD =PP3V3_GPU_VDD33
94 76
IN
GPU_CLK27M_XTALOUT_R
3
NC_GPU_MIOB_VSYNC
75
NO STUFF
5% 1/16W MF-LF 402 2
Y8780
27MHZ
1 SM-2
2 4
76 75 8 6
R8782
10M
5% 1/16W MF-LF 402
CRITICAL
NC_GPU_MIOB_HSYNC
GPU_MIOB_HSYNC
75
NC NC
C8781
12pF
1 2
76 75 75
R8750
4.7K
5% 1/16W MF-LF 402
R8751
4.7K
5% 1/16W MF-LF 402
R8752
4.7K
5% 1/16W MF-LF 402
R8753
4.7K
5% 1/16W MF-LF 402
1
76 75
OUT
GPU_XTALOUT
Unused Clocks
GPU_XTALSSIN GPU_XTALOUTBUFF GPU_SS_INT
76 75 8 6
=PP3V3_GPU_VDD33 R8796
1
5% 50V CERM 402
R8797
2.2K
5% 1/16W MF-LF 402
R8780 1
10K
5% 1/16W MF-LF 402
R8781 1
10K
5% 1/16W MF-LF 402
80 76
IN BI IN BI
DP_EG_DDC_CLK DP_EG_DDC_DATA DP_IG_DDC_CLK DP_IG_DDC_DATA

76
2.2K
5% 1/16W MF-LF 402 2
80 76 76 75 8 6
=PP3V3_GPU_VDD33
DP_CA_DET_EG_FET DP_CA_DET_EG_FET 1
80 9
Q8742
SOD-VESM-HF
SMC_GFX_OVERTEMP_R_L SMC_GFX_THROTTLE_R_L
80 9
R8742
100K
76
R8798 R8799
0 0
1 1
SMC_GFX_OVERTEMP_L 5% 1/16W 5% MF-LF 402 SMC_GFX_THROTTLE_L 1/16W MF-LF 402 EG_LCD_PWR_EN EG_BKLT_EN
42
42
1% 1/16W MF-LF 402 2
SSM3K15FV
76 83
76 83
G96 GPIOs & Straps

76
EG_DP_CA_DET
2
DP_CA_DET
IN
80 81 83
GPIO7_FBVDD_ALTVO FB_VREF_UNTERM
76 82
72 73 74 76

R8743
1
R8792
DP_CA_DET_EG
IN
83
R8793
1K
5% 1/16W MF-LF 402
R8794
1K
5% 1/16W MF-LF 402
NO STUFF 1
R8795
1K
5% 1/16W MF-LF 402
1K
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 402 DP_CA_DET_EG_PLD
Isolation FETs for DP MUX inputs

8 7 6 5 4 3
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
76
96
7
Sum of peak currents: 240mA
8
6
L8800
FERR-220-OHM
1 2
5
?mA peak per diff pair ?mA peak for all pairs
Page Notes
Power aliases required by this page: - =PP1V8_GPU_IFPX - =PP3V3_GPU_IFPCD_IOVDD =PP1V8_GPU_IFPX PP1V8_GPU_IFPAB_IOVDD_F
0402
Signal aliases required by this page: (NONE) BOM options provided by this page: (NONE)
C8800
4.7UF
20% 6.3V CERM 603
C8801
0.1UF
20% 10V CERM 402
C8803
0.1UF
20% 10V CERM 402
OMIT
2
U8000
NB9P-GS
BGA
AG9 AG10 AJ8 AK8 AE7 AD7
AK9
77
Place at AG9
Place at AG10
D
GPU_IFPEF_RSET GPU_IFPCD_RSET GPU_IFPAB_RSET
L8805
77 77 77
77
PP1V1_GPU_IFPCD_IOVDD_F PP1V1_GPU_IFPEF_IOVDD_F
FERR-220-OHM
1 2
80mA peak
PP1V8_GPU_IFPAB_PLLVDD_F
1
77
0402
C8805
4.7UF
20% 6.3V CERM 603
C8806
0.1UF
20% 10V CERM 402
GPU_IFPAB_RSET PP1V8_GPU_IFPCD_PLLVDD_F GPU_IFPCD_RSET PP1V8_GPU_IFPEF_PLLVDD_F GPU_IFPEF_RSET
AJ11 AJ9 AK7 AJ6 AL1
2
77 77
R8855
1K
R8850
1K
R8851
1K
1% 1/16W MF-LF 2 402
1% 1/16W MF-LF 2 402
1% 1/16W MF-LF 2 402
AP13 AN13 AN8 AP8 AP10 AN10 AR11 AR10 AN11 AP11 AP2 AN3 AM7 AM6 AL5 AM5 AM3 AM4 AP1 AR2 AP4
77 77
LVDS_EG_B_CLK_P LVDS_EG_B_CLK_N LVDS_EG_B_DATA_P<0> LVDS_EG_B_DATA_N<0> LVDS_EG_B_DATA_P<1> LVDS_EG_B_DATA_N<1> LVDS_EG_B_DATA_P<2> LVDS_EG_B_DATA_N<2> LVDS_EG_B_DATA_P<3> LVDS_EG_B_DATA_N<3> DP_EG_AUX_CH_P DP_EG_AUX_CH_N DP_EG_ML_P<0> DP_EG_ML_N<0> DP_EG_ML_P<1> DP_EG_ML_N<1> DP_EG_ML_P<2> DP_EG_ML_N<2> DP_EG_ML_P<3> DP_EG_ML_N<3>
76 76
83 94 83 94 83 94 83 94 83 94 83 94 76 76
L8810
FERR-220-OHM
8
=PP1V1_GPU_IFPCD_IOVDD
?mA peak per diff pair ?mA peak for all pairs
PP1V1_GPU_IFPCD_IOVDD_F
77
0402
C8810
4.7UF
20% 6.3V CERM 603
C8811
0.1UF
20% 10V CERM 402
C8813
0.1UF
20% 10V CERM 402

76 76
BI BI
GPU_I2CA_SCL GPU_I2CA_SDA
G1 G4
Place at AJ8
Place at AK8
76 76
IFPC_AUX IFPC_AUX*
BI BI
80 94
80 94 80 94
L8815
FERR-220-OHM
1 2
I2CS must be pulled up if not used I2CS addr fixed at 0x9E,0x9F 160mA peak
GPU_I2CC_SCL GPU_I2CC_SDA
E3 E4
I2CC_SCL I2CC_SDA
PP1V8_GPU_IFPCD_PLLVDD_F
1
77
0402
C8815
4.7UF
20% 6.3V CERM 603
C8816
0.1UF
20% 10V CERM 402
45 45
BI BI
=GPU_I2CS_SCL =GPU_I2CS_SDA
E2 E1
I2CS_SCL I2CS_SDA
PP1V1_GPU_IFPEF_IOVDD_F PP1V8_GPU_IFPEF_PLLVDD_F
77
I2CS must be pulled up if not used. I2CS addr fixed at 0x9E,0x9F

76
IFPC_L0 IFPC_L0* IFPC_L1 IFPC_L1* IFPC_L2 IFPC_L2* IFPC_L3 IFPC_L3* IFPD_AUX IFPD_AUX*
NO STUFF
80 94 80 94 80 94 80 94 80 94 80 94 80 94
R8861
1K
5% 1/16W MF-LF 402
R8860
1K
5% 1/16W MF-LF 402
77
BI BI
Power inputs must be pulled down if not used

1
76
GPU_I2CH_SCL GPU_I2CH_SDA
F6 G6
NC AN4 NC
AR8 NC AR7 AP7 AN7 NC AN5 AP5 NC AR5 AR4 AE4 AD4
I2CH_SCL I2CH_SDA
R8856
10K
R8857
10K
76 76
5% 1/16W MF-LF 2 402
5% 1/16W MF-LF 2 402
BI BI
GPU_I2CB_SCL GPU_I2CB_SDA
G3 G2
I2CB_SCL I2CB_SDA
IFPD_L0 IFPD_L0* IFPD_L1 IFPD_L1* IFPD_L2 IFPD_L2* IFPD_L3 IFPD_L3* IFPE_AUX IFPE_AUX* IFPE_L0 IFPE_L0* IFPE_L1 IFPE_L1* IFPE_L2 IFPE_L2* IFPE_L3 IFPE_L3* IFPF_AUX IFPF_AUX* IFPF_L0 IFPF_L0* IFPF_L1 IFPF_L1* IFPF_L2 IFPF_L2* IFPF_L3 IFPF_L3*
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC
76 76
BI BI
GPU_I2CD_SCL GPU_I2CD_SDA
F4 G5
I2CD_SCL I2CD_SDA
AH6 NC AH5 AH4 AG4 NC AF4 AF5 NC AE6 AE5 AF3 AF2
76 76
BI BI
GPU_I2CE_SCL GPU_I2CE_SDA
D5 E5
I2CE_SCL I2CE_SDA
AL2 NC AL3 AJ3 AJ2 NC AJ1 AH1 NC AH2 AH3
AJ12
DACA_VDD
DACA_RED DACA_GREEN DACA_BLUE DACA_HSYNC DACA_VSYNC
AM15 NC AM14 AL14 AM13 AL13
NC NC NC NC NC NC NC
NC AK13 NC
GPU_DACA_VDD GPU_DACB_VDD GPU_DACC_VDD
AC6
AK12
DACA_VREF DACA_RSET
DACB_VDD
AC5 NC AB6
R8852
10K
5% 1/16W MF-LF 402
R8853
10K
5% 1/16W MF-LF 402
R8854
10K
5% 1/16W MF-LF 402
NC
DACB_VREF DACB_RSET DACC_VDD
DACB_RED DACB_GREEN DACB_BLUE DACB_CSYNC DACC_RED DACC_GREEN DACC_BLUE DACC_HSYNC DACC_VSYNC
AA4
AB4 NC Y4 AB5
NV G96 Video Interfaces

AG7
AK4 NC AL4

NC AJ4 NC
AM1 AM2
NC AH7 NC
AK6
DACC_VREF DACC_RSET
NC NC
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
77
96
SYMBOL 5 OF 9 IFPA_IOVDD IFPA_TXC IFPB_IOVDD IFPA_TXC* IFPC_IOVDD IFPA_TXD0 IFPD_IOVDD IFPA_TXD0* IFPE_IOVDD IFPA_TXD1 IFPF_IOVDD IFPA_TXD1* IFPAB_PLLVDD IFPA_TXD2 IFPAB_RSET IFPA_TXD2* IFPA_TXD3 IFPCD_PLLVDD IFPA_TXD3* IFPCD_RSET IFPB_TXC IFPEF_PLLVDD IFPB_TXC* IFPEF_RSET IFPB_TXD4 IFPB_TXD4* IFPB_TXD5 IFPB_TXD5* IFPB_TXD6 IFPB_TXD6* I2CA_SCL I2CA_SDA IFPB_TXD7 IFPB_TXD7*
AM11 AM12 AM8 AL8
LVDS_EG_A_CLK_P LVDS_EG_A_CLK_N LVDS_EG_A_DATA_P<0> LVDS_EG_A_DATA_N<0> LVDS_EG_A_DATA_P<1> LVDS_EG_A_DATA_N<1> LVDS_EG_A_DATA_P<2> LVDS_EG_A_DATA_N<2> LVDS_EG_A_DATA_P<3> LVDS_EG_A_DATA_N<3>
83 94 83 94
83 94 83 94 83 94 83 94 83 94 83 94 76 76
AM10 AM9 AK10 AL10 AK11 AL11
8
8
7
R8911
1
GPU VCore Regulator

=PP5V_S3_GPUVCORE 1
2
PP5V_S5_GFXIMVP6_PVCC
5% 1/16W MF-LF 402
C8902 1
20% 6.3V X5R-CERM 2 402
C8903
0.01uF CRITICAL CRITICAL
8
4.7UF
10% 2 16V CERM 402
=PPVIN_GPU_GPUVCORE
C8931 1 R8904
22UF
C8930 1
22UF
10
PP5V_S5_GFXIMVP6_VDD
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM VOLTAGE=5V 1
C8932 1UF 10% C8933 1 2 25V

1 X5R 603-1 10% 25V 2 X5R 603-1
C8934
1000PF
1UF
1% 1/16W MF-LF 402
10% 2 25V X7R 402
C8901
1uF
10% 2 10V X5R 402
R89301
VDD PVCC
R8905
2
150K 1
1% 1/16W MF-LF 402
CRITICAL GFXIMVP6_RBIAS
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM RBIAS
U8900
QFN
VIN
GFXIMVP6_VIN
5% 1/16W MF-LF 402 2
1K
2 10% 16V X5R 402

47
GFXIMVP6_SOFT
LFPAK-HF
SOFT BOOT
GFXIMVP6_BOOT
C8956 1
0.22UF
10% 16V 2 X7R 603
GFXIMVP6_IMON
IMON PGOOD VID0 VID1 VID2 VID3 VID4 VR_ON AF_EN FDE
1 2 3
CRITICAL 0.68UH-16A
1 PCMB065T-SM 2
R8940
0.001
1% 1W MF 1206
68 78 8
OUT
78 78
=PP3V3_GPU_VCORELOGIC
R8907
10K
R8910
10K
83 68
78 78 78
5% 1/16W MF-LF 402 2
5% 1/16W MF-LF 2 402
IN
GPUVCORE_PGOOD GFXIMVP6_VID0 GFXIMVP6_VID1 GFXIMVP6_VID2 GFXIMVP6_VID3 GFXIMVP6_VID4 =GPUVCORE_EN GFXIMVP6_AF_EN GFXIMVP6_FDE
L8920
Vout = 1.05V - 0.96V

=PPVCORE_GPU_REG
8 46
PHASE
GFXIMVP6_PHASE
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM SWITCH_NODE=TRUE 5
PPVCORE_GPU_REG_R
1 3
2 4
C8966 1 C8968
10UF
1
CRITICAL
LGATE
GFXIMVP6_LGATE
Q8951
LFPAK-HF
CRITICAL
C8969 1
1000PF
10% 25V X7R 2 402
10UF
RJK0328DPB
20% 6.3V 2 X5R 603
20% 6.3V 2 X5R 603
C8942 1
330UF
20% 2.0V 2 3 POLY-TANT D2T-SM2
12A max output (L8920 limit)
C8965
10UF
1 3
C8967
10UF
CRITICAL
C
70
95
R8920
GPU_VDD_SENSE
MIN_NECK_WIDTH=0.20 mm MIN_LINE_WIDTH=0.25 mm VOLTAGE=1.25V 1
20
GFXIMVP6_VSEN_P 95 GFXIMVP6_VSEN_N
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM 1
VSEN RTN
1 2 3
20% 6.3V 2 X5R 603
20% 2 6.3V X5R 603
C8943
330UF
20% 2 2.0V POLY-TANT D2T-SM2
2 1
5% 1/16W MF-LF 402
C8920
0.001UF
C8923
R8908
70
10% 2 50V CERM 402
10% 2 50V CERM 402
0.001UF 0.001UF
C8921 1
10% 50V CERM 2 402 1
C8953
680pF
GFXIMVP6_PHASE_VSUM
GPU_GND_SENSE
MIN_NECK_WIDTH=0.20 mm MIN_LINE_WIDTH=0.25 mm VOLTAGE=0V
20
(GFXIMVP6_AGND) GFXIMVP6_VW
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM VW
5% 1/16W MF-LF 402
10% 50V 2 CERM 402
R89031
1% 1/16W MF-LF 402 2
1K
R8909
4.99K
PLACEMENT_NOTE=Place R8920 at U8900 PLACEMENT_NOTE=Place R8908 at U8900
C8922
1000PF
C8950
180PF
2 1 5% 50V CERM 402
1% 1/16W MF-LF 402 2
10% 2 25V X7R 402
GFXIMVP6_COMP_RC
GFXIMVP6_COMP
COMP
VO
GFXIMVP6_VO
R8950
374K
C8952
68PF
OCSET
R8900
1
1% 1/16W MF-LF 2 402
5% 2 50V CERM 402-1
GFXIMVP6_OCSET
5.11K 2
1% 1/16W MF-LF 402
GFXIMVP6_FB
1
GFXIMVP6_VSUM
FB ISP ISN MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM
C8906 1
330PF
5% 50V 2 COG 402
R8951
4.99K
R8953
2.21K
GFXIMVP6_DFB
1% 1/16W MF-LF 2 402
C8951
560PF
1 2 10% 50V CERM 402
1% 1/16W MF-LF 2 402
R89022
VDIFF PGND VSS ICOMP THRM_PAD
R8901
5.11K (PPVCORE_GPU_REG)
GFXIMVP6_VDIFF_RC
GFXIMVP6_VDIFF
9.76K
1% 1/16W MF-LF 402 1
C8971
68PF
1 2 5% 50V CERM 402-1
1% 1/16W MF-LF 2 402
GFXIMVP6_DROOP
C8972 1
0.1uF
10% 16V 2 X5R 402
GND_GFXIMVP6_AGND
XW8900 SM
1 2
GPU VCore Setpoints

VID3 VID2 VID1 VID0 Voltage 0.90125V 0.92700V 1.00425V Max Batt M98 Balanced Max perf M98 1 1 1 1 1 0 1 1 1 1 0 1 M98 -
78 8
=PP3V3_GPU_VCORELOGIC GPUVID0_1 GPUVID1_1 GPUVID2_1

1
R8986
76
IN
GPU_VCORE_VID0
R89871
2.2K
5% 1/16W MF-LF 402 2
R8984
2.2K
5% 1/16W MF-LF 402
R89821
2.2K
5% 1/16W MF-LF 402 2
R8980
0
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
R8990
76
IN
GPU_VCORE_VID1
A
76
5% 1/16W MF-LF 402
R8994
IN
GPUVID1_0
GPUVID2_0
GFXIMVP6_VID0 GFXIMVP6_VID1 GFXIMVP6_VID2 GFXIMVP6_VID3 GFXIMVP6_VID4

1
Other VID states may not be valid

78 78 78 78 78
M98 Default Vcore Setpoints

TABLE_BOMGROUP_HEAD
GPU (G84M) Core Supply

GPU_VCORE_VID2
R8985
2.2K
5% 1/16W MF-LF 402
R8983
2.2K
5% 1/16W MF-LF 402
5% 1/16W MF-LF 402
R8988
0
BOM GROUP GPUVID_0P90V GPUVID_1P00V
BOM OPTIONS
TABLE_BOMGROUP_ITEM
5% 1/16W MF-LF 2 402
GPUVID2_1,GPUVID1_1,GPUVID0_1
TABLE_BOMGROUP_ITEM
GPUVID2_0,GPUVID1_1,GPUVID0_1
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
78
96
0.033UF
C8904
ISL6263C UGATE
GFXIMVP6_UGATE
Q8950
CRITICAL
RJK0305DPB
LCD (LVDS) INTERFACE

8
=PP3V3_S5_LCD
R9000 1
100K
5% 1/16W MF-LF 402
0.0022uF
1 10% 50V CERM 402 2
CRITICAL
L9000
PP3V3_SW_LCD_UF CRITICAL FERR-250-OHM
SM 1
R9001
100K
5% 1/16W MF-LF 402
LCD_PWREN_L_RC
3
Q9000
FDC638P_G
SM
C9001
0.1UF
10% 16V X5R 402
C9002
1000PF
10% 25V X7R 402
LCD_PWREN_L
Q9001
SSM3K15FV
SOD-VESM-HF
83
CRITICAL
D 3
20474-040E-11
IN
J9000
F-RT-SM 41 42
LCD_PWR_EN
76 8 7
=PP3V3_S0_DDC_LCD
R9094
10K
5% 1/16W MF-LF 402
S 2
1
100K pull-ups are for no-panel case (development). Panel has 2K pull-ups
80 7 80 7
R9010 1
100K
5% 1/16W MF-LF 402
R9011
100K
5% 1/16W MF-LF 402
84 7
PP3V3_SW_LCD
2 3 4 5 6 7
BKL_SYNC
LVDS_DDC_CLK LVDS_DDC_DATA
94 80 7
C9010
1000PF
10% 25V X7R 402
94 80 7
LVDS_CONN_A_DATA_N<0> LVDS_CONN_A_DATA_P<0> LVDS_CONN_A_DATA_N<1> LVDS_CONN_A_DATA_P<1> LVDS_CONN_A_DATA_N<2> LVDS_CONN_A_DATA_P<2> LVDS_CONN_A_CLK_F_N LVDS_CONN_A_CLK_F_P LVDS_CONN_B_DATA_N<0> LVDS_CONN_B_DATA_P<0> LVDS_CONN_B_DATA_N<1> LVDS_CONN_B_DATA_P<1> LVDS_CONN_B_DATA_N<2> LVDS_CONN_B_DATA_P<2>
8 9 10
94 80 7 94 80 7
11 12 13
CRITICAL
L9010
90-OHM-100MA DLP11S
SYM_VER-1
94 80 7 94 80 7
14 15 16
94 80
LVDS_CONN_A_CLK_N
3
94 7
17 18 19
94 80
LVDS_CONN_A_CLK_P
94 7
Place close to the connector
94 80 7 94 80 7
20 21 22
94 80 7
23 24 25
CRITICAL
94 80 7
B
94 80
L9011
90-OHM-100MA DLP11S
SYM_VER-1
94 80 7 94 80 7
26 27 28
LVDS_CONN_B_CLK_N
94 80
LVDS_CONN_B_CLK_P
2
84 7
Place close to the connector
84 7 84 7 84 7 84 7 84 7
LVDS_CONN_B_CLK_F_N LVDS_CONN_B_CLK_F_P LED_RETURN_1 LED_RETURN_2 LED_RETURN_3 LED_RETURN_4 LED_RETURN_5 LED_RETURN_6

94 7 94 7
29 30 31 32 33 34 35 36 37 38 39
518S0651
NC
84 7
PPVOUT_S0_LCDBKLT
40
43 44
LVDS Display Connector
SYNC_MASTER=MUXGFX

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
79
96
C9000
4 1 2 5 6
DisplayPort Mux
80 8
=PP3V3_S0_DPMUX
A2 J4
LVDS Transmitter Termination

All emulated LVDS outputs require this termination
89 9 89 9
MUXGFX
1
MUXGFX
1
C9320
0.1UF
C9321
0.1UF
20% 402
IN IN IN IN IN IN IN IN BI
DP_IG_ML_P<0> DP_IG_ML_N<0> DP_IG_ML_P<1> DP_IG_ML_N<1> DP_IG_ML_P<2> DP_IG_ML_N<2> DP_IG_ML_P<3> DP_IG_ML_N<3> DP_IG_AUX_CH_P DP_IG_DDC_CLK DP_IG_DDC_DATA
B4 A4 B5 A5 B6 A6 A8 A9
DIN1_0+ DIN1_0DIN1_1+ DIN1_1-
VDD
MUXGFX
20% 2 10V CERM 402
2 10V CERM
D
94 83
PLACEMENT_NOTE=Place at U9200
(All 24 resistors)
89 9 89 9
R9320
IN
U9320
CBTL06141EE
BGA
D
OUT OUT
81 94 81 94
LVDS_A_CLK_P
270
LVDS_CONN_A_CLK_P
1
OUT
79 94 89 9 89 9
1% 1/16W MF-LF 402
R9321
133
R9322
94 83
1% SIGNAL_MODEL=EMPTY 1/16W MF-LF 2 402
89 9 89 9
DIN1_2+ CRITICAL DIN1_2SIGNAL_MODEL=DPMUX DOUT_0+ DIN1_3+ DIN1_3DOUT_0DAUX1+ DAUX1DDC_CLK1 DDC_DAT1 HPD_1
B2 B1
DP_ML_P<0> DP_ML_N<0>
C9330 C9331
IN
LVDS_A_CLK_N
270
89 18
LVDS_CONN_A_CLK_N
OUT
79 94
89 18
BI
DP_IG_AUX_CH_N
76 9 76 9
0.1uF
1
2 95 DP_IG_AUX_CH_C_P 10% 16V X5R 402 2 95 DP_IG_AUX_CH_C_N 10% 16V X5R 402
H9 J9 H8 J8 J2
R9325
1
94 83
IN
LVDS_A_DATA_P<0>
270
BI
2 1
LVDS_CONN_A_DATA_P<0>
OUT
7 79 94 9
1% 1/16W MF-LF 402
OUT
DP_IG_HPD
94 77 94 77
R9326
133
SIGNAL_MODEL=EMPTY
DOUT_2+ DOUT_2-
E2 E1
OUT OUT
81 94 81 94
R9327
94 83
1% 1/16W MF-LF 2 402
R93041
100K
OUT
7 79 94
IN IN IN IN IN IN IN IN BI BI IN BI
DP_EG_ML_P<0> DP_EG_ML_N<0> DP_EG_ML_P<1> DP_EG_ML_N<1> DP_EG_ML_P<2> DP_EG_ML_N<2> DP_EG_ML_P<3> DP_EG_ML_N<3> DP_EG_AUX_CH_P DP_EG_AUX_CH_N DP_EG_DDC_CLK DP_EG_DDC_DATA
B8 B9 D8 D9 E8 E9 F8 F9
DIN2_0+ DIN2_0DIN2_1+ DIN2_1DIN2_2+ DIN2_2DIN2_3+ DIN2_3DAUX2+ DAUX2DDC_CLK2 DDC_DAT2 HPD_2 LO=PORT1 HI=PORT2 GPU_SEL XSD*
B3 C8
IN
LVDS_A_DATA_N<0>
270
LVDS_CONN_A_DATA_N<0>
5% 1/16W MF-LF 402 2
94 77 94 77
DOUT_3+ DOUT_3-
F2 F1
OUT OUT
81 94 81 94
R9330
94 83
IN
LVDS_A_DATA_P<1>
270
1% 1/16W MF-LF 402
94 77
2 1
OUT
7 79 94
R93061
1K
5% 1/16W MF-LF 402 2
94 77
AUX+ AUX-
H2 H1
DP_AUX_CH_C_P DP_AUX_CH_C_N
BI BI
81 94 81 94
1% 1/16W MF-LF 402
94 77 94 77
R9331
133
SIGNAL_MODEL=EMPTY
C9335 C9336
C
94 83
R9332
IN
1% 1/16W MF-LF 2 402
94 77 94 77
0.1uF
1
2 94 DP_EG_AUX_CH_C_P 10% 16V X5R 402 2 94 DP_EG_AUX_CH_C_N 10% 16V X5R 402
H6 J6 H5 J5 H3
PLACEMENT_NOTE=Place at U9320 MUXGFX
R9307
HPDIN
J1
LVDS_A_DATA_N<1>
270
76
0.1uF
DP_HPD_R
1K
DP_HPD
IN
81
OUT
7 79 94
76
1% 1/16W MF-LF 402

94 83
R9335
1
76
OUT
DP_EG_HPD
5% 1/16W MF-LF 402 LO=AUX_CH HI=DDC DDC_AUX_SEL GND

G8 H4 H7
IN
LVDS_A_DATA_P<2>
270
2 1
OUT
7 79 94
1% 1/16W MF-LF 402
R9305
100K
83
IN
DP_MUX_SEL_EG DP_MUX_XSD_L DPMUX_EN_HPD DPMUX_EN_HPD

1
A1 B7
C2 G2
DP_CA_DET
MAKE_BASE=TRUE
IN
76 81 83
R9336
133
SIGNAL_MODEL=EMPTY
R9337
94 83
1% 1/16W MF-LF 2 402
5% 1/16W MF-LF 402 2
TST0
80 8
=PP3V3_S0_DPMUX
DPMUX_EN_S0&DPMUX_EN_PLD
R93011
10K
1% 1/16W MF-LF 402 2
83
C9301
1UF
IN
LVDS_A_DATA_N<2>
270
R93021
OUT
7 79 94
10K DPMUX_EN_PLD
R9340
94 83
IN
LVDS_B_CLK_P
270
1% 1/16W MF-LF 402
2 1
LVDS_CONN_B_CLK_P
R9303
OUT
79 94 83
1% 1/16W MF-LF 402 2
10% 6.3V 2 CERM-X5R 402
OUT OUT
DP_HOTPLUG_DET
MAKE_BASE=TRUE
1% 1/16W MF-LF 402
IN
DP_MUX_EN
18
DP_IG_CA_DET
R9341
133
1% 1/16W MF-LF SIGNAL_MODEL=EMPTY
5% 1/16W MF-LF 402
R9342
94 83
2 402
IN
LVDS_B_CLK_N
270
LVDS_CONN_B_CLK_N
OUT
79 94
1% 1/16W MF-LF 402
R9345
1
94 83
IN
LVDS_B_DATA_P<0>
270
2 1
LVDS_CONN_B_DATA_P<0>
OUT
7 79 94
1% 1/16W MF-LF 402
R9346
133
LVDS DDC MUX

8
R9347
94 83
=PP3V3_GPU_LVDS_DDC
2 402
IN
LVDS_B_DATA_N<0>
270
LVDS_CONN_B_DATA_N<0>
OUT
7 79 94
R9350
94 83
IN
LVDS_B_DATA_P<1>
270
1% 1/16W MF-LF 402
R93701
8
R9371
20K
=PP3V3_S0_LVDSDDCMUX
20K
5% 1/16W MF-LF 402 2 1 14
2 1
OUT
7 79 94
1% 1/16W MF-LF 402
5% 1/16W MF-LF 2 402
R9351
133
SIGNAL_MODEL=EMPTY
C9370
0.1UF
R93721
20K
R9373
20K
R9352
94 83
1% 1/16W MF-LF 2 402
20% 10V CERM 2 402 OUT

7 79 94 83
1% 1/16W MF-LF 402

94 83
R9355
1
SN74LV4066A
IN
LVDS_B_DATA_N<1>
270
IN
LVDS_DDC_SEL_EG LVDS_DDC_SEL_IG
13
C1 C2 C3 C4
U9370 QFN1
VCC
5% 1/16W MF-LF 402 2 1
5% 1/16W MF-LF 2 402
A1 2 B1 A2 3 B2 A3 9 B3
11 8 4
LVDS_EG_DDC_CLK LVDS_IG_DDC_CLK LVDS_DDC_CLK LVDS_EG_DDC_DATA LVDS_IG_DDC_DATA LVDS_DDC_DATA
IN
76
IN
LVDS_B_DATA_P<2>
270
83
IN
IN OUT BI
18 7 79
2 1
OUT
7 79 94
1% 1/16W MF-LF 402
R9356
133
12
76
R9357
2 402
94 83
IN
LVDS_B_DATA_N<2>
270
A4 10 B4 GND THRM
7 15
BI BI
18 7 79
Muxed Graphics Support

OUT
7 79 94
1% 1/16W MF-LF 402

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
80
96
1% 1/16W MF-LF 402
IN
0.1uF
DOUT_1+ DOUT_1-
D2 D1
OUT OUT
81 94 81 94
Port Power Switch

CRITICAL
U9480
D
83 68 44 42 37 34 21 7
=PP3V3_S5_DP_PORT_PWR
IN
PM_SLP_S3_L
TPS2051B SOT23 5 IN OUT 1

4 EN
DP_ESD CRITICAL
PP3V3_S0_DPILIM TP_DPPWR_OC_L
DP_ESD CRITICAL
D9410
FERR-120-OHM-3A 1 2 PP3V3_S0_DPPWR
0603 1
D9410
RCLAMP0524P
SLP2510P8
OC* 3 GND 2
L9400
RCLAMP0524P
SLP2510P8
C9400
0.01UF
5 IO 6 NC
IO 4 NC 7 GND
2 IO 9 NC
IO 1 NC 10 GND
3
CRITICAL
C9480
10UF
20% 6.3V X5R 603
C9481
0.1UF
20% 10V CERM 402
C9485
0.1UF
20% 10V CERM 402
C9486
22UF
20% 2 50V CERM 603
R94201
100K
5% 1/16W MF-LF 402 2
R9400 R9401
NO STUFF 0 0
1 2
NO STUFF 0 0
1 2
R9430
1/16W MF-LF 402 1/16W MF-LF 402
NO STUFF
1 2
5% 5%
1/16W 1/16W
MF-LF 402 MF-LF 402
HDMI_CEC
CRITICAL
J9400
R9431
NO STUFF
1 2
5% 5%
R9403
NO STUFF 0 0
1 2
DSPLYPRT-M97-2
F-RT-THSM
C
1
R9413 R9425
1M
5% 1/16W MF-LF 2 402
94 80
NO STUFF
1 2
5% 5%
1/16W MF-LF 402 BOT ROW 1/16W MF-LF 402

2 4
TH PINS
FL9400
TOP ROW
SM PINS
94
FL9403 12-OHM-100MA
IN
C9414 C9415
1 1
0.1uF
94 80
2 94 DP_ML_C_P<3> 10% 16V X5R 402 2 94 DP_ML_C_N<3> 10% 16V X5R 402
TCM1210-4SM
SYM_VER-2
1
94
DP_ML_CONN_P<3> DP_ML_CONN_N<3>
8 10
DP_HPD DP_C_A_DET HDMI_CEC GND ML_LANE3P ML_LANE3N GND AUX_CHP AUX_CHN DP_PWR
IN
94
12 14 16 18
0.1uF
94 80
BI
DP_AUX_CH_C_P DP_AUX_CH_C_N DP_ESD CRITICAL
94 80
BI
20
GND ML_LANE0P ML_LANE0N GND ML_LANE1P ML_LANE1N GND ML_LANE2P ML_LANE2N RETURN
1 3 5 7 9 11 13 15 17 19
94 94
94
12-OHM-100MA TCM1210-4SM
SYM_VER-2
FL9401
94
12-OHM-100MA TCM1210-4SM
SYM_VER-2
2 4
3 1
FL9402 12-OHM-100MA
TCM1210-4SM
SYM_VER-2
94
81 8
=PP3V3_S0_DPCONN
DP_ML_C_P<0> C9410 1 0.1uF 1 94 DP_ML_C_N<0> C9411 0.1uF 94 DP_ML_C_P<1> C9412 1 0.1uF 94 DP_ML_C_N<1> C9413 1 0.1uF 94 DP_ML_C_P<2> C9416 1 0.1uF C9417 1 94 DP_ML_C_N<2> 0.1uF
94
2 DP_ML_P<0> 10% 16V X5R 402 2 DP_ML_N<0> 10% 16V X5R 402 2 DP_ML_P<1> 10% 16V X5R 402 2 DP_ML_N<1> 10% 16V X5R 402 2 DP_ML_P<2> 10% 16V X5R 402 2 DP_ML_N<2> 10% 16V X5R 402
C
IN
80 94
IN
80 94
IN
80 94
IN
80 94
IN
80 94
IN
80 94
SHIELD PINS
22 21
R94431
100K DP_CA_DET
5% 1/16W MF-LF 402 2
R94421
100K
5% 1/16W MF-LF 402 2
D9411
RCLAMP0524P
R94211
100K
5% 1/16W MF-LF 402 2
SLP2510P8
R9402 R9432
NO STUFF 0 0
1 2
NO STUFF
1 2
5% 5%
1/16W MF-LF 402 1/16W MF-LF 402
83 80 76
OUT
2 IO 9 NC
IO 1 NC 10 GND
2N7002DW-X-G
SOT-363
Q9440
1
D 2
DP_CA_DET_L_Q
3
DP_ESD CRITICAL
RCLAMP0504F
D G 5
D9400
SC70-6-1
DP_ESD CRITICAL
D9411
RCLAMP0524P
SLP2510P8
2N7002DW-X-G
SOT-363
Q9440
MF-LF 402 2
81 8
=PP3V3_S0_DPCONN
R9445 1
10K
5% 1/16W MF-LF 402
80
R9444
10K
5% 1/16W MF-LF 402
OUT
DP_HPD
6
Q9441
2N7002DW-X-G
SOT-363
D
2
S
1
DP_HPD_L_Q
3
Q9441
2N7002DW-X-G
SOT-363
D
5
GND
DP_CA_DET_Q DP to DVI/HDMI 4 R94221 Cable Adapter 1M (CA) has 100k 5% Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm 1/16W pull-up to DP_PWR.
S
1 2
6 5 IO 6 NC
IO 4 NC 7
DisplayPort Connector
G
DP_HPD_Q
SYNC_MASTER=MUXGFX
R9423 1
100K
5% 1/16W MF-LF 402
DP Source must pull down HPD input with greater than or equal to 100K (DPv1.1a).

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
81
96
20% 6.3V 2 X5R-CERM 603
D
=PPVIN_S0GPU_P1V8P1V1 CRITICAL
C9540 1
C9545
1UF
CRITICAL
22UF
PWRPK-1212-8
SI7904BDN
4.7
PVIN_S0GPU_P1V1
5% 1/16W MF-LF 402

G 4
P1V1GPU_DRVH
C9500 1
10UF
10% 25V 2 X5R 805
=PP5V_S0GPU_P1V1P1V8_GPU
C9501 1
10% 10V 2 X5R 402-1
1UF
Q9510 CRITICAL
PWRPK-1212-8 6
SI7904BDN
(Internal 10-ohm path from PVCC to VCC) PP5V_S0GPU_P1V1P1V8_VCC

CRITICAL
Q9560
FDMS9600S
MLP
9 4 3 2
PP5V_S0GPU_VREF
19
C
8
G 2 S
P1V1GPU_DRVL
3 5 MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM GATE_NODE=TRUE
C9504 1
PVCC VCC VREF3 10% 10V 2 X5R 402-1 7 8 24 26 25 23 30 27 32 31 1 13 28
C9503 1
10% 10V 2 X5R 402-1
P1V8FB_DRVH
1UF
1UF
CRITICAL 2.2UH-14A
Q1 8 10 SW 1 MMD06CZ-SM 2
=PP1V8_GPU_REG
L9560
=PP1V1_S0GPU_REG

1
C9530 1
CRITICAL 3.3UH-3.5A
1 2 PCMB053T
0.1UF
L9510
10% 50V 2 X7R 603-1
P1V1GPU_VBST
P1V1GPU_LL
XW9515 SM
1 2
C9510
20% 2 2.0V POLY-TANT B2-SM
CRITICAL 330UF
C9515 1
10UF
20% 6.3V 2 X5R 603
P1V1GPU_VFB P1V1GPU_TRIP
6 17 15 16 18 10 14 9 11 12 29 4 20 2
LDO VIN LDOREFIN BOOT1 CRITICAL BOOT2 UGATE1 UGATE2 PHASE1 ISL6236 PHASE2 LGATE1 LGATE2 QFN OUT1 OUT2 EN1 EN2 BYP FB1 REFIN2 ILIM1 ILIM2 SKIP* EN_LDO REF SECFB POK1 TON POK2
NC
(SGND) P1V8FB_VBST
CRITICAL
C9560 1
Q2 20% 2.5V 2 POLY-TANT CASE-B2-SM2
U9500
220UF
Vout = 1.8V 6A max output (Q9560 limit?) f = 300 kHz 1 C9565

20% 2 6.3V X5R 603
P1V8FB_DRVL (=PP1V8FB_S0_REG)
1
10UF
C9580
0.1UF
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM GATE_NODE=TRUE 7 6 5
GPU_P1V8_REFIN P1V8FB_TRIP PP2V_S0GPU_P1V8_REF

VOLTAGE=2V
10% 50V 2 X7R 603-1
P1V8FB_LL
<Ra> R95631
R95851
130K
1% 1/16W MF-LF 402 2
XW9565 SM
2 1
P1V8_GPU_VSNS
THRM_PAD GND 33 21
PGND 22
14.0K
PLACEMENT_NOTE=Place next to C7665
P1V1S0_VSNS
<Ra> 1 R9520
1% 1/16W MF-LF 402 2
NO STUFF
1% 1/16W MF-LF 2 402
5.76K
C9520
100PF
1 1
5% 50V CERM 2 402
R9535
280K GND_P1V1P1V8_SGND
<Rb> R9521
10K
1% 1/16W MF-LF 2 402
XW9500 SM
1 2
C9585
0.1UF
20% 10V 2 CERM 402
<Rb> R95641
127K
1% 1/16W MF-LF 402 2
R9562
78.7K
1% 1/16W MF-LF
C9561
0.01UF
Vout = 0.7V * (1 + Ra / Rb) (Rb should be between 10K and 100K)
10% 16V 2 CERM 402
2 402
B
Q9565
3
GPUFB_VID_L
D
SSM3K15FV
SOD-VESM-HF
1% 1/16W MF-LF 2 402

2
83 68 68 68 83 68 67
G 1
GPIO7_FBVDD_ALTVO 76
IN OUT OUT IN
=P1V1GPU_EN P1V1GPU_PGOOD P1V8FB_PGOOD =P1V8FB_EN
1.1V / 1V8 FB Power Supply
SYNC_MASTER=MUXGFX

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
82
96
10% 2 25V X5R 603-1
Q9510 CRITICAL
C9590 1 R9500
22UF
C9595
1UF
10% 2 25V X5R 603-1
8
83 8
4
=PP3V3_S0_GMUX
=PP3V3_S0_GMUX
GMUX CPLD
8 83
LVDS Receiver Termination

PLACEMENT_NOTE=Place at U9200 (All 14 resistors)
89 83 18 89 83 18 89 83 18 89 83 18
C9610
0.1UF
C9621
0.1UF
C9622
0.1UF
C9623
0.1UF
C9624
0.1UF
C9625
0.1UF
C9626
0.1UF
C9628
0.1UF
C9629
0.1UF
C9630
0.1UF
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
LVDS_IG_A_CLK_P LVDS_IG_A_DATA_P<0> LVDS_IG_A_DATA_P<1> LVDS_IG_A_DATA_P<2> LVDS_IG_B_DATA_P<0> LVDS_IG_B_DATA_P<1> LVDS_IG_B_DATA_P<2> LVDS_EG_A_CLK_P LVDS_EG_A_DATA_P<0> LVDS_EG_A_DATA_P<1> LVDS_EG_A_DATA_P<2> LVDS_EG_B_DATA_P<0> LVDS_EG_B_DATA_P<1> LVDS_EG_B_DATA_P<2>
L9631
8
89 83 18 89 83 18 89 83 18
=PP2V5_S0_GMUX
PP3V3_S0_ULC_F
1
FERR-220-OHM
1 0402 2
D
C9611
0.1UF
1
R9650 R9651 R9652 R9653 R9654 R9655 R9656 R9660 R9661 R9662 R9663 R9664 R9665 R9666
100 100 100 100 100 100 100 100 100 100 100 100 100 100
1 1 1 1 1 1 1
2 2 2 2 2 2 2 1% 1% 1% 1/16W 1/16W 1/16W MF-LF MF-LF MF-LF 402 402 402 1% 1% 1% 1% 1/16W 1/16W 1/16W 1/16W MF-LF MF-LF MF-LF MF-LF 402 402 402 402
LVDS_IG_A_CLK_N LVDS_IG_A_DATA_N<0> LVDS_IG_A_DATA_N<1> LVDS_IG_A_DATA_N<2> LVDS_IG_B_DATA_N<0> LVDS_IG_B_DATA_N<1> LVDS_IG_B_DATA_N<2> LVDS_EG_A_CLK_N LVDS_EG_A_DATA_N<0> LVDS_EG_A_DATA_N<1> LVDS_EG_A_DATA_N<2> LVDS_EG_B_DATA_N<0> LVDS_EG_B_DATA_N<1> LVDS_EG_B_DATA_N<2> =PP3V3_S0_GMUX
18 83 89 18 83 89 18 83 89 18 83 89
18 83 89 18 83 89 18 83 89
C9612
0.1UF
C9613
0.1UF
C9614
0.1UF
C9615
0.1UF
C9616
0.1UF
C9617
0.1UF
C9631
0.1UF
94 83 77
1 1 1 1 1 1 1
2 2 2 2 2 2 2 1% 1% 1% 1/16W 1/16W 1/16W MF-LF MF-LF MF-LF 402 402 402 1% 1% 1% 1% 1/16W 1/16W 1/16W 1/16W MF-LF MF-LF MF-LF MF-LF 402 402 402 402
77 83 94 77 83 94 77 83 94 77 83 94
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V 2 CERM 402
20% 10V CERM 2 402
L9627
FERR-220-OHM
94 83 77 94 83 77 94 83 77
PP3V3_S0_LRC_F
8
1 0402
94 83 77 94 83 77
77 83 94 77 83 94 77 83 94
=PP1V2_S0_GMUX
C9627
0.1UF
94 83 77
4.7UF
20% 4V X5R 2 402
20% 10V 2 CERM 402
0.1UF
20% 10V 2 CERM 402
0.1UF
20% 10V 2 CERM 402
0.1UF
20% 10V 2 CERM 402
0.1UF
20% 10V 2 CERM 402
0.1UF
20% 10V 2 CERM 402
0.1UF
Required Pullups
83
GMUX_DEBUG_RESET_L JTAG_GMUX_TCK EG_CLKREQ_OUT_L NO STUFF
R9680 R9690 R9695
1K 4.7K 10K
5%
1 2
1/16W MF-LF 402 1/16W MF-LF 402
83 6
5% B11 C4 J3 J13 N11 P8 C11 J2 J14 M8 B5 B7 A12 C14 F13 M12 M9 M3 N5 M1 C3 F2 K12 A4 P11
83 9
5%
1/16W MF-LF 402
VCC
VCCAUX
VCCJ
R9640
10K
R9645
10K
9 6 9 6 9 6
83 6
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 2 402
IN OUT IN
JTAG_GMUX_TCK JTAG_GMUX_TDI JTAG_GMUX_TDO JTAG_GMUX_TMS GMUX_TOE GMUX_CFG0
R96791
SILK_PART=GMUX_RST
K14 L13 K13 L12 K2 K1 P2 N2 P4 N4 N3 M4 P5 M5 P6 M6 P7 M7 N7 N8 P9 N9 P10 M10 P12 P13 N12 P14 B1 B2 C2 D3 D1 E1 D2 E3 F1 G1 F3 G2 H2 G3 H1 H3 L1 L3 K3 L2 N1 P1
TCK TDI TDO TMS TOE CFG0 PB2A PB2B PB14A PB14B PB15A (OD) PB15B PB16A PB16B PB17A PB17B PB18A PB18B (OD) PB19A PB19B PB20A PB20B PB30A PB30B PB31A PB31B PB32A PB32B PL2A PL2B PL10A PL10B PL11A PL11B PL12A PL12B PL13A PL13B PL14A PL14B PL15A PL15B PL16A PL16B PL18A PL18B PL19A PL19B PL32A PL32B
10K
OMIT CRITICAL
1% 1/16W MF-LF 402 2
PLACEMENT_NOTE=Place on top side at U9200
C
9 84 83 83 80
U9600
XP28
CSBGA-HF PT2A PT2B PT3A PT3B PT4A PT4B PT14A PT14B PT15A PT15B PT16A PT16B PT17A PT17B PT18A PT18B PT19A PT19B PT20A PT20B PT32A PT32B PR2A PR2B PR10A PR10B PR11A PR11B PR12A PR12B PR13A PR13B PR14A PR14B PR15A PR15B PR16A PR16B PR18A PR18B PR30A PR30B A2 A3 A1 B3 C5 A5 B6 C7 A6 A7 C8 C9 A8 B9 A9 C10 B10 A10 A11 B12 B13 A13 A14 B14 D12 D13 D14 E14 E12 F12 F14 G14 G12 G13 H13 H12 H14 J12 L14 M13 N14 N13
Required Pulldowns
LVDS_B_DATA_P<0> LVDS_B_DATA_N<0> LVDS_B_DATA_P<1> LVDS_B_DATA_N<1> LVDS_B_DATA_P<2> LVDS_B_DATA_N<2> EG_PWRSEQ_EN GMUX_DEBUG_RESET_L LVDS_A_CLK_P LVDS_A_CLK_N LVDS_B_CLK_P LVDS_B_CLK_N LVDS_A_DATA_P<0> LVDS_A_DATA_N<0> LVDS_A_DATA_P<1> LVDS_A_DATA_N<1> LVDS_A_DATA_P<2> LVDS_A_DATA_N<2> TP_GMUX_PT20A TP_GMUX_PT20B TP_GMUX_PT32A TP_GMUX_PT32B DP_CA_DET DP_HOTPLUG_DET LVDS_EG_A_DATA_P<0> LVDS_EG_A_DATA_N<0> LVDS_EG_A_DATA_P<1> LVDS_EG_A_DATA_N<1> LVDS_EG_A_DATA_P<2> LVDS_EG_A_DATA_N<2> LVDS_EG_B_DATA_P<0> LVDS_EG_B_DATA_N<0> LVDS_EG_B_DATA_P<1> LVDS_EG_B_DATA_N<1> LVDS_EG_B_DATA_P<2> LVDS_EG_B_DATA_N<2> LVDS_EG_A_CLK_P LVDS_EG_A_CLK_N IG_LCD_PWR_EN EG_LCD_PWR_EN IG_BKLT_EN EG_BKLT_EN
OUT OUT OUT OUT OUT OUT IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT
80 94 80 94 80 94 83 80 80 94 80 94 80 94 83 83 80 94 80 94 83 9 80 94 80 94 80 94 80 94 80 94 84 83 80 94 80 94 80 94 83 83 9 83 80 83 80
OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT BI BI BI BI BI IN IN OUT
NO STUFF
NO STUFF
1
83 80 80 83 80 83 9 83 83 83 83 83 9 76 79 90 44 42 19 90 44 42 19 90 44 42 19 90 44 42 19 90 44 42 19 90 26 19 26 83 9
R9641
10K
R9646
10K
BANK0
1% 1/16W MF-LF 402 2
1% 1/16W MF-LF 2 402
BANK1
LCD_BKLT_EN LCD_BKLT_PWM LVDS_DDC_SEL_EG LVDS_DDC_SEL_IG DP_MUX_EN DP_MUX_SEL_EG EG_RESET_L EG_RAIL1_EN EG_RAIL2_EN EG_RAIL3_EN EG_RAIL4_EN EG_CLKREQ_OUT_L DP_CA_DET_EG LCD_PWR_EN LPC_AD<0> LPC_AD<1> LPC_AD<2> LPC_AD<3> LPC_FRAME_L LPC_RESET_L LPC_CLK33M_GMUX GMUX_INT LVDS_IG_B_DATA_P<2> LVDS_IG_B_DATA_N<2> TP_GMUX_PL10A TP_GMUX_PL10B LVDS_IG_A_DATA_P<0> LVDS_IG_A_DATA_N<0> LVDS_IG_A_DATA_P<1> LVDS_IG_A_DATA_N<1> LVDS_IG_A_DATA_P<2> LVDS_IG_A_DATA_N<2> LVDS_IG_B_DATA_P<0> LVDS_IG_B_DATA_N<0> LVDS_IG_B_DATA_P<1> LVDS_IG_B_DATA_N<1> LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N LVDS_MUX_SEL_EG TP_GMUX_PL18B_VSYNC =GMUX_PCIE_RESET_L GMUX_PM_SLP_S3_L ALL_EG_PGOOD EG_CLKREQ_IN_L
DP_MUX_SEL_EG LVDS_DDC_SEL_IG LVDS_DDC_SEL_EG
R9681 R9682 R9683
10K 10K 10K
5%
1 2
1/16W MF-LF 402
5%
1 2
1/16W
MF-LF 402
5%
1/16W MF-LF 402
(Use open-drain PGOOD output to hold off the start of the GPU PWRSEQ until the first GPU rails source is valid)
EG_RESET_L GMUX_INT LCD_BKLT_PWM EG_CLKREQ_IN_L
R9691 R9692 R9693 R9694 R9630
NO STUFF 100K 20K 100K

1 2
5%
1 2
1/16W
MF-LF 402
5%
1 2
1/16W
MF-LF 402
5%
1/16W
MF-LF 402
100K 1 EG_PWRSEQ_HW 0 1 2
5%
5%
1/16W MF-LF 402 EXTGPU_PWR_EN OUT =P1V1GPU_EN OUT P3V3GPU_EN OUT =GPUVCORE_EN
68
1/16W MF-LF 402
83
EG_RAIL1_EN
EG_PWRSEQ_GMUX R9631 0 1 2 EG_PWRSEQ_GMUX R9632 0 1 2
5%
1/16W MF-LF 402
68 82
89 83 18
IN IN
76 80 81 80 77 83 94 77 83 94 83 77 83 94 77 83 94 77 83 94 77 83 94 77 83 94 77 83 94 77 83 94 77 83 94 77 83 94 77 83 94 77 83 94 77 83 94 9 76 9 76 83 83
89 83 18
EG_RAIL2_EN
5% EG_RAIL3_EN
1/16W MF-LF 402
68 69
EG_PWRSEQ_GMUX R9633 0 1 2
5% 1/16W MF-LF 402
89 83 18 89 83 18 89 83 18
OUT
68 78
IN IN IN IN IN IN IN IN IN IN IN IN OUT
NO STUFF
1
89 83 18 89 83 18 89 83 18 89 83 18 89 83 18 89 83 18 89 83 18 89 83 18 89 83 18 9
R9647
10K
BANK2
EG_RAIL4_EN
R9634
EG_PWRSEQ_GMUX 0 1 2
=P1V8FB_EN OUT 67 68 82 5% 1/16W MF-LF 402 The MAKE BASE properties for these signals are on the POWER CONTROL page.
NO STUFF NO STUFF
1
1% 1/16W MF-LF 2 402
C9691
0.1UF
C9693
0.1UF NO STUFF
1
20% 10V 2 CERM 402
20% 10V 2 CERM 402
NO STUFF
1
C9692
0.1UF
C9694
0.1UF
26 83 9
IN IN IN
83 IN (Tie/strap low if EGPU doesnt provide CLKREQ_L output, provide pullup to GPU rail if using CLKREQ_L output from EGPU)
PM_SLP_S3_L Isolation
83 8
GND J1
ULC_GNDPLL LRC_GNDPLL
GNDIO0
GNDIO1
GNDIO2
GNDIO3 GNDIO4
GNDIO5
GNDIO6
GNDIO7
BANK3
20% 10V 2 CERM 402
20% 10V 2 CERM 402
B8 C6 C12 C13 E13 M14 N10 N6 P3 M2 C1 E2
=PP3V3_S0_GMUX
B4 M11
GMUX_JTAG_TCK Inversion
83 6
Graphics MUX (GMUX)

A
42 37 34 21 7 81 68 44
Q9670
SSM6N15FEAPE
G 2
SOT563
JTAG_GMUX_TCK
TABLE_5_HEAD
R9670
10K
EG_PWRSEQ_EN

83
1% 1/16W MF-LF 2 402
PART# 336S0027
83
QTY 1 1
DESCRIPTION IC,XP2-8,HF,CPLD,BLANK IC,CPLD,LATTICE,132CSBGA,M98
REFERENCE DESIGNATOR(S) U9600 U9600
CRITICAL CRITICAL CRITICAL
BOM OPTION
TABLE_5_ITEM
Q9670
SSM6N15FEAPE
SOT563
GMUX_8K_BLANK
TABLE_5_ITEM
IN
PM_SLP_S3_L
GMUX_PM_SLP_S3_L
MAKE_BASE=TRUE
341S2350
GMUX_PROG 4 S
II NOT TO REPRODUCE OR COPY IT
G 5
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
GMUX_JTAG_TCK_L
IN
17
SIZE
DRAWING NUMBER
REV.
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
83
96
C9600 1
C9604
C9605
C9606
C9607
C9608
C9609
20% 10V 2 CERM 402
SIGNAL_MODEL=EMPTY
ULC_VCCPLL LRC_VCCPLL
VCCIO0
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
BANK5 BANK4 BANK7 BANK6
*Q9701, D9701, C9709, C9710, L9701, R9702, AND R9715 SHOULD ALL BE PLACED NEAR EACHOTHER. *BOOST_FET_CNTL AND PPVOUT_S0_LCDBKLT_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.
CRITICAL 22UH-2.5A
85 84
L9701
IN
PPBUS_S0_LCDBKLT_PWR
VOLTAGE=12.6V MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=0.4 mm
PPVIN_S0_LCDBKLT_BUF
2
VOLTAGE=12.6V MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.5MM
1 IHLP2525CZ-SM
PPVOUT_S0_LCDBKLT_SW
VOLTAGE=30V MIN_NECK_WIDTH=0.25 mm MIN_LINE_WIDTH=0.5 mm SWITCH_NODE=TRUE
PLACEMENT_NOTE=Place near Q9701 PLACEMENT_NOTE=Place near C9710 DO222-SM PLACEMENT_NOTE=Place near J9000 1 2
D9701
R9730
0.1 1%
1/6W MF 402-HF
R9701
1/16W MF-LF 402
STPS1H100MF
D
CRITICAL CRITICAL 2.2UF
10% 100V X7R 1210
CRITICAL
1
100 1%
PLACEMENT_NOTE=Place near Q9701
1 2 5 6
D
C9701
10UF
1
PLACEMENT_NOTE=Place near L9701
10% 2 25V X5R 805
PLACEMENT_NOTE=Place near PPVOUT_S0_LCDBKLT_SW
Q9701
SSOT6
1 C9709 1 C9710
BKL_VIN
1
BOOST_FET_CNTL
MIN_NECK_WIDTH=0.20MM MIN_LINE_WIDTH=0.6MM
G S
FDC5612
2.2UF
10% 100V X7R 1210
XW9701 SM
GND_BKL_PWRGND
1 2
84
C9702
0.1UF
4 PLACEMENT_NOTE=Place near C9709

GND_BKL_PWRGND
PLACEMENT_NOTE=Place near C9701
BOOST_SINK
GND_BKL_PWRGND
PLACEMENT_NOTE=Place near C9709 and Q9701
BKL_VREF_4V9 R9731
85 84
84
1
BKLT_EN
BKLT_PLL
79 7
1/16W MF-LF 402
100 1%
1/6W MF 402
0.4 1%
R9704
R9702
R9715
1/6W MF 402
0.4 1%
187K
1% 1/16W MF-LF 402
2
IN
XW9702 SM
BKL_VSYNC
3
GND_BKL_PWRGND_X
84
BKL_VREF_4V9
BKL_SYNC
R9734
0 5%
2
1
PLACEMENT_NOTE=Place near C9709 and Q9701
R9707
3.01K 1%
1/16W MF-LF 402
C9703
1UF
C9713
0.1UF
R9705
100K 1%
1/16W MF-LF 402
1/16W MF-LF 402
R9706
1/16W MF-LF 402
*R9702 AND R9715 PIN 1 SHOULD BE PLACED NEAR C9709 PIN 2

VIN
10% 10V 2 X5R 402
10K 5%
10% 2 25V X5R 402
4 5 17
VREF ENA
U9701 QFN
C9712
47PF
DRV
1 2 BKL_ISWSEN
GOSHAWK6P
ISWSEN ISEN1 ISEN2 ISEN3 ISEN4 ISEN5 ISEN6 VSEN THRM_PAD VSYNC ISET RT SSTCMP DIM LPF LRT GNDA
5% 2 50V CERM 402
PPVOUT_S0_LCDBKLT
VOLTAGE=30V MIN_NECK_WIDTH=0.20 mm MIN_LINE_WIDTH=0.5 mm
OUT
7 79 84
NOSTUFF
R9717
1
10 BKL_ISEN1 11 BKL_ISEN2 12 BKL_ISEN3 14 BKL_ISEN4 15 BKL_ISEN5 16 BKL_ISEN6 9

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm
10.2 2
LED_RETURN_6
OUT
7 79
PLACEMENT_NOTE=Away from Q9701 PLACEMENT_NOTE=Away from Q9701 PLACEMENT_NOTE=Away from Q9701
BKL_ISET BKL_RT BKL_SSTCMP BKLT_PWM_RC

2 2 1
8 6 7 20 19
0.1% 1/16W TF 402
R9718
1
10.2 2
LED_RETURN_5
OUT
7 79
R9708
100K 1%
1/16W MF-LF 402
R9709
1/16W MF-LF 402 1
BKL_DIM BKL_LPF
1 C9714
0.1% 1/16W TF 402
1K 1%
R9703
2.0M 5%
1/16W MF-LF 402
10% 50V CERM 402
R9733
1 C9706 2
1/16W MF-LF 402
0 5%
R9719
1
10.2 2
LED_RETURN_4
OUT
7 79
1UF
10% 10V X5R 402
BKL_LRT 18
0.0022UF NOSTUFF
0.1% 1/16W TF 402
13
21
NOSTUFF
R9720
1
BKL_SSTCMP_RC
1 2
10.2 2
LED_RETURN_3
OUT
7 79
C9705
0.01UF
20% 16V CERM 402
84
0.1% 1/16W TF 402
BKL_VREF_4V9
2
R9721
PLACEMENT_NOTE=Away from Q9701
R9713
1/16W MF-LF 402 2
84
GND_BKL_PWRGND
1
10.2 2
LED_RETURN_2
OUT
7 79
0 5%
0.1% 1/16W TF 402
BKLT_PLL
R9722
2
R9714
1/16W MF-LF 402 1
10K 5%
R9727
1/16W MF-LF 402
1
10.2 2
LED_RETURN_1
OUT
7 79
Q9702
SOT-963
S D
BKLT_PLL
1
CRITICAL NTUD3127CXXG
84
BKLT_PLL_NOT
75K 1%
0.1% 1/16W TF 402
C9707
2.2UF
BKL_VREF_4V9
2
BKL_VREF_IN_4V9
2
20% 2 6.3V CERM 402-LF
BKLT_PLL BKL_LRT_RC
1 2
PPVOUT_S0_LCDBKLT
7 79 84
C9708
0.1UF
10% 25V X5R 402
R9700
1/16W MF-LF 402
100K 1%
BKL_PWR_EN_L
R9710
1% 1/16W MF-LF 402
10K
2
R9723
1% 1/10W MF-LF 603
CRITICAL
1.2M
Q9702
NTUD3127CXXG
SOT-963
83
N-CHN
6
D
R9711
30.1K 1%
BKL_VSEN
2 1/16W MF-LF 402
IN
LCD_BKLT_PWM
G S
LCD BACKLIGHT DRIVER
R9724
1% 1/16W MF-LF 402
71.5K
SYNC_MASTER=YITE_M98_MLB

D
APPLE INC.
051-7546
SHT NONE OF
A.0.0
*R9707, R9708, R9709, R9713, R9714, R9727, AND R9729 SHOULD AWAY FROM BOOST CIRCUIT
SCALE
84
96
10% 25V 2 X5R 402
P-CHN
Q9806
FDC638APZ_SBMS001
SSOT6-HF
2AMP-32V
8
PPBUS S0 LCDBkLT FET

MOSFET CHANNEL RDS(ON) LOADING FDC638APZ P-TYPE 43 mOhm @4.5V 0.4 A (EDP)
IN
=PPBUS_S0_LCDBKLT
PPBUS_S0_LCDBKLT_FUSED
1 2 5 6
F9800
4
0402-HF
R9808
301K
1% 1/16W MF-LF 402
C9802
0.1UF
10% 16V X5R 402
PPBUS_S0_LCDBKLT_EN_DIV
R9809
147K
1% 1/16W MF-LF
2 402
PPBUS_S0_LCDBKLT_EN_L
Q9807
SSM6N15FEAPE
SOT563
D 3
85 9
IN
LVDS_BKL_ON
5 G
S 4
BKLT_EN_L
OUT
84
Q9807
SSM6N15FEAPE
SOT563
D 6
C
26
IN
BKLT_PLT_RST_L
2 G
S 1
LVDS_BKL_ON
9 85
R9840
4.7K
5% 1/16W MF-LF
LCD Backlight Support

SYNC_MASTER=YITE_M98_MLB SYNC_DATE=07/02/2008
2 402

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
85
96
2.5V/1.2V S3 Switcher
D D
=PP3V3_S0_P1V2P2V5
C9900
2.2UF
CRITICAL 2.2UH-1.2A P1V2S0_SW

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE 1 PCAA031B-SM 2 1
L9980
20% 6.3V CERM 2 402-LF
=PP1V2_S0_REG
C9982 1
10PF
<Ra> R9982
280K
VIN
5% 50V CERM 2 402
1% 1/16W MF-LF 2 402
U9900 DFN-HF
LTC3547
P1V2S0_VFB
1
Vout = 1.2V 300mA max output (Switcher limit) f = 2.25 MHz 1 C9985
20% 2 4V X5R 402
CRITICAL 6 1 VFB1 SW2 8 VFB2

RUN1 2 RUN2 7
SW1 4
<Rb> R9983
280K
4.7UF
CRITICAL 2.2UH-1.2A P2V5S0_SW

1 PCAA031B-SM 2
THRML PAD 9
L9900
1% 1/16W MF-LF 2 402
GND 5
=PP2V5_S0_REG
C9901 1
10PF
5% 50V CERM 2 402
<Ra>
1
R9900
475K
1
P2V5S0_VFB
1% 1/16W MF-LF 2 402
Vout = 2.5V 0.3A max output (Switcher limit) f = 2.25 MHz C9905
4.7UF
<Rb>
1
68
IN
=P2V5S0_EN =P1V2S0_EN
R9901
150K
20% 4V 2 X5R 402
68
1% 1/16W MF-LF 2 402
Vout = 0.6V * (1 + Ra/Rb)
Misc Power Supplies
SYNC_MASTER=MUXGFX

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
86
96
8
PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH
7
MINIMUM NECK WIDTH MAXIMUM NECK LENGTH
6
TABLE_PHYSICAL_RULE_HEAD
5
DIFFPAIR NECK GAP
TABLE_PHYSICAL_RULE_ITEM
4
CPU / FSB Net Properties
ELECTRICAL_CONSTRAINT_SET FSB_DATA_GROUP0 FSB_DATA_GROUP0 FSB_DSTB0 FSB_DSTB0 FSB_DATA_GROUP1 FSB_DATA_GROUP1 FSB_DSTB1 FSB_DSTB1 FSB_DATA_GROUP2 FSB_DATA_GROUP2 FSB_DSTB2 FSB_DSTB2 FSB_DATA_GROUP3 FSB_DATA_GROUP3 FSB_DSTB3 FSB_DSTB3 FSB_ADDR_GROUP0 FSB_ADDR_GROUP0 FSB_ADSTB0 FSB_ADDR_GROUP1 FSB_ADSTB1 FSB_1X FSB_BREQ0_L FSB_BREQ1_L FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_CPURST_L FSB_1X FSB_1X CPU_ASYNC CPU_BSEL CPU_FERR_L CPU_ASYNC CPU_INIT_L CPU_ASYNC_R CPU_ASYNC_R CPU_PROCHOT_L CPU_PWRGD CPU_ASYNC CPU_ASYNC PM_THRMTRIP_L FSB_CPUSLP_L CPU_FROM_SB CPU_DPRSTP_L CPU_ASYNC MCP_CPU_COMP MCP_CPU_COMP MCP_CPU_COMP MCP_CPU_COMP FSB_CLK_CPU FSB_CLK_CPU FSB_CLK_ITP FSB_CLK_ITP FSB_CLK_MCP FSB_CLK_MCP CPU_IERR_L PM_DPRSLPVR NET_TYPE PHYSICAL SPACING FSB_50S FSB_50S FSB_DSTB_50S FSB_DSTB_50S FSB_50S FSB_50S FSB_DSTB_50S FSB_DSTB_50S FSB_50S FSB_50S FSB_DSTB_50S FSB_DSTB_50S FSB_50S FSB_50S FSB_DSTB_50S FSB_DSTB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S FSB_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S MCP_50S MCP_50S MCP_50S MCP_50S CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CLK_FSB_100D CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_27P4S CPU_50S CPU_27P4S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_AGTL CPU_AGTL CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_8MIL CPU_8MIL CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB FSB_DATA FSB_DATA FSB_DSTB FSB_DSTB FSB_ADDR FSB_ADDR FSB_ADSTB FSB_ADDR FSB_ADSTB FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X FSB_1X CPU_AGTL CPU_AGTL CPU_8MIL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL CPU_8MIL CPU_AGTL CPU_AGTL CPU_AGTL CPU_AGTL MCP_FSB_COMP MCP_FSB_COMP MCP_FSB_COMP MCP_FSB_COMP CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB CLK_FSB
FSB (Front-Side Bus) Constraints

DIFFPAIR PRIMARY GAP
FSB_50S FSB_DSTB_50S
* *
=50_OHM_SE
=50_OHM_SE =50_OHM_SE
TABLE_SPACING_RULE_HEAD
=STANDARD =1:1_DIFFPAIR
=STANDARD
=50_OHM_SE
=1:1_DIFFPAIR
FSB 4X Signal Groups
FSB_D_L<15..0> FSB_DINV_L<0> FSB_DSTB_L_P<0> FSB_DSTB_L_N<0> FSB_D_L<31..16> FSB_DINV_L<1> FSB_DSTB_L_P<1> FSB_DSTB_L_N<1> FSB_D_L<47..32> FSB_DINV_L<2> FSB_DSTB_L_P<2> FSB_DSTB_L_N<2> FSB_D_L<63..48> FSB_DINV_L<3> FSB_DSTB_L_P<3> FSB_DSTB_L_N<3> FSB_A_L<16..3> FSB_REQ_L<4..0> FSB_ADSTB_L<0> FSB_A_L<35..17> FSB_ADSTB_L<1> FSB_ADS_L FSB_BREQ0_L FSB_BREQ1_L FSB_BNR_L FSB_BPRI_L FSB_DBSY_L FSB_DEFER_L FSB_DRDY_L FSB_HIT_L FSB_HITM_L FSB_LOCK_L FSB_CPURST_L FSB_RS_L<2..0> FSB_TRDY_L CPU_A20M_L CPU_BSEL<2..0> CPU_FERR_L CPU_IGNNE_L CPU_INIT_L CPU_INTR CPU_NMI CPU_PROCHOT_L CPU_PWRGD CPU_SMI_L CPU_STPCLK_L PM_THRMTRIP_L FSB_CPUSLP_L CPU_DPSLP_L CPU_DPRSTP_L FSB_DPWR_L MCP_BCLK_VML_COMP_VDD MCP_BCLK_VML_COMP_GND MCP_CPU_COMP_VCC MCP_CPU_COMP_GND FSB_CLK_CPU_P FSB_CLK_CPU_N FSB_CLK_ITP_P FSB_CLK_ITP_N FSB_CLK_MCP_P FSB_CLK_MCP_N CPU_IERR_L PM_DPRSLPVR IMVP_DPRSLPVR CPU_GTLREF CPU_COMP<3> CPU_COMP<2> CPU_COMP<1> CPU_COMP<0> XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L<4..0> XDP_BPM_L<5> XDP_CPURST_L CPU_VID<6..0> IMVP6_VID<6..0> CPU_VCCSENSE_P CPU_VCCSENSE_N IMVP6_VSEN_P IMVP6_VSEN_N
7 10 14 7 10 14 7 10 14 7 10 14
SPACING_RULE_SET
LAYER
LINE-TO-LINE SPACING
WEIGHT
TABLE_SPACING_RULE_ITEM
SPACING_RULE_SET
LAYER
WEIGHT
FSB_DATA FSB_DSTB
* * * * *
=2x_DIELECTRIC =3x_DIELECTRIC =STANDARD =2x_DIELECTRIC =STANDARD
?
FSB_DATA FSB_DSTB
TOP,BOTTOM TOP,BOTTOM TOP,BOTTOM TOP,BOTTOM TOP,BOTTOM
=4x_DIELECTRIC =5x_DIELECTRIC =3x_DIELECTRIC =4x_DIELECTRIC =3x_DIELECTRIC
?
7 10 14 7 10 14 7 10 14 7 10 14
? ?
?
FSB_ADDR FSB_ADSTB FSB_1X
FSB_ADDR FSB_ADSTB
?
? ?
?
7 10 14 7 10 14 7 10 14 7 10 14
FSB_1X
All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended. FSB 4X signals / groups shown in signal table on right. Signals within each 4x group should be matched within 5 ps of strobe. DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps. Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s. DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs. FSB 2X signals / groups shown in signal table on right. Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps. Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#. FSB 1X signals shown in signal table on right. Signals within each 1x group should be matched to CPU clock, +0/-1000 mils.
7 10 14 7 10 14 7 10 14 7 10 14
FSB 2X Signals
7 10 14 7 10 14
7 10 14 7 10 14
7 10 14 9 10 14 14 10 14 10 14 10 14 10 14 10 14 7 10 14 7 10 14 7 10 14 9 10 13 14 10 14 10 14
NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened. SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2 SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3
CPU Signal Constraints

PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER?
FSB 1X Signals
Design Guide recommends each strobe/signal group is routed on the same layer. Intel Design Guide recommends FSB signals be routed only on internal layers.
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

CPU_50S CPU_27P4S
* *
=50_OHM_SE
=27P4_OHM_SE
=50_OHM_SE =27P4_OHM_SE
=STANDARD 7 MIL
=STANDARD
7 MIL
NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.
TABLE_SPACING_RULE_HEAD TABLE_SPACING_RULE_HEAD
10 14 9 10 10 14 10 14 10 14 9 10 14 9 10 14 10 14 43 62 10 13 14 10 14 10 14 10 14 43 10 14 10 14 9 10 14 62 10 14 14 14 14 14
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
CPU_AGTL CPU_8MIL CPU_COMP CPU_GTLREF CPU_ITP CPU_VCCSENSE
* * * * * *
=STANDARD 8 MIL 25 MIL 25 MIL =2:1_SPACING 25 MIL
?
CPU_AGTL
TOP,BOTTOM
=2x_DIELECTRIC
?
?
?
SR DG recommends at least 25 mils, >50 mils preferred

? ?
Most CPU signals with impedance requirements are 55-ohm single-ended. Some signals require 27.4-ohm single-ended impedance. SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2 SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4
MCP FSB COMP Signal Constraints

PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

MCP_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
10 14 10 14 13 14 13 14 14 14
B
SPACING_RULE_SET LAYER LINE-TO-LINE SPACING
WEIGHT
MCP_FSB_COMP
8 MIL
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4
10
FSB Clock Constraints

21 62 62
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER? =100_OHM_DIFF
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

(See above)
CPU_GTLREF CPU_COMP CPU_COMP CPU_COMP CPU_COMP XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L XDP_BPM_L5
CLK_FSB_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
10 27 10 10 10 10
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
CLK_FSB
=3x_DIELECTRIC
CLK_FSB
TOP,BOTTOM
=4x_DIELECTRIC
6 10 13 6 10 6 10 13 6 10 13 6 10 13 10 13 10 13 13
(FSB_CPURST_L)
9 11 9 62 11 62 11 62 62 62
CPU/FSB Constraints
CPU_VCCSENSE CPU_VCCSENSE
(CPU_VCCSENSE) (CPU_VCCSENSE)

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
87
96
7 10 14
8
Memory Bus Constraints
7
6
5
DIFFPAIR NECK GAP
4
Memory Net Properties
ELECTRICAL_CONSTRAINT_SET MEM_A_CLK MEM_A_CLK MEM_A_CNTL MEM_A_CNTL MEM_A_CNTL MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_DQ_BYTE0 MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE2 MEM_A_DQ_BYTE3 MEM_A_DQ_BYTE4 MEM_A_DQ_BYTE5 MEM_A_DQ_BYTE6 MEM_A_DQ_BYTE7 MEM_A_DQ_BYTE0 MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE2 MEM_A_DQ_BYTE3 MEM_A_DQ_BYTE4 MEM_A_DQ_BYTE5 MEM_A_DQ_BYTE6 MEM_A_DQ_BYTE7 MEM_A_DQS0 MEM_A_DQS0 MEM_A_DQS1 MEM_A_DQS1 MEM_A_DQS2 MEM_A_DQS2 MEM_A_DQS3 MEM_A_DQS3 MEM_A_DQS4 MEM_A_DQS4 MEM_A_DQS5 MEM_A_DQS5 MEM_A_DQS6 MEM_A_DQS6 MEM_A_DQS7 MEM_A_DQS7 MEM_B_CLK MEM_B_CLK MEM_B_CNTL MEM_B_CNTL MEM_B_CNTL MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE3 MEM_B_DQ_BYTE4 MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE7 MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE3 MEM_B_DQ_BYTE4 MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE7 MEM_B_DQS0 MEM_B_DQS0 MEM_B_DQS1 MEM_B_DQS1 MEM_B_DQS2 MEM_B_DQS2 MEM_B_DQS3 MEM_B_DQS3 MEM_B_DQS4 MEM_B_DQS4 MEM_B_DQS5 MEM_B_DQS5 MEM_B_DQS6 MEM_B_DQS6 MEM_B_DQS7 MEM_B_DQS7 MCP_MEM_COMP MCP_MEM_COMP NET_TYPE PHYSICAL SPACING MEM_70D_VDD MEM_70D_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D_VDD MEM_70D_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S_VDD MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MEM_70D MCP_MEM_COMP MCP_MEM_COMP MEM_CLK MEM_CLK MEM_CTRL MEM_CTRL MEM_CTRL MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_CLK MEM_CLK MEM_CTRL MEM_CTRL MEM_CTRL MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MCP_MEM_COMP MCP_MEM_COMP
MEM_40S MEM_40S_VDD MEM_70D MEM_70D_VDD
* * * *
=70_OHM_DIFF =70_OHM_DIFF
=40_OHM_SE =40_OHM_SE =70_OHM_DIFF =70_OHM_DIFF

=STANDARD =STANDARD =70_OHM_DIFF =70_OHM_DIFF
=STANDARD
=STANDARD
MEM_A_CLK_P<5..0> MEM_A_CLK_N<5..0> MEM_A_CKE<3..0> MEM_A_CS_L<3..0> MEM_A_ODT<3..0> MEM_A_A<14..0> MEM_A_BA<2..0> MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L MEM_A_DQ<7..0> MEM_A_DQ<15..8> MEM_A_DQ<23..16> MEM_A_DQ<31..24> MEM_A_DQ<39..32> MEM_A_DQ<47..40> MEM_A_DQ<55..48> MEM_A_DQ<63..56> MEM_A_DM<0> MEM_A_DM<1> MEM_A_DM<2> MEM_A_DM<3> MEM_A_DM<4> MEM_A_DM<5> MEM_A_DM<6> MEM_A_DM<7> MEM_A_DQS_P<0> MEM_A_DQS_N<0> MEM_A_DQS_P<1> MEM_A_DQS_N<1> MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<3> MEM_A_DQS_N<3> MEM_A_DQS_P<4> MEM_A_DQS_N<4> MEM_A_DQS_P<5> MEM_A_DQS_N<5> MEM_A_DQS_P<6> MEM_A_DQS_N<6> MEM_A_DQS_P<7> MEM_A_DQS_N<7> MEM_B_CLK_P<5..0> MEM_B_CLK_N<5..0> MEM_B_CKE<3..0> MEM_B_CS_L<3..0> MEM_B_ODT<3..0> MEM_B_A<14..0> MEM_B_BA<2..0> MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L MEM_B_DQ<7..0> MEM_B_DQ<15..8> MEM_B_DQ<23..16> MEM_B_DQ<31..24> MEM_B_DQ<39..32> MEM_B_DQ<47..40> MEM_B_DQ<55..48> MEM_B_DQ<63..56> MEM_B_DM<0> MEM_B_DM<1> MEM_B_DM<2> MEM_B_DM<3> MEM_B_DM<4> MEM_B_DM<5> MEM_B_DM<6> MEM_B_DM<7> MEM_B_DQS_P<0> MEM_B_DQS_N<0> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<7> MEM_B_DQS_N<7> MCP_MEM_COMP_VDD MCP_MEM_COMP_GND
15 28 15 28
=70_OHM_DIFF
15 28 15 28 15 28
=70_OHM_DIFF
15 28 15 28 15 28 15 28 15 28
SPACING_RULE_SET
LAYER
WEIGHT
MEM_CLK2MEM MEM_CTRL2CTRL MEM_CTRL2MEM MEM_CMD2CMD MEM_CMD2MEM MEM_DATA2DATA MEM_DATA2MEM MEM_DQS2MEM MEM_2OTHER
* * * * * * * * *
=4:1_SPACING =2:1_SPACING =2.5:1_SPACING =1.5:1_SPACING =3:1_SPACING =1.5:1_SPACING =3:1_SPACING =3:1_SPACING 25 MIL
?
?
?
15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28
?
?
?
?
?
15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28
Memory Bus Spacing Group Assignments

TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
TABLE_SPACING_ASSIGNMENT_ITEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CLK MEM_CLK MEM_CLK MEM_CLK MEM_CLK
MEM_CLK MEM_CTRL MEM_CMD MEM_DATA MEM_DQS
* * * * *
MEM_CLK2MEM
MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD
* * * * *
MEM_CMD2MEM
MEM_CLK2MEM
MEM_CMD2MEM
MEM_CLK2MEM
MEM_CMD2CMD
15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28 15 28
MEM_CLK2MEM
MEM_CMD2MEM
MEM_CLK2MEM
TABLE_SPACING_ASSIGNMENT_HEAD
MEM_CMD2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_CTRL MEM_CTRL MEM_CTRL MEM_CTRL MEM_CTRL
* * * * *
MEM_CTRL2MEM
MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA
* * * * *
MEM_DATA2MEM
MEM_CTRL2CTRL
MEM_DATA2MEM
MEM_CTRL2MEM
MEM_DATA2MEM
MEM_CTRL2MEM
MEM_DATA2DATA
MEM_CTRL2MEM
MEM_DATA2MEM
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS
* * * * *
MEM_DQS2MEM
* * * * *
* * * * *
MEM_2OTHER
15 29 15 29
MEM_DQS2MEM
MEM_2OTHER
15 29 15 29 15 29
MEM_DQS2MEM
MEM_2OTHER
MEM_DQS2MEM
MEM_2OTHER
MEM_DQS2MEM
MEM_2OTHER
15 29 15 29 15 29 15 29 15 29
Need to support MEM_*-style wildcards!
DDR2:
DQ signals should be matched within 20 ps of associated DQS pair. DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement. All DQS pairs should be matched within 100 ps of clocks. CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps. A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement. All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate). DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.
15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29
DDR3:
DQ signals should be matched within 5 ps of associated DQS pair. DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps No DQS to clock matching requirement. CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps. A/BA/cmd signals should be matched within 5 ps of CLK pairs. All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate). DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric. SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3 SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2
15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29
MCP MEM COMP Signal Constraints

15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29 15 29
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

MCP_MEM_COMP
7 MIL
7 MIL
=STANDARD
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
MCP_MEM_COMP
8 MIL
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4
Memory Constraints

16 16
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
88
96
8
PCI-Express
PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? =90_OHM_DIFF =100_OHM_DIFF MINIMUM LINE WIDTH
7
6
5
DIFFPAIR NECK GAP
4
ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D CLK_PCIE_100D PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE MCP_PEX_COMP CRT CRT CRT CRT_SYNC CRT_SYNC MCP_DAC_COMP MCP_DAC_COMP DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT
PCIE_90D CLK_PCIE_100D
* *
13.1 MM =100_OHM_DIFF
=90_OHM_DIFF
=100_OHM_DIFF
PEG_R2D
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
PEG_D2R
PCIE CLK_PCIE
* * *
=3X_DIELECTRIC 20 MIL 8 MIL
?
PCIE
TOP,BOTTOM
=4X_DIELECTRIC
?
PEG_R2D_P<15..0> PEG_R2D_N<15..0> PEG_R2D_C_P<15..0> PEG_R2D_C_N<15..0> PEG_D2R_P<15..0> PEG_D2R_N<15..0> PEG_D2R_C_P<15..0> PEG_D2R_C_N<15..0> PCIE_MINI_R2D_P PCIE_MINI_R2D_N PCIE_MINI_R2D_C_P PCIE_MINI_R2D_C_N PCIE_MINI_D2R_P PCIE_MINI_D2R_N PCIE_FW_R2D_P PCIE_FW_R2D_N PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_FW_D2R_C_P PCIE_FW_D2R_C_N PCIE_EXCARD_R2D_P PCIE_EXCARD_R2D_N PCIE_EXCARD_R2D_C_P PCIE_EXCARD_R2D_C_N PCIE_EXCARD_D2R_P PCIE_EXCARD_D2R_N PEG_CLK100M_P PEG_CLK100M_N PCIE_CLK100M_MINI_P PCIE_CLK100M_MINI_N PCIE_CLK100M_FW_P PCIE_CLK100M_FW_N PCIE_CLK100M_EXCARD_P PCIE_CLK100M_EXCARD_N MCP_PEX_CLK_COMP CRT_IG_R_C_PR CRT_IG_G_Y_Y CRT_IG_B_COMP_PB CRT_IG_HSYNC CRT_IG_VSYNC MCP_TV_DAC_RSET MCP_TV_DAC_VREF TMDS_IG_TXC_P TMDS_IG_TXC_N TMDS_IG_TXD_P<2..0> TMDS_IG_TXD_N<2..0> DP_IG_ML_P<3..0> DP_IG_ML_N<3..0> DP_IG_AUX_CH_P DP_IG_AUX_CH_N MCP_HDMI_RSET MCP_HDMI_VPROBE
70 70 9 70 9 70 9 70 9 70 70 70
MCP_PEX_COMP
?
PCIE_MINI_R2D
31 95 31 95 17 31 17 31 17 31 17 31
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4
Analog Video Signal Constraints

PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
PCIE_MINI_D2R
CRT_50S
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=50_OHM_SE
=STANDARD
=STANDARD
36 36 17 36 17 36 17 36 17 36 36 36
SPACING_RULE_SET
LAYER
WEIGHT
NET_SPACING_TYPE1
NET_SPACING_TYPE2
AREA_TYPE
SPACING_RULE_SET
PCIE_FW_R2D PCIE_FW_D2R
CRT CRT_2CRT CRT_2CLK CRT_2SWITCHER CRT_SYNC MCP_DAC_COMP
* * * * * *
=4:1_SPACING =STANDARD 50 MIL 250 MIL 16 MIL =2:1_SPACING
?
CRT
CRT
CRT_2CRT
?
?
?
7 32 95 7 32 95 17 32 17 32 7 17 32 7 17 32
?
PCIE_EXCARD_R2D PCIE_EXCARD_D2R
CRT signal single-ended impedence varies by location: - 37.5-ohm from MCP to first termination resistor. - 50-ohm from first to second termination resistor. - 75-ohm from output of three-pole filter to connector (if possible). R/G/B signals should be matched as close as possible and < 10 inches. SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.1 & 2.5.2.
MCP_PE0_REFCLK MCP_PE1_REFCLK MCP_PE2_REFCLK

17 70 17 70 17 31 17 31 17 36 17 36 17 32 17 32 17
C Digital Video Signal Constraints

PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? =100_OHM_DIFF =100_OHM_DIFF Y MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
MCP_PE3_REFCLK MCP_PEX_CLK_COMP CRT_RED CRT_GREEN CRT_BLUE CRT_SYNC CRT_SYNC MCP_DAC_RSET MCP_DAC_VREF TMDS_IG_TXC TMDS_IG_TXC TMDS_IG_TXD TMDS_IG_TXD DP_ML DP_ML DP_AUX_CH DP_AUX_CH MCP_HDMI_RSET MCP_HDMI_VPROBE LVDS_IG_A_CLK LVDS_IG_A_CLK LVDS_IG_A_DATA LVDS_IG_A_DATA LVDS_IG_A_DATA3 LVDS_IG_A_DATA3 LVDS_IG_B_CLK LVDS_IG_B_CLK LVDS_IG_B_DATA LVDS_IG_B_DATA LVDS_IG_B_DATA3 LVDS_IG_B_DATA3 MCP_IFPAB_RSET MCP_IFPAB_VPROBE SATA_HDD_R2D
DP_100D LVDS_100D MCP_DV_COMP
* * *
=100_OHM_DIFF =100_OHM_DIFF 20 MIL

=100_OHM_DIFF =100_OHM_DIFF 20 MIL
=100_OHM_DIFF =100_OHM_DIFF =STANDARD
=100_OHM_DIFF =100_OHM_DIFF =STANDARD
=100_OHM_DIFF
=100_OHM_DIFF
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
CRT_50S CRT_50S CRT_50S CRT_50S CRT_50S
18 25 18 25 18 25 18 25 18 25 18 25 18 25
DISPLAYPORT LVDS
* *
=3x_DIELECTRIC =3x_DIELECTRIC
?
DISPLAYPORT LVDS
TOP,BOTTOM TOP,BOTTOM
?
LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length. DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps. DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals. Max length of LVDS/DisplayPort/TMDS traces: 12 inches. SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.
DP_100D DP_100D DP_100D DP_100D DP_100D DP_100D DP_100D DP_100D MCP_DV_COMP MCP_DV_COMP LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D MCP_DV_COMP
9 80 9 80 18 80 18 80
SATA Interface Constraints

PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

SATA_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
18 25 18 25
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
SATA SATA_TERMP
* *
=4x_DIELECTRIC 8 MIL
?
SATA
TOP,BOTTOM
=3x_DIELECTRIC
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.
LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS
LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N LVDS_IG_A_DATA_P<2..0> LVDS_IG_A_DATA_N<2..0> LVDS_IG_A_DATA_P<3> LVDS_IG_A_DATA_N<3> LVDS_IG_B_CLK_P LVDS_IG_B_CLK_N LVDS_IG_B_DATA_P<2..0> LVDS_IG_B_DATA_N<2..0> LVDS_IG_B_DATA_P<3> LVDS_IG_B_DATA_N<3> MCP_IFPAB_RSET MCP_IFPAB_VPROBE
18 83 18 83 18 83 18 83 9 18 9 18 9 18 9 18 18 83 18 83 9 18 9 18
18 25 18 25
SATA_HDD_D2R
SATA_ODD_R2D
SATA_ODD_D2R
SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D
SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA_TERMP
SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_D2R_P SATA_HDD_D2R_N SATA_HDD_D2R_C_P SATA_HDD_D2R_C_N SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N SATA_ODD_D2R_P SATA_ODD_D2R_N SATA_ODD_D2R_C_P SATA_ODD_D2R_C_N MCP_SATA_TERMP
20 39 20 39 39 39 20 39 20 39 39 39 20 39 20 39 7 39 7 39 20 39 20 39 7 39 7 39
MCP Constraints 1

MCP_SATA_TERMP
20
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
89
96
8
PCI Bus Constraints
7
6
5
DIFFPAIR NECK GAP
4
ELECTRICAL_CONSTRAINT_SET MCP_DEBUG PCI_AD PCI_AD24 PCI_AD PCI_AD PCI_C_BE_L PCI_CNTL PCI_CNTL PCI_CNTL PCI_CNTL PCI_CNTL PCI_CNTL PCI_CNTL PCI_REQ0_L PCI_GNT0_L PCI_REQ1_L PCI_GNT1_L PCI_INTW_L PCI_INTX_L PCI_INTY_L PCI_INTZ_L MCP_PCI_CLK2 NET_TYPE PHYSICAL SPACING PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S PCI_55S CLK_PCI_55S CLK_PCI_55S LPC_55S LPC_55S LPC_55S CLK_LPC_55S CLK_LPC_55S CLK_LPC_55S USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D MCP_USB_RBIAS SMB_55S SMB_55S SMB_55S SMB_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S HDA_55S SMB SMB SMB SMB HDA HDA HDA HDA HDA HDA HDA HDA HDA HDA MCP_HDA_COMP CLK_SLOW_55S CLK_SLOW_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S CLK_SLOW CLK_SLOW SPI SPI SPI SPI SPI SPI SPI SPI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI PCI CLK_PCI CLK_PCI LPC LPC LPC CLK_LPC CLK_LPC CLK_LPC USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB
PCI_55S CLK_PCI_55S
* *
=STANDARD =STANDARD
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
PCI CLK_PCI
* *
=STANDARD 8 MIL
?
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.
LPC Bus Constraints

PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

LPC_55S CLK_LPC_55S
* *
=STANDARD =STANDARD
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
LPC CLK_LPC
* *
6 MIL 8 MIL
?
PCI_CLK33M_MCP_R PCI_CLK33M_MCP LPC_AD<3..0> LPC_FRAME_L LPC_RESET_L LPC_CLK33M_SMC_R LPC_CLK33M_SMC LPC_CLK33M_LPCPLUS USB_EXTA_P USB_EXTA_N USB_EXTA_MUXED_P USB_EXTA_MUXED_N USB_MINI_P USB_MINI_N USB_EXTD_P USB_EXTD_N USB_CAMERA_P USB_CAMERA_N USB_BT_P USB_BT_N USB_TPAD_P USB_TPAD_N USB_IR_P USB_IR_N USB_EXTB_P USB_EXTB_N USB_EXCARD_P USB_EXCARD_N USB_EXTC_P USB_EXTC_N MCP_USB_RBIAS_GND SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 HDA_SDIN_CODEC HDA_SDOUT HDA_SDOUT_R MCP_HDA_PULLDN_COMP PM_CLK32K_SUSCLK_R PM_CLK32K_SUSCLK SPI_CLK_R SPI_CLK SPI_MOSI_R SPI_MOSI SPI_MISO SPI_MISO_R SPI_CS0_R_L SPI_CS0_L
19 19
USB 2.0 Interface Constraints

PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

LPC_AD LPC_FRAME_L LPC_RESET_L MCP_LPC_CLK0
19 42 44 83 19 42 44 83 19 26 83
MCP_USB_RBIAS USB_90D
* *
=STANDARD
=90_OHM_DIFF
8 MIL =90_OHM_DIFF
8 MIL =90_OHM_DIFF
=STANDARD =90_OHM_DIFF
=STANDARD =90_OHM_DIFF
=STANDARD
19 26 26 42 26 44
=90_OHM_DIFF
USB_EXTA
20 40 20 40
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
USB
=2x_DIELECTRIC
USB
TOP,BOTTOM
=4x_DIELECTRIC
?
USB_MINI USB_EXTD
9 20 9 20 9 20 9 20 20 31 20 31 20 31 20 31 20 50 20 50 20 41 20 41 20 40 20 40 20 32 20 32 9 20 9 20
SMBus Interface Constraints

USB_CAMERA USB_BT
SMB_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
USB_TPAD USB_IR
SMB
=2x_DIELECTRIC
HD Audio Interface Constraints

USB_EXTB USB_EXCARD USB_EXTC
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

HDA_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
MCP_USB_RBIAS SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK SMBUS_MCP_1_DATA HDA_BIT_CLK

20
HDA MCP_HDA_COMP
* *
=2x_DIELECTRIC 8 MIL
?
7 13 21 45 7 13 21 45 21 45 21 45
B SIO Signal Constraints

PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP
9 21 21 21 54 21 21 21 54 21 54
HDA_SYNC HDA_RST_L HDA_SDIN0 HDA_SDOUT
DIFFPAIR NECK GAP

CLK_SLOW_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPACING_RULE_SET
LAYER
WEIGHT
CLK_SLOW
8 MIL
21 54 21
MCP_HDA_PULLDN_COMP MCP_SUS_CLK
21
SPI Interface Constraints

21 26 26 42
SPI_55S
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=55_OHM_SE
=STANDARD
=STANDARD
SPI_CLK SPI_MOSI
21 44 44 53 21 44 44 53 21 44 53 21 44
SPACING_RULE_SET
LAYER
WEIGHT
SPI
8 MIL
SPI_MISO SPI_CS0
MCP Constraints 2
SYNC_MASTER=MUXGFX

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
90
96
MCP_DEBUG<7..0> PCI_AD<23..8> PCI_AD<24> PCI_AD<31..25> PCI_PAR PCI_C_BE_L<3..0> PCI_IRDY_L PCI_DEVSEL_L PCI_PERR_L PCI_SERR_L PCI_STOP_L PCI_TRDY_L PCI_FRAME_L PCI_REQ0_L PCI_GNT0_L PCI_REQ1_L PCI_GNT1_L PCI_INTW_L PCI_INTX_L PCI_INTY_L PCI_INTZ_L
13 19
D
19
19
8
7
6
5
DIFFPAIR NECK GAP
4
ELECTRICAL_CONSTRAINT_SET MCP_MII_COMP MCP_MII_COMP MCP_CLK25M_BUF0 NET_TYPE PHYSICAL SPACING MCP_MII_COMP MCP_MII_COMP ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MII_55S ENET_MDI MCP_BUF0_CLK MCP_BUF0_CLK ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII ENET_MII
MCP RGMII (Ethernet) Constraints

MCP_MII_COMP ENET_MII_55S
* *
=STANDARD =55_OHM_SE
7.5 MIL =55_OHM_SE

7.5 MIL =55_OHM_SE
=STANDARD =55_OHM_SE
=STANDARD =STANDARD
=STANDARD
=STANDARD
MCP_MII_COMP_VDD MCP_MII_COMP_GND MCP_CLK25M_BUF0_R RTL8211_CLK25M_CKXTAL1 ENET_INTR_L ENET_MDIO ENET_MDC ENET_PWRDWN_L ENET_CLK125M_RXCLK_R ENET_CLK125M_RXCLK ENET_RXD_R<3..0> ENET_RXD<0> ENET_RXD<3..1> ENET_RX_CTRL ENET_CLK125M_TXCLK ENET_TXD<0> ENET_TXD<3..1> ENET_TX_CTRL ENET_RESET_L ENET_MDI_P<3..0> ENET_MDI_N<3..0>
18 18
18 34 33 34
SPACING_RULE_SET
LAYER
WEIGHT
MCP_BUF0_CLK ENET_MII
* *
=3:1_SPACING 12 MIL
?
SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4
ENET_INTR_L ENET_MDIO ENET_MDC ENET_PWRDWN_L
18 33 18 33
88E1116R (Ethernet PHY) Constraints

33 18 33 33 18 33 18 33 18 33
ENET_RXCLK
DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
ENET_MDI_100D
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
=100_OHM_DIFF
ENET_RXD ENET_RXD_STRAP ENET_RXD ENET_TXCLK ENET_TXD0 ENET_TXD ENET_TXD
SPACING_RULE_SET
LAYER
WEIGHT
18 33 18 33 18 33 18 33
ENET_MDI
25 MIL
18 33
ENET_MDI_100D ENET_MDI ENET_MDI_100D ENET_MDI
33 35 33 35
Ethernet Constraints
SYNC_MASTER=MUXGFX

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
91
96
8
PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? =110_OHM_DIFF MINIMUM LINE WIDTH
7
6
5
DIFFPAIR NECK GAP
4
FireWire Net Properties
ELECTRICAL_CONSTRAINT_SET FW_P0_TPA FW_P0_TPA FW_P0_TPB FW_P0_TPB FW_P1_TPA FW_P1_TPA FW_P1_TPB FW_P1_TPB NET_TYPE PHYSICAL SPACING FW_110D FW_110D FW_110D FW_110D FW_110D FW_110D FW_110D FW_110D FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP
FireWire Interface Constraints

FW_110D
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
=110_OHM_DIFF
SPACING_RULE_SET
LAYER
WEIGHT
FW_TP
=3:1_SPACING
FW_P0_TPA_P FW_P0_TPA_N FW_P0_TPB_P FW_P0_TPB_N FW_P1_TPA_P FW_P1_TPA_N FW_P1_TPB_P FW_P1_TPB_N
36 38 36 38 36 38 36 38 36 38 36 38 36 38 36 38
D
Port 2 Not Used
FireWire Constraints
SYNC_MASTER=MUXGFX

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
92
96
8
7
6
5
DIFFPAIR NECK GAP
4
SMC SMBus Net Properties
ELECTRICAL_CONSTRAINT_SET SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA NET_TYPE PHYSICAL SPACING SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB_55S SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB
1TO1_DIFFPAIR
=STANDARD
=STANDARD
=STANDARD
=STANDARD
0.1 MM
0.1 MM
SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA
7 45 7 45 45 45 45 45 45 45 45 45
SMBus Charger Net Properties

ELECTRICAL_CONSTRAINT_SET CHGR_CSI NET_TYPE PHYSICAL SPACING 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR
CHGR_CSI_P CHGR_CSI_N CHGR_CSO_P CHGR_CSO_N
61 61
61
SMC Constraints
SYNC_MASTER=MUXGFX

D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
93
96
CHGR_CSO
61
8
PHYSICAL_RULE_SET
GDDR3_40R55SE GDDR3_40SE GDDR3_80D
7
LAYER
* * *
6
5
GDDR3 FB A/B Net Properties
DIFFPAIR NECK GAP
4
NET_TYPE PHYSICAL GDDR3_80D GDDR3_80D SPACING GDDR3_CLK GDDR3_CLK GDDR3_CLK GDDR3_CLK GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA
3
NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL GDDR3_80D GDDR3_80D FB_D_CLK_P GDDR3_80D GDDR3_80D FB_CD_CMD FB_CD_CMD FB_CD_CMD FB_CD_CMD FB_CD_CMD FB_CD_CMD FB_CD_CMD_PD FB_CD_CS0 FB_CD_CMD_PD FB_C_CMD FB_D_CMD FB_C_WDQS0 FB_C_WDQS1 FB_C_WDQS2 FB_C_WDQS3 FB_C_RDQS0 FB_C_RDQS1 FB_C_RDQS2 FB_C_RDQS3 FB_C_DQ_BYTE0 FB_C_DQ_BYTE1 FB_C_DQ_BYTE2 FB_C_DQ_BYTE3 FB_C_DQM0 FB_C_DQM1 FB_C_DQM2 FB_C_DQM3 FB_D_WDQS0 FB_D_WDQS1 FB_D_WDQS2 FB_D_WDQS3 FB_D_RDQS0 FB_D_RDQS1 FB_D_RDQS2 FB_D_RDQS3 FB_D_DQ_BYTE0 FB_D_DQ_BYTE1 FB_D_DQ_BYTE2 FB_D_DQ_BYTE3 FB_D_DQM0 FB_D_DQM1 FB_D_DQM2 FB_D_DQM3 GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE
2
SPACING GDDR3_CLK GDDR3_CLK GDDR3_CLK GDDR3_CLK GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA
GDDR3 Frame Buffer Signal Constraints

=55_OHM_SE
GDDR3 FB C/D Net Properties

FB_A_CLK_P<0> FB_A_CLK_N<0> FB_A_CLK_P<1> FB_A_CLK_N<1> FB_A_MA<1..0> FB_A_MA<12..6> FB_A_BA<2..0> FB_A_RAS_L FB_A_CAS_L FB_A_WE_L FB_A_CKE FB_A_CS0_L FB_A_DRAM_RST FB_A_LMA<5..2> FB_A_UMA<5..2> FB_A_WDQS<0> FB_A_WDQS<1> FB_A_WDQS<2> FB_A_WDQS<3> FB_A_RDQS<0> FB_A_RDQS<1> FB_A_RDQS<2> FB_A_RDQS<3> FB_A_DQ<7..0> FB_A_DQ<15..8> FB_A_DQ<23..16> FB_A_DQ<31..24> FB_A_DQM_L<0> FB_A_DQM_L<1> FB_A_DQM_L<2> FB_A_DQM_L<3> FB_A_WDQS<4> FB_A_WDQS<5> FB_A_WDQS<6> FB_A_WDQS<7> FB_A_RDQS<4> FB_A_RDQS<5> FB_A_RDQS<6> FB_A_RDQS<7> FB_A_DQ<39..32> FB_A_DQ<47..40> FB_A_DQ<55..48> FB_A_DQ<63..56> FB_A_DQM_L<4> FB_A_DQM_L<5> FB_A_DQM_L<6> FB_A_DQM_L<7>
72 73 72 73 72 73 72 73
MINIMUM LINE WIDTH

=40_OHM_SE =40_OHM_SE =80_OHM_DIFF
MINIMUM NECK WIDTH

0.095 MM 0.095 MM 0.095 MM
MAXIMUM NECK LENGTH

12.7 MM =40_OHM_SE =80_OHM_DIFF

=STANDARD =STANDARD =80_OHM_DIFF
ELECTRICAL_CONSTRAINT_SET FB_A_CLK_P
=STANDARD
FB_C_CLK_P
=40_OHM_SE
=STANDARD
=80_OHM_DIFF
=80_OHM_DIFF
FB_B_CLK_P
GDDR3_80D GDDR3_80D
FB_B_CLK_P<0> FB_B_CLK_N<0> FB_B_CLK_P<1> FB_B_CLK_N<1> FB_B_MA<1..0> FB_B_MA<12..6> FB_B_BA<2..0> FB_B_RAS_L FB_B_CAS_L FB_B_WE_L FB_B_CKE FB_B_CS0_L FB_B_DRAM_RST FB_B_LMA<5..2> FB_B_UMA<5..2> FB_B_WDQS<0> FB_B_WDQS<1> FB_B_WDQS<2> FB_B_WDQS<3> FB_B_RDQS<0> FB_B_RDQS<1> FB_B_RDQS<2> FB_B_RDQS<3> FB_B_DQ<7..0> FB_B_DQ<15..8> FB_B_DQ<23..16> FB_B_DQ<31..24> FB_B_DQM_L<0> FB_B_DQM_L<1> FB_B_DQM_L<2> FB_B_DQM_L<3> FB_B_WDQS<4> FB_B_WDQS<5> FB_B_WDQS<6> FB_B_WDQS<7> FB_B_RDQS<4> FB_B_RDQS<5> FB_B_RDQS<6> FB_B_RDQS<7> FB_B_DQ<39..32> FB_B_DQ<47..40> FB_B_DQ<55..48> FB_B_DQ<63..56> FB_B_DQM_L<4> FB_B_DQM_L<5> FB_B_DQM_L<6> FB_B_DQM_L<7>
72 74 72 74 72 74 72 74
FB_AB_CMD FB_AB_CMD
GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE
72 73 72 73 72 73 72 73 72 73 72 73 72 73 72 73 72 73
72 74 72 74 72 74 72 74 72 74 72 74 72 74 72 74 72 74
SPACING_RULE_SET
LAYER
* * * *
=2.5:1_SPACING =2.5:1_SPACING =2.5:1_SPACING =2.5:1_SPACING
WEIGHT
FB_AB_CMD FB_AB_CMD FB_AB_CMD
GDDR3_CLK GDDR3_CMD GDDR3_DATA GDDR3_DQS
?
?
FB_AB_CMD FB_AB_CMD_PD FB_AB_CS0

? ?
FB_AB_CMD_PD FB_A_CMD FB_B_CMD FB_A_WDQS0 FB_A_WDQS1 FB_A_WDQS2 FB_A_WDQS3 FB_A_RDQS0 FB_A_RDQS1 FB_A_RDQS2 FB_A_RDQS3 FB_A_DQ_BYTE0 FB_A_DQ_BYTE1
72 73 72 73
72 74 72 74
72 73 72 73 72 73 72 73
72 74 72 74 72 74 72 74
72 73 72 73 72 73 72 73
72 74 72 74 72 74 72 74
72 73 72 73 72 73 72 73
72 74 72 74 72 74 72 74
From T18 MXM: Digital Video Signal Constraints

FB_A_DQ_BYTE2 FB_A_DQ_BYTE3 FB_A_DQM0 FB_A_DQM1
72 73 72 73 72 73 72 73
72 74 72 74 72 74 72 74
PHYSICAL_RULE_SET
LAYER
ALLOW ROUTE ON LAYER? =100_OHM_DIFF =100_OHM_DIFF
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

FB_A_DQM2 FB_A_DQM3 FB_B_WDQS0 FB_B_WDQS1 FB_B_WDQS2 FB_B_WDQS3
DP_100D LVDS_100D
* *
=100_OHM_DIFF
=100_OHM_DIFF
72 73 72 73 72 73 72 73
72 74 72 74 72 74 72 74
SPACING_RULE_SET
LAYER
WEIGHT
SPACING_RULE_SET
LAYER
WEIGHT
FB_B_RDQS0 FB_B_RDQS1 FB_B_RDQS2
72 73 72 73 72 73 72 73
72 74 72 74 72 74 72 74
DISPLAYPORT LVDS
* *
?
DISPLAYPORT LVDS
TOP,BOTTOM TOP,BOTTOM
?
FB_B_RDQS3 FB_B_DQ_BYTE0 FB_B_DQ_BYTE1 FB_B_DQ_BYTE2 FB_B_DQ_BYTE3 FB_B_DQM0 FB_B_DQM1 FB_B_DQM2 FB_B_DQM3
LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length. DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps. DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals. Max length of LVDS/DisplayPort/TMDS traces: 12 inches. SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.
72 73 72 73 72 73 72 73
72 74 72 74 72 74 72 74
72 73 72 73 72 73 72 73
72 74 72 74 72 74 72 74
MUXGFX Net Properties

NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL LVDS_100D LVDS_100D SPACING I148 I149
G96 Net Properties

NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL CLK_SLOW_55S CLK_SLOW_55S LVDS_100D LVDS_100D LVDS_100D LVDS_100D SPACING CLK_SLOW CLK_SLOW LVDS LVDS LVDS LVDS LVDS LVDS
LVDS_A_CLK LVDS_A_CLK
LVDS_A_CLK_P LVDS_A_CLK_N
80 83
(CK505_DOT96)
80 83
CK505_CLK27MSS
LVDS_EG_A_CLK
I199 I198
LVDS_A_DATA LVDS_A_DATA
LVDS_100D LVDS_100D
LVDS LVDS
LVDS_A_DATA_P<2..0> LVDS_A_DATA_N<2..0>
LVDS_EG_A_CLK
80 83
LVDS_EG_A_DATA
80 83
LVDS_EG_A_DATA
GPU_CLK27M GPU_CLK27M_SS LVDS_EG_A_CLK_P LVDS_EG_A_CLK_N LVDS_EG_A_DATA_P<2..0> LVDS_EG_A_DATA_N<2..0>
76 76 77 83 77 83 77 83 77 83
I152 I153
LVDS_B_CLK LVDS_B_CLK
LVDS_100D LVDS_100D
LVDS LVDS
LVDS_B_CLK_P LVDS_B_CLK_N
80 83 80 83
LVDS_EG_B_DATA LVDS_EG_B_DATA
LVDS_100D LVDS_100D
LVDS LVDS
LVDS_EG_B_DATA_P<2..0> LVDS_EG_B_DATA_N<2..0>
77 83 77 83
I201 I200 I183 I182 I184 I185 I190 I191 I192 I193 I194 I195 I196 I197
LVDS_B_DATA LVDS_B_DATA
LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D LVDS_100D
LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS
LVDS_B_DATA_P<2..0> LVDS_B_DATA_N<2..0> LVDS_CONN_A_CLK_F_P LVDS_CONN_A_CLK_F_N LVDS_CONN_B_CLK_F_P LVDS_CONN_B_CLK_F_N LVDS_CONN_A_CLK_P LVDS_CONN_A_CLK_N LVDS_CONN_A_DATA_P<2..0> LVDS_CONN_A_DATA_N<2..0> LVDS_CONN_B_CLK_P LVDS_CONN_B_CLK_N LVDS_CONN_B_DATA_P<2..0> LVDS_CONN_B_DATA_N<2..0>
80 83
I142
80 83
I144
7 79 7 79 7 79 7 79 79 80 79 80 7 79 80 7 79 80 79 80 79 80 7 79 80 7 79 80
I145 I143 I139 I138
DP_ML DP_ML DP_AUX_CH DP_AUX_CH
DP_100D DP_100D DP_100D DP_100D DP_100D DP_100D
DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT
DP_EG_ML_P<3..0> DP_EG_ML_N<3..0> DP_EG_AUX_CH_P DP_EG_AUX_CH_N DP_EG_AUX_CH_C_P DP_EG_AUX_CH_C_N
77 80 77 80 77 80 77 80 80 80
GPU (G96) Constraints
I161 I160 I155 I157 I202 I203
DP_ML DP_ML DP_ML
DP_100D DP_100D DP_100D DP_100D DP_100D DP_100D
DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT
DP_ML_C_P<3..0> DP_ML_C_N<3..0> DP_ML_P<3..0> DP_ML_N<3..0> DP_ML_CONN_P<3..0> DP_ML_CONN_N<3..0>
81 81 80 81 80 81 81 81
SYNC_MASTER=MUXGFX

I159 I158
DP_AUX_CH DP_AUX_CH
DP_100D DP_100D
DISPLAYPORT DISPLAYPORT
DP_AUX_CH_C_P DP_AUX_CH_C_N
80 81 80 81
SIZE
DRAWING NUMBER
REV.
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
94
96
8
PHYSICAL_RULE_SET
SENSE_1TO1_55S THERM_1TO1_55S DIFFPAIR
7
LAYER
* * *
6
5
DIFFPAIR NECK GAP
4
NET_TYPE PHYSICAL ENET_MDI_100D ENET_MDI_100D SPACING ENETCONN ENETCONN
3
NET_TYPE ELECTRICAL_CONSTRAINT_SET PHYSICAL PCIE_90D PCIE_90D PCIE_90D PCIE_90D
2
SPACING PCIE PCIE PCIE PCIE

=1:1_DIFFPAIR
MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR

=1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR
M99 Specific Net Properties

ELECTRICAL_CONSTRAINT_SET
M99 Specific Net Properties

ENETCONN_P<3..0> ENETCONN_N<3..0>
35
=1:1_DIFFPAIR
=1:1_DIFFPAIR
=1:1_DIFFPAIR
I164
35
=1:1_DIFFPAIR
=1:1_DIFFPAIR
I146 I145 I144
I142 I143 I140
SPACING_RULE_SET
LAYER
* * *
=2:1_SPACING =2:1_SPACING =2:1_SPACING
WEIGHT
SENSE THERM AUDIO
?
I141 I139
?
SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D SATA_100D

SENSE_DIFFPAIR SENSE_1TO1_55S SENSE_1TO1_55S SENSE_DIFFPAIR SENSE_1TO1_55S SENSE_1TO1_55S
SATA SATA SATA SATA SATA SATA SATA SATA

SENSE SENSE SENSE SENSE THERM THERM THERM THERM THERM THERM THERM THERM THERM THERM THERM THERM SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE SENSE
SPACING_RULE_SET
ENETCONN
LAYER
*
25 MILS
WEIGHT
I124 I125 I127 I126
CPUTHMSNS_D2_DP
THERM_1TO1_55S THERM_1TO1_55S
CPU_THERMD_DP
SPACING_RULE_SET
GND PP1V8_MEM
LAYER
* *
=STANDARD =STANDARD
WEIGHT
I128 I130 I129
THERM_1TO1_55S GPU_THERMD_DP THERM_1TO1_55S THERM_1TO1_55S
I174
48
USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D DP_100D
USB USB USB USB USB USB
31 31 40 40 7 32 7 32
?
I172
48 76
I173
48 76
?
I138
MCPTHMSNS_D_DP
I171
48
USB_LT2_P USB_LT2_N
USB2_EXCARD_CONN_P USB2_EXCARD_CONN_N
I169
48
I137 I135 I136 I156 I157 I155 SENSE_DIFFPAIR SENSE_DIFFPAIR MCP_THERMD_DP
SPACING_RULE_SET
GND_P2MM PWR_P2MM
LAYER
* *
0.20 MM 0.20 MM
WEIGHT
THERM_1TO1_55S THERM_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S SENSE_1TO1_55S
I170
21 48
I183
21 48
DISPLAYPORT DISPLAYPORT
1000
1000
NET_SPACING_TYPE1
MEM_CLK MEM_CMD
NET_SPACING_TYPE2
GND GND GND GND GND
AREA_TYPE
* * * * *
SPACING_RULE_SET
I154 I153 I152 I151 I150 I149 I148 I158 I147 I186 I185
SENSE_DIFFPAIR
SENSE_1TO1_55S SENSE_1TO1_55S
GND_P2MM
SENSE_DIFFPAIR
GND_P2MM
MEM_CTRL MEM_DATA MEM_DQS
GND_P2MM
SENSE_DIFFPAIR
GND_P2MM
SENSE_DIFFPAIR
GND_P2MM
SENSE_DIFFPAIR
1V05CPUISNS_R_P 1V05CPUISNS_R_N DDRISNS_R_P DDRISNS_R_N GPUISENS_P GPUISENS_N 1V05CPU_P 1V05CPU_N DDRISNS_P DDRISNS_N P1V8GPU_P P1V8GPU_N ISNS_CPU_P ISNS_CPU_N GND
I184
47
DP_100D
I187
47
MCP_PE4_REFCLK PCIE_FC_R2D PCIE_FC_D2R
I188
47
CLK_PCIE_100D CLK_PCIE_100D
PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D PCIE_90D
CLK_PCIE CLK_PCIE
PCIE PCIE PCIE PCIE PCIE PCIE
I189
47
I190
47
I191
47
I192
47 66
I193
47 66
I194
47
I195
47
I196
47
I198
47
SPK_OUT SPK_OUT SPK_OUT
I197
46
I201
46
I200
GND
NET_SPACING_TYPE1
CLK_FSB
NET_SPACING_TYPE2
GND GND GND GND FSB_DSTB
AREA_TYPE
* * * * *
SPACING_RULE_SET
I199 I202 I206
GND_P2MM
SB_POWER SB_POWER
NET_SPACING_TYPE1
CLK_PCIE PCIE SATA USB CLK_PCIE SATA USB
NET_SPACING_TYPE2
GND GND GND GND SB_POWER SB_POWER SB_POWER
AREA_TYPE
* * * * * * *
SPACING_RULE_SET
CPU_COMP CPU_GTLREF CPU_VCCSENSE FSB_DSTB
GND_P2MM
GND_P2MM
GND_P2MM
SB_POWER
I131 I132 I134 I133
SENSE_DIFFPAIR
SENSE SENSE SENSE SENSE
GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM
SENSE_DIFFPAIR
PP3V3_S5 PP3V3_S0 PP1V5_S0 P1V8GPUISNS_P P1V8GPUISNS_N P1V8GPUISNS_R_P P1V8GPUISNS_R_N
7 8 7 8
I207 I204 I205 I208 I203
CLK_PCIE_100D CLK_PCIE_100D DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR
CLK_PCIE CLK_PCIE AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO
DP_IG_AUX_CH_C_P 80 DP_IG_AUX_CH_C_N 80 PCIE_CLK100M_FC_P 9 32 PCIE_CLK100M_FC_N 9 32 PCIE_FC_R2D_C_P 9 32 PCIE_FC_R2D_C_N 9 32 PCIE_FC_D2R_P 9 32 PCIE_FC_D2R_N 9 32 PCIE_FC_R2D_P 32 PCIE_FC_R2D_N 32 PCIE_CLK100M_EXCARD_CONN_N 7 32 PCIE_CLK100M_EXCARD_CONN_P 7 32 SPKRCONN_L_P_OUT 7 57 58 SPKRCONN_L_N_OUT 7 57 58 SPKRCONN_S_P_OUT 7 57 58 SPKRCONN_S_N_OUT 7 57 58 SPKRCONN_R_P_OUT 7 57 58 SPKRCONN_R_N_OUT 7 57 58 SPKRAMP_L_P_OUT 57 SPKRAMP_L_N_OUT 57 SPKRAMP_R_P_OUT 57 SPKRAMP_R_N_OUT 57 SPKRAMP_S_P_OUT 57 SPKRAMP_S_N_OUT 57
47 47
GND_P2MM
TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM
NET_SPACING_TYPE1
ENET_MDI
NET_SPACING_TYPE2
GND
AREA_TYPE
*
SPACING_RULE_SET
PWR_P2MM
GND_P2MM
PWR_P2MM
PWR_P2MM
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

MEM_40S
OVERRIDE
*
OVERRIDE OVERRIDE OVERRIDE
0.09 MM
OVERRIDE
5.8 MM
NET_SPACING_TYPE1
LVDS
NET_SPACING_TYPE2
GND
AREA_TYPE
*
SPACING_RULE_SET
MEM_40S_VDD
OVERRIDE
*
0.09 MM
OVERRIDE
5.8 MM
GND_P2MM
MEM_70D
OVERRIDE
*
0.09 MM
OVERRIDE
5.8 MM
Memory Constraint Relaxations

Allow 0.127 mm necks for >0.127 mm lines for GMCH fanout.
MEM_70D_VDD
OVERRIDE
*
0.09 MM
OVERRIDE
100 MIL
PCIE_90D
OVERRIDE MAXIMUM NECK LENGTH
6.35 MM
*
0.09 MM
OVERRIDE
100 MIL
PHYSICAL_RULE_SET
MEM_70D
LAYER
BOTTOM
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH

0.127 MM
DIFFPAIR NECK GAP

USB_90D
OVERRIDE
TOP
0.09 MM
OVERRIDE
500 MIL
MCP_DV_COMP
OVERRIDE
TOP
0.1 MM
OVERRIDE
500 MIL
MCP_MEM_COMP
OVERRIDE
TOP
0.1 MM
OVERRIDE
500 MIL
MCP_MII_COMP
OVERRIDE
TOP
0.1 MM
OVERRIDE
500 MIL
MCP_USB_RBIAS
OVERRIDE
TOP
0.1 MM
OVERRIDE
500 MIL
MCP_DV_COMP
OVERRIDE
*
0.25 MM
OVERRIDE
250 MIL
Graphics ,SATA Constraint Relaxations

Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)
TABLE_PHYSICAL_ASSIGNMENT_HEAD
CPU_27P4S
OVERRIDE
BOTTOM
0.23 MM
OVERRIDE
100 MIL
PHYSICAL_RULE_SET
LAYER
MINIMUM LINE WIDTH
MINIMUM NECK WIDTH
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

NET_PHYSICAL_TYPE
AREA_TYPE
BGA BGA BGA
PHYSICAL_RULE_SET
TABLE_PHYSICAL_ASSIGNMENT_ITEM
MEM_40S
OVERRIDE
ISL4,ISL9
OVERRIDE ISL3,ISL10 OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
Project Specific Constraints

N
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
LVDS_100D DP_100D SATA_100D
100_DIFF_BGA
MEM_40S_VDD
OVERRIDE
SYNC_MASTER=MUXGFX
100_DIFF_BGA

MEM_70D
OVERRIDE
ISL4,ISL9
OVERRIDE ISL3,ISL10 OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
100_DIFF_BGA
MEM_70D_VDD
OVERRIDE
N
OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE
Ground-referenced memory signals (DQ,DQM,DQS) MAY route on ISL9 (VDD-referenced plane)but not next to VDD island. Forces power-referenced memory signals (CLK,ADDR,CTRL) to not route on ISL3, ISL4 & ISL10(GND-referenced planes).
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
95
96
GPUTHMSNS_D_DP
THERM_1TO1_55S
SATA_ODD_R2D_UF_P SATA_ODD_R2D_UF_N SATA_ODD_D2R_UF_P SATA_ODD_D2R_UF_N SATA_HDD_D2R_UF_P SATA_HDD_D2R_UF_N SATA_HDD_R2D_UF_P SATA_HDD_R2D_UF_N GFXIMVP6_VSEN_P GFXIMVP6_VSEN_N MCPCOREISNS_P MCPCOREISNS_N CPUTHMSNS_D2_P CPUTHMSNS_D2_N CPU_THERMD_P CPU_THERMD_N GPUTHMSNS_D_P GPUTHMSNS_D_N GPU_TDIODE_P GPU_TDIODE_N MCPTHMSNS_D_P MCPTHMSNS_D_N MCP_THMDIODE_P MCP_THMDIODE_N
I162
39
(PCIE_EXCARD) (PCIE_EXCARD) (PCIE_MINI) (PCIE_MINI)
I163
39
I161
39
PCIE_EXCARD_R2D_P PCIE_EXCARD_R2D_N PCIE_MINI_R2D_P PCIE_MINI_R2D_N
7 32 89 7 32 89 31 89 31 89 31 31 61 61 46 61 46 61 40 40 40 40
I160
39
I159
39
I168
39
I166
39
I167
39
I165
78
CLK_PCIE_100D CLK_PCIE CLK_PCIE_100D CLK_PCIE 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR

USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB_90D USB USB USB USB USB USB USB USB
PCIE_CLK100M_MINI_CONN_P PCIE_CLK100M_MINI_CONN_N
CHGR_CSI_R_P CHGR_CSI_R_N CHGR_CSO_R_P CHGR_CSO_R_N

USB2_EXTA_MUXED_P USB2_EXTA_MUXED_N
I182
78
I181
47 65
I179
47 65
I180
48
I177
48
I178
10 48
I176
10 48
I175
48
(USB_EXTA) (USB_EXTA) (USB_EXTA) (USB_EXTA) (USB_EXTD) (USB_EXTD) (USB_CAMERA) (USB_CAMERA)
USB2_LT1_P USB2_LT1_N
CONN_TPAD_USB_P CONN_TPAD_USB_N USB_CAMERA_CONN_P USB_CAMERA_CONN_N CONN_USB2_BT_P CONN_USB2_BT_N
31 31
8
BOARD LAYERS
TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM
7
BOARD AREAS
NO_TYPE,BGA
6
TABLE_BOARD_INFO
5
BOARD UNITS (MIL or MM)
MM
M99 Board-Specific Spacing & Physical Constraints

ALLEGRO VERSION
15.5.1
PHYSICAL_RULE_SET
DEFAULT STANDARD
LAYER
* *

Y Y
MINIMUM LINE WIDTH

=50_OHM_SE =DEFAULT
MINIMUM NECK WIDTH

=50_OHM_SE =DEFAULT
MAXIMUM NECK LENGTH

14 MM 10 MM

0 MM =DEFAULT
DIFFPAIR NECK GAP

SPACING_RULE_SET
DEFAULT
LAYER
* * * * *
0.1 MM =DEFAULT =DEFAULT =DEFAULT =DEFAULT
WEIGHT
NET_SPACING_TYPE1
*
NET_SPACING_TYPE2
* * * * * FSB_DSTB
AREA_TYPE
BGA BGA BGA BGA BGA BGA
SPACING_RULE_SET
0 MM
?
BGA_P1MM
=DEFAULT
STANDARD BGA_P1MM
?
MEM_CLK CLK_FSB
BGA_P2MM
? ?
BGA_P2MM
PHYSICAL_RULE_SET
55_OHM_SE 55_OHM_SE
LAYER
TOP,BOTTOM *

Y Y
MINIMUM LINE WIDTH

0.090 MM 0.076 MM
MINIMUM NECK WIDTH

0.090 MM
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

BGA_P2MM
CLK_PCIE CLK_SLOW FSB_DSTB

BGA_P2MM
BGA_P3MM
BGA_P2MM
0.076 MM
=STANDARD
=STANDARD
=STANDARD
BGA_P3MM
SPACING_RULE_SET
LAYER
* * * * * *
0.15 MM 0.18 MM 0.2 MM 0.25 MM 0.3 MM 0.4 MM
WEIGHT
NOTE:From T18 MLB, changed to reflect M99 stackup.

PHYSICAL_RULE_SET
50_OHM_SE 50_OHM_SE
LAYER
TOP,BOTTOM *

Y Y
1.5:1_SPACING 1.8:1_SPACING 2:1_SPACING 2.5:1_SPACING 3:1_SPACING 4:1_SPACING
?
MINIMUM LINE WIDTH

0.110 MM 0.090 MM
MINIMUM NECK WIDTH

0.095 MM
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

?
SPACING_RULE_SET
LAYER
WEIGHT
?
2X_DIELECTRIC 3X_DIELECTRIC
* * * *
0.140 MM 0.210 MM 0.280 MM 0.350 MM
?
0.090 MM
=STANDARD
=STANDARD
=STANDARD ? ?
4X_DIELECTRIC 5X_DIELECTRIC
?
PHYSICAL_RULE_SET
40_OHM_SE 40_OHM_SE
LAYER
TOP,BOTTOM *

Y Y
MINIMUM LINE WIDTH

0.165 MM 0.135 MM
MINIMUM NECK WIDTH

0.095 MM
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

0.135 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
27P4_OHM_SE 27P4_OHM_SE
LAYER
TOP,BOTTOM *

Y Y
MINIMUM LINE WIDTH

0.310 MM 0.250 MM
MINIMUM NECK WIDTH

0.095 MM
MAXIMUM NECK LENGTH
DIFFPAIR NECK GAP

0.250 MM
=STANDARD
=STANDARD
=STANDARD
PHYSICAL_RULE_SET
70_OHM_DIFF 70_OHM_DIFF 70_OHM_DIFF 70_OHM_DIFF 70_OHM_DIFF
LAYER
* ISL3,ISL4 ISL9,ISL10 ISL2,ISL11 TOP,BOTTOM

N Y Y Y Y
MINIMUM LINE WIDTH

=STANDARD 0.160 MM 0.160 MM 0.170 MM 0.170 MM
MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=STANDARD

DIFFPAIR NECK GAP

PHYSICAL_RULE_SET
1:1_DIFFPAIR
LAYER
*

Y
MINIMUM LINE WIDTH

=STANDARD
MINIMUM NECK WIDTH

=STANDARD
MAXIMUM NECK LENGTH

=STANDARD

0.1 MM
DIFFPAIR NECK GAP

=STANDARD
0.1 MM
0.175 MM
0.175 MM
0.150 MM
0.150 MM
PHYSICAL_RULE_SET
LAYER

N Y Y Y Y
MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=STANDARD

DIFFPAIR NECK GAP

=STANDARD
0.180 MM
0.180 MM
0.190 MM
0.190 MM
PHYSICAL_RULE_SET
LAYER

N Y Y Y Y
MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=STANDARD

DIFFPAIR NECK GAP

=STANDARD
0.220 MM
0.220 MM
0.230 MM
0.230 MM
PHYSICAL_RULE_SET
100_OHM_DIFF 100_OHM_DIFF 100_OHM_DIFF
LAYER

N Y Y Y Y
MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=STANDARD

DIFFPAIR NECK GAP

PHYSICAL_RULE_SET
100_DIFF_BGA
LAYER
* ISL3,ISL4 ISL9,ISL10

=100_OHM_DIFF
MINIMUM LINE WIDTH

=100_OHM_DIFF 0.075 MM 0.075 MM
MINIMUM NECK WIDTH

=100_OHM_DIFF 0.075 MM 0.075 MM
MAXIMUM NECK LENGTH

=100_OHM_DIFF

=100_OHM_DIFF 0.125 MM 0.125 MM
DIFFPAIR NECK GAP

=STANDARD
=100_OHM_DIFF
0.200 MM
100_DIFF_BGA 100_DIFF_BGA
Y Y
0.125 MM
0.200 MM 0.220 MM
0.125 MM
PCB Rule Definitions

100_OHM_DIFF 100_OHM_DIFF
NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.

0.220 MM
PHYSICAL_RULE_SET
LAYER

N Y Y Y Y
MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=STANDARD

DIFFPAIR NECK GAP

=STANDARD
0.330 MM
0.330 MM
0.330 MM
D
APPLE INC.
SCALE NONE
051-7546
SHT OF
A.0.0
0.330 MM
96
96

Apple Macbook PRO A1286 (Late 2008-Early 2009), Laptop Logic Board Schematic Diagram

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Apple Macbook PRO A1286 (Late 2008-Early 2009), Laptop Logic Board Schematic Diagram

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8

53 54 55 56 57 58 59 61 62 63 65 66 67 68 69 70 71 72 73 75 76 77 78 79 80 81 82 84 85 86 87 88 89 90 93 94 95 96 97 98 99 100 101 102 103

104 105 106 107 108 109

DIMENSIONS ARE IN MILLIMETERS

X.XXX ENG APPD ANGLES MFG APPD

SCALE NONE SIZE

MATERIAL/FINISH NOTED AS APPLICABLE

FSB 64-Bit 800/1067/1333 MHz

2 UDIMMs DDR2-800MHZ DDR3-1067/1333MHZ

SPI Boot ROM

FAN CONN AND CONTROL

Fan Ser Prt

LPC Conn Port80,serial

DP OUT HDMI OUT 0 1 2 3 4 5 6 7 8 9 DVI OUT

DISPLAY PORT CONN

(UP TO FOUR PORTS)

System Block Diagram

Line Out Amp

NOTICE OF PROPRIETARY PROPERTY

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

Mini PCI-E AirPort

M98 POWER SYSTEM ARCHITECTURE

PP3V42_G3H_REG LT3470 U6990 (PAGE 59)

PPCPUVTT_S0_REG (6A MAX CURRENT)

VR_PWRGD_CLKENVRMPWRGD PLT_RST_L PLTRST*

IMVP_VR_ON_R U7100 VR_ON

PPVCORE_CPU_S0 CPUVCORE_IOUT VR_PWRGD_CLKEN_L VR_PWRGOOD_DELAY Q7920

MCP_PS_PWRGD CPU_PWRGD PWROK CPUPWRGD(GPIO49)

U1400 (PAGE 14~22)

P3V3S3_EN P5VS3_EN LIO_S3_EN

P1V1GPU_EN EN1 P1V8FB_EN EN2 U7859

U1000 (PAGE 10,11) RESET*

1.8V(R/H) TPS51124 U9500 (PAGE 82)

PP5V_S3 PP3V3_S5 PP1V05_S5_MCP

(PAGE 62) PGOOD1,2 VREG3

ISL8009 V4 U7750 (PAGE 66)

U9701 ENA VOUT (PAGE 84)

IMVP_VR_ON IMVP_VR_ON(P16) RSMRST_IN(P13) PLT_RST* PWR_BUTTON(P90) PM_PWRBTN_L P17(BTN_OUT)

VINLTC3407 VOUT1 RUN2 U3850 (PAGE 33) RUN1 VOUT2

P1V05S0_PGOOD P5VRIGHT_PGOOD MCPCORES0_PGOODPM_SLP_S5_L CPUVTTS0_PGOOD PM_SLP_S4_L

SLP_S5_L(P95) SLP_S4_L(P94) SLP_S3_L(P93)

U4900 (PAGE 42)

1.8V S5 VOUT1 PPDDR_S3_REG (12A MAX CURRENT) S3 0.9VVOUT2

Power Block Diagram

TPS51116 U7300 (PAGE 63) MCP_CORE

NOTICE OF PROPRIETARY PROPERTY

P3V3S0_EN (S0) PBUSVSENS_EN (S0)

(25A MAX CURRENT) (5A MAX CURRENT)

VIN U7500 (PAGE 65)

(PAGE 60) LIO_DCIN_ISENSE PBUS SUPPLY/ BATTERY CHARGER

GPU VCORE VOUT VIN ISL6263B U8900 PM_GPUVCORE_EN EN_PSV

(18A MAX CURRENT) GPUVCORE_IOUT

Power Block Diagram

NOTICE OF PROPRIETARY PROPERTY

M98 BOM Groups

BOM GROUP M98_COMMON M98_COMMON1 M98_COMMON2 M98_COMMON3 M98_DEBUG M98_PROGPARTS

BOM OPTIONS ALTERNATE,COMMON,M98_COMMON1,M98_COMMON2,M98_COMMON3,M98_DEBUG,M98_PROGPARTS

Bar Code Labels / EEE #s

IC,SGRAM,GDDR3,16Mx32,800MHZ,136 FBGA IC,SGRAM,GDDR3,16Mx32,900MHZ,136 FBGA IC,SGRAM,GDDR3,32Mx32,900MHZ,136 FBGA IC,SGRAM,GDDR3,32Mx32,900MHZ,136 FBGA

138S0603 353S1681 152S0276 341S2367

Murata alt to Samsung

Maglayers alt to Dale/Vishay

Macronix alt to SST