Switched-Capacitor Circuits: Advanced Analog IC Design Switched-Capacitor Circuits Professor Y. Chiu ECE 581 Fall 2009

1
Advanced Analog IC Design Switched-Capacitor Circuits Professor Y. Chiu

ECE 581 Fall 2009
Switched-Capacitor Circuits
2
ECE 581 Fall 2009
Continuous-Time Integrator
Goal:
C
2
V
i
V
o
R
1
C
2
V
i
V
o
SC
( ) ( )
( ) ( )
1 2
1 2
1
1 1
t
o in
o
i
v t v d
R C
V
H s s
V R C s

| |
= =
|
\ .
}
Approach: emulating resistors with switched capacitors
1 2
R C t =
3
ECE 581 Fall 2009
Concept of Switched Capacitor
( )
B A
V V
T
C
T
q
i = =

( )
B A
V V
R
i =
1
1
C
T
R
eq
=
A switched capacitor is a discrete-time resistor
RC time constant set by capacitor ratio C
2
/C
1
(match considerably better
than R and C) and clock period T (flexibility)
R
V
A
V
B
i
C
2
1
V
A
V
B
<i>
so,
1
2
2
1
2 1 ,
C
C
T C
C
T
C R
eq
= = = t
Non-overlapping
two-phase clock
4
ECE 581 Fall 2009
2
Switched Capacitors
Shunt- and series-type SCs are simple and cheap to implement
Stray-insensitive SC requires 2 more switches, whats the advantage
besides being more flexible (i.e., w/ or w/o the T/2 delay)?
2-phase clock
1
V
A
V
B
C
1
V
A
V
B
C
2
Series-type Shunt-type
C
2
2
(
1
)
1
(
2
)
V
A
V
B
Stray-insensitive
5
ECE 581 Fall 2009
Discrete-Time Integrator (DTI)
2-phase clock
C
2
V
i
V
o
1
C
1
2
What are the VTFs (z-domain) of these DTIs, assuming no parasitic
capacitance is present?
C
2
V
i
V
o
C
1
2
6
ECE 581 Fall 2009
Shunt-Type DTI
1
(sample)
Charge conservation law (ideal):
Total charge on C
1
and C
2
during
1

2
transition must remain unchanged!
C
2
V
i
V
o
C
1
C
2
V
o
C
1
V
i
2
(update)
2
T
v
i
(t)
0 t
v
o
(t)
0 t
(n-1)
(n)
(n+1)
(n-1)
(n)
(n+1)
7
ECE 581 Fall 2009
Shunt-Type DTI
1
(sample)
2
(update)
C
2
V
i
V
o
C
1
C
2
V
o
C
1
V
i
( ) ( ) ( )
2 1 1
C n V C n V Q
o i
=
( ) ( )
2 1 2
1 0 C n V C Q
o
+ =

( ) ( ) ( ) ( ) ( )
2 1 2 1 2 1
1 0 C n V C C n V C n V Q Q
o o i
+ = =

( ) ( ) ( )
2 2 1
C z V z C z V C z V
o o i
=
( )
( )
( )
1 1/ 2
1 1
1 1
2 2

1 1
o
i
V z
C C z z
H z or
V z C z C z

= =

8
ECE 581 Fall 2009
Series-Type DTI
1
(sample/update)
2
(reset C
1
)

C
2
V
i
V
o
C
1
2
( )
( )
( )
1
2
1
1
1
= =
z C
C
z V
z V
z H
i
o
VTF:
2
T
v
i
(t)
0 t
v
o
(t)
0 t
(n-1)
(n)
(n+1)
(n-1)
(n)
(n+1)
9
ECE 581 Fall 2009
Stray Capacitance
C
u
C
u
C
u
C
u
C
u
C
1
C
2
Strays derive from D/S diodes and
wiring capacitance
VTF is modified due to strays
Strays at the summing node is of no
significance (virtual ground)
4
1
2
=
C
C
C
2
V
i
V
o
C
1
2
A
C
2
V
i
V
o
C
1
2
A
10
ECE 581 Fall 2009
Stray-Insensitive SC Integrator
( )
1
2
1
1
1
=
z C
C
z H
VTF:
( )
1
1
2
1
1

+ =
z
z
C
C
z H
Capacitors can be significantly sized down to save power/area
Sizes are eventually limited by kT/C noise, mismatch, etc.
C
1
2
(
1
)
1
(
2
)
C
2
V
i
V
o
A B
Inverting Non-inverting
VTF:
11
ECE 581 Fall 2009
SC Amplifier
( )
1
1
2
C
H z z
C
= +
Non-integrating, memoryless (less the delay)
Used in many applications of parametric amplification
VTF:
V
i
C
2
C
1
1
1
V
o
12
ECE 581 Fall 2009
SC Applications
13
ECE 581 Fall 2009
CT Filter
R
C V
i
V
o
L
R
1
C
A
R
R
R
3
R
4
C
B
R
2
V
i
V
o
RLC prototype
Active-RC
Tow-Thomas
CT biquad

14
ECE 581 Fall 2009
SC DT Filter
SC DT
biquad
C
A
C
B
V
i
V
o
C
1
1
C
2
C
4
1
C
3
2
R
1
C
A
R
R
R
3
R
4
C
B
R
2
V
i
V
o
Active-RC
Tow-Thomas
CT biquad

15
ECE 581 Fall 2009
Sigma-Delta () Modulator
C
I
2
V
i
D
o
+V
R 1-b
DAC
-V
R
C
S
DTI + 1-bit comparator + 1-bit DAC = first-order ADC
16
ECE 581 Fall 2009
Pipelined ADC
SC amplifier + 2 comparators + 3-level DAC = 1.5-bit pipelined ADC
V
o
V
i
0
-V
R
V
R
1.5-b
DAC
1
C
1
1
C
2
2
-V
R
/4
V
R
/4
17
ECE 581 Fall 2009
Noise in SC Circuits
18
ECE 581 Fall 2009
Noise of CT Integrator
Noise in CT circuits can be simulated with SPICE (.noise)
R
C
V
i
V
o
R
C
V
o
V
N1
2
V
N2
2
H
1
(f)
H
2
(f)
( ) ( ) ( ) ( )
2 2
2 2
2
1 2
1 2
N N
oN
V V
V f H f df f H f df
f f
= + +
A A
} }
19
ECE 581 Fall 2009
Noise of SC Integrator
SC circuits are NOT noise-free! Switches and op-amps introduce noise.
2
C
2
C
1
2
V
i
V
o
20
ECE 581 Fall 2009
Noise is indistinguishable from signal after sampling
The noise acquired by C
1
will be amplified in
2
just like signal
Sampling (
1
) Ideal Voltage Source
( ) ( ) ( ) ( )
| |
( )
2 2
2
2 1 2
1
0
2
1 2
0
1 2
1
1
4 4
1 2
N N
N
V V
V f f H f df
f f
kTR kTR df
j f R R C
kT
C
(
= +
(
A A
(

= +
+ +
=
}
}
C
1
V
i
R
1
R
2
V
N1
2
V
N2
2
21
ECE 581 Fall 2009
Integration (
2
)
No simulator can directly simulate the aggregated output noise!
( ) ( ) ( ) ( ) ( ) ( )
2 2 2
2 2
2 3 4 5
34 5
2
N N N
N
V V V
V f f H f df f H f df
f f f
(
= + + +
(
A A A
(

} }
( ) ( ) 2 1
2 2
2
2
1
2
| |
N N oN
V V
C
C
V +
|
|
.
|
\
|
=
V
o
V
N3
2
V
N5
2
H
34
(f)
H
5
(f)
C
1
C
2
R
4
V
N4
2
R
3
22
ECE 581 Fall 2009
Sampling (
1
) Noise Cascaded Stages
C
1
' R
1
R
2
V
N3
2
V
N5
2
V
N1
2
V
N2
2
C
1
C
2
R
4
V
N4
2
R
3
Finite op-amp BW limits the noise bandwidth, resulting in less overall kT/C noise
(noise filtering).
But parasitic loop delay may introduce peaking in freq. response, resulting in more
integrated noise (noise peaking).
C
2
C
2
'
V
i
V
o
C
1
1
C
1
'
2

23
ECE 581 Fall 2009
Sampled Noise Spectrum
Total integrated noise power remains constant
SNR remains constant
CT
DT
PSD
f
s
/2 f
s
3/2f
s
0
PSD
f
s
2f
s
0
Alias
24
ECE 581 Fall 2009
Nonideal Effects in
SC Circuits
25
ECE 581 Fall 2009
Nonideal Effects in SC Circuits
Capacitors (poly-poly, metal-metal, MIM, MOM, sandwich, gate cap,
accumulation-mode gate cap, etc.)
PP, MIM, and MOM are linear up to 14-16 bits (nonlinear voltage
coefficients negligible for most applications)
Gate caps are typically good for up to 8-10 bits
Switches (MOS transistors)
Nonzero on-resistance (voltage dependent)
(Nonlinear) stray capacitance added (C
gs
, C
gd
, C
gb
, C
db
, C
sb
)
Switch-induced sampling errors (charge injection, clock feedthrough,
junction leakage, drain-source leakage, and gate leakage)
Operational amplifiers
Offset
Finite-gain effects (voltage dependent)
Finite bandwidth and slew rate (measured by settling speed)
26
ECE 581 Fall 2009
Nonideal Effects of
Switches
27
ECE 581 Fall 2009
Nonzero On-Resistance
FET channel resistance (thus tracking bandwidth) depends on signal level
Usually (R
on
C
S
)
-1
(3-5)
-3dB
of closed-loop op-amp for settling purpose
V
GS
V
out
C
C
S
C
S
R
on
0 V
DD
V
out
V
Tn
V
Tp
PMOS
NMOS
CMOS
( )
out th DD ox on
V V V
L
W
C R =
1
28
ECE 581 Fall 2009
Clock Bootstrapping
Small on-resistance leads to large switches large parasitic caps and
large clock buffers
Clock bootstrapping keeps V
GS
of the switch constant constant on-
resistance (body effect?) and less parasitics w/o the PMOS
C
S
Out In
M1
V
DD
2
CMOS Bootstrapped NMOS
29
ECE 581 Fall 2009
Simplified Clock Bootstrapper
Pros
Linearity
Bandwidth
Cons
Device reliability
Complexity
Out
C
In
M2
M1
V
DD
V
SS
Out In
M1
V
DD
2
30
ECE 581 Fall 2009
Switch-Induced Errors
Channel charge injection and clock feedthrough (on drain side) result in
charge trapped on C
S
after switch is turned off.
V
out
C
S
Z
i
V
in
C
gd
C
gs
Q
ch
Clock feedthrough
Charge injection
31
ECE 581 Fall 2009
Clock Feedthrough and Charge Injection
Both phenomena sensitive to Z
i
, C
S
, and clock rise/fall time
Offset, gain error, and nonlinearity introduced to the sampling
Clock feedthrough can be simulated by SPICE, but charge injection
cannot be simulated with lumped transistor models
V
DD
0
V
in
+V
th
Switch on Switch off
V
out
C
S
Z
i
V
in
C
gd
C
gs
Q
ch
32
ECE 581 Fall 2009
Clock Rise/Fall-Time Dependence
V
DD
0
V
in
+V
th
Switch on Switch off
V
out
C
S
Z
i
V
in
C
gd
C
gs
Q
ch
Clock feedthrough Charge injection
Fast turn-off
Slow turn-off
DD
S gs
gs
V
C C
C
V
+
= A
( )
( )
S gs
in th DD ox
C C
V V V WL C
V
+

= A
2
( )
th in
S gs
gs
V V
C C
C
V +
+
= A
0 = AV
33
ECE 581 Fall 2009
Dummy Switch
Difficult to achieve precise cancellation due to the nonlinear
dependence of V on Z
i
, C
S
, and clock rise/fall time
Sensitive to the phase alignment between and _
V
out
W
L C
S
W
2L
V
in
34
ECE 581 Fall 2009
CMOS Switch
Very sensitive to phase alignment between and _
Subject to threshold mismatch between PMOS and NMOS
Exact cancellation occurs only for one specific V
in
(which one?)
V
out
C
S
V
in
Same size for

P and N FETs
35
ECE 581 Fall 2009
Differential Signaling
Signal-independent errors (offset) and even-order distortions cancelled
Gain error and odd-order nonlinearities remain
Balanced diff. input
V
op
C
Sp
V
ip
M
1
V
on
C
Sn
V
in
M
2
36
ECE 581 Fall 2009
Switch Performance
( )
( )
ch
2
i th DD ox
2
i th DD ox
on
Q
L
V V V WL C
L
V V V
L
W
C
1
R =

=

=
S
ch
C
Q
2
1
V ~
Charge injection:
Bandwidth:
S
2
ch
S on
C L
Q
C R
1
BW = ~
2 2
ch S
S ch
Q L C V 1 L
=
BW 2 C Q 2
Performance FoM:
Technology scaling improves switch performance!
On-resistance:
37
ECE 581 Fall 2009
Leakage in SC Circuits
I1 diode leakage (existing in the old days too)
I2 sub-threshold drain-source leakage of summing-node switch
I3 gate leakage (FN tunneling) of amplifier input transistors
Leakage currents are highly temperature- and process-dependent; the
lower limit of clock frequency is often determined by leakage
V
o
(t)
0 t
1
= high,
2
= low
V
i
V
o
C
2
C
1
A
0
V
x
1
V
B
I
2
I
1
I
3
38
ECE 581 Fall 2009
Gate Leakage
Direct tunneling through the thin gate oxide
Short-channel MOSFET behaves increasingly like BJTs
Violates the high-impedance assumption of the summing node
( ) ( )
GS ox GS
V t WL I exp exp
39
ECE 581 Fall 2009
Switch Size Optimization
To minimize switch-induced error voltages, small transistor size,
slow turn-off, low source impedance should be used.
For fast settling (high-speed design), large W/L should be used, and
errors will be inevitably large as well.

Guidelines
Always use minimum channel length for switches as long as
leakage allows.
For a given speed, switch sizes can be optimized w/ simulation.
Be aware of the limitations of simulators (SPICE etc.) using lumped
device models.
40
ECE 581 Fall 2009
Nonideal Effects of
Op-Amps
41
ECE 581 Fall 2009
Nonideal Effects of Op-Amps
Offset
Finite-gain effects (voltage dependent)
Finite bandwidth and slew rate (measured by settling
speed)
42
ECE 581 Fall 2009
Offset Voltage
( ) ( ) ( ) | |
2 1 1
C V n V C n V Q
os o i
+ =

( ) ( ) | |
2 1 2
1 C V n V C V Q
os o os
+ + =

( ) ( )
1
1
1
2
1
o i
C z
V z V z
C z
V
i
V
o
C
2
C
1
1
1 V
os
V
o
(t)
0 t
2
V
i
= 0
( ) ( )
1
2
0 1
i o o os
C
V V n V n V
C
| |
= + =
|
\ .
43
ECE 581 Fall 2009
Autozeroing
( ) ( ) | |
2 1 1
C V C V n V Q
os os i
=

( ) ( ) | |
2 1 2
C V n V C V Q
os o os
+ =

( )
( )
( )
2
1
C
C
z V
z V
z H
i
o
= =
V
i
V
o
C
2
C
1
1
1
V
os
1
Also eliminates low-frequency noise, e.g., 1/f noise
A.k.a. correlated double sampling (CDS)
44
ECE 581 Fall 2009
Chopper Stabilization
Ref: K. C. Hsieh, P. R. Gray, D. Senderowicz, and D. G. Messerschmitt, A low-noise
chopper-stabilized differential switched-capacitor filtering technique, IEEE Journal of
Solid-State Circuits, vol. 16, issue 6, pp. 708-715, 1981.
V
i
V
o
A
1
V
n
2
A
2
f
C
1
-1
A B
45
ECE 581 Fall 2009
Chopper Stabilization
Also eliminates DC offset
voltage of A
1

V
i
V
o
A
1
V
n
2
A
2
f
C
1
-1
A B
|V
i
|
2
f
0
S
N
(f)
f
0
f
0
|V
A
|
2
|V
B
|
2
f
0
f
C
f
C
f
C
f
C
46
ECE 581 Fall 2009
Chopper-Stabilized Differential Op-Amp
V
i+
V
i-
V
o-
V
o+
Integrators/amplifiers can be built using these op-amps

Some oversampling is useful to facilitate the implementation
47
ECE 581 Fall 2009
Ideal SC Amplifier
1
2
CL
C
A
C
=
Closed-loop gain is determined by the capacitor ratio by design
But this is assuming X is an ideal summing node (the op-amp is ideal)
V
i
C
2
C
1
1
1
V
o
X
48
ECE 581 Fall 2009
Finite-Gain Effect in SC Amplifier
1 1 1 2
1 2
2 2 2
2
1
1
1
o
CL
i
V C C C C
A
C C
V C C C A
C A
| | +
= = ~
|
+
\ .
+
V
i
A
C
2
C
1
1
1
V
o
X
( ) ( ) ( )
( ) ( ) ( )
1 1 1 1 2
1 1 1
0
i x
x o x
Q V V C C
V V V A
| | |
| | |
= + (

= =
( ) ( ) ( )
1 2 1 1 2 i x o x
Q Q V C V C V V C | | = = +

( ) ( ) ( ) ( )
( ) ( )
2 2 1 2 2 2
2 2
x o x
o x
Q V C V V C
V V A
| | | |
| |
= + (

=
o x
V V A =
49
ECE 581 Fall 2009
Practical Issues
50
ECE 581 Fall 2009
Analog vs. Digital Supply Lines
Sharing sensitive analog supplies with digital ones is a very bad idea.
Analog
circuits
Digital
circuits
Pad
Pad
V
DD
C
BP
i
d
=
dt
di
L V
d
L
= A R i V
d R
= A
R L DD A
V V V V A A =
51
ECE 581 Fall 2009
Analog vs. Digital Supply Lines
Dedicated pads
for analog and
digital supplies
On-chip bypass
capacitors help
(watch ringing)
Off-chip chokes
(large inductors)
can stop noise
propagation at
board level
Analog
circuits
Digital
circuits
Pad
Pad
V
DD
C
BP
Pad
Pad
i
d
=
52
ECE 581 Fall 2009
Supply Capacitance
Any summing-node stray capacitance can be a potential coupling path.
V
DD
, V
SS
, substrate, clock line, and digital noises, body effect, etc.
Fully differential circuits help to reject common-mode noise and coupling.
C
p
V
DD
V
SS
M
2
M
5
M
3
M
4
M
7
M
6
V
o
C
C
V
i
C
2
C
1
1
1
M
1
S
Y
X
C
gs
C
gd
2
C
C
V V
stray
o
A = A
53
ECE 581 Fall 2009
Supply Capacitance
Avoid connecting bottom-plate parasitics to the summing node
Avoid crossing other signal lines with the summing node
Shielding can mitigate substrate noise coupling
n substrate
p+
p well
C
bot
C
2
54
ECE 581 Fall 2009
Clock Generation
Clock-gated ring structure
Non-overlapping time determined by inverter delays, sensitive to process,
voltage, and temperature (PVT) variations
DLL is an alternative, often used in high-speed designs
CLK

Switched-Capacitor Circuits: Advanced Analog IC Design Switched-Capacitor Circuits Professor Y. Chiu ECE 581 Fall 2009

Caricato da

Informazioni sul documento

Titolo originale

Copyright

Formati disponibili

Condividi questo documento

Condividi o incorpora il documento

Opzioni di condivisione

Hai trovato utile questo documento?

Questo contenuto è inappropriato?

Copyright:

Formati disponibili

Switched-Capacitor Circuits: Advanced Analog IC Design Switched-Capacitor Circuits Professor Y. Chiu ECE 581 Fall 2009

Caricato da

Copyright:

Formati disponibili

1

Advanced Analog IC Design Switched-Capacitor Circuits Professor Y. Chiu

Same size for

Integrators/amplifiers can be built using these op-amps

Potrebbero piacerti anche