1. Computer Evolution and Computing 2. Computer Architecture 3. CPU Organization and Structure, Functions 4. ISA Structure Cycles 5.

Simple computer ( F-D-I ) 6. Memory Hierarchy 7. Main memory ( RAM types ) 8. Bus System in Computer 9. Addressing Mode 10. Cache Memory 11. Mapping in Cache Memory 12. Virtual Memory 13. VM Mapping 14. Pipelining 15. I/O devices 16. External devices ( HDD/ RAID technology ) 17. Multiprocessors Chapter1 ( Organization and Architecture, Structure and Function ) 2. Computer Architecture Review Questions 1.1. What, in general terms, is the distinction between computer organization and computer architecture? 1.2. What, in general terms, is the distinction between computer structure and computer function? 1.3. What are the four main functions of a computer? 1.4. List and briefly define the main structural components of a computer. 1.5. List and briefly define the main structural components of a processor. Chapter2 ( COMPUTER EVOLUTION AND PERFORMANCE ) 1. Computer Evolution and Computing Review Questions 2.1. What is a stored program computer? 2.2. What are the four main components of any general-purpose computer?

2.3. At the integrated circuit level, what are the three principal constituents of a computer system? 2.4. Explain Moores law. 2.5. List and explain the key characteristics of a computer family. Problems 2.3. On the IAS, describe in English the process that the CPU must undertake to read a value from memory and to write a value to memory in terms of what is put into the MAR, MBR, address bus, data bus, and control bus. 2.10. A benchmark program is run on a 40 MHz processor.The executed program consists of 100,000 instruction executions, with the following instruction mix and clock cycle count: Determine the effective CPI, MIPS rate, and execution time for this program. 2.11. Consider two different machines, with two different instruction sets, both of which have a clock rate of 200 MHz. The following measurements are recorded on the two machines running a given set of benchmark programs: a. Determine the effective CPI, MIPS rate, and execution time for each machine. b. Comment on the results. 2.13. Four benchmark programs are executed on three computers with the following results: The table shows the execution time in seconds, with 100,000,000 instructions executed in each of the four programs. Calculate the MIPS values for each computer for each program. Then calculate the arithmetic and harmonic means assuming equal weights for the four programs, and rank the computers based on arithmetic mean and harmonic mean. 2.16. Consider the example in Section 2.5 for the calculation of average CPI and MIPS rate, which yielded the result of CPI 2.24 and MIPS rate 178. Now assume that the program can be executed in eight parallel tasks or threads with roughly equal number of instructions executed in each task. Execution is on an 8-core system with each core (processor) having the same performance as the single processor originally used. Coordination and synchronization between the parts adds an extra 25,000 instruction executions to each task. Assume the same instruction mix as in the example for each task, but increase the CPI for memory reference with cache miss to 12 cycles due to contention for memory. a. Determine the average CPI. b. Determine the corresponding MIPS rate. c. Calculate the speedup factor. d. Compare the actual speedup factor with the theoretical speedup factor determined by Amdhals law.

Chapter3 (A TOP-LEVEL VIEW OF COMPUTER FUNCTION AND INTERCONNECTION) 3. CPU Organization and Structure, Functions 4. ISA Structure Cycles 5. Simple computer ( F-D-I ) Review Questions 3.1 What general categories of functions are specified by computer instructions? 3.2 List and briefly define the possible states that define an instruction execution. 3.3 List and briefly define two approaches to dealing with multiple interrupts. 3.4 What types of transfers must a computers interconnection structure (e.g., bus) support? 3.5 What is the benefit of using a multiple-bus architecture compared to a single-bus architecture? 3.6 List and briefly define the functional groups of signal lines for PCI. Problems 3.1 The hypothetical machine of Figure 3.4 also has two I/O instructions: 0011 Load AC from I/O 0011 Store AC to I/O In these cases, the 12-bit address identifies a particular I/O device. Show the program execution (using the format of Figure 3.5) for the following program: 1. Load AC from device 5. 2. Add contents of memory location 940. 3. Store AC to device 6. Assume that the next value retrieved from device 5 is 3 and that location 940 contains a value of 2. 3.2 The program execution of Figure 3.5 is described in the text using six steps. Expand this description to show the use of the MAR and MBR. 3.3 Consider a hypothetical 32-bit microprocessor having 32-bit instructions composed of two fields: the first byte contains the opcode and the remainder the immediate operand or an operand address. a. What is the maximum directly addressable memory capacity (in bytes)? b. Discuss the impact on the system speed if the microprocessor bus has 1. a 32-bit local address bus and a 16-bit local data bus, or 2. a 16-bit local address bus and a 16-bit local data bus. c. How many bits are needed for the program counter and the instruction register? 3.4 Consider a hypothetical microprocessor generating a 16-bit address (for example, assume

that the program counter and the address registers are 16 bits wide) and having a 16-bit data bus. a. What is the maximum memory address space that the processor can access directly if it is connected to a 16-bit memory? b. What is the maximum memory address space that the processor can access directly if it is connected to an 8-bit memory? c. What architectural features will allow this microprocessor to access a separate I/O space? d. If an input and an output instruction can specify an 8-bit I/O port number, how many 8-bit I/O ports can the microprocessor support? How many 16-bit I/O ports? Explain. 3.5 Consider a 32-bit microprocessor, with a 16-bit external data bus, driven by an 8-MHz input clock.Assume that this microprocessor has a bus cycle whose minimum duration equals four input clock cycles. What is the maximum data transfer rate across the bus that this microprocessor can sustain, in bytes/s? To increase its performance, would it be better to make its external data bus 32 bits or to double the external clock frequency supplied to the microprocessor? State any other assumptions you make, and explain. Hint: Determine the number of bytes that can be transferred per bus cycle. 3.11 For a synchronous read operation (Figure 3.19), the memory module must place the data on the bus sufficiently ahead of the falling edge of the Read signal to allow for signal settling. Assume a microprocessor bus is clocked at 10 MHz and that the Read signal begins to fall in the middle of the second half of T3. a. Determine the length of the memory read instruction cycle. b. When, at the latest, should memory data be placed on the bus? Allow 20 ns for the settling of data lines. 3.12 Consider a microprocessor that has a memory read timing as shown in Figure 3.19. After some analysis, a designer determines that the memory falls short of providing read data on time by about 180 ns. a. How many wait states (clock cycles) need to be inserted for proper system operation if the bus clocking rate is 8 MHz? b. To enforce the wait states, a Ready status line is employed. Once the processor has issued a Read command, it must wait until the Ready line is asserted before attempting to read data. At what time interval must we keep the Ready line low in order to force the processor to insert the required number of wait states? 3.13 A microprocessor has a memory write timing as shown in Figure 3.19. Its manufacturer specifies that the width of the Write signal can be determined by T _ 50, where T is the clock period in ns.

a. What width should we expect for the Write signal if bus clocking rate is 5 MHz? b. The data sheet for the microprocessor specifies that the data remain valid for 20 ns after the falling edge of the Write signal.What is the total duration of valid data presentation to memory? c. How many wait states should we insert if memory requires valid data presentation for at least 190 ns? 3.17 Consider a 32-bit microprocessor whose bus cycle is the same duration as that of a 16-bit microprocessor. Assume that, on average, 20% of the operands and instructions are 32 bits long, 40% are 16 bits long, and 40% are only 8 bits long. Calculate the improvement achieved when fetching instructions and operands with the 32-bit microprocessor.

3.19 Draw and explain a timing diagram for a PCI write operation (similar to Figure 3.23). Chapter4 (Cash memory) 6. Memory Hierarchy 9. Addressing Mode 10. Cache Memory 11. Mapping in Cache Memory Review Questions 4.1 What are the differences among sequential access, direct access, and random access? 4.2 What is the general relationship among access time, memory cost, and capacity? 4.3 How does the principle of locality relate to the use of multiple memory levels? 4.4 What are the differences among direct mapping, associative mapping, and setassociative mapping? 4.5 For a direct-mapped cache, a main memory address is viewed as consisting of three fields. List and define the three fields. 4.6 For an associative cache, a main memory address is viewed as consisting of two fields. List and define the two fields. 4.7 For a set-associative cache, a main memory address is viewed as consisting of three fields. List and define the three fields.

4.8 What is the distinction between spatial locality and temporal locality? 4.9 In general, what are the strategies for exploiting spatial locality and temporal locality? Problems 4.1 A set-associative cache consists of 64 lines, or slots, divided into four-line sets. Main memory contains 4K blocks of 128 words each. Show the format of main memory addresses. 4.2 A two-way set-associative cache has lines of 16 bytes and a total size of 8 kbytes.The 64Mbyte main memory is byte addressable. Show the format of main memory addresses. 4.3 For the hexadecimal main memory addresses 111111, 666666,BBBBBB, show the following information, in hexadecimal format: a. Tag, Line, and Word values for a direct-mapped cache, using the format of Figure 4.10 b. Tag and Word values for an associative cache, using the format of Figure 4.12 c. Tag, Set, and Word values for a two-way set-associative cache, using the format of Figure 4.15 4.4 List the following values: a. For the direct cache example of Figure 4.10: address length, number of addressable units, block size, number of blocks in main memory, number of lines in cache, size of tag b. For the associative cache example of Figure 4.12: address length, number of addressable units, block size, number of blocks in main memory, number of lines in cache, size of tag c. For the two-way set-associative cache example of Figure 4.15: address length, number of addressable units, block size, number of blocks in main memory, number of lines in set, number of sets, number of lines in cache, size of tag 4.5 Consider a 32-bit microprocessor that has an on-chip 16-KByte four-way set-associative cache. Assume that the cache has a line size of four 32-bit words. Draw a block diagram of this cache showing its organization and how the different address fields are used to determine a cache hit/miss.Where in the cache is the word from memory location ABCDE8F8 mapped? 4.6 Given the following specifications for an external cache memory: four-way set associative; line size of two 16-bit words; able to accommodate a total of 4K 32-bit words from main memory; used with a 16-bit processor that issues 24-bit addresses. Design the cache structure with all pertinent information and show how it interprets the processors addresses. 4.7 The Intel 80486 has an on-chip, unified cache. It contains 8 KBytes and has a four-way setassociative organization and a block length of four 32-bit words. The cache is organized into 128 sets. There is a single line valid bit and three bits, B0, B1, and B2

(the LRU bits), per line. On a cache miss, the 80486 reads a 16-byte line from main memory in a bus memory read burst. Draw a simplified diagram of the cache and show how the different fields of the address are interpreted. 4.8 Consider a machine with a byte addressable main memory of 216 bytes and block size of 8 bytes. Assume that a direct mapped cache consisting of 32 lines is used with this machine. a. How is a 16-bit memory address divided into tag, line number, and byte number? b. Into what line would bytes with each of the following addresses be stored? c. Suppose the byte with address 0001 1010 0001 1010 is stored in the cache.What are the addresses of the other bytes stored along with it? d. How many total bytes of memory can be stored in the cache? e. Why is the tag also stored in the cache? Chapter5 ( INTERNAL MEMORY ) 7. Main memory ( RAM types ) Review Questions 5.1 What are the key properties of semiconductor memory? 5.2 What are two senses in which the term random-access memory is used? 5.3 What is the difference between DRAM and SRAM in terms of application? 5.4 What is the difference between DRAM and SRAM in terms of characteristics such as speed, size, and cost? 5.5 Explain why one type of RAM is considered to be analog and the other digital. 5.6 What are some applications for ROM? 5.7 What are the differences among EPROM, EEPROM, and flash memory? 5.8 Explain the function of each pin in Figure 5.4b. 5.9 What is a parity bit? 5.10 How is the syndrome for the Hamming code interpreted? 5.11 How does SDRAM differ from ordinary DRAM? Problems 5.1 Suggest reasons why RAMs traditionally have been organized as only 1 bit per chip

whereas ROMs are usually organized with multiple bits per chip. 5.2 Consider a dynamic RAM that must be given a refresh cycle 64 times per ms. Each refresh operation requires 150 ns; a memory cycle requires 250 ns. What percentage of the memorys total operating time must be given to refreshes? 5.3 Figure 5.16 shows a simplified timing diagram for a DRAM read operation over a bus. The access time is considered to last from t1 to t2. Then there is a recharge time, lasting from t2 to t3, during which the DRAM chips will have to recharge before the processor can access them again. a. Assume that the access time is 60 ns and the recharge time is 40 ns. What is the memory cycle time? What is the maximum data rate this DRAM can sustain, assuming a 1-bit output? b. Constructing a 32-bit wide memory system using these chips yields what data transfer rate? 5.4 Figure 5.6 indicates how to construct a module of chips that can store 1 MByte based on a group of four 256-Kbyte chips. Lets say this module of chips is packaged as a single 1-Mbyte chip, where the word size is 1 byte. Give a high-level chip diagram of how to construct an 8-Mbyte computer memory using eight 1-Mbyte chips. Be sure to show the address lines in your diagram and what the address lines are used for.

CHAPTER 8 / OPERATING SYSTEM SUPPORT 10. Cache Memory 11. Mapping in Cache Memory 12. Virtual Memory 13. VM Mapping Review Questions 8.1 What is an operating system? 8.2 List and briefly define the key services provided by an OS. 8.3 List and briefly define the major types of OS scheduling. 8.4 What is the difference between a process and a program?

8.5 What is the purpose of swapping? 8.6 If a process may be dynamically assigned to different locations in main memory, what is the implication for the addressing mechanism? 8.7 Is it necessary for all of the pages of a process to be in main memory while the process is executing? 8.9 Is it necessary for the pages of a process in main memory to be in sequential order? 8.10 What is the purpose of a translation lookaside buffer? Problems 8.6 Suppose the page table for the process currently executing on the processor looks like the following. All numbers are decimal, everything is numbered starting from zero, and all addresses are memory byte addresses. The page size is 1024 bytes. a. Describe exactly how, in general, a virtual address generated by the CPU is translated into a physical main memory address. b. What physical address, if any, would each of the following virtual addresses correspond to? (Do not try to handle any page faults, if any.) (i) 1052 (ii) 2221 (iii) 5499 8.9 The following sequence of virtual page numbers is encountered in the course of execution on a computer with virtual memory: Assume that a least recently used page replacement policy is adopted. Plot a graph of page hit ratio (fraction of page references in which the page is in main memory) as a function of main-memory page capacity n for Assume that main memory is initially empty. 8.14 A computer has a cache, main memory, and a disk used for virtual memory. If a referenced word is in the cache, 20 ns are required to access it. If it is in main memory but not in the cache, 60 ns are needed to load it into the cache, and then the reference is started again. If the word is not in main memory, 12 ms are required to fetch the word from disk, followed by 60 ns to copy it to the cache, and then the reference is started again. The cache hit ratio is 0.9 and the main-memory hit ratio is 0.6.What is the average time in ns required to access a referenced word on this system? 8.15 Assume a task is divided into four equal-sized segments and that the system builds an

eight-entry page descriptor table for each segment. Thus, the system has a combination of segmentation and paging. Assume also that the page size is 2 KBytes. a. What is the maximum size of each segment? b. What is the maximum logical address space for the task? c. Assume that an element in physical location 00021ABC is accessed by this task. What is the format of the logical address that the task generates for it? What is the maximum physical address space for the system? 8.16 Assume a microprocessor capable of accessing up to 232bytes of physical main memory. It implements one segmented logical address space of maximum size 231bytes. Each instruction contains the whole two-part address. External memory management units (MMUs) are used, whose management scheme assigns contiguous blocks of physical memory of fixed size 222bytes to segments. The starting physical address of a segment is always divisible by 1024. Show the detailed interconnection of the external mapping mechanism that converts logical addresses to physical addresses using the appropriate number of MMUs, and show the detailed internal structure of an MMU (assuming that each MMU contains a 128-entry directly mapped segment descriptor cache) and how each MMU is selected. 8.17 Consider a paged logical address space (composed of 32 pages of 2 KBytes each) mapped into a 1-MByte physical memory space. a. What is the format of the processors logical address? b. What is the length and width of the page table (disregarding the access rights bits)? c. What is the effect on the page table if the physical memory space is reduced by half? CHAPTER 11 / INSTRUCTION SETS:ADDRESSING MODES AND FORMATS 9. Addressing Mode Review Questions 11.1 Briefly define immediate addressing. 11.2 Briefly define direct addressing. 11.3 Briefly define indirect addressing. 11.4 Briefly define register addressing. 11.5 Briefly define register indirect addressing. 11.6 Briefly define displacement addressing.

11.7 Briefly define relative addressing. Problems 11.1 Given the following memory values and a one-address machine with an accumulator, what values do the following instructions load into the accumulator? Word 20 contains 40. Word 30 contains 50. Word 40 contains 60. Word 50 contains 70. a. LOAD IMMEDIATE 20 b. LOAD DIRECT 20 c. LOAD INDIRECT 20 d. LOAD IMMEDIATE 30 e. LOAD DIRECT 30 f. LOAD INDIRECT 30 11.2 Let the address stored in the program counter be designated by the symbol X1. The instruction stored in X1 has an address part (operand reference) X2. The operand needed to execute the instruction is stored in the memory word with address X3.An index register contains the value X4.What is the relationship between these various quantities if the addressing mode of the instruction is (a) direct; (b) indirect; (c) PC relative; (d) indexed? 11.3 An address field in an instruction contains decimal value 14. Where is the corresponding operand located for a. immediate addressing? b. direct addressing? c. indirect addressing? d. register addressing? e. register indirect addressing? 11.11 Consider a processor that includes a base with indexing addressing mode. Suppose an instruction is encountered that employs this addressing mode and specifies a displacement of 1970, in decimal. Currently the base and index register contain the decimal numbers 48022 and 8, respectively.What is the address of the operand? 11.14 Justify the assertion that a 32-bit instruction is probably much less than twice as useful as a 16-bit instruction. 11.19 Is there any possible justification for an instruction with two opcodes? 14. Pipelining

15. I/O devices 16. External devices ( HDD/ RAID technology ) 17. Multiprocessors

Review Questions 7.1 List three broad classifications of external, or peripheral, devices. 7.2 What is the International Reference Alphabet? 7.3 What are the major functions of an I/O module? 7.4 List and briefly define three techniques for performing I/O. 7.5 What is the difference between memory-mapped I/O and isolated I/O? 7.6 When a device interrupt occurs, how does the processor determine which device issued the interrupt? 7.7 When a DMA module takes control of a bus, and while it retains control of the bus, what does the processor do? Review Questions 12.1 What general roles are performed by processor registers? 12.2 What categories of data are commonly supported by user-visible registers? 12.3 What is the function of condition codes? 12.4 What is a program status word? 12.5 Why is a two-stage instruction pipeline unlikely to cut the instruction cycle time in half, compared with the use of no pipeline? 12.6 List and briefly explain various ways in which an instruction pipeline can deal with conditional branch instructions. 12.7 How are history bits used for branch prediction? Review Questions 13.1 What are some typical distinguishing characteristics of RISC organization? 13.2 Briefly explain the two basic approaches used to minimize register-memory operations on RISC machines. 13.3 If a circular register buffer is used to handle local variables for nested procedures, describe two approaches for handling global variables. 13.4 What are some typical characteristics of a RISC instruction set architecture? 13.5 What is a delayed branch?