module traffic(clk, reset, p1, p2, p3, p4, pt, dir);

input clk;
input reset;
output [4:0] p1;
output [4:0] p2;
output [4:0] p3;
output [4:0] p4;
output [3:0] pt;
output [2:0] dir;
reg [4:0] p1;
reg [4:0] p2;
reg [4:0] p3;
reg [4:0] p4;
reg [3:0] pt;
reg [31:0] sig;
reg [2:0] dir;
always @ (posedge clk or negedge reset)
begin
if (reset == 1'b0) begin
dir <= 3'b111;
p1 <= 5'b00100;
p2 <= 5'b00100;
p3 <= 5'b00100;
p4 <= 5'b00100;
pt <= 4'b1111;
sig <= 8'h00000000;
end
else begin
dir <= 3'b111;
sig <= sig + 1;
case (sig[29:24])
6'b000000 : begin
p1 <= 5'b10011;// d5,d4,d3,d2,d1
(Green)
p2 <= 5'b00100;
p3 <= 5'b00100;
p4 <= 5'b00100;
pt <= 4'b1111;
end
6'b000100 : begin
p1 <= 5'b01000;
//Yellow
p2 <= 5'b00100;
p3 <= 5'b00100;
p4 <= 5'b00100;
pt <= 4'b1111;
end
6'b001000 : begin
p1 <= 5'b00100;
// d10,d9,d8,d7,d6
p2 <= 5'b10011;
//Green
p3 <= 5'b00100;
p4 <= 5'b00100;
pt <= 4'b1111;
end
6'b001100 : begin
p1 <= 5'b00100;
p2 <= 5'b01000;
//Yellow
p3 <= 5'b00100;
p4 <= 5'b00100;
pt <= 4'b1111;

end
6'b010000 : begin
p1 <= 5'b00100;
p2 <= 5'b00100;
p3 <= 5'b10011;
p4 <= 5'b00100;
pt <= 4'b1111;
end
6'b010100 : begin
p1 <= 5'b00100;
p2 <= 5'b00100;
p3 <= 5'b01000;
p4 <= 5'b00100;
pt <= 4'b1111;
end
6'b011000 : begin
p1 <= 5'b00100;
p2 <= 5'b00100;
p3 <= 5'b00100;
p4 <= 5'b10011;
pt <= 4'b1111;
end
6'b011100 : begin
p1 <= 5'b00100;
p2 <= 5'b00100;
p3 <= 5'b00100;
p4 <= 5'b01000;
pt <= 4'b1111;
end
6'b100000 : begin
p1 <= 5'b00100;
p2 <= 5'b00100;
p3 <= 5'b00100;
p4 <= 5'b00100;
pt <= 4'b0000;
end
6'b100100 : sig <= 8'h00000000;
default : begin

// d15,d14,d13,d12,d11
//Green

//yellow

// d20,d19,d18,d17,d16

//Green

//Yellow

// dl1,dl2,dl3,dl4,dl5,dl6,dl7,dl8

//Pedestrain

end
endcase
end
end
endmodule

module traffic(clk, reset, p1, p2, p3, p4, pt, dir);

input clk;
input reset;
output [4:0] p1;
output [4:0] p2;
output [4:0] p3;
output [4:0] p4;
output [3:0] pt;
output [2:0] dir;
reg [4:0] p1;
reg [4:0] p2;
reg [4:0] p3;
reg [4:0] p4;
reg [3:0] pt;
reg [31:0] sig;
reg [2:0] dir;
always @ (posedge clk or negedge reset)
begin
if (reset == 1'b0) begin
dir <= 3'b111;
p1 <= 5'b00100;
p2 <= 5'b00100;
p3 <= 5'b00100;
p4 <= 5'b00100;
pt <= 4'b1111;
sig <= 8'h00000000;
end
else begin
dir <= 3'b111;
sig <= sig + 1;
case (sig[29:24])
6'b000000 : begin
p1 <= 5'b10011; // d5,d4,d3,d2,d1
(Green)
p2 <= 5'b00100;
p3 <= 5'b00100;
p4 <= 5'b00100;
pt <= 4'b1111;
end
6'b000100 : begin
p1 <= 5'b01000; //Yellow
p2 <= 5'b00100;
p3 <= 5'b00100;
p4 <= 5'b00100;
pt <= 4'b1111;
end
6'b001000 : begin
p1 <= 5'b00100; // d10,d9,d8,d7,d6
p2 <= 5'b10011; //Green
p3 <= 5'b00100;
p4 <= 5'b00100;
pt <= 4'b1111;
end
6'b001100 : begin
p1 <= 5'b00100;
p2 <= 5'b01000; //Yellow
p3 <= 5'b00100;
p4 <= 5'b00100;
pt <= 4'b1111;

end
6'b010000 : begin
p1 <= 5'b00100; // 15,d14,d13,d12,d11
p2 <= 5'b00100;
p3 <= 5'b10011; //Green
p4 <= 5'b00100;
pt <= 4'b1111;
end
6'b010100 : begin
p1 <= 5'b00100;
p2 <= 5'b00100;
p3 <= 5'b01000; //yellow
p4 <= 5'b00100;
pt <= 4'b1111;
end
6'b011000 : begin
p1 <= 5'b00100;//d20,d19,d18,d17,d16
p2 <= 5'b00100;
p3 <= 5'b00100;
p4 <= 5'b10011; //Green
pt <= 4'b1111;
end
6'b011100 : begin
p1 <= 5'b00100;
p2 <= 5'b00100;
p3 <= 5'b00100;
p4 <= 5'b01000; //Yellow
pt <= 4'b1111;
end
6'b100000 : begin
p1 <= 5'b00100;
//dl1,dl2,dl3,dl4,dl5,dl6,dl7,dl8
p2 <= 5'b00100;
p3 <= 5'b00100;
p4 <= 5'b00100;
pt <= 4'b0000; //Pedestrain
end
6'b100100 : sig <= 8'h00000000;
default : begin
end
endcase
end
end
endmodule

Full adder
module fa(a,b,cin, sum,cout);
input a,b,cin;
output sum,cout;
assign sum= a^b^cin;
assign cout=(a&b)|(b&cin)|(cin&a);
endmodule
Multiplexer
module multi(a,b,c,d,s0,s1, out);
input a,b,c,d,s0,s1;
output out;
assign
out=(a&(~s0&~s1))|(b&(~s0&s1))|(c&(s0&~s1))|(d&(s0&s1));
endmodule
Encoder
module enc(d1,d2,d3,d4, a,b);
input d1,d2,d3,d4;
output a,b;
assign a=(d3|d4);
assign b=(d2|d4);
endmodule
D-Flip Flop
module Dfflop(d,clk, q,qn);
input d,clk;
output q,qn;
reg q=1'b0;
always @ (posedge clk)
q=d;
assign qn=~q;
endmodule
JK-Flip Flop
module jk(J,K,clk, q,qn);
input J,K,clk;
output q,qn;
reg q=1'b0;
always @ (posedge clk)
q=(J*(~qn))+(~K*qn);
assign qn=~q;
endmodule
SR-Flip Flop
module srrrrr(S,R,clk, q,qn);
input S,R,clk;
output q,qn;
reg q=1'b0;
always @ (posedge clk)
q=S+((~R)*qn);
assign qn=~q;
endmodule
T-Flip Flop
module tf(t,clk, q,qn);
input t,clk;
output q,qn;
reg q=1'b0;
always @ (posedge clk)
q=t^q;
assign qn=~q;
endmodule

Arithmatic & Logic unit

module alu(s, a,b, r);
input [2:0] s;
input [3:0] a,b;
output [7:0] r;
reg r=0;
always @ (s,a,b)
begin
case (s)
0:r=a+b; 1:r=a-b;
5:r=a|b; 6:r=~a;
endmodule

2:r=a*b;
7:r=a^b;

3:r=0;
endcase

4:r=a&b;
end

Up/ Down counter

module hai(clk,dir,clock,count);
input clk,dir;
output clock;
output [3:0] count;
reg clock=0;
reg count=0;
reg [23:0]temp=0;
always @ (posedge clk)
begin
temp=temp+1;
case(temp[23:22])
2'b00:clock=0;
2'b01:clock=1;
2'b10:clock=0;
endcase
end
always@(posedge clock)
begin
if(dir==1'b1 & count<=15)
count=count+1;
else if(dir==1'b0 & count>=0)
count=count-1;
else
count=0;
end
endmodule
Seven segment display
module sevseg(ip,op1,op2,sel);
input sel;
input [3:0]ip;
output [7:0]op1,op2;
reg [7:0]temp=0;
reg op1=0;
reg op2=0;
always@(ip)
case(ip)
0:temp=8'b11111100;
1:temp=8'b01100000;
2:temp=8'b11011010;
3:temp=8'b11110010;
4:temp=8'b01100110;
5:temp=8'b10110110;
6:temp=8'b10111110;
7:temp=8'b11100000;
8:temp=8'b11111110;
9:temp=8'b11110110;
10:temp=8'b11101110; 11:temp=8'b00111110;
12:temp=8'b10011100; 13:temp=8'b01111010;
14:temp=8'b11011110; 15:temp=8'b10001110;
endcase
always @ (sel)
case (sel)
0:op1=temp;
1:op2=temp; endcase endmodule

Parallel in serial out

module pisooo(pin,clk, sout,s);
input s,clk;
input [3:0]pin;
output sout;
reg sout=0;
reg [23:0] temp=0;
reg clock=0;
reg [3:0]q=0;
always @ (posedge clk)
if (s==0)
q=pin;
else if (s==1)
begin
temp=temp+1;
case (temp[23:22])
2'b00:clock=0;
2'b01:clock=1;
2'b10:temp=0;
endcase
end
always @ (posedge clock)
begin
q=q>>1;
q={pin[3],q[2:0]};
sout=q[0];
end
endmodule
Paralel in parallel out
module pipooo(pin,clk, pout);
input clk;
input [3:0]pin;
output [3:0] pout;
reg [23:0] temp=0;
reg clock=0;
reg [3:0]pout=0;
always @ (posedge clk)
begin
temp=temp+1;
case (temp[23:22])
2'b00:clock=0;
2'b01:clock=1;
2'b10:temp=0;
endcase
end
always @ (posedge clock)
pout=pin;
endmodule

Serial in serial out

module sisooo(sin,clk, sout);
input sin,clk;
output sout;
reg sout=1'b0;
reg [3:0]q=0;
reg [23:0] temp=0;
reg clock=0;
always @ (posedge clk)
begin
temp=temp+1;
case (temp[23:22])
2'b00:clock=0;
2'b01:clock=1;
2'b10:temp=0;
endcase
end
always @ (posedge clock)
begin
q=q>>1;
q={sin,q[2:0]};
sout=q[0];
end
endmodule
Serial in parallel out
module sipooo(sin,clk, pout);
input sin,clk;
output [3:0]pout;
reg pout=0;
reg [23:0] temp=0;
reg clock=0;
always @ (posedge clk)
begin
temp=temp+1;
case (temp[23:22])
2'b00:clock=0;
2'b01:clock=1;
2'b10:temp=0;
endcase
end
always @ (posedge clock)
begin
pout=pout>>1;
pout={sin,pout[2:0]};
end
endmodule