A

BTQ00 Rev0.1 Schematics Document

Intel Prescott uFCPGA-478 / P4 Northwood

with Springdale / ICH5 / nVIDIA NV18/34/31M chipset

2003/02/20

Title
Size
B
Date:
A

Compal Electronics, Inc.

Document Number

Cove r Sheet

LA-1841

Thursday, February 20, 2003

Sheet
E

Rev
0.1
1

of

57

Compal Confidential
File Name : BTQ00

Fan Controlpage

Desktop Prescott uFCPGA-478 CPU

Desktop Northwood uFCPGA-478 CPU

45

Clock Generator

Thermal Sensor
ADM1032AR

ICS 952623

page 4,5,6
page 5

CRT Connector

H_A#(3..31)

page 22

LVDS Interface
page

22

page 15

H_D#(0..63)

Memory BUS(DDR)

VGA
AGP BUS(8X)
NV18/31/34M
PIRQA#

PSB
400/533/667/800MHz

DDR-SO-DIMM X2

Intel Springdale MCH

BANK 0, 1, 2, 3

FCBGA-932

p age 16,17,
18,19

p age 12,13,14

2.5V DDR- 200/266

p a g e 7,8,9,10,11

TV OUT Connector
(4Pin Reverse)

USB2.0

page 22

USB Conn *4
page 37

VRAM DDR
32MB/64MB (FBGA)

Hub-Link

MDC & BT Conn

3.3V 33 MHz
IDSEL: AD18
PIRQC#, PIRQD#
GNT1#, REQ1#

IEEE 1394
TSB43AB21

Mini PCI
socket

page 30

page 29

RTC CKT.

PCI BUS

Intel ICH5

IDSEL: AD17
IDSEL: AD20
PIRQB#, GNT3#, REQ3# PIRQB#, SIRQ, GNT2#, REQ2#

page 26

S e condary IDE

p age 23,24,25

master

ATA-100

page 27,28

RJ45/11 CONN

Slot 0,1

page 26

Power On/Off CKT.

N
EC NS87591L

Int.KBD

page 44

Audio DJ
OZ-168
page 34

SMsC LPC47N227
Super I/O

page 39

Touch Pad

page 36

DC/DC Interface CKT.

PARALLEL

page 39

BIOS (1MB)
page

page 40

Module Conn.

Module Conn.

(Main Module)

(2nd Module)

page 35

page 35

Floppy

page 38

EC I/O Buffer

Audio AMP
page 32

HDD
Connector

master/slave

LPC BUS

page 41

page 32

page 31

page 27

Power OK CKT.

HW EQ CKT

ALC202

page 35

SD Conn.

page 28

AC97 Codec

ATA-100
P rimary IDE

mBGA-460

CardBus Controller
Toshiba TC6385XB

LAN
RTL 8101L

AC-LINK

IDSEL: AD16
PIRQA#, GNT0#, REQ0#

page 38

page 20,21

FIR

40

page 37

Power Circuit DC/DC

Title

Compal Electronics, Inc.

Block Diag ram

Size

Document Number

Rev
0.1

LA-1841
A

Date:

Thursday, February 20, 2003

Sheet

of

57

Voltage Ra ils

SIGNAL

STATE
Power P lane

Description

S1

S3

+VALW

+V

+VS

HIGH

HIGH

HIGH

HIGH

ON

ON

ON

VIN

Adapter powersupply (19V)

N/A

N/A

B+

AC or battery power rail for powercircuit.

N/A

N/A

N/A

+CPU_CORE

Core voltageforCPU

ON

OFF

OFF

+CPU_VID

1.2V switched power railforCPUAGTLBus

ON

OFF

OFF

+VTT_GMCH

+1.225V (Prescott) / +1.45V(Northwood)

ON

OFF

OFF

+VGA_CORE

1.2V switched power ra ilforVGAchip

ON

OFF

OFF

+1.2 5VS

1.25V switched powerrail

ON

OFF

OFF

+1.5VS

AGP 4X/8X

ON

OFF

OFF

+2.5V

2.5V power rail

ON

ON

OFF

+2.5VS

2.5V switched powerrail

ON

OFF

OFF

+3VALW

3.3V always on powerrail

ON

ON

ON*

+3V

3.3V power rail

ON

ON

OFF

+3VS

3.3V switched powerrail

ON

OFF

OFF

S1(Power On Suspend)

LOW

HIGH

HIGH

HIGH

ON

ON

ON

LOW

S3 (Suspend to RAM)

LOW

LOW

HIGH

HIGH

ON

ON

OFF

OFF

S4 (Suspend to Disk)

LOW

LOW

LOW

HIGH

ON

OFF

OFF

OFF

S5 (Soft OFF)

LOW

LOW

LOW

LOW

ON

OFF

OFF

OFF

5V always on powerrail

ON

ON

ON*

+5V

5V power rail

ON

ON

OFF

+5VS

5V switched powerrail

ON

OFF

OFF

+12VALW

12V always on powerrail

ON

ON

ON*

+RTCVCC

RTC power

ON

ON

ON

Note : ON* means that this power plane is ON only withACpoweravailable,otherwiseitisOFF.

Vcc
Ra

REQ#/GNT#

PIRQA

CardBus

AD20

PIRQA/PIRQB

LAN

AD17

PIRQB

Mini-PCI

AD18

1/4

PIRQC/PIRQD

1394

AD16

PIRQA

SD

AD22

Address

Smart Battery

0001 011X b

EEPROM(24C16/02)
(24C04)

1010 000X b
1011 000Xb

3.3V +/- 5%
100K +/- 5%
Rb
0
8.2K +/- 5%
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
NC

Board ID
0
1
2
3
4
5
6
7

Device

VAD_BID min
0 V
0.216 V
0.436 V
0.712 V
1.036 V
1.453 V
1.935 V
2.500 V

V AD_BID typ
0 V
0.250 V
0.503 V
0.819 V
1.185 V
1.650 V
2.200 V
3.300 V

V AD_BID max
0 V
0.289 V
0.538 V
0.875 V
1.264 V
1.759 V
2.341 V
3.300 V

Interrupts

VGA

EC SM Bus1 address

0
1
2
3
4
5
6
7

External PCI Device s

IDSEL#

ON

Board ID Table for AD channel

+5VALW

Device

Clock

N/A

Board ID

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

S5

Full ON
1

EC SM Bus2 address
Device

Address

ADM1032

1001 110X b

OZ168

0011 0100 b

PCB Revision
0.1

ICH4 SM Bus address

4

Device

Address

Clock Generator
( ICS 952623)

1101 001Xb

DDR DIMM0

1001 000Xb

DDR DIMM1

1001 001Xb

Title

Compal Electronics, Inc.

Notes

Size
B
Date:
A

Document Number

Rev
0.1

LA-1841
Thursday, February 20, 2003

Sheet
E

of

57

H6
D2
G2
G4
AF22
AF23

AP#0
AP#1
BINIT#
IERR#
BR0#
BPRI#
BNR#
LOCK#
BCLK0
BCLK1

HIT#
HITM#
DEFER#

H1
H4 VSS_0
H23 VSS_1
H26 VSS_2
A11 VSS_3
A13 VSS_4
A15 VSS_5
A17 VSS_6
A19 VSS_7
A21 VSS_8
A24 VSS_9
A26 VSS_10
A3 VSS_11
A9 VSS_12
AA1 VSS_13
AA11VSS_14
AA13VSS_15
AA15VSS_16
AA17VSS_17
AA19VSS_18
AA23VSS_19
AA26VSS_20
AA4 VSS_21
AA7 VSS_22
AA9 VSS_23
AB10VSS_24
AB12VSS_25
AB14VSS_26
AB16VSS_27
AB18VSS_28
AB20VSS_29
AB21VSS_30
AB24VSS_31
AB3 VSS_32
AB6 VSS_33
AB8 VSS_34
AC11VSS_35
AC13VSS_36
AC15VSS_37
AC17VSS_38
AC19VSS_39
AC2 VSS_40
AC22VSS_41
AC25VSS_42
AC5 VSS_43
AC7 VSS_44
AC9 VSS_45
AD10VSS_46
AD12VSS_47
AD14VSS_48
AD16VSS_49
AD18VSS_50
AD21VSS_51
AD23VSS_52
AD4 VSS_53
AD8 VSS_54
VSS_55

F3
E3
E2

AC1
V5
AA3
AC3

R e f e r e n ce Intel document
D e s k t o p P 4 S p e c . : 10988 P4 0.13u 512KB L2 EMTS Rev.2.0
Desktop

Prescott

P i n number

N orthwood
P in name

B6

FERR#

Spec.: 11910 Prescott EMTS Rev.0.5

C ommend

P rescott
P in name

BOOTSELECT

2
2

REQ#0
REQ#1
REQ#2
REQ#3
REQ#4
ADS#

VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_80
VCC_79
VCC_78
VCC_77
VCC_76
VCC_75
VCC_74

1
1

D#0
D#1
D#2
D#3
D#4
D#5
D#6
D#7
D#8
D#9
D#10
D#11
D#12
D#13
D#14
D#15
D#16
D#17
D#18
D#19
D#20
D#21
D#22
D#23
D#24
D#25
D#26
D#27
D#28
D#29
D#30
D#31
D#32
D#33
D#34
D#35
D#36
D#37
D#38
D#39
D#40
D#41
D#42
D#43
D#44
D#45
D#46
D#47
D#48
D#49
D#50
D#51
D#52
D#53
D#54
D#55
D#56
D#57
D#58
D#59
D#60
D#61
D#62
D#63

B21
B22
A23
A25
C21
D22
B24
C23
C24
B25
G22
H21
C26
D23
J21
D25
H22
E24
G23
F23
F24
E25
F26
D26
L21
G26
H24
M21
L22
J24
K23
H25
M23
N22
P21
M24
N23
M26
N26
N25
R21
P24
R25
R24
T26
T25
T22
T23
U26
U24
U23
V25
U21
V22
V24
W26
Y26
W25
Y23
Y24
Y21
AA25
AA22
AA24

F13
F15
F17
F19
F9
F11
E8
E20
E18
E16
E14
E12

J1
K5
J4
J3
H3
G1

Prescott

AD1

A#3
A#4
A#5
A#6
A#7
A#8
A#9
A#10
A#11
A#12
A#13
A#14
A#15
A#16
A#17
A#18
A#19
A#20
A#21
A#22
A#23
A#24
A#25
A#26
A#27
A#28
A#29
A#30
A#31
A#32
A#33
A#34
A#35

K2
K4
L6
K1
L3
M6
L2
M3
M4
N1
M1
N2
N4
N5
T1
R2
P3
P4
R3
T2
U1
P6
U3
T4
V2
R6
W1
T5
U4
V3
W2
Y1
AB1

VCC_0
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73

A10
A12
A14
A16
A18
A20
A8
AA10
AA12
AA14
AA16
AA18
AA8
AB11
AB13
AB15
AB17
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
AE12
AE14
AE16
AE18
AE20
AE6
AE8
AF11
AF13
AF15
AF17
AF19
AF2
AF21
AF5
AF7
AF9
B11
B13
B15
B17
B19
B7
B9
C10
C12
C14
C16
C18
C20
C8
D11
D13
D15
D17
D19
D7
D9
E10

R_C
P o p : Northwood
D e p op: Prescott

C ommend
N orthwood

P u l l-up 62ohm
t o +VCC_CORE

F ERR#/PBE#

P u l l-up 62ohm
t o +VCC_CORE

P rescott

Pop

Pop

AA20

I TPCLKOUT0

P u l l-up56ohm
t o +VCC_CORE

T ESTHI6

P u l l-up 62ohm
t o +VCC_CORE

Pop

Pop

AB22

I TPCLKOUT1

P u l l-up 56ohm
t o +VCC_CORE

T ESTHI7

P u l l-up 62ohm
t o +VCC_CORE

Pop

Pop

float

V IDPWRGD

P u l l -up 8.2Kohm
t o +VCCVID

Depop

Pop

Depop

Pop

Depop

Pop

Pop

Depop

Compal Electronics, Inc.

Pop

Depop

Prescott Processor in uFCPGA478 (1/2)

AD2
AD3

NC
NC

float

VID5

AF3

V CCVIDLB

P u l l-up1Kohm to
+ 3 V R UN & connect
t o PWRIC
C o n n ect to +VCCVID

NC

float

AD20

VCCA

C o n nect to CPU
Filter

V CCIOPLL

AF23

V CCIOPLL

C o n nect to CPU
Filter

VCCA

C o n nect to CPU
Filter

AD1

VSS

C o n nect to GND

B OOTSELECT

C P U determine

AE26

VSS

C o n nect to GND

O PTIMIZED/
COMPAT#

float

C o n nect to CPU
Filter

LA-1841
5

P l a ce near ICH

A2
1
1
1
1
1
1

2
2
2
2
2
2

AC6
AB5
AC4
Y6
AA5
AB4

N o t e : P l e a s e change to 10uH, DC current

o f 1 0 0 m A parts and close to cap

D4
C1
D5
F7
E6

AD20
AE23

A5
A4
AF3

AD22
AC26
AD26

L24
P1

1.Place cap within 600 mils of

the VCCA and VSSA pins.

P o p : Prescott
D e p o p: Northwood

PLL Layout note:

LINT0
LINT1
INIT#
RESET#
DBSY#
DRDY#
BSEL0
BSEL1
THERMDA
THERMDC

Prescott

THERMTRIP#
BPM#0
BPM#1
BPM#2
BPM#3
BPM#4
BPM#5
TCK
TDI
TDO
TMS
TRST#
VCCIOPLL
VCCA
VCCSENSE
VSSSENSE
VCCVIDLB
VSSA
ITP_CLK0
ITP_CLK1
COMP0
COMP1

2.H_VCCIOPLL,HVCCA,HVSSA trace wide

12 mils(min)

DSTBP#0
DSTBP#1
DSTBP#2
DSTBP#3
ADSTB#0
ADSTB#1
DBI#0
DBI#1
DBI#2
DBI#3
DBR#
PROCHOT#
MCERR#
SLP#
NC1
NC2
NC3
NC4
NC5

P o p : Northwood
D e p op: Prescott

R_G

AE26

AD24
AA2
AC21
AC20
AC24
AC23
AA20
AB22
U6
W4
Y3
A6
AD25

1
1

2
2

1
1
1
1
1

2
2
2
2
2
1
1

E22
K22
R22
W22

2
2

P o p : P4 Protability
D e p o p : Prescott/Northwood

F21
J23
P23
W23

L5
R5
E21
G25
P26
V21
AE25
C3
V6
AB26
A22
A7
AF25
AF24
AE21

RE
P o p : Prescott
D e p o p: Northwood

R_E

SKTOCC#

DSTBN#0
DSTBN#1
DSTBN#2
DSTBN#3

AA21
AA6
F20
F6

VCCVID

B3
C4

TESTHI0
TESTHI1
TESTHI2
TESTHI3
TESTHI4
TESTHI5
TESTHI6
TESTHI7
TESTHI8
TESTHI9
TESTHI10
TESTHI11
TESTHI12

J26
K25
K26
L25

AF4

H5
H2
AD6
AD5

OPTIMIZED/COMPAT#

VIDPWRGD

D1
E5
W5
AB25

DP#0
DP#1
DP#2
DP#3
GTLREF0
GTLREF1
GTLREF2
GTLREF3

A20M#
FERR#
IGNNE#
SMI#
PWRGOOD
STPCLK#

AD2

C6
B6
B2
B5
AB23
Y4

RS#0
RS#1
RS#2
RSP#
TRDY#

F1
G5
F4
AB2
J6

VID0
VID1
VID2
VID3
VID4
VID5

AE5
AE4
AE3
AE2
AE1
AD3

F8
G 2 1 VSS_129
G 2 4 VSS_130
G 3 VSS_131
G 6 VSS_132
J2 VSS_133
J22 VSS_134
J25 VSS_135
J5 VSS_136
K21 VSS_137
K24 VSS_138
K3 VSS_139
K6 VSS_140
L 1 VSS_141
L 2 3 VSS_142
L 2 6 VSS_143
L 4 VSS_144
M2 VSS_145
M22 VSS_146
M25 VSS_147
M5 VSS_148
N21 VSS_149
N24 VSS_150
N3 VSS_151
N6 VSS_152
P2 VSS_153
P22 VSS_154
P25 VSS_155
P5 VSS_156
R1 VSS_157
R23 VSS_158
R26 VSS_159
R4 VSS_160
T21 VSS_161
T24 VSS_162
T3 VSS_163
T6 VSS_164
U2 VSS_165
U22 VSS_166
U25 VSS_167
U5 VSS_168
V1 VSS_169
V23 VSS_170
V26 VSS_171
V4 VSS_172
W21 VSS_173
W24 VSS_174
W3 VSS_175
W6 VSS_176
Y2 VSS_177
Y22 VSS_178
Y25 VSS_179
Y5 VSS_180
VSS_181

VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128

P l a ce near CPU
1

AF26

AE11
AE13
AE15
AE17
AE19
AE22
AE24
AE7
AE9
AF1
AF10
AF12
AF14
AF16
AF18
AF20
AF6
AF8
B10
B12
B14
B16
B18
B20
B23
B26
B4
B8
C11
C13
C15
C17
C19
C2
C22
C25
C5
C7
C9
D10
D12
D14
D16
D18
D20
D21
D24
D3
D6
D8
E1
E11
E13
E15
E17
E19
E23
E26
E4
E7
E9
F10
F12
F14
F16
F18
F2
F22
F25
F5

5
6
7
8

4
3
2
1

Layout note:

1
1

GTL Reference Voltage

22

2
2

1. +CPU_GTLREF Trace wide

12mils(min),Space 15mils

2. Place R_A and R_B near CPU.

3. Place decoupling cap 220PF near CPU.

+ C P U _ G MCH_GTLREF trace
w i d e 1 2mils(min),Space
15mils

2
3
8

R_A
2

8
7
6
5

D+

VDD1

D-

ALERT#

SCLK

THERM#

SDATA

GND

1
6
4
5

R_B
2

1
2
3
4

Compal Electronics, Inc.

C l o s e to the CPU

Prescott Processor in uFCPGA478 (2/2)

LA-1841
5

Place 11 North of Socket(Stuff 8)

22uF depop reference

Springdale Customer Schematic R1.2 page82
Place 12 Inside Socket(Stuff all)

Place 9 South of Socket(Unstuff all)

470uF _ERS10m ohm* 15,

ESR=0.5m ohm

Decoupling Reference Document:

Springdale Chipset Platform Design guide Rev1.11
(12474)page239

Decoupling Reference Requirement:

560uF Polymer, ESR:5m ohm(each) * 10
22uF X5R * 32

Compal Electronics, Inc.

CPU Decoupling
LA-1841
5

T r a c e width 10mils,Space
7mils

1 2

HD_SWING
1 C159

R369
102_0603_1%

0.01U_0402_16V7K

HDRCOMP

R362
24.9_0603_1%

H_REQ#[0..4]

5
5

H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31

D26
D30
L23
E29
B32
K23
C30
C31
J25
B31
E30
B33
J24
F25
D34
C32
F28
C34
J27
G27
F29
E28
H27
K24
E32
F31
G30
J26
G26

H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

B29
J23
L22
C29
J21
B30
D28

H_ADSTB#0
H_ADSTB#1

B7
C7

15 CLK_HCLK
15 CLK_HCLK#

+CPU_GMCH_GTLREF

+GMCH_GTLREF
R359

200_0603_1%
1
R647

2
0_0603_5%

GTL Reference Voltage

Layout note:
B

1
2

1. +GMCH_GTLREF Trace wide

12mils(min),Space 15mils.
2. Place decoupling cap 220PF near GMCH. 5

C160
220P_0402_50V8K

H_RS#[0..2]

4 H_ADS#
5 H_TRDY#
5 H_DRDY#
4 H_DEFER#
4 H_HITM#
4 H_HIT#
4 H_LOCK#
4 H_BR0#
4 H_BNR#
4 H_BPRI#
5 H_DBSY#

HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HADSTB0#
HADSTB1#
HCLKP
HCLKN
HDSTBP0#
HDSTBN0#
DINV0#
HDSTBP1#
HDSTBN1#
DINV1#
HDSTBP2#
HDSTBN2#
DINV2#
HDSTBP3#
HDSTBN3#
DINV3#

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

H_RS#0
H_RS#1
H_RS#2

F27
D24
G24
L21
E23
K21
E25
B24
B28
B26
E27
G22
C27
B27
E8
AE14

ADS#
HTRDY#
DRDY#
DEFER#
HITM#
HIT#
HLOCK#
BREQ0#
BNR#
BPRI#
DBSY#
RS0#
RS1#
RS2#
CPURST#
PWROK#

PROCHOT#

+VTT_GMCH

B19
C19
C17
L19
K19
L17
G9
F9
L14
D12
E12
C15

H_DSTBP#0
H_DSTBN#0
H_DINV#0
H_DSTBP#1
H_DSTBN#1
H_DINV#1
H_DSTBP#2
H_DSTBN#2
H_DINV#2
H_DSTBP#3
H_DSTBN#3
H_DINV#3

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

5
H_RESET#
24,42 SYS_PWROK

HDRCOMP
HD_SWING

+GMCH_GTLREF

E24
C25
F23

H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63

5
5
5
5
5
5
5
5
5
5
5
5

H_D#[0..63]
B23
E22
B21
D20
B22
D22
B20
C21
E18
E20
B16
D16
B18
B17
E16
D18
G20
F17
E19
F19
J17
L18
G16
G18
F21
F15
E15
E21
J19
G14
E17
K17
J15
L16
J13
F13
F11
E13
K15
G12
G10
L15
E11
K13
J11
H10
G8
E9
B13
E14
B14
B12
B15
D14
C13
B11
D10
C11
E10
B10
C9
B9
D8
B8

BSEL0
BSEL1

L20
L13
L12

HDRCOMP
HDSWING
HDVREF

S P R INGDALE_UFCBGA932

H_PROCHOT#

H_PROCHOT#

5,52

MCH_CLKSEL0
MCH_CLKSEL1

15
15

U36F
AR32
AR29
AR27
AR25
AR23
AR20
AR16
AR13
AR11
AR9
AN32
AN30
AN28
AN26
AN24
AN22
AN20
AN18
AN16
AN14
AN12
AN10
AM35
AM29
AM27
AM25
AM23
AM21
AM19
AM17
AM15
AM13
AM11
AM9
AL32
AL1
AK28
AK26
AK24
AK22
AK20
AK18
AK16
AK14
AK12
AK10
AK8
AK3
AJ35
AJ32
AJ9
AJ4
AJ1
AH33
AH30
AH24
AH22
AH20
AH18
AH16
AH14
AH12
AH10
AH6
AH3
AG35
AG32
AG28
AG26
AG24
AG22
AG20
AG18
AG16
AG14
AG8
AG4
AF33
AF30
AF25
AF24
AF22
AF20
AF18
AF16
AF14
AF11
AF9
AF6
AF3
AE35
AE32
AE26
AE25
AE13
AE12

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

U36G
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AE11
AE10
AE4
AE1
AD33
AD30
AD28
AD10
AD9
AD8
AD6
AD3
AC35
AC32
AC4
AC1
AB33
AB30
AB28
AB27
AB26
AB10
AB9
AB8
AB6
AB3
AA32
AA4
AA1
Y35
Y33
Y30
Y28
Y27
Y26
Y10
Y9
Y8
Y6
Y3
W32
W18
W17
W4
V33
V30
V28
V27
V26
V19
V17
V10
V9
V8
V6
V3
U32
U19
U18
U4
T35
T33
T30
T28
T27
T26
T10
T9
T8
T6
T3
T1
R32
R4
R1
P33
P30
P28
P27
P26
P9
P8
P6
P3
N35
N32
N4
N1
M33
M30
M28
M27
M26
M6
M3
L35

L31
L26
L25
L24
K33
K29
K27
K25
K22
K20
K18
K16
K14
K12
K11
J35
J32
J28
J22
J20
J18
J16
J14
J12
J10
H33
H30
H26
H24
H22
H20
H18
H16
H14
H12
H9
H8
H5
H2
G35
G31
G28
F26
F24
F22
F20
F18

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

GND

U36A

H_A#[3..31]

R365
301_0603_1%
D

+VTT_GMCH

GND

FSB

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

F16
F14
F12
F10
F8
F5
F3
F1
E3
E1
D35
D33
D31
D29
D27
D25
D23
D21
D19
D17
D15
D13
D11
D9
D1
C28
C26
C24
C22
C20
C18
C16
C14
C12
C10
C8
C4
A32
A29
A27
A25
A23
A20
A16
A13
A11
A9
A7

S P R INGDALE_UFCBGA932

S P R INGDALE_UFCBGA932

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

Size
B
Date:

Compal Electronics, Inc.

Springdale-Host/GND (1/4)
Document Number

Rev
0.1

LA-1841
Thursday, February 20, 2003

Sheet
1

of

57

DDRA_SCS#0
DDRA_SCS#1

12,14 DDRA_SCS#0
12,14 DDRA_SCS#1

AA34
Y31
Y32
W34

DDRA_CKE0
DDRA_CKE1

12,14 DDRA_CKE0
12,14 DDRA_CKE1

AL20
AN19
AM20
AP20

+SM_VREF_A

DDRA_CLK1
DDRA_CLK1#
DDRA_CLK2
DDRA_CLK2#

+ S M _ V R E F _ A trace width of 12mils and space

12mils(min)

E34
2 C528
1

2 C522

2.2U_0805_16V4Z

0.1U_0402_16V4Z

SMXRCOMP

AK9

SMXRCOMPVOH

AN9

SMXRCOMPVOL

AL9

SCS_A0#
SCS_A1#
SCS_A2#
SCS_A3#
SCKE_A0
SCKE_A1
SCKE_A2
SCKE_A3
SCMDCLK_A0
SCMDCLK_A0#
SCMDCLK_A1
SCMDCLK_A1#
SCMDCLK_A2
SCMDCLK_A2#
SCMDCLK_A3
SCMDCLK_A3#
SCMDCLK_A4
SCMDCLK_A4#
SCMDCLK_A5
SCMDCLK_A5#
SMVREF_A
SMXRCOMP

SDQ_A16
SDQ_A17
SDQ_A18
SDQ_A19
SDQ_A20
SDQ_A21
SDQ_A22
SDQ_A23
SDQS_A3
SDM_A3
SDQ_A24
SDQ_A25
SDQ_A26
SDQ_A27
SDQ_A28
SDQ_A29
SDQ_A30
SDQ_A31
SDQS_A4
SDM_A4

SMXRCOMPVOH
SMXRCOMPVOL

SDQ_A32
SDQ_A33
SDQ_A34
SDQ_A35
SDQ_A36
SDQ_A37
SDQ_A38
SDQ_A39
SDQS_A5
SDM_A5

C l o se to GMCH(E34)

SDQ_A40
SDQ_A41
SDQ_A42
SDQ_A43
SDQ_A44
SDQ_A45
SDQ_A46
SDQ_A47

+2.5V

SDQS_A6
SDM_A6

T r a c e w idth of 12mils and space

10mils(min)
R151
40.2_0603_1%

2.2U_0805_16V4Z

SMXRCOMP

SDQ_A48
SDQ_A49
SDQ_A50
SDQ_A51
SDQ_A52
SDQ_A53
SDQ_A54
SDQ_A55

C h ange to 42.2_1%

C201

R152
40.2_0603_1%

SDQS_A7
SDM_A7

P l a ce resistors within
1 . 0 inch of GMCH (AK9)

SDQ_A56
SDQ_A57
SDQ_A58
SDQ_A59
SDQ_A60
SDQ_A61
SDQ_A62
SDQ_A63

C hange to 42.2_1%
2

AM30
AP30
AP28
AP29
AP33
AM33
AM28
AN29
AM31
AN34
AF34
AF31

+2.5V

AP23
AM24
AP22
AM22
AL24
AN27
AP21
AL22
AP25
AP27

12,14
12,14

DDRA_SDQS2
DDRA_SDM2

R390
10K_0603_1%

2.2U_0805_16V4Z

12,14
12,14

DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23

T r a c e width of 12mils and space

10mils(min)

2 C523

1
C533
1U_0603_10V6K

SMXRCOMPVOH

R391
30.9K_0603_1%

1
C196
0.01U_0402_16V7K

C lose to Pin AN9

DDRA_SDQS3
DDRA_SDM3

DDRA_SDQS4
DDRA_SDM4

C l ose to GMCH <1"

12,14
12,14

* C hange to 31.12K

DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31

AH32
AG34
AF32
AD32
AH31
AG33
AE34
AD34

F o l l o w Intel design guide

R 1 . 1 1 (12474) page124,125

12,14
12,14

DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39

V34
W33

AC34
AB31
V32
V31
AD31
AB32
U34
U33

DDRA_SDQS5
DDRA_SDM5

DDRA_SDQS6
DDRA_SDM6

12,14
12,14

DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55

2
1

C217
2.2U_0805_16V4Z

T r a c e width of 12mils and space

10mils(min)
R153
30.9K_0603_1%

H31
H32
J33
H34
E33
F33
K31
J34
G34
F34

+2.5V

M32
M34
T34
T32
K34
K32
T31
P34
L34
L33

12,14
12,14

DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47

DDRA_SDQS1
DDRA_SDM1
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15

SDQS_A2
SDM_A2

12,14

12
12
12
12

AK32
AK31
AP17
AN17
N33
N34
AK33
AK34
AM16
AL16
P31
P32

SBA_A0
SBA_A1

DDRA_SDQ[0..63]

AE33
AH34

SWE_A#
SCAS_A#
SRAS_A#

SDQ_A8
SDQ_A9
SDQ_A10
SDQ_A11
SDQ_A12
SDQ_A13
SDQ_A14
SDQ_A15

DDRA_SDQ[0..63]

AP15
AP16
AP14
AM14
AL18
AP19
AL14
AN15
AP18
AM18

12,14
12,14

12,14 DDRA_SBS0
12,14 DDRA_SBS1

SMAB_A1
SMAB_A2
SMAB_A3
SMAB_A4
SMAB_A5

DDRA_SDQS0
DDRA_SDM0

DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7

AB34
Y34
AC33

SDQS_A1
SDM_A1

AN11
AP12
AP10
AP11
AM12
AN13
AM10
AL10
AL12
AP13

DDRA_SDQS7
DDRA_SDM7

12,14
12,14

SMXRCOMPVOL

12,14 DDRA_SWE#
12,14 DDRA_SCAS#
12,14 DDRA_SRAS#

SDQS_A0
SDM_A0
SDQ_A0
SDQ_A1
SDQ_A2
SDQ_A3
SDQ_A4
SDQ_A5
SDQ_A6
SDQ_A7

C220
1U_0603_10V6K

R154
10K_0603_1%

1
2

DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63

C190
0.01U_0402_16V7K

C lose to Pin AL9

AL34
AM34
AP32
AP31
AM26

SMAA_A0
SMAA_A1
SMAA_A2
SMAA_A3
SMAA_A4
SMAA_A5
SMAA_A6
SMAA_A7
SMAA_A8
SMAA_A9
SMAA_A10
SMAA_A11
SMAA_A12

AJ34
AL33
AK29
AN31
AL30
AL26
AL28
AN25
AP26
AP24
AJ33
AN23
AN21

U36B
DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12

DDR Channel A

DDRA_SMA[0..12]

12,14 DDRA_SMA[0..12]

C l ose to GMCH <1"

S P R INGDALE_UFCBGA932

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Size
B

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.

Date:

Compal Electronics, Inc.

Springdale-DDR Interface-A(2/5)
Document Number

Rev
0.1

LA-1841
Thursday, February 20, 2003

Sheet
1

of

57

DDRB_CKE0
DDRB_CKE1

AK19
AF19
AG19
AE18

+SM_VREF_B

+2.5V

2
1

R392

DDRB_CLK1
DDRB_CLK1#
DDRB_CLK2
DDRB_CLK2#

+ S M _ V REF_B trace width of

1 2 mils and space
12mils(min)
C539

AP9

SMYRCOMP

2.2U_0805_16V4Z

150_0603_1%

AA33

SMYRCOMPVOH

R34

SMYRCOMPVOL

R33

SCKE_B0
SCKE_B1
SCKE_B2
SCKE_B3

SDQS_B3
SDM_B3

SCMDCLK_B0
SCMDCLK_B0#
SCMDCLK_B1
SCMDCLK_B1#
SCMDCLK_B2
SCMDCLK_B2#
SCMDCLK_B3
SCMDCLK_B3#
SCMDCLK_B4
SCMDCLK_B4#
SCMDCLK_B5
SCMDCLK_B5#
SMVREF_B
SMYRCOMP

SDQ_B24
SDQ_B25
SDQ_B26
SDQ_B27
SDQ_B28
SDQ_B29
SDQ_B30
SDQ_B31
SDQS_B4
SDM_B4
SDQ_B32
SDQ_B33
SDQ_B34
SDQ_B35
SDQ_B36
SDQ_B37
SDQ_B38
SDQ_B39

SMYRCOMPVOH
SMYRCOMPVOL

SDQS_B5
SDM_B5

2.2U_0805_16V4Z

SDQ_B40
SDQ_B41
SDQ_B42
SDQ_B43
SDQ_B44
SDQ_B45
SDQ_B46
SDQ_B47

C200
0.1U_0402_16V4Z

150_0603_1%

C547

C l ose to GMCH(AP9)

SDQS_B6
SDM_B6

+2.5V

2
R399
40.2_0603_1%

C h ange to 42.2_1%

SMYRCOMP

SDQ_B48
SDQ_B49
SDQ_B50
SDQ_B51
SDQ_B52
SDQ_B53
SDQ_B54
SDQ_B55

2.2U_0805_16V4Z

SDQS_B7
SDM_B7

T r a ce width of 12mils
a n d space 10mils(min)

SDQ_B56
SDQ_B57
SDQ_B58
SDQ_B59
SDQ_B60
SDQ_B61
SDQ_B62
SDQ_B63

C h ange to 42.2_1%

C553

R400
40.2_0603_1%
2

AH27
AJ28
AK25
AH26
AG27
AF27
AJ26
AJ27
AD25
AF28
AD29
AC31
AE30
AC27
AC30
Y29
AE31
AB29
AA26
AA27

P l a c e resistors within
1 . 0 inch of GMCH (AA33)

DDRB_SDQS2
DDRB_SDM2

13,14
13,14

DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23

2
1

DDRB_SDQS3
DDRB_SDM3

13,14
13,14

DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31

DDRB_SDQS4
DDRB_SDM4

DDRB_SDQS5
DDRB_SDM5

1
C546
1U_0603_10V6K

SMYRCOMPVOH
1

R398
30.9K_0603_1%

0.01U_0402_50V7K

C lose to Pin R14

+2.5V

C219

DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55

1
2

DDRB_SDQS7
DDRB_SDM7

R163
30.9K_0603_1%

2.2U_0805_16V4Z

13,14
13,14

T r a c e w idth of 12mils and space

10mils(min)

SMYRCOMPVOL
1

R164
10K_0603_1%

C223
1U_0603_10V6K

C211
0.01U_0402_50V7K

C lose to Pin R33

C l ose to GMCH <1"

13,14
13,14

DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63

S P R INGDALE_UFCBGA932

Title

C213

C l ose to GMCH <1"

13,14
13,14

1
DDRB_SDQS6
DDRB_SDM6

J30
J31
K30
H29
F32
G33
N25
M25
J29
G32

R394
10K_0603_1%

2.2U_0805_16V4Z

13,14
13,14

DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47

L27
M29
P29
R30
K28
L30
R31
R26
P25
L32

T r a c e width of 12mils and space

10mils(min)

DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39

U30
U31

AA30
W30
U27
T25
AA31
V29
U25
R27

C541

AE19
AE20
AG23
AK23
AL19
AK21
AJ24
AE22

13,14
13,14

+2.5V

AG21
AE21

2
R396

SCS_B0#
SCS_B1#
SCS_B2#
SCS_B3#

SDQ_B16
SDQ_B17
SDQ_B18
SDQ_B19
SDQ_B20
SDQ_B21
SDQ_B22
SDQ_B23

DDRB_SDQS1
DDRB_SDM1
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15

S M _ V REF_B and SM_VREF_A

a r e c onnected inside GMCH.

AG29
AG30
AF17
AG17
N27
N26
AJ30
AH29
AK15
AL15
N31
N30

SBA_B0
SBA_B1

13,14

13,14 DDRB_CKE0
13,14 DDRB_CKE1

U26
T29
V25
W25

SDQS_B2
SDM_B2

DDRB_SDQ[0..63]

DDRB_SCS#0
DDRB_SCS#1

SWE_B#
SCAS_B#
SRAS_B#

DDRB_SDQ[0..63]

AG13
AG15
AE17
AL13
AK17
AL17
AK13
AJ14
AJ16
AJ18

13,14
13,14

13,14 DDRB_SCS#0
13,14 DDRB_SCS#1

SDQ_B8
SDQ_B9
SDQ_B10
SDQ_B11
SDQ_B12
SDQ_B13
SDQ_B14
SDQ_B15

DDRB_SDQS0
DDRB_SDM0

DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7

Y25
AA25

13,14 DDRB_SBS0
13,14 DDRB_SBS1

SMAB_B1
SMAB_B2
SMAB_B3
SMAB_B4
SMAB_B5

SDQS_B1
SDM_B1

AF15
AG11
AJ10
AE15
AL11
AE16
AL8
AF12
AK11
AG12

W27
W31
W26

13,14 DDRB_SWE#
13,14 DDRB_SCAS#
13,14 DDRB_SRAS#

SDQS_B0
SDM_B0
SDQ_B0
SDQ_B1
SDQ_B2
SDQ_B3
SDQ_B4
SDQ_B5
SDQ_B6
SDQ_B7

AE27
AD26
AL29
AL27
AE23

SMAA_B0
SMAA_B1
SMAA_B2
SMAA_B3
SMAA_B4
SMAA_B5
SMAA_B6
SMAA_B7
SMAA_B8
SMAA_B9
SMAA_B10
SMAA_B11
SMAA_B12

AG31
AJ31
AD27
AE24
AK27
AG25
AL25
AF21
AL23
AJ22
AF29
AL21
AJ20

13
13
13
13

U36C
DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12

DDR Channel B

DDRB_SMA[0..12]

13,14 DDRB_SMA[0..12]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

Size
B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.

Date:

Compal Electronics, Inc.

Springdale-DDR Interface-B(3/5)
Document Number

Rev
0.1

LA-1841
Thursday, February 20, 2003

Sheet
1

of

57

+1.5VS

C h ange to 43.2_1%

C h ange to 52.3_1%

+1.5VS

R121

GRCOMP

@10K_0402_5%
1

51.1_0603_1%
2

R116

HI_RCOMP_MCH

16 AGP_FRAME#
15 CLK_MCH_66M
16 AGP_DEVSEL#
16 AGP_IRDY#
16 AGP_TRDY#
16 AGP_STOP#
16 AGP_PAR
16 AGP_REQ#
16 AGP_GNT#

AGP_PAR

1: External AGP
0: Internal Graphics
+1.5VS
1

Note:
H I _ S WING_MCH, HI_VREF_MCH
t r a c e width of 10mils and
space 7mils

R353
226_0603_1%
2
1

147_0603_1%

2 0.1U_0402_16V4Z

C498
0.01U_0402_16V7K

AGP_PAR

GRCOMP
AGP_SWING
+AGP_VREF

AGP_ST0
AGP_ST1
AGP_ST2

23 HUB_HL[0..10]

0.1U_0402_16V4Z

C503
0.01U_0402_16V7K

HI_RCOMP_MCH
HI_SWING_MCH
HI_VREF_MCH

AD4
AE3
AE2

23 HUB_HLSTRF
23 HUB_HLSTRS

CLK_MCH_66M
1

C l o s e to GMCH ball <250mils

R337
@10_0402_5%

R122
226_0603_1%

Note:
C I _ S WING_MCH, CI_VREF_MCH
t r a c e width of 10mils and
space 20mils

1 2

R127

0.1U_0402_16V4Z

147_0603_1%

C155
0.01U_0402_16V7K

CI_VREF_GMCH
1 C l ose to GMCH(AF4)

R130

0.1U_0402_16V4Z

113_0603_1%

C165
0.01U_0402_16V7K

R92

24 ICH_SYNC#
23,26,27,29,30,36,39
PCIRST#

C l o s e to GMCH ball <250mils

+1.5VS

R31

GRCOMP/DVOBCGCOMP
GVSWING
GVREF
GRBF
GWBF
DBI_HI
DBI_LO
GST0
GST1
GST2
HI0
HI1
HI2
HI3
HI4
HI5
HI6
HI7
HI8
HI9
HI10
HISTRF
HISTRS

54.9_0603_1%
CI_SWING_GMCH
CI_VREF_GMCH
1

2
R134

0_0402_5%

1
0_0402_5%

AK7
AH7
AD11
AF7
AD7
AC10
AF8
AG7
AE9
AH9
AG6
AJ6
AJ5
AG2
AF2
AF4
G4
AP8
AJ8
AK4

AG10
AG9
AN35
AP34
AR1

2
1

1
2

C9
0.1U_0402_16V4Z

1
2

HI_RCOMP
HI_SWING
HI_VREF
CI0
CI1
CI2
CI3
CI4
CI5
CI6
CI7
CI8
CI9
CI10
CISTRF
CISTRS

CI_RCOMP
CI_SWING
CI_VREF
DREFCLK
EXTTS#
ICH_SYNC#
RSTIN#
RESERVED_1
RESERVED_2
RESERVED_3
RESERVED_4
RESERVED_5

0.01U_0402_16V7K

Follow Springdale Chipset Platform Design guide Rev1.11(12474)

R55

100_0603_1%

C127
0.01U_0402_16V7K

GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31
GSBSTBF
GSBSTBS#
GSBA0#
GSBA1#
GSBA2#
GSBA3#
GSBA4#
GSBA5#
GSBA6#
GSBA7#
DDCA_DATA
DDCA_CLK

C113

+AGP_VREF

GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GADSTBF1
GADSTBS1#

AGP_SWING
R32
39.2_0603_1%

AGP

C l o s e G M C H ball (AC3) less than 250mils

60.4_0603_1%

1
2
R56
33.2_0603_1%

R375

C166

+1.5VS

0.35V

1
B

C486
@10P_0402_50V8K

c h ange to 52.3_1%

C l o s e to GMCH ball <250mils

1 C l ose to GMCH(AF2)

GFRAME
GCLKIN
GDEVSEL
GIRDY
GTRDY
GSTOP
GPAR/ADD_DETECT
GREQ
GGNT

CSA

CI_SWING_GMCH

1 C147

0.8V

+1.5VS

GADSTBF0
GADSTBS0#

N3
N5
N2

GCBE0
GCBE1
GCBE2
GCBE3

HUB

113_0603_1%

1 C l o se to GMCH(AE2)

C500

AC2
AC3
AD2

AF5
AG3
AK2
AG5
AK5
AL3
AL2
AL4
AJ2
AH2
AJ3
AH5
AH4

HI_VREF_MCH
1

U6
H4
AB4
V11
AB5
W11
AB2
N6
M7

HUB_HL0
HUB_HL1
HUB_HL2
HUB_HL3
HUB_HL4
HUB_HL5
HUB_HL6
HUB_HL7
HUB_HL8
HUB_HL9
HUB_HL10

C l o s e to GMCH ball <250mils

R372

Y7
W5
AA3
U2

R10
R9
M4
M5

16
AGP_RBF#
16
AGP_WBF#
16
AGP_DBIHI
16
AGP_DBILO
16 AGP_ST[0..2]

1 C l o se to GMCH(AE3)

C499

CLK_MCH_66M

+AGP_VREF

HI_SWING_MCH
R368

AGP_C/BE#0
AGP_C/BE#1
AGP_C/BE#2
AGP_C/BE#3

1
R123
43_0402_5%

U36D
16 AGP_C/BE#[0..3]

VGA

+1.5VS

RED
RED#
GREEN
GREEN#
BLUE
BLUE#
HSYNC
VSYNC
REFSET
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20

AC6
AC5
AE6
AC11
AD5
AE5
AA10
AC9
AB11
AB7
AA9
AA6
AA5
W10
AA11
W6
W9
V7

AGP_AD_STBF0
AGP_AD_STBS0

AGP_AD[0..31]

AGP_AD_STBF1
AGP_AD_STBS1

16

16
16

AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31

U11
T11

AGP_SB_STBF
AGP_SB_STBS
AGP_SBA[0..7]

R6
P7
R3
R5
U9
U10
U5
T7

AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7

H3
F2

R88 2
R84 2

1 0_0402_5%
1 0_0402_5%

F4
E4
H6
G5
H7
G6

R91 2

1 0_0402_5%

R1012

1 0_0402_5%

R1042

1 0_0402_5%

R3222

1 0_0402_5%

16
16
16

G3
E2
D2
A3
A33
A35
AF13
AF23
AJ12
AN1
AP2
AR3
AR33
AR35
B2
B25
B34
C1
C23
C35
E26
M31
R25

Analog RGB/CRT guidelines for Springdale-P

S P R INGDALE_UFCBGA932

Note:
S p r i n g d a l e Customer Schematic R1.2 page18
A G P _ S W I N G o nly had 0.1u cap ; But Springdale
C h i p s e t P l a tform Design guide Rev1.11(12474)
p a g e 1 3 8 h a d a 0.01uf cap. need confirm with
Intel.

C l o s e GMCH ball (AD2)

l e ss than 250mils

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.

V4
V5
AA2
Y4
Y2
W2
Y5
V2
W3
U3
T2
T4
T5
R2
P2
P5
P4
M2

16
16

AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15

Size
B
Date:

Springdale-AGP/HUB/VGA/CSA (4/5)
Document Number

LA-1841
Thursday, February 20, 2003

Sheet

10

of

57

Rev
0.1

+2.5V
1

Note:
Placed less than 100 mils from ball
Route to GMCH ball without via

+1.5VS

C174
22U_1206_10V4Z

C186
4.7U_0805_6.3V6K

C169
0.1U_0402_10V6K

C238
0.1U_0402_10V6K

C191
0.1U_0402_10V6K

C198
0.1U_0402_10V6K

C172
0.1U_0402_10V6K

C195
0.1U_0402_10V6K

C199
0.1U_0402_10V6K

U36E

0.47U_0603_16V7K

+VTT_GMCH

2
1

+2.5V
C535
0.1U_0402_10V6K

C552

C532

Trace 14mils

C548
0.1U_0402_10V6K
2
1
VCC_DDR_DCAP5
VCC_DDR_DCAP4
1
0.22U_0603_10V7K

C520
0.47U_0603_16V7K
VCC_DDR_DCAP1
2
1
1
0.22U_0603_10V7K
+3VS
C163
0.1U_0402_10V6K
2
1
VCC_AGP_DCAP2
+1.5VS

1
VTT_DCAP3
C168
0.1U_0402_10V6K
VCCA_FSB
R321 2
1 0_0402_5%
VCCA_DPLL
2
1
VCCA_DAC
R316
0_0402_5%
1
2
VCC_DDR_DCAP2
C242
0.1U_0402_10V6K
VCCA1P5_DDR_SM

(1A)

AA35
AL6
AL7
AM1
AM2
AM3
AM5
AM6
AM7
AM8
AN2
AN4
AN5
AN6
AN7
AN8
AP3
AP4
AP5
AP6
AP7
AR15
AR21
AR31
AR4
AR5
AR7
E35
R35
G1
G2
AG1
Y11
A31
B4
B3
C2
AL35
AB25
AC25
AC26

VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR
VCC_DDR

+1.5VS

+2.5V
1
2

C189
0.1U_0402_10V6K

C185
0.1U_0402_10V6K

VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP
VCC_AGP

VCC_DAC
VCC_DAC

C222
0.1U_0402_10V6K

VCCA_AGP
VCCA_AGP
VCCA_FSB
VCCA_FSB
VCCA_DPLL
VCCA_DAC
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR

VSSA_DAC

D3

C175
0.1U_0402_10V6K

1
2

C171
0.1U_0402_10V6K

C112
0.1U_0402_10V6K

C135
0.1U_0402_10V6K

+1.5VS

C125
0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

C181
0.1U_0402_10V6K

C167
0.1U_0402_10V6K

C143
0.1U_0402_10V6K

C184
0.1U_0402_10V6K

+VTT_GMCH

1
+ C72
2

C106

2 C157

C156

4.7U_0805_6.3V6K

10U_1206_16V4Z

1
+ C28

2 C70

470U_D4_2.5VM

470U_D4_2.5VM

2 C47

0.1U_0402_16V4Z

2 C60

4.7U_0805_6.3V6K

4.7U_0805_6.3V6K

1 C42
2

1 C26

1U_0603_6.3V6M

0.47U_0603_16V7K

P l a c e a t the output of the 1.5V VR

+1.5VS

+VTT_GMCH
1

+2.5V

C92
0.1U_0402_10V6K

P lace near GMCH

C126
0.1U_0402_10V6K

P lace near ball

Y 1 1,routing trace
f r om cap to ball

C183
0.1U_0402_10V6K

P lace near GMCH

N o t e : P l e a se change to 0.82uH, DC current

o f 3 0 m A parts and close to cap

+1.5VS

VCC_AGP_DCAP1

C117
0.1U_0402_10V6K

L21

Trace 14mils

2
R315
0_0603_5%

1 VCCA_FSB1

Trace 14mils
2

VCCA_FSB

LQG21F4R7N00_0805

C32

150U_D2_6.3VM
2

S P R INGDALE_UFCBGA932

Note:
Placed less than 100 mils from ball
Route to GMCH ball without via

C99

+1.5VS

J1
J2
J3
J4
J5
K2
K3
K4
K5
L1
L2
L3
L4
L5
Y1

J6
J7
J8
J9
K6
K7
K8
K9
L6
L7
L9
L10
L11
M8
M9
M10
M11
N9
N10
N11
P10
P11
R11
T16
T17
T18
T19
T20
U16
U17
U20
V16
V18
V20
W16
W19
W20
Y16
Y17
Y18
Y19
Y20

0.47U_0603_16V7K

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

1 C496

VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT

1 C490

A15
A21
A4
A5
A6
B5
B6
C5
C6
D5
D6
D7
E6
E7
F7

POWER

VTT_DCAP1
VTT_DCAP2

2
1

C475
0.1U_0402_16V4Z

Close to GMCH

Decoupling Reference Document:

Springdale Chipset Platform Design guide Rev1.11
(12474)page246,248

+1.5VS

N o t e : P l e a s e change to 1uH(0.54uH-D-IN), DC current

o f 1 0 0 0 mA parts and close to cap
Trace 50mils
T r a c e 3 5 mils (under GMCH ball field)
L16
2
1 VCCA_DDR
R144
0_0603_5%
(1A)

Trace 35mils
2

VCCA1P5_DDR_SM

LQG21F4R7N00_0805

Decoupling Reference Document:

Springdale Customer Schematic R1.2 page84

C197

(1A)

22U_1210_6.3V6M

2
1

C212
0.1U_0402_16V4Z

Close to GMCH
A

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
5

Size
B
Date:

Compal El ectronics, Inc.

Springdale-Decoupling (5/5)

Document Number

Rev
0.1

LA-1841
Thursday, February 20, 2003

Sheet
1

11

of

57

DDRA_SDQ8
DDRA_SDQS1
DDRA_SDQ10
DDRA_SDQ15
8
8

DDRA_CLK1
DDRA_CLK1#
DDRA_SDQ20
DDRA_SDQ16
DDRA_SDQS2
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQS3
DDRA_SDQ30
DDRA_SDQ27

8,14 DDRA_CKE1

DDRA_CKE1
DDRA_SMA12
DDRA_SMA9
DDRA_SMA7
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1

8,14 DDRA_SBS0
8,14 DDRA_SWE#
8,14 DDRA_SCS#0

DDRA_SMA10
DDRA_SBS0
DDRA_SWE#
DDRA_SCS#0
DDRA_SDQ36
DDRA_SDQ37

DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ44
DDRA_SDQ41
DDRA_SDQS5
DDRA_SDQ43
DDRA_SDQ46

DDRA_SDQ48
DDRA_SDQ53
DDRA_SDQS6
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQS7
DDRA_SDQ62
DDRA_SDQ59

13,15,23
13,15,23

ICH_SMB_DATA
ICH_SMB_CLK
+3VS

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
CK2#
VDD
CKE1
DU/A13
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE#
S0#
DU
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDD_SPD
VDD_ID

DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/RESET#
VSS
VSS
VDD
VDD
CKE0
DU/BA2
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
RAS#
CAS#
S1#
DU
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

DDRA_VREF
DDRA_SDQ5
DDRA_SDQ4

1 C305

DDRA_SDM0
DDRA_SDQ7

KEYLINK_5762-3-111

+2.5V

0.1U_0402_16V4Z

R204

DDRA_SDQ3
DDRA_SDQ9

DDRA_SDM[0..7]

8,14 DDRA_SDM[0..7]

DDRA_SDQ13
DDRA_SDM1

R203
75_0603_1%

DDRA_SDQ14
DDRA_SDQ11

DDRA_SDQ21
DDRA_SDQ17

System Memory Decoupling caps

+2.5V

DDRA_SDM2
DDRA_SDQ22

DDRA_SDQ23
DDRA_SDQ24

DDRA_SDQ25
DDRA_SDM3

C331
22U_1206_10V4Z

C314
0.1U_0402_10V6K

C339
0.1U_0402_10V6K

1
2

C312
0.1U_0402_10V6K

C337
0.1U_0402_10V6K

1
2

C311
0.1U_0402_10V6K

C336
0.1U_0402_10V6K

DDRA_SDQ26
DDRA_SDQ31
+2.5V
1
2

DDRA_CKE0
DDRA_SMA11
DDRA_SMA8

DDRA_CKE0

C310

0.1U_0402_10V6K

1
2

C335

0.1U_0402_10V6K

C334

0.1U_0402_10V6K

C308
0.1U_0402_10V6K

1
2

C333
0.1U_0402_10V6K

C307
0.1U_0402_10V6K

1
2

C332
0.1U_0402_10V6K

C306
0.1U_0402_10V6K

8,14

DDRA_SMA6
DDRA_SMA4
DDRA_SMA2
DDRA_SMA0

DDRA_SBS1
DDRA_SRAS#
DDRA_SCAS#
DDRA_SCS#1

DDRA_SBS1
DDRA_SRAS#
DDRA_SCAS#
DDRA_SCS#1

8,14
8,14
8,14
8,14

DDRA_SDQ32
DDRA_SDQ33
DDRA_SDM4
DDRA_SDQ38

Decoupling Reference Document:

Springdale Customer Schematic R1.2 page22
each Channel(two DIMMs) requirement 22uF*1 ; 0.1uF*14
B

Decoupling Reference Document:

Springdale Chipset Platform Design guide Rev1.11
(12474)pag 271 each DIMM(two) requirement 0.1uF*42

DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ45
DDRA_SDM5
DDRA_SDQ42
DDRA_SDQ47

DDRA_CLK2#
DDRA_CLK2

DDRA_SDQ49
DDRA_SDQ52
DDRA_SDM6
DDRA_SDQ51
DDRA_SDQ50
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDM7
DDRA_SDQ63
DDRA_SDQ58

SO-DIMM 0
REVERSE

Title

H = 5.2mm

DDRA_SMA[0..12]

8,14 DDRA_SMA[0..12]

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
5

DDRA_SDQS[0..7]

8,14 D DRA_SDQS[0..7]

75_0603_1%

C lose to SO-DIMM

DDRA_SDQ[0..63]

8,14 DDRA_SDQ[0..63]

VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS

VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0#
VSS

DDRA_SDQ2
DDRA_SDQ12

JP26

DDRA_SDQS0
DDRA_SDQ6

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

D D R A _ VREF trace width of

1 2 m i l s and space 12mils(min)

DDRA_SDQ0
DDRA_SDQ1

+2.5V

+2.5V

Size
Date:

Compal Electronics, Inc.

DDR-SODIMM SLOT1

Document Number

LA-1841

Thursday, February 20, 2003

Sheet

12

Rev
0.1
of

57

DDRB_SDQ12
DDRB_SDQS1
DDRB_SDQ10
DDRB_SDQ14
9
9

DDRB_CLK1
DDRB_CLK1#
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQS2
DDRB_SDQ22
DDRB_SDQ17
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQS3
DDRB_SDQ26
DDRB_SDQ30

9,14 DDRB_CKE1

DDRB_CKE1
DDRB_SMA12
DDRB_SMA9
DDRB_SMA7
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1

9,14 DDRB_SBS0
9,14 DDRB_SWE#
9,14 DDRB_SCS#0

DDRB_SMA10
DDRB_SBS0
DDRB_SWE#
DDRB_SCS#0
DDRB_SDQ33
DDRB_SDQ34

DDRB_SDQS4
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ40
DDRB_SDQ44
DDRB_SDQS5
DDRB_SDQ43
DDRB_SDQ42

DDRB_SDQ52
DDRB_SDQ49
DDRB_SDQS6
DDRB_SDQ55
DDRB_SDQ50
DDRB_SDQ60
DDRB_SDQ56
DDRB_SDQS7
A

DDRB_SDQ58
DDRB_SDQ57
12,15,23
12,15,23

ICH_SMB_DATA
ICH_SMB_CLK
+3VS

41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199

DQ16
DQ17
VDD
DQS2
DQ18
VSS
DQ19
DQ24
VDD
DQ25
DQS3
VSS
DQ26
DQ27
VDD
CB0
CB1
VSS
DQS8
CB2
VDD
CB3
DU
VSS
CK2
CK2#
VDD
CKE1
DU/A13
A12
A9
VSS
A7
A5
A3
A1
VDD
A10/AP
BA0
WE#
S0#
DU
VSS
DQ32
DQ33
VDD
DQS4
DQ34
VSS
DQ35
DQ40
VDD
DQ41
DQS5
VSS
DQ42
DQ43
VDD
VDD
VSS
VSS
DQ48
DQ49
VDD
DQS6
DQ50
VSS
DQ51
DQ56
VDD
DQ57
DQS7
VSS
DQ58
DQ59
VDD
SDA
SCL
VDD_SPD
VDD_ID

DQ20
DQ21
VDD
DM2
DQ22
VSS
DQ23
DQ28
VDD
DQ29
DM3
VSS
DQ30
DQ31
VDD
CB4
CB5
VSS
DM8
CB6
VDD
CB7
DU/RESET#
VSS
VSS
VDD
VDD
CKE0
DU/BA2
A11
A8
VSS
A6
A4
A2
A0
VDD
BA1
RAS#
CAS#
S1#
DU
VSS
DQ36
DQ37
VDD
DM4
DQ38
VSS
DQ39
DQ44
VDD
DQ45
DM5
VSS
DQ46
DQ47
VDD
CK1#
CK1
VSS
DQ52
DQ53
VDD
DM6
DQ54
VSS
DQ55
DQ60
VDD
DQ61
DM7
VSS
DQ62
DQ63
VDD
SA0
SA1
SA2
DU

42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200

KLINK_5746-3-111

H= 9.2mm
5

+2.5V

DDRB_SDQ2
DDRB_SDQ6

C300
0.1U_0402_16V4Z

DDRB_SDQS[0..7]

9,14 D DRB_SDQS[0..7]
R197

DDRB_SDM0
DDRB_SDQ1

DDRB_SDQ[0..63]

9,14 DDRB_SDQ[0..63]
1

DDRB_VREF

DDRB_SMA[0..12]

9,14 DDRB_SMA[0..12]

75_0603_1%

DDRB_SDM[0..7]

9,14 DDRB_SDM[0..7]

VREF
VSS
DQ4
DQ5
VDD
DM0
DQ6
VSS
DQ7
DQ12
VDD
DQ13
DM1
VSS
DQ14
DQ15
VDD
VDD
VSS
VSS

D D R B _VREF trace width of

1 2 m i l s and space 12mils(min)

DDRB_SDQ3
DDRB_SDQ13

R196

DDRB_SDQ11
DDRB_SDM1

75_0603_1%

DDRB_SDQ15
DDRB_SDQ8

System Memory Decoupling caps

+2.5V
DDRB_SDQ19
DDRB_SDQ16

DDRB_SDM2
DDRB_SDQ18

C299
0.1U_0402_10V6K

C270
0.1U_0402_10V6K

C298
0.1U_0402_10V6K

C269
0.1U_0402_10V6K

C297
0.1U_0402_10V6K

C267
0.1U_0402_10V6K

C296
0.1U_0402_10V6K

C266
0.1U_0402_10V6K

DDRB_SDQ23
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDM3
DDRB_SDQ27
DDRB_SDQ31
+2.5V

DDRB_SDQ5
DDRB_SDQ9

VREF
VSS
DQ0
DQ1
VDD
DQS0
DQ2
VSS
DQ3
DQ8
VDD
DQ9
DQS1
VSS
DQ10
DQ11
VDD
CK0
CK0#
VSS

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40

1 C294
2

DDRB_CKE0

DDRB_CKE0

DDRB_SMA11
DDRB_SMA8

1 C292

0.1U_0402_10V6K

1 C264

0.1U_0402_10V6K

1 C263

0.1U_0402_10V6K

1 C291

0.1U_0402_10V6K

1 C262

0.1U_0402_10V6K

1 C290

0.1U_0402_10V6K

1 C261

0.1U_0402_10V6K

0.1U_0402_10V6K

9,14

DDRB_SDQS0
DDRB_SDQ7

JP24

DDRB_SMA6
DDRB_SMA4
DDRB_SMA2
DDRB_SMA0

DDRB_SBS1
DDRB_SRAS#
DDRB_SCAS#
DDRB_SCS#1

DDRB_SBS1
DDRB_SRAS#
DDRB_SCAS#
DDRB_SCS#1

9,14
9,14
9,14
9,14

DDRB_SDQ32
DDRB_SDQ36

Decoupling Reference Document:

Springdale Customer Schematic R1.2 page26
each Channel(two DIMMs) requirement 0.1uF*24
B

+2.5V

DDRB_SDQ4
DDRB_SDQ0

+2.5V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39

+2.5V

DDRB_SDM4
DDRB_SDQ39
DDRB_SDQ35
DDRB_SDQ46

1 C338

DDRB_SDQ45
DDRB_SDM5

0.1U_0402_10V6K

1 C313
2

0.1U_0402_10V6K

1 C295
2

1 C265

0.1U_0402_10V6K

0.1U_0402_10V6K

1 C271
2

1 C309

0.1U_0402_10V6K

0.1U_0402_10V6K

1 C293
2

1 C268

0.1U_0402_10V6K

0.1U_0402_10V6K

DDRB_SDQ41
DDRB_SDQ47

DDRB_CLK2#
DDRB_CLK2

DDRB_SDQ48
DDRB_SDQ53
DDRB_SDM6
DDRB_SDQ51
DDRB_SDQ54
DDRB_SDQ62
DDRB_SDQ61
DDRB_SDM7
A

DDRB_SDQ59
DDRB_SDQ63
+3VS

SO-DIMM 2

REVERSE

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
3

Size
Date:

Compal Electronics, Inc.

DDR-SODIMM SLOT2

Document Number

LA-1841

Thursday, February 20, 2003

Sheet

13

Rev
0.1
of

57

Channel A(DIMM0) Termination resistors & Decoupling caps

+1.25VS

+1.25VS

4
3

1
2

DDRA_SDQ28
DDRA_SDQ19

1
2

RP80

DDRA_SDQ5
DDRA_SDQ4

1
2

4 DDRA_SCS#0
3 DDRA_SCS#1

DDRA_SDQ1
DDRA_SDQ0

56_0404_4P2R_5%
RP114
1
4
2
3

56_0404_4P2R_5%
RP68
4
1 DDRA_SDQ26
3
2 DDRA_SDQ31

56_0404_4P2R_5%
RP66
4
1 DDRA_SMA8
3
2 DDRA_SMA6

DDRA_SDQ6
DDRA_SDQS0

56_0404_4P2R_5%
RP115
1
4
2
3

56_0404_4P2R_5%
RP132
4
1 DDRA_SDQ53
3
2 DDRA_SDQ48

56_0404_4P2R_5%
RP67
4
1 DDRA_SMA12
3
2 DDRA_SMA11

DDRA_SCS#0
DDRA_SCS#1

8,12
8,12

DDRA_SDQ[0..63]

8,12 DDRA_SDQ[0..63]

DDRA_SMA[0..12]

8,12 DDRA_SMA[0..12]

DDRA_SDM[0..7]

8,12 DDRA_SDM[0..7]

4
3

+1.25VS

4
3

RP45

1
2

DDRB_SDQS3
DDRB_SDQ25

RP37

DDRB_SDQ2
DDRB_SDQ6

1
2

DDRB_SDQ0
DDRB_SDQ4

56_0404_4P2R_5%
RP52
1
4
2
3

56_0404_4P2R_5%
RP44
4
1 DDRB_SDQ30
3
2 DDRB_SDQ26

56_0404_4P2R_5%
RP38
4
1 DDRB_SMA10
3
2 DDRB_SBS0

DDRB_SDQ7
DDRB_SDQS0

56_0404_4P2R_5%
RP51
1
4
2
3

56_0404_4P2R_5%
RP24
4
1 DDRB_SDQ62
3
2 DDRB_SDQ59

56_0404_4P2R_5%
RP41
4
1 DDRB_SMA12
3
2 DDRB_SMA9

DDRB_SDM0
DDRB_SDQ1

56_0404_4P2R_5%
RP93
1
4
2
3

56_0404_4P2R_5%
RP30
4
1 DDRB_SDQ55
3
2 DDRB_SDQS6

56_0404_4P2R_5%
RP89
1
4 DDRB_SMA8
2
3 DDRB_SMA11

56_0404_4P2R_5%
RP25
4
1 DDRB_SDQ63
3
2 DDRB_SDQ61

D DRA_SDQS[0..7]

8,12 DDRA_SDQS[0..7]

RP92

4
3

1 DDRB_SCS#0
2 DDRB_SWE#

DDRB_SCS#0
DDRB_SWE#

9,13
9,13

DDRB_SBS0

DDRB_SDQ[0..63]

9,13 DDRB_SDQ[0..63]

D DRB_SDQS[0..7]

9,13 D DRB_SDQS[0..7]

56_0404_4P2R_5%
RP125
4
1 DDRA_SMA3
3
2 DDRA_SMA5

DDRA_SDQ13
DDRA_SDM1

56_0404_4P2R_5%
RP74
1
4
2
3

56_0404_4P2R_5%
RP78
4
1 DDRA_SDQ63
3
2 DDRA_SDQ58

56_0404_4P2R_5%
RP126
4
1 DDRA_SMA10
3
2 DDRA_SMA1

DDRB_SDQ3
DDRB_SDQ13

56_0404_4P2R_5%
RP94
1
4
2
3

DDRA_SDQ3
DDRA_SDQ9

56_0404_4P2R_5%
RP75
1
4
2
3

56_0404_4P2R_5%
RP135
4
1 DDRA_SDQS7
3
2 DDRA_SDQ61

56_0404_4P2R_5%
RP65
4
1 DDRA_SMA4
3
2 DDRA_SMA2

DDRB_SDQ15
DDRB_SDQ8

1
2

56_0404_4P2R_5%
RP96
4
3

4
3

56_0404_4P2R_5%
RP29
1 DDRB_SDQ60
2 DDRB_SDQ50

4
3

56_0404_4P2R_5%
RP91
1 DDRB_SMA6
2 DDRB_SMA4

DDRA_SDQ14
DDRA_SDQ11

1
2

56_0404_4P2R_5%
RP73
4
3

4
3

56_0404_4P2R_5%
RP133
1 DDRA_SDQ54
2 DDRA_SDQS6

4
3

56_0404_4P2R_5%
RP124
1 DDRA_SMA7
2 DDRA_SMA9

DDRB_SDQ9
DDRB_SDQ5

1
2

56_0404_4P2R_5%
RP50
4
3

4
3

56_0404_4P2R_5%
RP43
1 DDRB_SDQ14
2 DDRB_SDQ10

4
3

56_0404_4P2R_5%
RP40
1 DDRB_SMA5
2 DDRB_SMA7

DDRA_SDQ12
DDRA_SDQ2

1
2

56_0404_4P2R_5%
RP116
4
3

4
3

56_0404_4P2R_5%
RP62
1 DDRA_SDQ32
2 DDRA_SDQ33

4
3

56_0404_4P2R_5%
RP64
1 DDRA_SMA0
2 DDRA_SBS1

DDRA_SBS1

DDRB_SDQ11
DDRB_SDM1

1
2

56_0404_4P2R_5%
RP95
4
3

4
3

56_0404_4P2R_5%
RP35
1 DDRB_SDQ37
2 DDRB_SDQS4

4
3

56_0404_4P2R_5%
RP102
1 DDRB_SMA2
2 DDRB_SMA0

DDRA_SDQS1
DDRA_SDQ8

1
2

56_0404_4P2R_5%
RP117
4
3

4
3

56_0404_4P2R_5%
RP61
1 DDRA_SDM4
2 DDRA_SDQ38

4
3

56_0404_4P2R_5%
RP63
1 DDRA_SRAS#
2 DDRA_SCAS#

DDRA_SRAS#
DDRA_SCAS#

DDRB_SDQS1
DDRB_SDQ12

1
2

56_0404_4P2R_5%
RP49
4
3

4
3

56_0404_4P2R_5%
RP104
1 DDRB_SDM4
2 DDRB_SDQ39

4
3

56_0404_4P2R_5%
RP42
1 DDRB_CKE1
2 DDRB_CKE0

DDRB_CKE1
DDRB_CKE0

9,13
9,13

DDRA_SDQ15
DDRA_SDQ10

56_0404_4P2R_5%
RP118
1
4
2
3

56_0404_4P2R_5%
RP127
4
1 DDRA_SDQ37
3
2 DDRA_SDQ36

56_0404_4P2R_5%
RP81
1
4 DDRA_CKE0
2
3 DDRA_CKE1

DDRB_SDQ19
DDRB_SDQ16

56_0404_4P2R_5%
RP97
1
4
2
3

56_0404_4P2R_5%
RP36
4
1 DDRB_SDQ34
3
2 DDRB_SDQ33

56_0404_4P2R_5%
RP110
4
1 DDRB_SCAS#
3
2 DDRB_SCS#1

DDRB_SCAS#
DDRB_SCS#1

9,13
9,13

DDRA_SDQ16
DDRA_SDQ20

56_0404_4P2R_5%
RP119
1
4
2
3

56_0404_4P2R_5%
RP128
4
1 DDRA_SDQ34
3
2 DDRA_SDQS4

56_0404_4P2R_5%
RP137
1
4 DDRA_SBS0
2
3 DDRA_SWE#

56_0404_4P2R_5%
RP48
1
4
2
3

56_0404_4P2R_5%
RP105
4
1 DDRB_SDQ35
3
2 DDRB_SDQ46

56_0404_4P2R_5%
RP90
1
4 DDRB_SRAS#
2
3 DDRB_SBS1

DDRB_SRAS#
DDRB_SBS1

9,13
9,13

56_0404_4P2R_5%
RP59
4
1 DDRA_SDQ45
3
2 DDRA_SDM5

56_0404_4P2R_5%

DDRA_SDQ21
DDRA_SDQ17

56_0404_4P2R_5%
RP72
1
4
2
3

DDRB_SDQ29
DDRB_SDM3

56_0404_4P2R_5%
RP100
1
4
2
3

56_0404_4P2R_5%
RP106
4
1 DDRB_SDQ45
3
2 DDRB_SDM5

DDRA_SDQ18
DDRA_SDQS2

56_0404_4P2R_5%
RP120
1
4
2
3

56_0404_4P2R_5%
RP60
4
1 DDRA_SDQ39
3
2 DDRA_SDQ40

1 C621

DDRB_SDQ22
DDRB_SDQS2

56_0404_4P2R_5%
RP47
1
4
2
3

56_0404_4P2R_5%
RP108
4
1 DDRB_SDQ48
3
2 DDRB_SDQ53

DDRA_SDM2
DDRA_SDQ22

56_0404_4P2R_5%
RP71
1
4
2
3

56_0404_4P2R_5%
RP58
4
1 DDRA_SDQ42
3
2 DDRA_SDQ47

DDRB_SDQ24
DDRB_SDQ17

56_0404_4P2R_5%
RP46
1
4
2
3

56_0404_4P2R_5%
RP34
4
1 DDRB_SDQ40
3
2 DDRB_SDQ38

DDRA_SDQ23
DDRA_SDQ24

1
2

DDRB_SDQ23
DDRB_SDQ28

1
2

DDRA_SDQ25
DDRA_SDM3

56_0404_4P2R_5%
RP69
1
4
2
3

56_0404_4P2R_5%
RP57
4
1 DDRA_SDQ49
3
2 DDRA_SDQ52

DDRB_SDM2
DDRB_SDQ18

56_0404_4P2R_5%
RP98
1
4
2
3

56_0404_4P2R_5%
RP33
4
1 DDRB_SDQS5
3
2 DDRB_SDQ44

DDRA_SDQS5
DDRA_SDQ41

56_0404_4P2R_5%
RP130
1
4
2
3

56_0404_4P2R_5%
RP122
4
1 DDRA_SDQS3
3
2 DDRA_SDQ29

DDRB_SDM6
DDRB_SDQ51

56_0404_4P2R_5%
RP109
1
4
2
3

56_0404_4P2R_5%
RP103
4
1 DDRB_SDQ32
3
2 DDRB_SDQ36

DDRA_SDM6
DDRA_SDQ51

1
2

56_0404_4P2R_5%
RP56
4
3

4
3

56_0404_4P2R_5%
RP123
1 DDRA_SDQ27
2 DDRA_SDQ30

DDRA_SDQ46
DDRA_SDQ43

1
2

56_0404_4P2R_5%
RP131
4
3

4
3

56_0404_4P2R_5%
RP136
1 DDRA_SDQ59
2 DDRA_SDQ62

2
0.1U_0402_10V6K
+1.25VS

DDRA_SDQ50
DDRA_SDQ56

1
2

56_0404_4P2R_5%
RP55
4
3

4
3

56_0404_4P2R_5%
RP134
1 DDRA_SDQ60
2 DDRA_SDQ55

56_0404_4P2R_5%
RP70
4
3

56_0404_4P2R_5%

4
3

56_0404_4P2R_5%
RP129
1 DDRA_SDQ44
2 DDRA_SDQ35

56_0404_4P2R_5%

DDRA_SBS0
DDRA_SWE#

+1.25VS
0.1U_0402_10V6K
1 C630

2
0.1U_0402_10V6K
+1.25VS

1 C631

8,12
8,12

8,12
8,12

DDRB_SDQ21
DDRB_SDQ20

8,12
8,12

0.1U_0402_10V6K
1 C629

2
0.1U_0402_10V6K

0.1U_0402_10V6K
1
1
C634
C622
2
0.1U_0402_10V6K
+1.25VS
1

C626

1 C632

0.1U_0402_10V6K
1 C633

2
0.1U_0402_10V6K

2
0.1U_0402_10V6K
+1.25VS
1

C323

C628

C320

C321

0.1U_0402_10V6K
1
C328
2

4.7U_1206_16V6K
1
C619
C618

2
4.7U_1206_16V6K

0.1U_0402_10V6K
1
C318

2
0.1U_0402_10V6K

2
0.1U_0402_10V6K

0.1U_0402_10V6K
1
C325
C324
2

0.1U_0402_10V6K
1
1
C624
C625

2
0.1U_0402_10V6K

0.1U_0402_10V6K
1
C316

2
0.1U_0402_10V6K

0.1U_0402_10V6K
1
C322

2
0.1U_0402_10V6K

2
0.1U_0402_10V6K

0.1U_0402_10V6K
1
C326
C329
2

0.1U_0402_10V6K
1
1
C327
C564

2
0.1U_0402_10V6K

0.1U_0402_10V6K
1
C627

Decoupling Reference Document:

Springdale Customer Schematic R1.2 page22
each Channel(two DIMMs) requirement4.7u*2;0.1uF*28
5

DDRA_CKE0
DDRA_CKE1

DDRA_SDM0
DDRA_SDQ7

56_0404_4P2R_5%
RP79
4
1 DDRA_SDQ57
3
2 DDRA_SDM7

8,12

C319

56_0404_4P2R_5%
RP107
1 DDRB_SDQ41
2 DDRB_SDQ47

4
3

4
3

56_0404_4P2R_5%
RP101
1 DDRB_SDQ27
2 DDRB_SDQ31

56_0404_4P2R_5%
RP26
1
2

4
3

4
3

56_0404_4P2R_5%
RP28
1 DDRB_SDQS7
2 DDRB_SDQ56

56_0404_4P2R_5%
RP31
1
2

4
3

4
3

56_0404_4P2R_5%
RP27
1 DDRB_SDQ57
2 DDRB_SDQ58

DDRB_SDM7
DDRB_SDQ54

DDRB_SDQ49
DDRB_SDQ52

4
3

56_0404_4P2R_5%
RP32
1
2

DDRB_SDQ42
DDRB_SDQ43

0.1U_0402_10V6K
1
C317

2
0.1U_0402_10V6K

56_0404_4P2R_5%
RP99
4
3

56_0404_4P2R_5%

9,13

56_0404_4P2R_5%
RP76
1
4
2
3

4
3

RP121

Channel B(DIMM1) Termination resistors & Decoupling caps

+1.25VS

RP77

DDRB_SMA[0..12]

9,13 DDRB_SMA[0..12]

DDRB_SDM[0..7]

9,13 DDRB_SDM[0..7]

56_0404_4P2R_5%
RP39
4
1 DDRB_SMA1
3
2 DDRB_SMA3

56_0404_4P2R_5%
+1.25VS
1 C284

1 C283

2
0.1U_0402_10V6K
+1.25VS
1

2
2
0.1U_0402_10V6K

C277

2
2
0.1U_0402_10V6K

C563

2
0.1U_0402_10V6K
+1.25VS
1

C570

C623

2
2
0.1U_0402_10V6K

2
0.1U_0402_10V6K

0.1U_0402_10V6K
1 C280

C566

0.1U_0402_10V6K
1
C571

2
4.7U_1206_16V6K

2
0.1U_0402_10V6K

2
0.1U_0402_10V6K

0.1U_0402_10V6K
1
1
C272
C562

0.1U_0402_10V6K
1
C567

2
0.1U_0402_10V6K

C573

0.1U_0402_10V6K
1 C279
1 C278

0.1U_0402_10V6K
1
1
C274
C273

2
0.1U_0402_10V6K

0.1U_0402_10V6K
1
C565

4.7U_1206_16V6K
1
C572

1 C281

2
0.1U_0402_10V6K

0.1U_0402_10V6K
1
1
C276
C275

2
0.1U_0402_10V6K
+1.25VS
1

0.1U_0402_10V6K
1 C282

0.1U_0402_10V6K
1
C569

C568

2
0.1U_0402_10V6K

C259

0.1U_0402_10V6K
1
C258

2
0.1U_0402_10V6K

Decoupling Reference Document:

Springdale Customer Schematic R1.2 page26
each Channel(two DIMMs) requirement4.7u*2;0.1uF*26

56_0404_4P2R_5%
Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

Size
B

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.

Date:

DDR Termination Resistors

Document Number

Rev
0.1

LA-1841
Thursday, February 20, 2003

Sheet
1

14

of

57

SEL0 SEL1 CPU

3V66[0..3]

REF0

REF1 SRC

USB/Dot
+3VS

100

66

14.3

14.3

100/200

MID

REF

REF

REF

REF

REF

200

66

14.3

14.3

100/200

Place near each pin

W>40 mil

+3VS_CLK

48
L29
1
2
BLM21A601SPT_0805
L28
1
2
BLM21A601SPT_0805

REF
48

133

66

14.3

14.3

100/200

48

166

66

14.3

14.3

100/200

48

MID

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Trace wide=40 mils

1
2

1
C591
10U_1206_6.3V7K

C583
0.1U_0402_10V6K

Hi-Z

U42
CLKREF1
CLKREF0

C602
@10P_0402_50V8K
2
1
1

CLK_XTAL_IN

C603
@10P_0402_50V8K
2
1

2
2
2

1 @0_0402_5%
1 @0_0402_5%
1 @0_0402_5%

R463
R412
R411

+3VS

+3VS
+3VS

@0_0402_5%

CLKSEL0

R186

0_0402_5%

CPU_CLKSEL0

CLKSEL1

R188

0_0402_5%

CPU_CLKSEL1

R189

@0_0402_5%

CPU_CLKC2

CLKSEL0
CLKSEL1

2 1K_0402_5%
2 1K_0402_5%
2 1K_0402_5%

SLP_S1#
STPPCI#
STPCPU#

51
56

21
49
50

SEL0
SEL1

CPUCLKC1

PWRDWN#
PCI_STP#
CPU_STP#

CLK_VTT_PG#

35

CK_SCLK
CK_SDATA

28
30

38

2
R438

1
CLK48M_OUT0
33_0402_5%

31
32

1
R437

C h e c k SPEC (250mA,300 ohm)

+3VS

L27
BLM11A601S_0603
1
2

2
475_0603_1%

52

CPUCLKT0

SCLK
SDATA

CPUCLKC0

48/66MHZ_OUT/3V66_4

SRCLKN_100MHZ

66MHZ_OUT2/3V66_2
66MHZ_OUT1/3V66_1
66MHZ_OUT0/3V66_0

SRCLKP_100MHZ

PCICLK_F2
PCICLK_F1

USB_48MHZ

PCICLK_F0

DOT_48MHZ

PCICLK6
PCICLK5

IREF

PCICLK4
PCICLK3

CLK_VDD_PLL
1
2

C578
10U_1206_6.3V7K

55
1
2

VDD_PLL

PCICLK2
PCICLK1

C579
0.1U_0402_16V4Z

54

1
2

VSS_PLL

6
11
17
25
33

C597
0.1U_0402_10V6K

C596
0.1U_0402_10V6K

C594
0.1U_0402_10V6K

C580

0.1U_0402_10V6K

45
47

CLK_CPU2

46

CLK_CPU2#

44

CLK_CPU1

1
R428

43

CLK_CPU1#

41

CLK_CPU0

PCICLK0

2
33_0402_5%
1
49.9_0402_1%

CLK_HCLK

CLK_HCLK

1
R429
1
R430

1
49.9_0402_1%
2
33_0402_5%
2
33_0402_5%
1
49.9_0402_1%

2
R414

1
R431
1
R432

1
49.9_0402_1%
2
33_0402_5%
2
33_0402_5%
1
49.9_0402_1%

2
R416

2
R418

CLK_HCLK#

CLK_HCLK#

CLK_ITP

CLK_ITP

CLK_ITP#

CLK_ITP#

CLK_BCLK
2
R417

CLK_BCLK

1
R433

CLK66M_OUT3

1
R457

2
33_0402_5%

CLK_AGP_66M

16

23

CLK66M_OUT1

PCICLK_F2

2
33_0402_5%
2
33_0402_5%
2
33_0402_5%

10

CLK66M_OUT0

1
R456
1
R455
1
R452

CLK_MCH_66M

22

1
R461
1
R460
1
R454
1
R459
1
R458
1
R453

2
33_0402_5%
2
33_0402_5%
2
33_0402_5%
2
33_0402_5%
2
33_0402_5%
2
33_0402_5%

CLK_PCI_MINI

27
26

Place near CK409

CLK_CPU0#

29

2
R415

1
49.9_0402_1%
2
33_0402_5%

40

2
R413

CLK_BCLK#

CLK_BCLK#

CLK_ICH_66M

23

CLK_PCI_ICH

23

20

PCICLK6

19

PCICLK5

18

PCICLK4

15

PCICLK3

14

PCICLK2

13

PCICLK1

12

29

CLK_PCI_PCM

27

CLK_PCI_LPC

39

CLK_PCI_1394

30

CLK_PCI_LAN

26

CLK_PCI_SIO

36

ICS952623BG_TSSOP56

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
4

0.1U_0402_10V6K

4.7U_0805_6.3V6K

Title

C595

C592

VTT_PWRGD#

VSS_SRC
VSS_IREF

7
7

0.1U_0402_10V6K

CK409

39
53

MCH_CLKSEL0
MCH_CLKSEL1

2
1
2

XTAL_OUT

66MHZ_OUT3/3V66_3

R190
2.49K_0603_1%

2.49K_0603_1%

CPUCLKT1

1Q40
MMBT3904_SOT23
3 12,13,23 ICH_SMB_CLK
12,13,23 ICH_SMB_DATA

24 CLK_ICH_48M

R185

CLK_XTAL_OUT

37

R443
2K_0603_1%

2K_0603_1%

CPUCLKT2

VSS_REF
VSS_PCI
VSS_PCI
VSS_3V66
VSS_48

2
R420

2
62_0402_5%

R187

2
1

220_0402_5%

R444
1K_0603_1%

1K_0603_1%

2
10K_0402_5%

1
1
1

VSS_CPU

XTAL_IN

1
R421

1
R422
1
R439

+CPU_CORE

14.31818MHz_20P_1BX14318CC1A~L

Place crystal within

500 mils of CK409

SLP_S1#
STPPCI#
STPCPU#

REF_0
REF_1

R462
R425
R424

C581

X3

1
2

0.1U_0402_10V6K

1
33_0402_5%

C582

42
48

VDD_CPU
VDD_CPU

R451

1
33_0402_5%
34
36

36 CLK_14M_SIO

VDD_48
VDD_SRC

R450

VDD_REF
VDD_PCI
VDD_PCI
VDD_3V66

24 CLK_ICH_14M

3
10
16
24

24 PM_SLP_S1#
24 STP_PCI#
24,53 STP_CPU#

Size
Date:

Compal Electronics, Inc.

Clock Generator
Document Number

LA-1841

Thursday, February 20, 2003

Rev
0.1
Sheet
1

15

of

57

I2CC_SDA

ALERT#

SCLK

THERM#

SDATA

GND

NV_THERCTL#

5
@0.1U_0402_16V4Z

AGP_AD[0..31]

10 AGP_AD[0..31]

AGP_SBA[0..7]

10 AGP_SBA[0..7]

AGP_C/BE#[0..3]

10 AGP_C/BE#[0..3]

AGP_ST[0..2]
C16
1

+3VS

@10P_0402_50V8K
R35
10K_0402_5%
STP_AGP#
1
2
1
2
AGP_BUSY#
R36
10K_0402_5%

L10
1
2
FCM2012C-800_0805

4.7U_0805_10V4Z
C31

C30

0.1U_0402_10V6K

10
10
10
10

C478

0.1U_0402_10V6K
4.7U_0805_10V4Z

1
R67
1
R69

2
220K_0402_5%
2
220K_0402_5%

@10_0402_5%

15 CLK_AGP_66M
23,35 B_PCIRST#
10
AGP_REQ#
10
AGP_GNT#
10
AGP_PAR
10
AGP_STOP#
10 AGP_DEVSEL#
10
AGP_TRDY#
10
AGP_IRDY#
10 AGP_FRAME#
23,27,30 PCI_PIRQA#

+3VS

+SVDD

R68

AGP_WBF#
AGP_RBF#
AGP_DBIHI
AGP_DBILO

10 AGP_SB_STBF
10 AGP_SB_STBS
10 AGP_AD_STBF0
10 AGP_AD_STBS0
10 AGP_AD_STBF1
10 AGP_AD_STBS1

AGP_AD_STBS0
AGP_AD_STBS1

S e l e c tion Table For W180

SST
Ratio

C l o se VGA ball (AK29)

l e ss than 250mils

SS%
0
1

+AGP_VREF

1.25%
3.75%

R42

C13
0.1U_0402_10V6K

22
22
22

1
R70

VDD

P L A CE COLSE TO VGA
P in AJ5, AJ7,

FS1

X2

FS2

SS%

1
R323

2 XTALSSIN
22_0402_5%

R343

4SPREAD_RATE
R345

W180-01GT_SO8

1
2
R341
@1K_0402_5%

AG12
AF15
AF13
AE15
AK18
AH17
AJ16
AJ17
AG16
AK16
AG15
AE10

AGP_WBF#
AGP_RBF#

AK13
AJ13
AK24
AJ25
AG21
AF21

AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
AGP_ST0
AGP_ST1
AGP_ST2

AJ11
AH11
AJ12
AH12
AJ14
AH14
AJ15
AH15
AG13
AE16
AE13

+AGP_REF
1 10K_0402_5%
AGP_BUSY#
STP_AGP#

AK29
AF16
AF12
AG11

CRMA
LUMA
COMPS
DACB_HSYNC
DACB_VSYNC
DACB_RSET
2
63.4_0603_1%

+SVDD

AJ6
AH6

XTALSSIN
XTALOUTBUFF
NV_THERMDA
NV_THERMDC

AJ7
AJ5
H2
H3
C2
C1
D1
E2
D2

10K_0402_5%

AE2
AD2
AD1
AF3
AE3
AD3
AE7
AF6
AD4
Y5
AC4

XTALIN
XTALOUT

PROPRIETARY NOTE

AG17
AG14
AJ18
AJ19

AGP_SB_STBF
AGP_SB_STBS
AGP_AD_STBF0
AGP_AD_STBS0
AGP_AD_STBF1
AGP_AD_STBS1

1
10K_0402_5%

SWAPRDY_B
N V31,NV34 use.
N V18 not use.

CLKOUT

+3VS

CLK_AGP_66M
B_PCIRST#
AGP_REQ#
AGP_GNT#
AGP_PAR
AGP_STOP#
AGP_DEVSEL#
AGP_TRDY#
AGP_IRDY#
AGP_FRAME#
PCI_PIRQA#

1
2
R317
1K_0402_5%

X1/CLK

GND

XTALOUTBUFF
+3VS R318
1K_0402_5%
1
2

CRMA
LUMA
COMPS

+SVDD
U31

AJ24
AH19
AF25
AG22

C/BE#0
C/BE#1
C/BE#2
C/BE#3
PCICLK
PCIRST#
PCIREQ#
PCIGNT#
PCIPAR
PCISTOP#
PCIDEVSEL#
PCITRDY#
PCIIRDY#
PCIFRAME#
PCIINTA#
NC

AGP4X/8X

AGPWBF#
AGPRBF#
AGPPIPE/ DBI_HI
NC/ DBI_LO

AGPSB_STB/ ADSTBF
AGPSB_STB#/ ADSTBS
AGPADSTB0/ ADSTBF0
AGPADSTB0#/ADSTBS0
AGPADSTB1/ ADSTBF1
AGPADSTB1#/ADSTBS1

ROMA14
ROMA15
ROMCS#
VIPPCLK
VIPHCTL
VIPHCLK
VIPHAD0
VIPHAD1
VIPD0
VIPD1
VIPD2
VIPD3
VIPD4
VIPD5
VIPD6
VIPD7
DVOD0
DVOD1
DVOD2
DVOD3
DVOD4
DVOD5
DVOD6
DVOD7
DVOD8
DVOD9
DVOD10
DVOD11

DVOHSYNC
DVOVSYNC
DVODE
DVOCLKOUT
DVOCLKOUT#
I2CC_SCL
I2CC_SDA
BUFRST#
DVOCLKIN
STRAP0
STRAP1
STRAP2
STRAP3

AGPSBA0
AGPSBA1
AGPSBA2
AGPSBA3
AGPSBA4
AGPSBA5
AGPSBA6
AGPSBA7
AGPST0
AGPST1
AGPST2

Modulation
Setting

AGP_C/BE#0
AGP_C/BE#1
AGP_C/BE#2
AGP_C/BE#3

PCI/AGP

FPBCLKOUT#
FPBCLKOUT

G5
F4
G4
H5
H4
J4
J5
J6
K4
K6

AGPVREF
NC/AGPMBDET#
AGP_BUSY#
STP_AGP#

DACB_RED/CHROMA
DACB_GREEN/LUMA
DACB_BLUE/COMPOSITE
DACB_HSYNC
DACB_VSYNC
DACB_RSET
I2CB_SCL
I2CB_SDA
SWAPRDY_B
STEREO
DACB_IDUMP
XTALIN
XTALOUT

XTALSSIN
XTALOUTBUFF
THERMDA
THERMDC
JTAG[0]
JTAG[1]
JTAG[2]
JTAG[3]
JTAG[4]
NV34M_EPBGA701

ENBKL
ENVDD

2
R132

VGA_GPIO5
R374
VAG_GPIO6
R129
POWER_SEL
NV_THERCTL#

SPREAD_RATE

1
0_0402_5%
ENBKL
ENVDD

22,39
22
1 @0_0402_5%
1 10K_0402_5%

2
2

R133

IFPATXDO#
IFPATXDO
IFPATXD1#
IFPATXD1
IFPATXD2#
IFPATXD2
IFPATXD3#
IFPATXD3
IFPATXC#
IFPATXC
IFPBTXD4#
IFPBTXD4
IFPBTXD5#
IFPBTXD5
IFPBTXD6#
IFPBTXD6
IFPBTXD7#
IFPBTXD7
IFPBTXC#
IFPBTXC

DACA_RED
DACA_GREEN
DACA_BLUE
DACA_HSYNC
DACA_VSYNC
DACA_RSET
I2CA_SCL
I2CA_SDA
SWAPRDY_A
DACA_IDUMP
IFPCTXD0#
IFPCTXD0
IFPCTXD1#
IFPCTXD1
IFPCTXD2#
IFPCTXD2
IFPCTXC#
IFPCTXC

(SUS_STAT#) +3VS

1 10K_0402_5%

POWER_SEL

R2
R1
AF2
L4
M4
M5

ROMA14
ROMA15

VIPHCTL

P3
P2
J3
J2
K2
K1
L3
L2
N2
N1
AG2
AH1
AG3
AJ1
AH2
AK1
AJ3
AK3
AH4
AK4
AJ4
AH5
AD5
AD6
AE4
AJ2
AK2
AG6
AG7
B1
AG1
G1
G2
F2
F3

T4
U4
AA1
Y2
W3
V3
V4
U5
V1
W2
V5
W4
AB2
AB3
W6
Y6
AC2
AC3
Y3
AA2

AG5
AF7
AF9
AG10
T2
R3
T3
U2
V2
U3
P4
P5

R377

SUB_VENDOR: 0-SYSTEM BIOS 1-ADAPTER BIOS

RAM_CFG[3:0]
(1001 = 4Mx32 DDR, DQS per byte)

NV18M

R376

R378
R334

2
2

10K_0402_5%

1 10K_0402_5%

STRAP1

@10K_0402_5%

STRAP2

R379

1 @10K_0402_5%

@10K_0402_5%

DVOD2

R335

1 10K_0402_5%

@10K_0402_5%

STRAP3

R381

1 @10K_0402_5%

10K_0402_5%

DVOD3

R330

1 @10K_0402_5%

NV31M:NV34M

R380

NV18M
R329

2
2

NV31M:NV34M

5
2

R49

10K_0402_5%

DACA_VSYNC

R29

1 @10K_0402_5%

R50

@10K_0402_5% DACA_HSYNC

R30

1 10K_0402_5%

CRYSTAL: (10)-27MHz

Low

R373

High

DVOD2
DVOD3
High
DVOD8
DVOD9

DVO_HSYNC

Low

STRAP0
STRAP1
STRAP2
STRAP3
TXOUT0TXOUT0+
TXOUT1TXOUT1+
TXOUT2TXOUT2+
TXOUT3TXOUT3+
TXCLKTXCLK+
TZOUT0TZOUT0+
TZOUT1TZOUT1+
TZOUT2TZOUT2+
TZOUT3TZOUT3+
TZCLKTZCLK+

DACA_RSET 1
R39
DDC_CLK
DDC_DATA
2
R41

10K_0402_5%

VIPD2
VIPD6

R357

1 10K_0402_5%

R340

1 10K_0402_5%

R361

1 @10K_0402_5%

R320

1 @10K_0402_5%

TVMODE: (01)-NTSC
DACB_VSYNC

0
1

R339

AGP8X/4X: (0)-8X / (1)-4X

AGP_SIDEBAND: (0)-ENABLE

10K_0402_5%

DACB_HSYNC

High

I2CC_SCL
I2CC_SDA

AK10
R
AJ10
G
B
AJ9
AH9 DACA_HSYNC
AJ8 DACA_VSYNC
AG8

STRAP0

Low
VIPD2
VIPD3
VIPD4
VIPD5
VIPD6
VIPD7

+3VS

PCI_AD_SWAP: 0-RVSERSED 1-NORMAL

R48

R360

10K_0402_5%

DVOD9

@10K_0402_5%

VIPD7

10 AGP_FASTWRITE: (0)-ENABLE
TXOUT0TXOUT0+
TXOUT1TXOUT1+
TXOUT2TXOUT2+
TXOUT3TXOUT3+
TXCLKTXCLK+
TZOUT0TZOUT0+
TZOUT1TZOUT1+
TZOUT2TZOUT2+
TZOUT3TZOUT3+
TZCLKTZCLK+

R319

22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22

@10K_0402_5%

11 PCI_DEVID[3:0]
Low

High

DVOD8

0110 NV18M

R366

10K_0402_5%

VIPD4

R367

1 @10K_0402_5%

R363

@10K_0402_5%

VIPD5

R364

1 10K_0402_5%

R370

@10K_0402_5%

VIPD3

R371

1 10K_0402_5%

R346

10K_0402_5%

DVO_HSYNC

R347

1 @10K_0402_5%

VIPHCTL

R126

1 10K_0402_5%

12 BUS_TYPE: (1)-AGP

ROM TYPE: (00)-PARALLEL

Low

R354

10K_0402_5%

ROMA14

R355

1 @10K_0402_5%

High

R351

10K_0402_5%

ROMA15

R352

1 @10K_0402_5%

R
22
G
22
B
22
DACA_HSYNC
22
DACA_VSYNC
22
2
63.4_0603_1%

XTALIN

DDC_CLK
22
DDC_DATA
22
1
+3VS
@10K_0402_5%

Y2

XTALOUT

1 C468

SWAPRDY_A
N V31,NV34 use.
N V18 not use.

Title

27MHZ_16PF
1
2
R311
@2M_0402_5%

T H I S S H E E T OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
Size
T R A D E S E C RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
U S E D B Y OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
3

51

+3VS

M2
M3

10 AGP_ST[0..2]

C479

C148

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9

VGA_GPIO0

VDD1

D-

nVIDIA
NV31/34
ZV PORT / EXT TMDS / GPIO / ROM

I2CC_SCL

D+

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

LVDS

AJ28
AK28
AH27
AK27
AJ27
AH26
AJ26
AH25
AH23
AJ23
AH22
AJ22
AJ21
AK21
AH20
AJ20
AG26
AE24
AG25
AG24
AF24
AG23
AE22
AF22
AE21
AG20
AG19
AF19
AE19
AF18
AG18
AE18

DAC1

NV_THERMDC

@ADM1032ARM_RM8

+3VS

U33
2

TMDS

@2.2K_0402_5%
2

@2.2K_0402_5%

@2200P_0402_50V7K
1
C145
NV_THERMDA
D

R124

DAC2

R128

AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31

SSC
CLK

Place close
to pin
H2 & H3

U35A

+3VS
1

+3VS

1 C469

22P_0402_50V8J

22P_0402_50V8J
A

Compal Electronics, Inc.

nVIDIA NV31M (AGP BUS)

Document Number

Rev
0.1

LA-1841
Thursday, February 20, 2003

Sheet

16

of

57

R_NDQMA[0..7]

21 R_NDQMB[0..7]

R_NDQMB[0..7]

R_NDQSA[0..7]

21 R_NDQSB[0..7]

R_NDQSB[0..7]

20 R_NMDA[0..63]

R_NMDA[0..63]

21

NMAB[0..11]

NMAB[0..11]

R_NMDB[0..63]

21 R_NMDB[0..63]

U35C

U35B

FBAWE#
FBACS0#
FBACS1#
FBACKE
FBACLK0
FBACLK0#
FBACLK1
FBACLK1#

R_NDQSA0
R_NDQSA1
R_NDQSA2
R_NDQSA3
R_NDQSA4
R_NDQSA5
R_NDQSA6
R_NDQSA7

P28

NMRASA#

P29

NMCASA#

NMCASA#

20

R28

NMWEA#

NMWEA#

20

U27

NMCSA0#

NMCSA0#

20

P27

NMRASA#

N30

NMCKEA

U21
V21

NMCLKA0
NMCLKA0#

N21
P21

NMCLKA1
NMCLKA1#

R26
R29

NMA_BA0
NMA_BA1

NMCKEA

20

FB_VREF

C28

NMCLKA0

A_REF

NMA_BA0
NMA_BA1

20
20

(10 mil)

20

R89
@120_0402_5%

20

NMCLKA0#

NMCLKA1
R105
@120_0402_5%

20

20

NMCLKA1#

FBABA0
FBABA1

R_NMDB0
R_NMDB1
R_NMDB2
R_NMDB3
R_NMDB4
R_NMDB5
R_NMDB6
R_NMDB7
R_NMDB8
R_NMDB9
R_NMDB10
R_NMDB11
R_NMDB12
R_NMDB13
R_NMDB14
R_NMDB15
R_NMDB16
R_NMDB17
R_NMDB18
R_NMDB19
R_NMDB20
R_NMDB21
R_NMDB22
R_NMDB23
R_NMDB24
R_NMDB25
R_NMDB26
R_NMDB27
R_NMDB28
R_NMDB29
R_NMDB30
R_NMDB31
R_NMDB32
R_NMDB33
R_NMDB34
R_NMDB35
R_NMDB36
R_NMDB37
R_NMDB38
R_NMDB39
R_NMDB40
R_NMDB41
R_NMDB42
R_NMDB43
R_NMDB44
R_NMDB45
R_NMDB46
R_NMDB47
R_NMDB48
R_NMDB49
R_NMDB50
R_NMDB51
R_NMDB52
R_NMDB53
R_NMDB54
R_NMDB55
R_NMDB56
R_NMDB57
R_NMDB58
R_NMDB59
R_NMDB60
R_NMDB61
R_NMDB62
R_NMDB63

F13
D13
E13
F12
E10
D10
D9
D8
B13
B12
C12
B11
B9
C9
B8
A7
F10
E9
F9
F7
C6
E6
D5
C4
C8
B7
B6
B5
A3
B3
A2
B2
B29
A29
B28
A28
B26
B25
B24
C23
E26
D26
E25
C25
E24
F22
E22
F21
A24
B23
C22
B22
B20
C19
B19
B18
D23
D22
D21
E21
F19
E18
D18
F18

FBCD0
FBCD1
FBCD2
FBCD3
FBCD4
FBCD5
FBCD6
FBCD7
FBCD8
FBCD9
FBCD10
FBCD11
FBCD12
FBCD13
FBCD14
FBCD15
FBCD16
FBCD17
FBCD18
FBCD19
FBCD20
FBCD21
FBCD22
FBCD23
FBCD24
FBCD25
FBCD26
FBCD27
FBCD28
FBCD29
FBCD30
FBCD31
FBCD32
FBCD33
FBCD34
FBCD35
FBCD36
FBCD37
FBCD38
FBCD39
FBCD40
FBCD41
FBCD42
FBCD43
FBCD44
FBCD45
FBCD46
FBCD47
FBCD48
FBCD49
FBCD50
FBCD51
FBCD52
FBCD53
FBCD54
FBCD55
FBCD56
FBCD57
FBCD58
FBCD59
FBCD60
FBCD61
FBCD62
FBCD63

FBCA0
FBCA1
FBCA2
FBCA3
FBCA4
FBCA5
FBCA6
FBCA7
FBCA8
FBCA9
FBCA10
FBCA11
FBCA12

M27
K30
G27
D30
AG30
AD26
AA29
W27

FBACAS#

R_NDQMA0
R_NDQMA1
R_NDQMA2
R_NDQMA3
R_NDQMA4
R_NDQMA5
R_NDQMA6
R_NDQMA7

FBARAS#

L27
K29
G25
E28
AF28
AD27
AA30
Y27

FBADQS0
FBADQS1
FBADQS2
FBADQS3
FBADQS4
FBADQS5
FBADQS6
FBADQS7

NMAA0
NMAA1
NMAA2
NMAA3
NMAA4
NMAA5
NMAA6
NMAA7
NMAA8
NMAA9
NMAA10
NMAA11

FBADQM0
FBADQM1
FBADQM2
FBADQM3
FBADQM4
FBADQM5
FBADQM6
FBADQM7

V30
U28
U29
T28
T29
T27
T30
T26
T25
R27
R25
R30
U24

20

+2.5VS

R138

1K_0402_1%

FBCDQM0
FBCDQM1
FBCDQM2
FBCDQM3
FBCDQM4
FBCDQM5
FBCDQM6
FBCDQM7
FBCDQS0
FBCDQS1
FBCDQS2
FBCDQS3
FBCDQS4
FBCDQS5
FBCDQS6
FBCDQS7

FBCRAS#
FBCCAS#
FBCWE#
FBCCS0#
FBCCS1#
FBCCKE
FBCCLK0
FBCCLK0#
FBCCLK1
FBCCLK1#

FBCBA0
FBCBA1

A18
C17
B17
C16
B16
D16
A16
E16
F16
D15
F15
A15
G17

NMAB0
NMAB1
NMAB2
NMAB3
NMAB4
NMAB5
NMAB6
NMAB7
NMAB8
NMAB9
NMAB10
NMAB11

D11
B10
D7
C5
C26
F24
B21
D20

R_NDQMB0
R_NDQMB1
R_NDQMB2
R_NDQMB3
R_NDQMB4
R_NDQMB5
R_NDQMB6
R_NDQMB7

D12
A10
E7
A4
A27
D24
A21
D19

R_NDQSB0
R_NDQSB1
R_NDQSB2
R_NDQSB3
R_NDQSB4
R_NDQSB5
R_NDQSB6
R_NDQSB7

C14

NMRASB#

B14

NMCASB#

C15
D17

NMRASB#

21

NMCASB#

21

NMWEB#

NMWEB#

21

NMCSB0#

NMCSB0#

21

A13

NMCKEB

NMCKEB

21

K18
K17

NMCLKB0
NMCLKB0#

K13
K14

NMCLKB1
NMCLKB1#

D14

E15
B15

NMCLKB0
R111
@120_0402_5%

NMB_BA0
NMB_BA1

21

NMCLKB0#
NMCLKB1

21
21

R110
@120_0402_5%
NMB_BA0
NMB_BA1

21
21

NMCLKB1#

21

NV34M_EPBGA701

C173

R135

0.1U_0402_10V6K

1K_0402_1%
2

NV34M_EPBGA701

FBAA0
FBAA1
FBAA2
FBAA3
FBAA4
FBAA5
FBAA6
FBAA7
FBAA8
FBAA9
FBAA10
FBAA11
FBAA12

FBAD0
FBAD1
FBAD2
FBAD3
FBAD4
FBAD5
FBAD6
FBAD7
FBAD8
FBAD9
FBAD10
FBAD11
FBAD12
FBAD13
FBAD14
FBAD15
FBAD16
FBAD17
FBAD18
FBAD19
FBAD20
FBAD21
FBAD22
FBAD23
FBAD24
FBAD25
FBAD26
FBAD27
FBAD28
FBAD29
FBAD30
FBAD31
FBAD32
FBAD33
FBAD34
FBAD35
FBAD36
FBAD37
FBAD38
FBAD39
FBAD40
FBAD41
FBAD42
FBAD43
FBAD44
FBAD45
FBAD46
FBAD47
FBAD48
FBAD49
FBAD50
FBAD51
FBAD52
FBAD53
FBAD54
FBAD55
FBAD56
FBAD57
FBAD58
FBAD59
FBAD60
FBAD61
FBAD62
FBAD63

N25
N27
N26
M25
K26
K27
J27
H27
N29
M29
M28
L29
J29
J28
H29
G30
K25
J26
J25
G26
F28
F26
E27
D27
H28
G29
F29
E29
C30
C29
B30
A30
AJ29
AJ30
AH29
AH30
AF29
AE29
AD29
AC28
AG28
AF27
AE26
AE28
AD25
AB25
AB26
AA25
AD30
AC29
AB28
AB29
Y29
W28
W29
V29
AC27
AB27
AA27
AA26
W25
V26
V27
V25

MEMORY
INTERFACE A

R_NMDA0
R_NMDA1
R_NMDA2
R_NMDA3
R_NMDA4
R_NMDA5
R_NMDA6
R_NMDA7
R_NMDA8
R_NMDA9
R_NMDA10
R_NMDA11
R_NMDA12
R_NMDA13
R_NMDA14
R_NMDA15
R_NMDA16
R_NMDA17
R_NMDA18
R_NMDA19
R_NMDA20
R_NMDA21
R_NMDA22
R_NMDA23
R_NMDA24
R_NMDA25
R_NMDA26
R_NMDA27
R_NMDA28
R_NMDA29
R_NMDA30
R_NMDA31
R_NMDA32
R_NMDA33
R_NMDA34
R_NMDA35
R_NMDA36
R_NMDA37
R_NMDA38
R_NMDA39
R_NMDA40
R_NMDA41
R_NMDA42
R_NMDA43
R_NMDA44
R_NMDA45
R_NMDA46
R_NMDA47
R_NMDA48
R_NMDA49
R_NMDA50
R_NMDA51
R_NMDA52
R_NMDA53
R_NMDA54
R_NMDA55
R_NMDA56
R_NMDA57
R_NMDA58
R_NMDA59
R_NMDA60
R_NMDA61
R_NMDA62
R_NMDA63

NMAA[0..11]

20 NMAA[0..11]

20 R_NDQSA[0..7]

MEMORY INTERFACE
B

20 R_NDQMA[0..7]

1
R358

2
NMCKEA
1K_0402_5%~D

1
R389

2
NMCKEB
1K_0402_5%~D

Title
Size

Compal Electronics, Inc.

Document Number

nVIDIA NV31M (DDR)

Rev
0.1

LA-1841
5

Date:

Thursday, February 20, 2003

Sheet

17

of

57

U35D

+1.5VS
R40
1
1
R82

+5VS

49.9_0603_1%
2
2
49.9_0603_1%

AGPCALPD_VDDQ
AGPCALPU_GND
+AGP_PLLVDD
+2.5VS

F BCAL_PD_VDDQ
N V31,NV34 use.
N V18 not use.
F BCAL_PUK_GND
N V31,NV34 use.
N V18 not use.
F BCAL_TERM_GND
N V 3 1 use (tie to GND).
N V 18,NV34 not use.
FBCAL_CLK_GND
NV31 use.
N V 18,NV34 not use.

N4
AE9
AA13
AA14
AE12
F8
F11
F14
F17
F20
F23
G8
G11
G20
G23
H24
H25
L24
L25
P25
U25
Y24
Y25
AC24
AC25
AA6
AC5
AF10
AG29
AE27
G9
Y28

VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VDD33
VD50CLAMP0
VD50CLAMP1
AGPCALPD_VDDQ
AGPCALPU_GND
AGP_PLLVDD
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ
FBVDDQ

IFPCPLLVDD
IFPCPLLGND
IFPCIOVDD
IFPCIOGND

+IFPABIOVDD

1
2

Y4
W5
AA3
R4

IFPCVPROBE

P10
N10

+IFPCPLLVDD

R5
R6

+IFPCIOVDD

C55

1
1
R112
1
R107

0.1U_0402_10V6K
2
2
1K_0402_5%
2
10K_0402_5%

1
R114

2
10K_0402_5%

4.7U_0805_10V4Z

C36
0.1U_0402_16V4Z

C40
0.022U_0402_16V7K

C39
0.022U_0402_16V7K

VIPVDDQ
VIPVDDQ
VIPVDDQ
VIPCAL_PD_VDDQ
VIPCAL_PU_GND

DVOVDDQ
DVOVDDQ
DVOVDDQ

+VIP/DVOVDDQ

L6
L7
M7
P6
P7

N V31 use only.

N V 18,NV34 not use.
VIPCAL_1
VIPCAL_2

R120 2
R125 1

0.022U_0402_16V7K

C53
4.7U_0805_10V4Z

+PLLVDD
1 C472

NV31 use only.

N V 18,NV34 not use.

DVOCAL_PD_VDDQ
DVOCAL_PU_GND
DVO_VREF

AB6
AB7
AF4

DVOCAL_1
DVOCAL_2

R349
R348

1
1

2
2

+VIP/DVOVDDQ

@49.9_0402_1%
@49.9_0402_1%

0.1U_0402_10V6K

C65
4700P_0402_25V7K

C41

C110
0.1U_0402_10V6K

+3VS
L11
1
2
KC FBM-L11-201209-221LMAT_0805
C24
470P_0402_50V8J

1
C474

4.7U_0805_10V4Z

1
C15

4700P_0402_25V7K

+3VS
L20
1
2
KC FBM-L11-201209-221LMAT_0805

470P_0402_50V8J

R76

1K_0603_1%

+DVO_VREF

TESTMODE
TESTMECLK

DACB_VDD
DACB_VREF
DACA_VDD
DACA_VREF

AE5
G24

AB4
AB5
AG9
AH8

R342

10K_0402_5%

R117

@10K_0402_5%

F5
E4
D3
E3

TESTMECLK
N V31,NV34 use.
N V18 not use.

+DACA/BVDD
DACAVREF

DACBVREF
1
C10
2

FBCAL_PD_VDDQ
FBCAL_PU_GND
FBCAL_TERM_GND
FBCAL_CLK_GND

FB_DLLVDD
PLLVDD

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC
NC
NC
NC
NC

C27
AK7

B4
B27
C11
C20
D6
D25
D29
E12
E19
F27
L28
M26
N5
W7
W26
Y7

C23

1 C87

1K_0603_1%

1
1
1
1

R136
R139
R385
R137

+IFPABIOVDD

1 C100
2

470P_0402_50V8J

1 C62
2

4700P_0402_25V7K

+3VS
L14
2
1
KC FBM-L11-201209-221LMAT_0805
1 C131
2

4.7U_0805_10V4Z

4700P_0402_25V7K

+3VS
L12
1
2
KC FBM-L11-201209-221LMAT_0805

+VIP/DVOVDDQ
1 C50
2

1 C114

470P_0402_50V8J

4700P_0402_25V7K

+FB_DLLVDD
+PLLVDD

+FB_DLLVDD
1
2

C176
@4700P_0402_25V7K

1
2

C182

+3VS

+3VS
L15
1
2
@KC FBM-L11-201209-221LMAT_0805

+AGP_PLLVDD

C471

@470P_0402_50V8J

4.7U_0805_10V4Z

C37
4700P_0402_25V7K

470P_0402_50V8J

+AGP_PLLVDD
N V31,NV34 use.
N V18 not use.
A

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
3

L19

2
KC FBM-L11-201209-221LMAT_0805
1
C43

+FB_DLLVDD
NV31 use.
N V 18,NV34 not use.

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

1 C88

470P_0402_50V8J

0.01U_0402_50V7K

+2.5VS

2
2
2
2

0.1U_0402_10V6K

C67

0.01U_0603_50V7K
49.9_0402_1%
49.9_0402_1%
@0_0402_5%
@549_0402_1%

+3VS
L13
2
1
KC FBM-L11-201209-221LMAT_0805

+IFPABPLLVDD

R71

Title

C49

@49.9_0402_1%
@49.9_0402_1%

1
2

AD8
AD9
AE8

+DACA/BVDD
1

NV34M_EPBGA701

C61

G14
H6
H7
M6
P24
U6
U7
AC6
AC7
AD12
AD15
AD19
AD22
AD16

IFPCVPROBE
IFPCRSET

T5
T6

+5VS

1
R113
2AGP_VDD2
0_0402_5%

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

+IFPABPLLVDD

+1.5VS

+3VS

IFPBIOVDD
IFPBIOGND

U10
V10

0.1U_0402_10V6K
2
2
1K_0402_5%

1
1
R109

IFPAIOVDD
IFPAIOGND

IFABVPROBE
IFPABREST

R108 1
0_0402_5%

IFPABPLLVDD
IFPABPLLGND

C44

AA4
V6

L11
L13
L14
L17
L18
L20
2 AGP_VDD1
N6
N11
N20
P11
P20
U11
U20
V11
V20
Y11
Y13
Y14
Y17
Y18
Y20
AA17
AA18

+VGA_CORE

IFPABVPROBE
IFPABRSET

AGPVDDQ
AGPVDDQ
AGPVDDQ
AGPVDDQ
AGPVDDQ
AGPVDDQ
AGPVDDQ
AGPVDDQ
AGPVDDQ
AGPVDDQ

I/O
POWER

AD11
AD14
AD17
AD20
AD23
AE11
AE14
AE17
AE20
AE23

+1.5VS

Size
Date:

Compal Electronics, Inc.

Document Number

nVIDIA NV31M POWER)

LA-1841

Thursday, February 20, 2003

Sheet

18

of

Rev
0.1
57

+VGA_CORE
U35E

R24
T24
W24
AB24
A1
AK30
G6
R7
T7

NC
NC
NC
NC
NC1
NC2
NC3
NC4
NC5

NC
NC
NC
NC
NC
NC
NC

AH13
AH16
AH18
AH21
AH24
AH28
AK6
AK9
AK12
AK15
AK19
AK22
AK25
G12
G15
G16
G19
G22
J24
M24

1 C129
2

1 C75

4.7U_0805_10V4Z

1 C71

4.7U_0805_10V4Z

1 C74

4.7U_0805_10V4Z

1 C130

1U_0603_10V6K

1 C102

1U_0603_10V6K

1 C96

1U_0603_10V6K

1 C115

1U_0603_10V6K

1 C111

0.1U_0402_10V6K

1 C84

0.1U_0402_10V6K

1 C123

0.1U_0402_10V6K

0.1U_0402_10V6K

+VGA_CORE
1
2

C119
470P_0402_50V8J

C109
470P_0402_50V8J

C89
470P_0402_50V8J

C90
470P_0402_50V8J

C118
4700P_0402_25V7K

C78
4700P_0402_25V7K

C77
4700P_0402_25V7K

+2.5VS

C58
1U_0603_10V6K

C97
1U_0603_10V6K

C79

1U_0603_10V6K

+2.5VS
1
2

4700P_0402_25V7K

+3VS
1 C54
2

C136

C152
4700P_0402_25V7K

C91

1U_0603_10V6K

1 C59

0.1U_0402_10V6K

C151

4700P_0402_25V7K

1 C85

1U_0603_10V6K

C105

C137

C66

0.1U_0402_10V6K

C150

0.022U_0402_16V7K

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

M12
M13
M14
M15
M16
M17
M18
M19
N12
N13
N14
N15
N16
N17
N18
N19
P12
P13
P14
P15
P16
P17
P18
P19
R12
R13
R14
R15
R16
R17
R18
R19
T12
T13
T14
T15
T16
T17
T18
T19
U12
U13
U14
U15
U16
U17
U18
U19
V12
V13
V14
V15
V16
V17
V18
V19
W12
W13
W14
W15
W16
W17
W18
W19

1 C48

0.1U_0402_10V6K

0.1U_0402_10V6K

C146

0.022U_0402_16V7K

1 C52

0.1U_0402_10V6K

T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND
T_GND

0.1U_0402_10V6K

1 C38
2

0.1U_0402_10V6K

0.1U_0402_10V6K

C120
0.1U_0402_10V6K

1
2

C121
0.1U_0402_10V6K

C138
0.1U_0402_10V6K

1
2

C153

0.1U_0402_10V6K

C149

0.022U_0402_16V7K

1 C51
2

1 C142

0.022U_0402_16V7K

0.022U_0402_16V7K
B

+3VS
1
2

C140

0.022U_0402_16V7K

1
2

C104

4700P_0402_25V7K

C101

4700P_0402_25V7K

C128
4700P_0402_25V7K

+VGA_CORE
2

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

GROUND

A9
A12
A19
A22
A25
C3
C7
C10
C13
C18
C21
C24
D4
D28
E5
E8
E11
E14
E17
E20
E23
F1
F6
F25
F30
G3
G28
H11
H20
H26
J1
J7
J30
K3
K5
K28
L5
L8
L23
L26
M1
M30
N3
N28
P26
T1
U26
V28
W1
W30
Y8
Y23
Y26
AA5
AA28
AB1
AB30
AC11
AC20
AC26
AD28
AE1
AE6
AE25
AE30
AF5
AF8
AF11
AF14
AF17
AF20
AF23
AF26
AG4
AG27
AH3
AH7
AH10
A6

R118
@470_0402_5%

NV34M_EPBGA701

Q8
@2N7002
2 SUSP
G

SUSP

41

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
5

Size
Date:

Compal Electronics, Inc.

nVIDIA NV31M (DECOUPL ING CAP)

Document Number

LA-1841

Thursday, February 20, 2003

Rev
0.1

Sheet

19

of

57

As close as ppossible to related pin

C133

22U_1206_10V4Z

C132

0.1U_0402_10V6K

C144

C162

0.1U_0402_10V6K

C161

0.01U_0402_16V7K

1
1
1
1

C510
0.1U_0402_10V6K

17

17
17
17
17

15_0402_5%
15_0402_5%
15_0402_5%
15_0402_5%

NMRASA#
NMCASA#
NMWEA#
NMCSA0#

17
NMCKEA
NMCLKA0

NMCLKA0

NDQSA0
NDQSA3
NDQSA1
NDQSA2

B2
H13
H2
B13

VR_VREF_1

N13
M13
L9
M10

NMRASA#
NMCASA#
NMWEA#
NMCSA0#
NMCKEA

R131
@120_0402_5%

17

NMCLKA0#

NMCLKA0#
RP10

NMDA9
NMDA11
NMDA10
NMDA8
NMDA13
NMDA12
NMDA14
NMDA15

9
10
11
12
13
14
15
16

8
7
6
5
4
3
2
1

R_NMDA9
R_NMDA11
R_NMDA10
R_NMDA8
R_NMDA13
R_NMDA12
R_NMDA14
R_NMDA15

22_16P8R_1206_5%
RP12

2
2
2
2

B3
H12
H3
B12

1K_0402_1%

NMDA22
NMDA23
NMDA21
NMDA20
NMDA17
NMDA19
NMDA16
NMDA18

1
2
3
4
5
6
7
8

C19

0.01U_0402_16V7K
1

C57

C56

0.1U_0402_10V6K

16
15
14
13
12
11
10
9

R_NMDA22
R_NMDA23
R_NMDA21
R_NMDA20
R_NMDA17
R_NMDA19
R_NMDA16
R_NMDA18

M2
L2
L3
N2
N12
M11
M12
C4
C11
H4
H11
L12
L13
M3
M4
N3
E7
E8
E10
K6
K7
K8
K9
L5
L10
E5

DM0
DM1
DM2
DM3
DQS0
DQS1
DQS2
DQS3
VREF
MCL
RFU1
RFU2
RAS#
CAS#
WE#
CS#

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

CKE
CK
CK#
NC
NC
NC
NC
NC
NC
NC
NC
NC

B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8

NMDA7
NMDA6
NMDA5
NMDA4
NMDA0
NMDA3
NMDA2
NMDA1
NMDA24
NMDA25
NMDA26
NMDA27
NMDA28
NMDA29
NMDA30
NMDA31
NMDA8
NMDA10
NMDA9
NMDA11
NMDA13
NMDA12
NMDA15
NMDA14
NMDA21
NMDA22
NMDA20
NMDA23
NMDA19
NMDA18
NMDA17
NMDA16

C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

16
15
14
13
12
11
10
9

RP9

1
2
3
4
5
6
7
8

R_NMDA48
R_NMDA49
R_NMDA50
R_NMDA51
R_NMDA52
R_NMDA54
R_NMDA53
R_NMDA55

22_16P8R_1206_5%

+2.5VS

R96

1K_0402_1%

N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7
N4
M5

R75
R86
R53
R90

1
1
1
1

2
2
2
2

15_0402_5%
15_0402_5%
15_0402_5%
15_0402_5%

NDQMA5
NDQMA6
NDQMA4
NDQMA7

B3
H12
H3
B12

R_NDQSA5
R_NDQSA6
R_NDQSA4
R_NDQSA7

R73
R93
R54
R95

1
1
1
1

2
2
2
2

15_0402_5%
15_0402_5%
15_0402_5%
15_0402_5%

NDQSA5
NDQSA6
NDQSA4
NDQSA7

B2
H13
H2
B13

VR_VREF_2

N13
M13
L9
M10

(25mil)

1K_0402_1%

17

17

+2.5VS

NMAA0
NMAA1
NMAA2
NMAA3
NMAA4
NMAA5
NMAA6
NMAA7
NMAA8
NMAA9
NMAA10
NMAA11
NMA_BA0
NMA_BA1

R_NDQMA5
R_NDQMA6
R_NDQMA4
R_NDQMA7

R98

C68
0.1U_0402_10V6K

NMRASA#
NMCASA#
NMWEA#
NMCSA0#
NMCKEA

NMCLKA1

NMCLKA1

R81
@120_0402_5%

16
15
14
13
12
11
10
9

1
2
3
4
5
6
7
8

R_NMDA39
R_NMDA38
R_NMDA37
R_NMDA36
R_NMDA35
R_NMDA34
R_NMDA33
R_NMDA32

E7
E8
E10
K6
K7
K8
K9
L5
L10
E5

22_16P8R_1206_5%
NMDA56
NMDA59
NMDA60
NMDA58
NMDA57
NMDA61
NMDA62
NMDA63

K4D263238A-GC_FBGA144

16
15
14
13
12
11
10
9

RP8

1
2
3
4
5
6
7
8

N12

C4
C11
H4
H11
L12
L13
M3
M4
N3

NMCLKA1#

NMCLKA1#

M2
L2
L3
N2

M11
M12

RP4
NMDA39
NMDA38
NMDA37
NMDA36
NMDA35
NMDA34
NMDA33
NMDA32

D7
D8
E4
E11
L4
L7
L8
L11

C21

2
D

0.01U_0402_16V7K

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

U29

22_16P8R_1206_5%
NMDA48
NMDA49
NMDA50
NMDA51
NMDA52
NMDA54
NMDA53
NMDA55

C46

A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DM0
DM1
DM2
DM3
DQS0
DQS1
DQS2
DQS3
VREF
MCL
RFU1
RFU2
RAS#
CAS#
WE#
CS#

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

CKE
CK
CK#
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8

NMDA47
NMDA46
NMDA45
NMDA44
NMDA40
NMDA43
NMDA41
NMDA42
NMDA49
NMDA48
NMDA50
NMDA51
NMDA54
NMDA52
NMDA55
NMDA53
NMDA32
NMDA33
NMDA35
NMDA34
NMDA36
NMDA37
NMDA39
NMDA38
NMDA62
NMDA61
NMDA60
NMDA63
NMDA58
NMDA57
NMDA59
NMDA56

C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11

+2.5VS

D7
D8
E4
E11
L4
L7
L8
L11

VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH

R119
R142
R102
R140

(25mil)
R386

R_NMDA45
R_NMDA47
R_NMDA42
R_NMDA40
R_NMDA41
R_NMDA44
R_NMDA43
R_NMDA46

R_NDQSA0
R_NDQSA3
R_NDQSA1
R_NDQSA2

NDQMA0
NDQMA3
NDQMA1
NDQMA2

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

R115
R143
R97
R141

NMA_BA0
NMA_BA1
2 15_0402_5%
2 15_0402_5%
2 15_0402_5%
2 15_0402_5%

A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1

1
2
3
4
5
6
7
8

1K_0402_1%

R_NDQMA0
R_NDQMA3
R_NDQMA1
R_NDQMA2

17
17
1
1
1
1

N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7
N4
M5

16
15
14
13
12
11
10
9

R382

C29

0.1U_0402_10V6K

+2.5VS

C20

0.1U_0402_10V6K
1

0.01U_0402_16V7K

RP7

R_NMDA31
R_NMDA30
R_NMDA29
R_NMDA28
R_NMDA27
R_NMDA26
R_NMDA25
R_NMDA24

NMAA0
NMAA1
NMAA2
NMAA3
NMAA4
NMAA5
NMAA6
NMAA7
NMAA8
NMAA9
NMAA10
NMAA11
NMA_BA0
NMA_BA1

9
10
11
12
13
14
15
16

22_16P8R_1206_5%

C473

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

U32

NMDA45
NMDA47
NMDA42
NMDA40
NMDA41
NMDA44
NMDA43
NMDA46

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

R_NMDA5
R_NMDA1
R_NMDA0
R_NMDA2
R_NMDA4
R_NMDA3
R_NMDA7
R_NMDA6

RP13
8
7
6
5
4
3
2
1

C14

22U_1206_10V4Z

VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH

16
15
14
13
12
11
10
9

22_16P8R_1206_5%

NMDA31
NMDA30
NMDA29
NMDA28
NMDA27
NMDA26
NMDA25
NMDA24

C139

0.1U_0402_10V6K
1

0.01U_0402_16V7K

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

1
2
3
4
5
6
7
8

22U_1206_10V4Z
1

C154

RP11
NMDA5
NMDA1
NMDA0
NMDA2
NMDA4
NMDA3
NMDA7
NMDA6

+2.5VS

0.01U_0402_16V7K

C178

0.1U_0402_10V6K

17 R_NMDA[0..63]

R_NMDA[0..63]

C122

NMAA[0..11]

17 NMAA[0..11]

R_NDQSA[0..7]

0.1U_0402_10V6K

R_NMDA56
R_NMDA59
R_NMDA60
R_NMDA58
R_NMDA57
R_NMDA61
R_NMDA62
R_NMDA63

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

17 R_NDQSA[0..7]

22U_1206_10V4Z

+2.5VS
R_NDQMA[0..7]

17 R_NDQMA[0..7]

K4D263238A-GC_FBGA144

22_16P8R_1206_5%

22_16P8R_1206_5%

Title
Size

Compal Electronics, Inc.

VGA DDR FOR CHANNEL A

Document Number

Rev
0.1

LA-1841
5

Date:

Thursday, February 20, 2003

Sheet

20

of

57

As close as ppossible to related pin

R_NMDB[0..63]

22U_1206_10V4Z

0.1U_0402_10V6K

1K_0402_1%

R_NDQSB0
R_NDQSB3
R_NDQSB1
R_NDQSB2

R158
R169
R170
R155

2
2
2
2

C244
0.1U_0402_10V6K

15_0402_5%
15_0402_5%
15_0402_5%
15_0402_5%

N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7
N4
M5

NDQMB0
NDQMB3
NDQMB1
NDQMB2

B3
H12
H3
B12

NDQSB0
NDQSB3
NDQSB1
NDQSB2

B2
H13
H2
B13

VR_VREF_3

N13
M13
L9
M10

17

17
17
17
17

NMRASB#
NMCASB#
NMWEB#
NMCSB0#

NMRASB#
NMCASB#
NMWEB#
NMCSB0#

17

NMCKEB

NMCKEB

NMCLKB0

NMCLKB0

17
NMDB15
NMDB14
NMDB13
NMDB12
NMDB11
NMDB8
NMDB9
NMDB10

NMCLKB0#

NMCLKB0#
8
7
6
5
4
3
2
1

RP21

9
10
11
12
13
14
15
16

R_NMDB15
R_NMDB14
R_NMDB13
R_NMDB12
R_NMDB11
R_NMDB8
R_NMDB9
R_NMDB10

22_16P8R_1206_5%
RP15
NMDB16
NMDB17
NMDB18
NMDB19
NMDB20
NMDB21
NMDB22
NMDB23

16
15
14
13
12
11
10
9

1
2
3
4
5
6
7
8

R_NMDB16
R_NMDB17
R_NMDB18
R_NMDB19
R_NMDB20
R_NMDB21
R_NMDB22
R_NMDB23

M2
L2
L3
N2
N12
M11
M12

R409
@120_0402_5%

1
1
1
1

(25mil)

1K_0402_1%

22U_1206_10V4Z

C229

0.1U_0402_10V6K
1

C235

C228

0.1U_0402_10V6K

0.01U_0402_16V7K
1

C234

0.1U_0402_10V6K

C241

C224

C4
C11
H4
H11
L12
L13
M3
M4
N3
E7
E8
E10
K6
K7
K8
K9
L5
L10
E5

A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DM0
DM1
DM2
DM3
DQS0
DQS1
DQS2
DQS3
VREF
MCL
RFU1
RFU2
RAS#
CAS#
WE#
CS#

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

CKE
CK
CK#
NC
NC
NC
NC
NC
NC
NC
NC
NC

B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8

NMDB7
NMDB5
NMDB6
NMDB4
NMDB0
NMDB3
NMDB2
NMDB1
NMDB25
NMDB24
NMDB27
NMDB26
NMDB29
NMDB28
NMDB31
NMDB30
NMDB9
NMDB8
NMDB11
NMDB10
NMDB13
NMDB12
NMDB14
NMDB15
NMDB21
NMDB22
NMDB20
NMDB23
NMDB19
NMDB17
NMDB18
NMDB16

0.01U_0402_16V7K
0.01U_0402_16V7K

1
2
3
4
5
6
7
8

R_NMDB40
R_NMDB41
R_NMDB42
R_NMDB43
R_NMDB44
R_NMDB45
R_NMDB46
R_NMDB47

C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

U39

RP22
NMDB55
NMDB53
NMDB54
NMDB52
NMDB50
NMDB51
NMDB49
NMDB48

9
10
11
12
13
14
15
16

8
7
6
5
4
3
2
1

R_NMDB55
R_NMDB53
R_NMDB54
R_NMDB52
R_NMDB50
R_NMDB51
R_NMDB49
R_NMDB48

22_16P8R_1206_5%

+2.5VS

R181

2
2
2
2

1
1
1
1

15_0402_5%
15_0402_5%
15_0402_5%
15_0402_5%

NDQMB5
NDQMB6
NDQMB4
NDQMB7

B3
H12
H3
B12

R_NDQSB5
R_NDQSB6
R_NDQSB4
R_NDQSB7

R162
R171
R172
R159

2
2
2
2

1
1
1
1

15_0402_5%
15_0402_5%
15_0402_5%
15_0402_5%

NDQSB5
NDQSB6
NDQSB4
NDQSB7

B2
H13
H2
B13

VR_VREF_4

N13
M13
L9
M10

(25mil)

1K_0402_1%

17

+2.5VS

NMDB32
NMDB33
NMDB34
NMDB35
NMDB36
NMDB37
NMDB38
NMDB39

D7
D8
E4
E11
L4
L7
L8
L11

N5
N6
M6
N7
N8
M9
N9
N10
N11
M8
L6
M7
N4
M5

R161
R167
R168
R160

R179

17

NMAB0
NMAB1
NMAB2
NMAB3
NMAB4
NMAB5
NMAB6
NMAB7
NMAB8
NMAB9
NMAB10
NMAB11
NMB_BA0
NMB_BA1

R_NDQMB5
R_NDQMB6
R_NDQMB4
R_NDQMB7

1K_0402_1%

C245
0.1U_0402_10V6K

NMCKEB

RP23

NMCLKB1#

1
2
3
4
5
6
7
8

R_NMDB32
R_NMDB33
R_NMDB34
R_NMDB35
R_NMDB36
R_NMDB37
R_NMDB38
R_NMDB39

RP17

K4D263238A-GC_FBGA144

16
15
14
13
12
11
10
9

1
2
3
4
5
6
7
8

N12

C4
C11
H4
H11
L12
L13
M3
M4
N3
E7
E8
E10
K6
K7
K8
K9
L5
L10
E5

22_16P8R_1206_5%
NMDB56
NMDB57
NMDB59
NMDB58
NMDB60
NMDB63
NMDB61
NMDB62

M2
L2
L3
N2

M11
M12
R183
@120_0402_5%

NMCLKB1#
16
15
14
13
12
11
10
9

NMRASB#
NMCASB#
NMWEB#
NMCSB0#

NMCLKB1

NMCLKB1

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

16
15
14
13
12
11
10
9

22_16P8R_1206_5%

22_16P8R_1206_5%

R_NMDB56
R_NMDB57
R_NMDB59
R_NMDB58
R_NMDB60
R_NMDB63
R_NMDB61
R_NMDB62

A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
BA0
BA1

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DM0
DM1
DM2
DM3
DQS0
DQS1
DQS2
DQS3
VREF
MCL
RFU1
RFU2
RAS#
CAS#
WE#
CS#

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

CKE
CK
CK#
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

B7
C6
B6
B5
C2
D3
D2
E2
K13
K12
J13
J12
G13
G12
F13
F12
F3
F2
G3
G2
J3
J2
K2
K3
E13
D13
D12
C13
B10
B9
C9
B8

NMDB47
NMDB46
NMDB45
NMDB44
NMDB40
NMDB43
NMDB41
NMDB42
NMDB53
NMDB55
NMDB52
NMDB54
NMDB51
NMDB50
NMDB48
NMDB49
NMDB38
NMDB39
NMDB36
NMDB37
NMDB34
NMDB35
NMDB33
NMDB32
NMDB62
NMDB61
NMDB60
NMDB63
NMDB58
NMDB57
NMDB59
NMDB56

C3
C5
C7
C8
C10
C12
E3
E12
F4
F11
G4
G11
J4
J11
K4
K11

+2.5VS

D7
D8
E4
E11
L4
L7
L8
L11

K4D263238A-GC_FBGA144

22_16P8R_1206_5%

Title
Size

Compal Electronics, Inc.

VGA DDR FOR CHANNEL B

Document Number

Rev
0.1

LA-1841
5

C239

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NMDB40
NMDB41
NMDB42
NMDB43
NMDB44
NMDB45
NMDB46
NMDB47

R157
R165
R166
R156

NMB_BA0
NMB_BA1
1 15_0402_5%
1 15_0402_5%
1 15_0402_5%
1 15_0402_5%

NMAB0
NMAB1
NMAB2
NMAB3
NMAB4
NMAB5
NMAB6
NMAB7
NMAB8
NMAB9
NMAB10
NMAB11
NMB_BA0
NMB_BA1

R178

0.01U_0402_16V7K

0.1U_0402_10V6K
1

C560

R180

R_NDQMB0
R_NDQMB3
R_NDQMB1
R_NDQMB2

17
17
2
2
2
2

C221

+2.5VS

C225

VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH

U40

22_16P8R_1206_5%
C

22U_1206_10V4Z
1

C227

RP18

R_NMDB31
R_NMDB30
R_NMDB29
R_NMDB28
R_NMDB27
R_NMDB26
R_NMDB25
R_NMDB24

1
2
3
4
5
6
7
8

RP20

0.1U_0402_10V6K

16
15
14
13
12
11
10
9

C232

0.01U_0402_16V7K

R_NMDB0
R_NMDB2
R_NMDB1
R_NMDB3
R_NMDB4
R_NMDB5
R_NMDB6
R_NMDB7

22_16P8R_1206_5%

NMDB31
NMDB30
NMDB29
NMDB28
NMDB27
NMDB26
NMDB25
NMDB24

C236

B4
B11
D4
D5
D6
D9
D10
D11
E6
E9
F5
F10
G5
G10
H5
H10
J5
J10
K5
K10

1
2
3
4
5
6
7
8

C237

VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

RP16

C240

VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH
VSS TH

16
15
14
13
12
11
10
9

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

NMDB0
NMDB2
NMDB1
NMDB3
NMDB4
NMDB5
NMDB6
NMDB7

C226

17 R_NMDB[0..63]

C559

+2.5VS

0.01U_0402_16V7K

NMAB[0..11]

NMAB[0..11]

17

C246

0.1U_0402_10V6K

F6
F7
F8
F9
G6
G7
G8
G9
H6
H7
H8
H9
J6
J7
J8
J9

R_NDQSB[0..7]

0.1U_0402_10V6K

17 R_NDQSB[0..7]

22U_1206_10V4Z
1

R_NDQMB[0..7]

+2.5VS
17 R_NDQMB[0..7]

Date:

Thursday, February 20, 2003

Sheet

21

of

57

Y ground
C ground
Y (luminance+sync)
C (crominance)

+LCDVDD

1000P_0402_50V7K
1

TZCLK+
TZCLK-

PID0
PID1
PID2
PID3

DISPOFF#
1

220P_0402_50V8K

@2N7002
Q57

ENBKL

C680
220P_0402_50V8K

2
G
3

+CRT_VCC

+CRT_VCC

+5VS

R12

R13

4.7K_0402_5%

+5VS

R11

4.7K_0402_5%
Q34
2N7002
1

100K_0402_5%

R10

4.7K_0402_5%

4.7K_0402_5%

DDC_DATA

Q35
2N7002
1

DDC_CLK_1

+5VS

R1

C453

D
1

1
C459

R551
10K_0402_5%

C456

D32
RB751V_SOD323
1
2

BKOFF#

16

DDC_CLK

16

220P_0402_50V8K

Compal Electronics, Inc.

4 DACA_VSYNC_1
Y U26
SN74AHCT1G125GW_SOT353-5

Title

CRT,TV-OUT & LVDSConnector

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.

TZCLK+
TZCLK-

PID0
PID1
PID2
PID3

16,39

DDC_DATA_1

@68P_0402_50V8K
2

16
16

TZOUT2+
TZOUT2TZOUT3+
TZOUT3-

1
A

6
11
1
7
12
2
8
13
3
9
14
4
10
15
5

100P_0402_50V8K

@68P_0402_50V8K

0.1U_0402_16V4Z
2

C457

TZOUT2+
TZOUT2TZOUT3+
TZOUT3-

2
39

JP15
CRT-15P

CRT_VCC

DACA_VSYNC_2

3
A

2
0_0603_5%

16
16
16
16

C455

5
1

DACA_HSYNC_2

R4
1K_0402_5%

+CRT_VCC

5
1
P
OE#

16 DACA_VSYNC

C2
3

U27
SN74AHCT1G125GW_SOT353-5

TZOUT0+
TZOUT0TZOUT1+
TZOUT1-

FUSE_1A

CH491D_SOT23

C454

L2

TZOUT0+
TZOUT0TZOUT1+
TZOUT1-

C458

15P_0402_50V8J

L1
15P_0402_50V8J
1
2
0_0603_5%

0.1U_0402_16V4Z

C460

16
16
16
16

TXCLK+
TXCLK-

+CRT_VCC

F1

CRT_B

C461

TXCLK+
TXCLK-

CRT_G

15P_0402_50V8J

75_0603_1% 75_0603_1%
18P_0402_50V8K
+CRT_VCC
DACA_HSYNC_1

16 DACA_HSYNC

C464

2
1

C463

18P_0402_50V8K

75_0603_1%

C1

C462

R9

R8

16
16

+R_CRT_VCC

CRT_R

18P_0402_50V8K
R7

1
2
FCM2012C-800_0805
L4
1
2
FCM2012C-800_0805
L5
1
2
FCM2012C-800_0805

P
OE#

16

16

TXOUT2+
TXOUT2TXOUT3+
TXOUT3-

2
G

D20

0.1U_0402_16V4Z

16

TXOUT2+
TXOUT2TXOUT3+
TXOUT3-

+3VS

+5VS

+3VS

L3

16
16
16
16

I-PEX_20324-040E-01

CRT Conn.

TXOUT0+
TXOUT0TXOUT1+
TXOUT1-

4.7U_0805_10V4Z

D22
DAN217_SOT23

D23
DAN217_SOT23

D24
DAN217_SOT23

TXOUT0+
TXOUT0TXOUT1+
TXOUT1-

36
36
36
36

22K
Q2
DTC124EK_SOT23

16
16
16
16

C108

22K

0.1U_0402_16V4Z

L6
DAC_BRIG
B_INVT_PWM
DISPOFF#

C107

Q4
DTC124EK_SOT23

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

22K

SI2302DS-T1_SOT23

1
1

200K_0402_5%

22K

8
7
6
5

ENVDD

1
2
3
4

RP6

10K_8P4R_1206_5%

16

ENVDD

2
1
S

C5

10U_1210_35V4Z

Q3
3

R25

4.7U_0805_10V4Z

2
G

1 1

R6
10K_0402_5%
1
2
R5
47K_0402_5%

PID3
PID2
PID1
PID0

C6

2
G
Q1
2N7002

C17

0.1U_0603_50V4Z

+3VS

12

100_0402_5%

C12

+3VS

100K_0402_5%

R16

39

JP1
INVPWR_B+

2
2

+LCDVDD

330P_0402_50V7K

R26

+5V

1
B+
1
CHB2012U170_0805
DAC_BRIG

B+

270P_0402_50V7K

L7
CHB2012U170_0805

B_INVT_PWM

SN74LVC32APWLE_TSSOP14
+3VALW POWER

1.
2.
3.
4.

1
2
3
4

11

SUYIN_030008FR004T101ZL

C502

+12VALW

+LCDVDD

U13D

75_0603_1%

C511
330P_0402_50V7K

75_0603_1%

1
2
3
4

LUMA_1
CRMA_1

270P_0402_50V7K

12

JP20

C512
22P_0402_50V8J

C497

13

INVT_PWM

C515

39

+3VS

DAN217_SOT23

R356

D26

R387

75_0603_1%

R74

CRMA
COMPS
1

16
16

LUMA

16

1
2 22P_0402_50V8J
L24
1
2
FBM-11-160808-121T_0603
L26
1
2
FBM-11-160808-121T_0603

C501

LVDS Conn.

+3VALW
14

D25
DAN217_SOT23

2
G

TV-OUT Conn.

CRT, TV-OUT & LVDS CONNECTOR

Size
B

Document Number

Date:

Thursday, February 20, 2003

Rev
0.1

LA-1841
Sheet
E

22

of

57

+3VS

RP140
4
3
2
1

5
6
7
8

PCI_REQ#2
ICH_GPIO3_PIRQF#
PCI_REQ#B
ICH_GPIO2_PIRQE#

8.2K_8P4R_1206_5%
+3VS

RP146
4
3
2
1

PCI_IRDY#
PCI_SERR#
PCI_DEVSEL#
PCI_PERR#

5
6
7
8

8.2K_8P4R_1206_5%
+3VS

RP143
4
3
2
1

5
6
7
8

PCI_STOP#
PCI_FRAME#
PCI_REQ#0
PCI_PIRQD#

8.2K_8P4R_1206_5%
26,27,29,30
26,27,29,30
26,27,29,30
26,27,29,30

RP142
4
3
2
1

5
6
7
8

ICH_GPIO5_PIRQH#
PCI_PIRQA#
PCI_PIRQC#

8.2K_8P4R_1206_5%
+3VS

D I S A BLE "TOP BLOCK SWAP"

1
R232

(GNTA#)
2
PIDERST#
8.2K_0402_5%

1
R512

2
PCI_PLOCK#
8.2K_0402_5%

2
R483

1
PCI_REQ#A
10K_0402_5%

1
R222

2
PCI_REQ#4
10K_0402_5%

1
R503

PCI_REQ#1
2
10K_0402_5%

1
R479

2
PCI_REQ#3
10K_0402_5%

30
29
27
26

PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3

30
29
27
26

PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3

15 CLK_PCI_ICH
26,27,29,30 PCI_FRAME#
26,27,29,30 PCI_DEVSEL#
26,27,29,30 PCI_IRDY#
26,27,29,30 PCI_PAR
26,27,29,30 PCI_PERR#
10,26,27,29,30,36,39
26,27,29,30
26,27,29,30
26,27,29,30

+1.5VS

35

R515

Note:
H I _ S WING_MCH, HI_VREF_MCH
t r a c e width of 10mils and
space 7mils

226_0603_1%

HI_SWING_ICH

R513
147_0603_1%

2
1

C371
0.1U_0402_16V4Z

PCIRST#
PCI_SERR#
PCI_STOP#
PCI_TRDY#

PIDERST#

D5
C1
C5
B6
C6

PCI_GNT#0
PCI_GNT#1
PCI_GNT#2
PCI_GNT#3

D4
A3
B7
C7
A4

CLK_PCI_ICH

N1

PCI_FRAME#
PCI_DEVSEL#
PCI_IRDY#
PCI_PAR
PCI_PERR#
PCI_PLOCK#
PCIRST#
PCI_SERR#
PCI_STOP#
PCI_TRDY#

D2
L3
M3
F1
K2
L2
V2
V4
L4
E5
E4

PCI_REQ#A
PCI_REQ#B

A5
E7

PIDERST#

E8
B4

C377
0.01U_0402_16V7K

0.1U_0402_16V4Z

CLK66

REQ0#
REQ1#
REQ2#
REQ3#
REQ4#/GPI40
GNT0#
GNT1#
GNT2#
GNT3#
GNT4#/GPO48

HI_STBF
HI_STBS

HIRCOMP
HIREF
HI_VSWING

Interrupt I/F

PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#/GPI2
PIRQF#/GPI3
PIRQG#/GPI4
PIRQH#/GPI5
IRQ14
IRQ15
SERIRQ

PCICLK

FRAME#
DEVSEL#
IRDY#
PAR
PERR#
PLOCK#
PME#
PCIRST#
SERR#
STOP#
TRDY#

EEPROM I/F

REQA#/GPI0
REQB#REQ5#/GPI1

EE_CS
EE_DIN
EE_DOUT
EE_SHCLK

LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN I/F
LAN_TXD1
LAN_TXD2
LAN_CLK
LAN_RSTSYNC
LAN_RST#

GNTA#/GPO16
GNTB#/GNT5#/GPO17

SMI#
R537
R531

H20
H21
J20
H23
M23
M21
N21
M20
L22
J22
K21
G22

HUB_HL0
HUB_HL1
HUB_HL2
HUB_HL3
HUB_HL4
HUB_HL5
HUB_HL6
HUB_HL7
HUB_HL8
HUB_HL9
HUB_HL10
HUB_HL11

GATEA20
H_A20M#

2
2

N22

1
1

B3
E1
A2
C2
D7
A6
E2
B1
Y17
Y24
F23

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
ICH_GPIO2_PIRQE#
ICH_GPIO3_PIRQF#
ICH_GPIO4_PIRQG#
ICH_GPIO5_PIRQH#
IDE_IRQ14
IDE_IRQ15
IRQ_SERIRQ

B10
B11
B9
A12

NC_EE_DOUT

C10
C9
C11
D9
E9
B12
E10
D10
AA1

LAN_RST#

39
5

2
10K_0402_5%

ICH_SMLINK1

1
R547

2
10K_0402_5%

LINK_ALERT#

1
R261

2
10K_0402_5%

GPI_11

1
R652

2
10K_0402_5%

ICH_SMB_CLK

1
R565

2
2.7K_0402_5%

ICH_SMB_DATA

1
R559

2
2.7K_0402_5%

+3VS

R249
2
R234
CLK_ICH_66M

1
62_0402_5%

@10_0402_5%

15

HUB_HLSTRF
10
HUB_HLSTRS
10
2
1
R522
54.9_0603_1%

2
1

C383
@10P_0402_50V8K

+1.5VS

c hange to 52.3_1%

PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#

16,27,30
26,27
27,29
27,29

+3VS
IDE_IRQ15
IDE_IRQ14

IDE_IRQ14
35
IDE_IRQ15
34,35
SERIRQ
27,36,39

IRQ_SERIRQ

2
8.2K_0402_5%

2
8.2K_0402_5%

1
R511

2
10K_0402_5%

R543
R262

2
1
R220
@1K_0402_5%

2
1
R544
10K_0402_5%

1
0.1U_0402_16V4Z

14
PCIRST#

C667
@10P_0402_50V8K

2
7

P
I
G

U51A
3
O
+3V POWER

B_PCIRST#

16,35
A

SN74LVC125APWLE_TSSOP14

C374
0.01U_0402_16V7K

C l o s e to ICH ball <250mils

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
5

1
R566

CLK_ICH_66M

K23
J24

HI_RCOMP_ICH
HI_VREF_ICH
HI_SWING_ICH

12,13,15
12,13,15

H_FERR#
5
H_IGNNE#
5
H_INIT#
5
H_INTR
5
H_NMI
5
H_PWRGOOD
5
KBRST#
39
H_CPUSLP#
5
H_SMI#
5
0_0402_5%
H_STPCLK#
5
0_0402_5%
H_DPSLP#
5

CLK_ICH_66M

N24
L24
L20

ICH_SMLINK0

+3VALW
ICH_SMB_CLK
ICH_SMB_DATA

+3V

1
2

1 C l ose to ICH(L24)
2

HUB I/F

R520
@10_0402_5%
2

113_0603_1%

2 C379

PCI I/F

C/BE0#
C/BE1#
C/BE2#
C/BE3#

T22
V23
A11
U24
R21
R23
U23
R22
P24
P23
P22
V24
T24
R24

2
C679

C l o s e to ICH ball <250mils

R241

HI0
HI1
HI2
HI3
HI4
HI5
HI6
HI7
HI8
HI9
HI10
HI11

INTRUDER#
ICH_SMLINK0
ICH_SMLINK1
LINK_ALERT#
ICH_SMB_CLK
ICH_SMB_DATA
GPI_11

CLK_PCI_ICH

HI_VREF_ICH
A

PCI_REQ#0
PCI_REQ#1
PCI_REQ#2
PCI_REQ#3
PCI_REQ#4

A20GATE
A20M#
NC
FERR#
IGNNE#
CPU I/F
INIT#
INTR
NMI
CPUPWRGD/GPO49
RCIN#
CPUSLP#
SMI#
STPCLK#
NC/(DPSLP#)

Y12
AD3
AA2
V5
AD2
AD1
AC3

ICH5

1 C l ose to ICH(L20)
2

E3
J1
N3
M2

PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3

INTRUDER#
SMLINK0
SMLINK1
SMB I/F LINKALERT#
SMBCLK
SMBDATA
SMBALERT#/GPI11

ICH5/(ICH5-M)

+3VS

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

2
10K_0402_5%

J4
J5
G3
K4
H5
H2
J3
J2
K5
F2
M4
H4
L5
G2
K1
G5
G4
L1
B2
P5
H3
N5
C4
N4
E6
P3
D3
N2
F5
P4
F4
P2

1
R264

8.2K_8P4R_1206_5%

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

INTRUDER#

PCI_TRDY#
ICH_GPIO4_PIRQG#
PCI_PIRQB#

HUB_HL[0..10]

10 HUB_HL[0..10]

5
6
7
8

+RTCVCC
U49A

4
3
2
1

PCI_AD[0..31]

PCI_AD[0..31]

OE#

RP144

26,27,29,30
+3VS

Size
Date:

Compal Electronics, Inc.

ICH5-PCI/HUB/LAN

Document Number

LA-1841

Thursday, February 20, 2003

Sheet

Rev
0.1
23

of

57

+3VALW

39

5 H_CPUPERF#
53
VGATE

2
R477

1 ICH_AC_SDOUT
@8.2K_0402_5%

2
R225
2
R230
2
R229

1 ICH_AC_BITCLK
@10K_0402_5%
1 ICH_AC_SDIN0
@10K_0402_5%
1 ICH_AC_SDIN1
@10K_0402_5%

1
R528

31 ICH_AC_SDIN0
38 ICH_AC_SDIN1

ICH_AC_SDOUT_R
I CH_AC_SYNC_R
LPC_AD[0..3]

36,39 LPC_AD[0..3]

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

4
3
2
1

RP141

5
6
7
8

USB_OC3#
USB_OC5#
USB_OC7#
USB_OC1#

10K_8P4R_1206_5%

+RTCVCC
2
R577
2
R576

1
330K_0402_5%
1
@10K_0402_5%

ICH_INTVRMEN

37
37

USBP0+
USBP0-

37
37
35
35
37
37
38
38
37
37
35
35

USBP2+
USBP2USBP3+
USBP3USBP4+
USBP4USBP5+
USBP5USBP6+
USBP6USBP7+
USBP7-

37

USB_OC0#

37

USB_OC2#

37

USB_OC4#

37

SPKR
1
@1K_0402_5%

2
R504

35

33
1

CLK_ICH_48M
R508
@10_0402_5%

R231

2
1

21

@10_0402_5%
C353
@4.7P_0402_50V8C

C15
D15
D14
C14
B14
A14
D13
C13

USBRBIAS

SIDERST#

C650
@10P_0402_50V8K

5 H_THERMTRIP#

A24
B24

T1
G23
F21

SIDERST#

ICH_INTVRMEN

D i s able timer timeout

CLK_ICH_14M

1
2
R500
22.6_0603_1%

GPO23/(SSMUXSEL)
GPO22/(CPUPERF#)
VRMPWRGD/(VGATE)

IST

AC_BIT_CLK
AC_RST#
AC_SDIN0
AC97 I/F
AC_SDIN1
AC_SDIN2
AC_SDOUT
AC_SYNC
LAD0
LAD1
LAD2
LAD3
LDRQ0#
LDRQ1#/GPI41
LFRAME#
USBP0P
USBP0N
USBP1P
USBP1N
USBP2P
USBP2N
USBP3P
USBP3N
USBP4P
USBP4N
USBP5P
USBP5N
USBP6P
USBP6N
USBP7P
USBP7N

IDE I/F

LPC I/F

SPKR

H_THERMTRIP#

PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
SDA0
SDA1
SDA2
SDCS1#
SDCS3#

SDDREQ
SDDACK#
SDIOR#
SDIOW#
SIORDY
SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

USB I/F

OC0#
OC1#
OC2#
OC3#
OC4#/GPI9
OC5#/GPI10
OC6#/GPI14
OC7#/GPI15

SATA0TXP
SATA0TXN
SATA0RXN
SATA0RXP

USBRBIAS
USBRBIAS#

+3VS

C23
D23
A22
B22
C21
D21
A20
B20
C19
D19
A18
B18
C17
D17
A16
B16

USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC7#

USB_OC6#

Note:
U S B R B I A S keep less than 500mils

D8
C12
E12
D12
A13
A9
B8
T5
R4
R3
U4
U5
R2
T4

LPC_DRQ1#
LPC_FRAME#

36 LPC_DRQ#1
36,39 LPC_FRAME#
+3VALW

F22
U20
R20

H_CPUPERF#
2
ICH_VGATE
0_0402_5%
ICH_AC_BITCLK
ICH_AC_RST_R#
ICH_AC_SDIN0
ICH_AC_SDIN1

31,38 ICH_AC_BITCLK

+3VS

EC_THRM#

EC_THRM#

AD10

SPKR

E24

1
R258

2
T21
0_0402_5%

15 CLK_ICH_14M

CLK_ICH_14M

15 CLK_ICH_48M

CLK_ICH_48M

F20
F24

GPIO32
GPIO33
GPIO34

SATA I/F

GPIO

INTVRMEN
SPKR

SATA1TXP
SATA1TXN
SATA1RXN
SATA1RXP
SATARBIAS
SATARBIAS#

MISC

CLK100P
CLK100N

THRMTRIP#

RTCRST#

CLK14

CLOCK

CLK48

RTCX1
RTCX2

+3VALW

IDE_PDA0
35
IDE_PDA1
35
IDE_PDA2
35
IDE_PDCS1#
35
IDE_PDCS3#
35

AC17
AC18
AD18
AA17
AA18

IDE_PDDREQ
IDE_PDDACK#
IDE_PDIOR#
IDE_PDIOW#
IDE_PDIORDY

IDE_PDDREQ
IDE_PDDACK#
IDE_PDIOR#
IDE_PDIOW#
IDE_PDIORDY

AB16
Y13
Y14
AC14
AA14
AC15
AD14
AB14
AD15
Y15
AD16
AA15
AC16
Y16
AA16
AB17

IDE_PDD0
IDE_PDD1
IDE_PDD2
IDE_PDD3
IDE_PDD4
IDE_PDD5
IDE_PDD6
IDE_PDD7
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15

W22
W23
W21
V22
V20

IDE_SDA0
IDE_SDA1
IDE_SDA2
IDE_SDCS1#
IDE_SDCS3#

Y20
W20
Y23
Y22
Y21

IDE_SDDREQ
IDE_SDDACK#
IDE_SDIOR#
IDE_SDIOW#
IDE_SDIORDY

AA22
AB23
AD23
AD24
AB21
AC21
AB20
AC20
Y19
AD22
AC22
AA20
AB22
AC24
AB24
AA23

IDE_SDD0
IDE_SDD1
IDE_SDD2
IDE_SDD3
IDE_SDD4
IDE_SDD5
IDE_SDD6
IDE_SDD7
IDE_SDD8
IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15

2
C392
5

IDE_PDA0
IDE_PDA1
IDE_PDA2
IDE_PDCS1#
IDE_PDCS3#

35
35
35
35
35

PM_SLPS4#

PM_SLPS5#

U17

IN1

IN2

ICH_SYNC#

SYS_PWROK

PM_SLP_S5#

39

ICH_PWROK

+3VS
IDE_PDIORDY

2
R572

1
4.7K_0402_5%

IDE_SDIORDY

2
R546

1
4.7K_0402_5%

+3VS
IDE_SDA0
34,35
IDE_SDA1
34,35
IDE_SDA2
34,35
IDE_SDCS1#
34,35
IDE_SDCS3#
34,35
IDE_SDDREQ
IDE_SDDACK#
IDE_SDIOR#
IDE_SDIOW#
IDE_SDIORDY

R580
@1K_0402_5%

R571

1 1

2
Q60
@MMBT3904_SOT23
10

ICH_SYNC#

IDE_PDD[0..15]

IDE_PDD[0..15]

35

IDE_SDD[0..15]

IDE_SDD[0..15]

34,35
2
1
J1
JOPEN

2
1ICH_VBIAS
R569
@10M_0603_5%

AC5
AD5

ICH_RTCX1

AA12

ICH_RTCRST#

AC11

ICH_RTCX1

AB12

ICH_RTCX2

R573

+RTCVCC

200K_0402_5%

C686
1U_0805_25V4Z

1
R578

C691
@0.047U_0402_16V4Z
2
R575
2
@22M_0603_5%

1
@1K_0402_5%

R568

ICH_RTCX2

2
R567
X6

C698

12P_0402_50V8J

12P_0402_50V8J

ICH_AC_BITCLK

@2.4M_0603_1%

1
10M_0603_5%

32.768KHZ_12.5PF_CM155
C697

ICH5

2 ICH_PWROK
0_0402_5%

1
R570

Note:
S A T A B I A S keep less than 500mils
1
24.9_0603_1%

2
Q59
@MMBT3904_SOT23

3 3

7,42 SYS_PWROK

2
1
R476
4.7K_0402_5%

2
R260

R582
@220_0402_5%

@220_0402_5%

34,35
34,35
34,35
34,35
34,35

ICH_RTCRST#

SATABIAS

1
0.1U_0402_16V4Z

S N 7 4AHC1G08HDCK_TSSOP5

AA8
AB8
AD7
AC7

Y11
Y9

39,44,46

37

AA19
AD19
AC19
AB19
Y18

AA10
AB10
AD9
AC9

ACIN

1
SUSCLK
@10K_0402_5%
1
EC_RSMRST#
10K_0402_5%

PDDREQ
PDDACK#
PDIOR#
PDIOW#
PIORDY

ACIN

2
R542
2
R265

15,53 STP_CPU#
15 STP_PCI#
27 SUSCLK

1
D36

1
H_CPUPERF#
10K_0402_5%

USB_EN#

RB751V_SOD323

2
R257

ICH_ACIN

+3VS
EC_SMI#
39
EC_SCI#
39
EC_LID_OUT#
39
EC_FLASH#
40

+CPU_CORE

PDA0
PDA1
PDA2
PDCS1#
PDCS3#

PM

R536
10K_0402_5%
ICH_ACIN
1
2
EC_SMI#
EC_SCI#
EC_LID_OUT#

EC_RSMRST#
PM_SLP_S1#
PM_SLP_S3#
PM_SLPS4#
PM_SLPS5#
STP_CPU#
STP_PCI#
SUSCLK

U3
Y2
W4
W5
W3
V3
W2

39 EC_SWI#
39,45 EC_RSMRST#
15 PM_SLP_S1#
39 PM_SLP_S3#

GPI

GPI7
GPI8
GPI12
GPI13
GPIO25
GPIO27
GPIO28

ICH_PWROK

ICH5/(ICH5-M)

PM_DPRSLPVR

53 PM_DPRSLPVR
39 PBTN_OUT#

GPI6/(AGPBUSY#)
SYS_RESET#
TP0/(BATLOW#)
GPO21/(C3_SAT#)
GPIO24/(CLKRUN#)
NC/(DPRSLPVR)
PWRBTN#
PWROK
RI#
RSMRST#
GPO19/(SLP_S1#)
SLP_S3#
SLP_S4#
SLP_S5#
GPO20/(STP_CPU#)
GPO18/(STP_PCI#)
SUSCLK
SUS_STAT#/LPCPD#
THRM#

1
ICH_VGATE
10K_0402_5%
EC_THRM#
1
4.7K_0402_5%
1
PM_CLKRUN#
10K_0402_5%

+3VS

U49B
R5
U1
AB2
R1
AC1
P20
Y4
AC12
AB3
AB13
T20
W1
U2
AA3
U22
U21
Y1
AB1
T2

SYS_RESET#
TP0_PU

2
R253
2
R530
2
R653

R251
10K_0402_5%
1
2

+3VS

1
TP0_PU
10K_0402_5%
1
SYS_RESET#
8.2K_0402_5%

2
R550
2
R540

31,38 ICH_AC_RST#
1
R254

2 H_THERMTRIP#
62_0402_5%

31,38 ICH_AC_SYNC
31,38 ICH_AC_SDOUT

Near ICH

2
R486
2
R485
2
R484

1 ICH_AC_RST_R#
33_0402_5%
1 I CH_AC_SYNC_R
33_0402_5%
1 ICH_AC_SDOUT_R
33_0402_5%

2
1

26,27,29,30,36,39

PM_CLKRUN#

C354
@10P_0402_50V8K

PM_CLKRUN#

Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.

@10_0402_5%
1

+CPU_CORE

R223

Size
Date:

Compal Electronics, Inc.

ICH5-IDE/LPC/PM/GPIO/USB

Document Number

LA-1841

Thursday, February 20, 2003

Sheet

24

of

Rev
0.1
57

V5REF_SUS
V_CPU_IO
V_CPU_IO
V_CPU_IO
VCCSATAPLL
VCCSATAPLL
VCCUSBPLL
VCCRTC

GND

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

+1.5VS

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Place near
ball T22

+1.5VS

C393
0.1U_0402_16V4Z

C401
0.1U_0402_16V4Z

C386
0.1U_0402_16V4Z

C368
0.1U_0402_16V4Z

1
2

C395
0.1U_0402_16V4Z

1
2

C360
0.1U_0402_16V4Z

C372

C382
0.1U_0402_16V4Z

0.01U_0402_16V7K

C384
0.01U_0402_16V7K

P l ace near ball D24

+1.5VS

+3VALW
1 C378
1
2

C356
0.01U_0402_16V7K

C361

0.1U_0402_16V4Z

C357

0.1U_0402_16V4Z

C391

0.1U_0402_16V4Z

1
2

C387

1 C394

0.1U_0402_16V4Z

1U_0603_10V6K

0.01U_0402_16V7K

P l ace near ball AD6

P l a c e0.1u near ball(VSS)

A 1 7 , A 23,V1.Addition cap near
A15,A19

A8
W14

ICH_V5REF

VCCSUS15_C

1 C362

1 C398

0.01U_0402_16V7K

D30
RB751V_SOD323

+CPU_CORE

Place near
ball (VSS)AD4

0.1U_0402_16V4Z

0.1U_0402_16V4Z

C636
1U_0603_10V6K
B

P l a ce near ball A8

Place near
ball (VSS)A19

+3VALW +5VALW

D12
RB751V_SOD323
ICH_V5REF_SUS

+RTCVCC
1

C349

+1.5VS

P14
P15
P21
R11
R14
T23
T3
T6
U19
V1
V21
W16
W18
Y3
Y6
Y7
Y8
Y10

1K_0402_5%

0.01U_0402_16V7K

ICH_V5REF_SUS

Place near
ball (VSS)A7

C390

R482

ICH_V5REF
1

1 C359

0.01U_0402_16V7K

+5VS
2

+3VS

Decoupling Reference Document:

Springdale Chipset Platform Design guide Rev1.11
(12474)page278

C402
2

0.1U_0402_10V6K

C358
0.1U_0402_16V4Z

R233
1K_0402_5%

C355
0.1U_0402_16V4Z

1
2

C364
1U_0603_10V6K

P l a c e near ball(VSS) A17

P l a ce near ball AD11
A

Title

ICH5
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
5

C388

0.1U_0402_16V4Z

P l a c e0.1u near ball(VSS)

G 2 4,H24,K24,M24,AD4
a n d AD18; 0.01u near to
ball AD8.

VCCSUS15_A
VCCSUS15_B

AD11

1
2

F19
Y5
AA4
AB4
F7
F8

C24

0.1U_0402_16V4Z

K10
K12
K13
L19
P19
R10
R6
H24
J19
K19
M15
N15
N23
E15
F15
F14
W19
R12
W9
W10
W11
W6
W7
W8
E22

AA6
AB6

1 C389

+1.5VS

+3VALW

R15
R19
T19

0.1U_0402_16V4Z

1 C381

P l a ce near ball(VSS)
D 1 , A 7,H1,P1,W24 and A21

E18
B15
E11
F10
F11
E13
E14
U6
V6
F16
F17
F18
K15

E16

1 C363

V5REF
V5REF

0.1U_0402_16V4Z

1 C385

VCCSUS1_5_A
VCCSUS1_5_B
VCCSUS1_5_B
VCCSUS1_5_B
VCCSUS1_5_C
VCCSUS1_5_C

1 C397

VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5

1 C373

VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3

Power

VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3

ICH5/(ICH5-M)

+CPU_CORE

+3VS

B5
F6
G1
H6
K6
L6
M10
N10
P6
R13
V19
W15
W17
W24
AD13
AD20
G19
G21

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

+3VS

U49C
A1
A7
A10
A15
A17
A19
A21
A23
AA5
AA7
AA9
AA11
AA13
AA21
AA24
AB5
AB7
AB9
AB11
AB15
AB18
AC2
AC4
AC6
AC8
AC10
AC13
AC23
AD4
AD6
AD8
AD17
AD21
AD12
B13
B17
B19
B21
B23
C3
C8
C16
C18
C20
C22
D1
D6
D11
D16
D18
D20
D22
D24
E17
E19
E20
E21
E23
F3
F9
G6
G20
G24
H1
H19
H22
J6
J21
J23
K3
K11
K14
K20
K22
K24
L10
L11
L12
L13
L14
L15
L21
L23
M1
M5
M11
M12
M13
M14
M22
M24
N11
N12
N13
N14
N20
P1
P10
P11
P12
P13

Size
Date:

Compal Electronics, Inc.

ICH5 Power & Decoupling

Document Number

LA-1841

Thursday, February 20, 2003

Sheet

25

Rev
0.1
of

57

LAN Realtek RT8101L

0.1U_0402_16V4Z

C540
@10P_0402_50V8K

ROMCS/OEB
NC

RST#
PCICLK
CLKRUN#
VDD
VDD
VDD
VDD
VDD
VDD
RTL8101L_LQFP100

DGND1
DGND2
DGND3
DGND4
DGND5
AGND1
AGND2
AGND3

Power

51
69
2
16
31
44
88
62
66
73

1
2

LAN_TD+
LAN_TD-

RJ45_TX+
RJ45_TX-

Pulse H0013
(NS0013)

49.9_0603_1%

RJ45_RX+
RJ45_RX-

R313
75_0402_5%

C476
0.1U_0402_16V4Z

R312
75_0402_5%

C485

RJ45_PR

0.1U_0402_16V4Z

10K

R327

0.1U_0402_16V4Z

16
15
14
13
12
11
10
9

Q9
@2SB1197K_SOT23

47K E

R326
49.9_0603_1%

C484

+3V

RX+
RXCT
NC
NC
CT
TX+
TX-

+3VS

reserve transistor for ver.C

+2.5V_LAN

C177

@22U_1206_10V4Z

Y1
25MHZ_20PF_6X25000017
LAN_X1
LAN_X2
C180
27P_0402_50V8J

+3V

100
99

Closed to RT8101L

RD+
RDCT
NC
NC
CT
TD+
TD-

56
1
3
4
5
7

2
15K_0402_5%
2
5.6K_0603_1%

R325
49.9_0603_1%

1
2
3
4
5
6
7
8

63

1
R146
1
R383

R324
49.9_0603_1%

65

2
1K_0402_5%

74

1
R145

64

U28
LAN_RD+
LAN_RD-

LAN_X2

C l osed to PULSE H0013

LAN_X1

60

+3V

61

Layout Note
H 0 013 pls close to
conn.

0.1U_0402_16V4Z

1
2
R384
5.6K_0402_5%

Q38
DTA114YKA_SOT23
1
1
2
R331
300_0402_5%

JP16
12
11
8
7

ACTIVITY#

RJ45_RX-

C179
27P_0402_50V8J

6
5
4

+3V

JP30

2
1

LAN_RD+
LAN_RD-

C504

10K

GPIO0
GPIO1

INTA#
INTB#
PME#

LAN_TD+
LAN_TD-

68
67

+3V

47K E

REQ#
GNT#

ACTIVITY#
LINK10_100#

5
DO
GND 6
DI
NC 7
SK
NC 8
CS
VCC
AT93C46-10SI-2.7_SO8

PERR#
SERR#

AC_RST#
AC_SYNC
AC_DOUT
AC_DIN
AC_BCK

78
77
76

U34

4
3
2
1

VCTRL

LAN_EEDO
LAN_EEDI
LAN_EECLK
LAN_EECS

RTT3

52
53
54
55

TRACE=30mil

PAR
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#

TRACE=20mil

RTSET

Power

ISOLATE#

IDSEL

+3V_LAN_VDD3

NC
NC

RJ45_TX-

RJ45_TX+

Q36
DTA114YKA_SOT23
1
1
2
R314
300_0402_5%

10
9

Amber LED+
Amber LED-

16

SHLD4

PR4-

15

SHLD3

PR4+
PR2-

PR3PR3+
PR2+
PR1-

14

SHLD2

PR1+

13

SHLD1

Green LEDGreen LED+

A M P 440470-4 RJ45 with LED

2
LINK10_100#

RJ45_RX+

12

R393
@10_0402_5%

LWAKE

75

CLK_PCI_LAN

X2

TRACE=20mil

10K

6
22
37
49
90
95

+3V

X1

0.1U_0402_16V4Z
TRACE=20mil

+3V_LAN_VDD2

R15
75_0402_5%

CLK_PCI_LAN

RXIN+
RXIN-

+3V_LAN_VDD1

70

72
71

RTL8101L has internal

+2.5V generator at pin58
+2.5V_LAN
1
2
+3V
L25
LQG21N4R7K10_0805

10,23,27,29,30,36,39
PCIRST#
15 CLK_PCI_LAN
24,27,29,30,36,39
PM_CLKRUN#

81
97
50

27,29,30,39

C/BE#0
C/BE#1
C/BE#2
C/BE#3

TXD+
TXD-

C505

47K

LAN_PME#

80
79
57

23,27 PCI_PIRQB#

LED0
LED1
LED2

C506

83
82

PCI_REQ#3
PCI_GNT#3

EEDO
EEDI
EESK
EECS

C507

23
23

25
26

PCI_PERR#
PCI_SERR#

AVDD

59

TRACE=20mil

23,27,29,30
23,27,29,30

24
18
19
20
21
23

AVDD

+2.5V_LAN

23,27,29,30 PCI_PAR
23,27,29,30 PCI_FRAME#
23,27,29,30 PCI_IRDY#
23,27,29,30 PCI_TRDY#
23,27,29,30 PCI_DEVSEL#
23,27,29,30 PCI_STOP#

98

AVDD

0.1U_0402_16V4Z

58

2 LAN_IDSEL
100_0402_5%

AVDD25

48
94

0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z

C509

1
R395

VDD25
VDD25

C508

PCI_AD17

22U_1206_16V4Z

PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3

38
27
17
84

C534

IDSEL:PCI_AD17

23,27,29,30
23,27,29,30
23,27,29,30
23,27,29,30

PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3

C519

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

PCI I/F
LAN I/F

PCI_AD[0..31]

47
46
45
43
42
41
40
39
36
35
34
33
32
30
29
28
15
14
13
12
11
10
9
8
96
93
92
91
89
87
86
85

Place closed to
RTL8101L pin58

+2.5V_DLAN

U37

AC-Link

23,27,29,30

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

PCI_AD[0..31]

0_0805_5%

TRACE=20mil
+2.5V_LAN
R388

R14
75_0402_5%

NC
SANTA_130403-1
A

C470
1000P_1206_2KV7K

T e r m i n a t i o n p l ane should be copled to chassis ground

@0.1U_0402_16V4Z
1

RJ45_PR

LANGND

C449

C450
4.7U_0805_10V4Z

NC

RJ11

+3V

C527

C516

C550

C549

C536

C529

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

Title

Compal Electronics, Inc.

LAN REALTEK RTL8101L

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
5

Size

Document Number

Rev
0.1

LA-1841
Date:

Thursday, February 20, 2003

Sheet

26

of

57

PCI_AD[31..0]

U5A

PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_DEVSEL#
PCI_REQ#2
PCI_GNT#2
PM_CLKRUN#
PCIRST#

W18
W17
Y18
Y17
W16
Y16
Y15
W19
K20

PCI_AD22
PCI_AD20
R403
PCI_AD21
R407
@100_0402_5%

100_0402_5%

IDSELSM
IDSELSD
IDSELVI
IDSELFL

N16
M16
L16
K16

R406
10K_0402_5%

23,36,39
16,23,30
23,26
23,29
23,29
26,29,30,39

IRQ_SERIRQ
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCM_PME#

T14
W15
V14
V15
U15
U12

R405

100_0402_5%

R404

100_0402_5%

SERIRQ
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCM_PME#

CLK_PCI_PCM

24 SUSCLK

SUSCLK
PCIRST#

39 PCM_SUSP#

PCM_FCMODE
100_0402_5%

R410

+3V

R445
33_0402_5%

C588
10P_0402_50V8K

IRQDT#
INTA#
INTB#
INTC#
INTD#
PME#

T4

SMLED#
SMLOCK#
SMEJCT#

PCICLK
CLK32
PCLR#
SUSPEND#
FCMODE

RSV0
RSV1
RSV2
RSV3
RSV4
RSV5
RSV6
RSV7
RSV8
RSV9
RSV10
RSV11
RSV12
RSV13
RSV14
RSV15
RSV16
RSV17
RSV18
RSV19
RSV20
RSV#0
RSV#1
RSV#2
RSV#3
RSV#4
RSV#5
RSV#6
RSV#7
RSV#8

H6
P6
P15
R5
R6
R7
R15
R16
T6
T15

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

L9
L10
L11
L12
M9
M10
M11
M12

GND
GND
GND
GND
GND
GND
GND
GND

GPIO Interface

CLK_PCI_PCM

IDSELSM
IDSELSD
IDSELVI
IDSELFL

W3
Y11
Y6
U13

SMRB#
SMCD#
SMLVD
SMWPD#
SMEJSW#

SMVC3EN

FRAME#
IRDY#
TRDY#
STOP#
DEVSEL#
REQ#
GNT#
CLKRUN#
PCIRST#

System
Interface

15 CLK_PCI_PCM

SMCLE
SMALE
SMCE#
SMWE#
SMRE#
SMWP#

SDCMD
SDCLK

T1
P1
V13

SDCD#
SDWP#
SDLED

R1

SDPWR

M1
N4
N5
P4
N1
N2
P2
N3

SMD0
SMD1
SMD2
SMD3
SMD4
SMD5
SMD6
SMD7

C586

C556

C584

C574

C589

C561

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

SDLED

43

U41
4

+3V

M3
M2
L1
L3
L2
K3

FLG#
VOUT

SDPWR

CE

GND

3
5

+SD3_VCC

C554

RT9702_SOT23-5

M4
L5
L4
K4
K5

Power Supply

GPO0
GPO1
GPO2
GPO3
GPO4
GPO5
GPO6
GPO7
GPO8
GPO9

P3
V12
W12
Y12
W11
U6
Y4
U9
U10
V9
U4
U5
W4
W2
V2
U3
U2
V6
P5
V1
V5
V4

GND
GND
GND
GND
GND
GND

V10
Y10
T10
T9
W9
Y9
W8
Y8
Y7
W6

R401
22K_0603_5%

4.7U_0805_10V4Z

+3V

M5
K2
K1

V11
Y5
V8
V7
U7
U8
U11
Y3
W7

VIN

+3V

R397

JP2

SDWP#
10K_0402_5%
SDC_D1
SDC_D0

11

SDCMD
SDC_D3

8
7
6
5
4
3
2
1

SDC_D2

SDCLK

+SD3_VCC

Wr_Pt
SD4
SD3
Vss2
SDCLK
Vdd
Vss1
SD2
SD1

Wr_Pt_Vss
VSS

10
12
+3VS
1

PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_DEVSEL#
PCI_REQ#2
PCI_GNT#2
PM_CLKRUN#
PCIRST#

PAR
PERR#
SERR#

SMD0
SMD1
SMD2
SMD3
SMD4
SMD5
SMD6
SMD7

U1
R4

C577

R191
10K_0402_5%

SD5
MMC_DET#
SD_SOCKET

13

Y14
V16
U16

SDCD#
SDWP
SDLED

SDC_D0
SDC_D1
SDC_D2
SDC_D3

PCI_PAR
PCI_PERR#
PCI_SERR#

SDCMD
SDCLK

R2
T2
R3
T3

PCI_PAR
PCI_PERR#
PCI_SERR#

C/BE#0
C/BE#1
C/BE#2
C/BE#3

Other Pins

V20
V19
V18
V17

SDCD0
SDCD1
SDCD2
SDCD3

SDPWR

PCI Interface

PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

SmartMedia Interface

K17
K18
K19
L17
L18
L19
L20
M17
M18
M19
M20
N17
N18
N19
N20
P17
P18
P19
P20
P16
R17
R18
R19
R20
T17
T18
T19
T20
U17
U18
U19
U20

SD Interface

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31

23,26,29,30
23,26,29,30
23,26,29,30
23,26,29,30
23,26,29,30
23
23
24,26,29,30,36,39
10,23,26,29,30,36,39

+3V

PCI_C/BE#[3..0]

PCI_C/BE#[3..0]

23,26,29,30
23,26,29,30
23,26,29,30

SDCD#

+3V

R441

100K_0402_5%

R436

100K_0402_5%

R419
R423
R434
R435

RP111

23,26,29,30
23,26,29,30

PCI_AD[31..0]

SMD3
SMD2
SMD1
SMD7

1
2
3
4

8
7
6
5

+3V

100K_8P4R_1206_5%
RP53
SMD6
SMD4
SMD5
SMD0

100K_0402_5%
100K_0402_5%
100K_0402_5%
100K_0402_5%

1
2
3
4

8
7
6
5

+3V

100K_8P4R_1206_5%
RP54
SDCMD
SDC_D1
SDC_D0
SDC_D2

T5
T16
W1
W20
Y2
Y19

1
2
3
4

8
7
6
5

+SD3_VCC

100K_8P4R_1206_5%

TC6385XB_PBGA328

Compal Electronics, Inc.

Title
PROPRIETARY NOTE

T H I S S H E E T OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
Size
T R A D E S E C RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
D E P A R T M E N T EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
U S E D B Y OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
3

C A R D B U S & SD CONN (1/2)

Document Number
LA-1841
Thursday, February 20, 2003

Rev
0.1
Sheet

27

of

57

RP19
U5B

E19
D20
D18
C20
C18
A18
B18
B17
E14
B13
B12
D13
A16
C14
A14
C16
E17
A13
D14
B14
D15
B15
D16
B16
C17
A17

S2_BVD1
S2_BVD2
S2_CD1#
S2_CD2#
S2_RDY#
S2_WAIT#
S2_WP
S2_INPACK#

E20
E18
G19
H20
A15
C19
G20
D17

S2_CE1#
S2_CE2#
S2_WE#
S2_IORD#
S2_IOWR#
S2_OE#
S2_VS1
S2_VS2
S2_REG#
S2_RST

D12
C12
C15
E13
C13
A12
H18
H19
D19
B19

BVCC3_EN
BVCC5_EN
BEN0
BEN1

J18
J19
J16
J17
T13
E15
F14
F15
F16
G15

+S2_VCC

A19
B20
E16
J11
J12
K11
K12
T7
T8
T11
T12
W14
W13
Y13

SLTA30/D0/CAD27
SLTA31/D1/CAD29
SLTA32/D2/RESERVED
SLTA2/D3/CAD0
SLTA3/D4/CAD1
SLTA4/D5/CAD3
SLTA5/D6/CAD5
SLTA6/D7/CAD7
SLTA64/D8/CAD28
SLTA65/D9/CAD30
SLTA66/D10/CAD31
SLTA37/D11/CAD2
SLTA38/D12/CAD4
SLTA39/D13/CAD6
SLTA40/D14/RESERVED
SLTA41/D15/CAD8

SLTB29/A0/CAD26
SLTB28/A1/CAD25
SLTB27/A2/CAD24
SLTB26/A3/CAD23
SLTB25/A4/CAD22
SLTB24/A5/CAD21
SLTB23/A6/CAD20
SLTB22/A7/CAD18
SLTB12/A8/CCBE#1
SLTB11/A9/CAD14
SLTB8/A10/CAD9
SLTB10/A11/CAD12
SLTB21/A12/CCBE#2
SLTB13/A13/CPAR
SLTB14/A14/CPERR#
SLTB20/A15/CIRDY#
SLTB19/A16/CCLK
SLTB46/A17/CAD16
SLTB47/A18/RESERVED
SLTB48/A19/CBLOCK#
SLTB49/A20/CSTOP#
SLTB50/A21/CDEVSEL#
SLTB53/A22/CTRDY#
SLTB54/A23/CFRAME#
SLTB55/A24/CAD17
SLTB56/A25/CAD19

SLTA29/A0/CAD26
SLTA28/A1/CAD25
SLTA27/A2/CAD24
SLTA26/A3/CAD23
SLTA25/A4/CAD22
SLTA24/A5/CAD21
SLTA23/A6/CAD20
SLTA22/A7/CAD18
SLTA12/A8/CCBE#1
SLTA11/A9/CAD14
SLTA8/A10/CAD9
SLTA10/A11/CAD12
SLTA21/A12/CCBE#2
SLTA13/A13/CPAR
SLTA14/A14/CPERR#
SLTA20/A15/CIRDY#
SLTA19/A16/CCLK
SLTA46/A17/CAD16
SLTA47/A18/RESERVED
SLTA48/A19/CBLOCK#
SLTA49/A20/CSTOP#
SLTA50/A21/CDEVSEL#
SLTA53/A22/CTRDY#
SLTA54/A23/CFRAME#
SLTA55/A24/CAD17
SLTA56/A25/CAD19

SLTB63/BVD1/CSTSCHG
SLTB62/BVD2/CAUDIO
SLTB36/CD#1/CCD#1
SLTB67/CD#2/CCD#2
SLTB16/BSY#/CINT#
SLTB59/WAIT#/CSERR#
SLTB33/WP#/CCLKRUN#
SLTB60/INPACK#/CREQ#

SLTA63/BVD1/CSTSCHG
SLTA62/BVD2/CAUDIO
SLTA36/CD#1/CCD#1
SLTA67/CD#2/CCD#2
SLTA16/BSY#/CINT#
SLTA59/WAIT#/CSERR#
SLTA33/WP#/CCLKRUN#
SLTA60/INPACK#/CREQ#

SLTB7/CE#1/CCBE#0
SLTB42/CE#2/CAD10
SLTB15/WE#/CGNT#
SLTB44/IORD#/CAD13
SLTB45/IOWR#/CAD15
SLTB9/OE#/CAD11
SLTB43/VS1/CVS1
SLTB57/VS2/CVS2
SLTB61/REG#/CCBE#3
SLTB58/RESET/CRST#

SLTA7/CE#1/CCBE#0
SLTA42/CE#2/CAD10
SLTA15/WE#/CGNT#
SLTA44/IORD#/CAD13
SLTA45/IOWR#/CAD15
SLTA9/OE#/CAD11
SLTA43/VS1/CVS1
SLTA57/VS2/CVS2
SLTA61/REG#/CCBE#3
SLTA58/RESET/CRST#

VC3ENB
VC5ENB
VPEN0B
VPEN1B

VC3ENA
VC5ENA
VPEN0A
VPEN1A

ZVBEN

ZVAEN

VCCB
VCCB
VCCB
VCCB
VCCB

VCCA
VCCA
VCCA
VCCA
VCCA

GND
GND
GND
GND
GND
GND
GND

GND
GND
GND
GND
GND
GND
GND

TSTI0
TSTI1
TSTI2
TSTI3

Slot B

Slot A
System
Interface

Test Pins

TSTO1
TSTO2
TSTO3

NC Pins

A8
D9
B9
J3
H5
H2
G5
G3
E9
C9
A9
J2
H3
H1
G4
G2

S1_D0
S1_D1
S1_D2
S1_D3
S1_D4
S1_D5
S1_D6
S1_D7
S1_D8
S1_D9
S1_D10
S1_D11
S1_D12
S1_D13
S1_D14
S1_D15

+3VALW

27

+5VALW

1
3

+12VALW

23

+5VALW

15
17

C8
E8
B7
D7
A6
C6
D6
B5
D4
E2
F3
E4
A4
D2
C4
A3
D5
E1
D3
D1
C3
C1
B2
B4
C5
A5

S1_A0
S1_A1
S1_A2
S1_A3
S1_A4
S1_A5
S1_A6
S1_A7
S1_A8
S1_A9
S1_A10
S1_A11
S1_A12
S1_A13
S1_A14
S1_A15
R_S1_A16
S1_A17
S1_A18
S1_A19
S1_A20
S1_A21
S1_A22
S1_A23
S1_A24
S1_A25

+12VALW

AVCC3_EN
AVCC5_EN
AEN0
AEN1

S1_CE1#
S1_CE2#
S1_WE#
S1_IORD#
S1_IOWR#
S1_OE#
S1_VS1
S1_VS2
S1_REG#
S1_RST

H17
G17
J20
H16

AVCC3_EN
AVCC5_EN
AEN0
AEN1

U14

AVPPIN

AUDIO
ALARM
EXSMI#
NC0
NC1
NC2
NC3

E6
F5
F6
F7
G6

AVPPOUT

AVCC3_EN
AVCC5_EN
AEN0
AEN1

13

BVCC3_EN
BVCC5_EN
BEN0
BEN1

AVCCOUT
AVCCOUT
AVCCOUT

Slot A
Power
Supply

AVCC5IN
AVCC5IN

6
5
7
8

+3VALW

NC0
NC1

BVCC3IN

Slot B
Power
Supply

BVCC5IN
BVCC5IN
BVPPIN

20
19
21
22

BVCCOUT
BVCCOUT
BVCCOUT
BVPPOUT

BVCC3_EN
BVCC5_EN
BEN0
BEN1

GND
GND

2
26
28

+S1_VCC

24

+S1_VPP
C542

AVCC5_EN
AVCC3_EN
AEN0
AEN1

+3VALW

2 S1_A16
R442
33_0402_5%

12
14
16

+S2_VCC

10

+S2_VPP
C531

C215

C544

C538

C537

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0805_25V7K

0.1U_0805_25V7K

C525

0.1U_0402_10V6K

0.1U_0402_10V6K

S1_REG#
S1_A3
S1_INPACK#
S1_A4
S1_WAIT#
S1_A5
S1_RST

C543

C530

0.1U_0402_10V6K

0.1U_0402_10V6K

S1_A6
S1_VS2
S1_A7
S1_A25
S1_A12
S1_A24
S1_A15

C247

+S1_VCC

0.1U_0805_25V7K

+S2_VCC

C551

C521

1U_0805_25V4Z

1U_0805_25V4Z

+S1_VCC
C253
0.1U_0402_10V6K

+S1_VCC

PCM_SPK#

33

A1
A20
Y1
Y20

C576

C575

C585

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

C557

C558

C555

0.1U_0402_10V6K

0.1U_0402_10V6K

0.1U_0402_10V6K

S1_A21
S1_RDY#
S1_A20
S1_WE#
S1_A19
S1_A14
S1_A18
S1_A13
S1_A17
S1_A8
S1_IOWR#
S1_A9
S1_IORD#
S1_A11
S1_VS1
S1_OE#
S1_CE2#

+S1_VCC

W5
V3
W10

S1_A23
S1_A16
S1_A22

+S1_VPP

This area close to MIC2563A-0BSM

A2
B1
E5
J9
J10
K9
K10

S1_WP
S1_CD2#
S1_D2
S1_D10
S1_D1
S1_D9
S1_D0
S1_D8
S1_A0
S1_BVD1
S1_A1
S1_BVD2
S1_A2

+12VALW

C545

S1_A10
S1_D15
S1_CE1#
S1_D14
S1_D7
S1_D13
S1_D6

+S2_VCC

S1_D12
S1_D5
S1_D11
S1_D4
S1_CD1#
S1_D3

C301

1000P_0402_50V7K

TC6385XB_PBGA328
A

1
2
3
4

8
7
6
5
47K_8P4R_1206_5%

JP21

1U_0805_25V4Z

4
18

BVCC5_EN
BVCC3_EN
BEN0
BEN1

CARDBUS
SOCKET

C526

+5VALW

8
7
6
5
47K_8P4R_1206_5%

1000P_0402_50V7K

1
2
3
4

1U_0805_25V4Z

11
25

MIC2563A-0BSM_SSOP28

B8
S1_BVD1
D8
S1_BVD2
J1
S1_CD1#
H4
S1_CD2#
S1_RDY#
B3
E7
S1_WAIT#
A10
S1_WP
C7 S1_INPACK#
G1
F4
C2
F1
E3
F2
J4
J5
A7
B6

AVCC3IN

S2_A0
S2_A1
S2_A2
S2_A3
S2_A4
S2_A5
S2_A6
S2_A7
S2_A8
S2_A9
S2_A10
S2_A11
S2_A12
S2_A13
S2_A14
S2_A15
S2_A16 1
2 R_S2_A16
R402
S2_A17
33_0402_5%
S2_A18
S2_A19
S2_A20
S2_A21
S2_A22
S2_A23
S2_A24
S2_A25

U38

SLTB30/D0/CAD27
SLTB31/D1/CAD29
SLTB32/D2/RESERVED
SLTB2/D3/CAD0
SLTB3/D4/CAD1
SLTB4/D5/CAD3
SLTB5/D6/CAD5
SLTB6/D7/CAD7
SLTB64/D8/CAD28
SLTB65/D9/CAD30
SLTB66/D10/CAD31
SLTB37/D11/CAD2
SLTB38/D12/CAD4
SLTB39/D13/CAD6
SLTBA40/D14/RESERVED
SLTB41/D15/CAD8

F17
F19
G16
E10
C10
E11
C11
A11
F18
F20
G18
D10
B10
D11
B11
E12

S2_D0
S2_D1
S2_D2
S2_D3
S2_D4
S2_D5
S2_D6
S2_D7
S2_D8
S2_D9
S2_D10
S2_D11
S2_D12
S2_D13
S2_D14
S2_D15

RP14

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75

This area close to TC6385XB

a68
a34
a67
a33
a66
a32
a65
a31
GND
a64
a30
a63
a29
a62
a28
a61
GND
a27
a60
a26
a59
a25
a58
a24
GND
a57
a23
a56
a22
a55
a21
a54
GND
a20
a53
a19
a52/a18
none
a51/a17
a16
a50
a15
GND
a49
a14
a48
a13
a47
a12
a46
GND
a11
a45
a10
a44
a9
a43
a8
GND
a42
a7
a41
a6
a40
a5
a39
GND
a4
a38
a3
a37
a2
a36
a1
a35

b68
b34
b67
b33
b66
b32
b65
b31
GND
b64
b30
b63
b29
b62
b28
b61
GND
b27
b60
b26
b59
b25
b58
b24
GND
b57
b23
b56
b22
b55
b21
b54
GND
b20
b53
b19
b52/b18
none
b51/b17
b16
b50
b15
GND
b49
b14
b48
b13
b47
b12
b46
GND
b11
b45
b10
b44
b9
b43
b8
GND
b42
b7
b41
b6
b40
b5
b39
GND
b4
b38
b3
b37
b2
b36
b1
b35

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75

S2_WP
S2_CD2#
S2_D2
S2_D10
S2_D1
S2_D9

C216
1000P_0402_50V7K

S2_D0
S2_D8
S2_A0
S2_BVD1
S2_A1
S2_BVD2
S2_A2
S2_REG#
S2_A3
S2_INPACK#
S2_A4
S2_WAIT#
S2_A5
S2_RST

S2_A6
S2_VS2
S2_A7
S2_A25
S2_A12
S2_A24
S2_A15
S2_A23
S2_A16
S2_A22

C248
0.1U_0805_25V7K
+S2_VPP
+S2_VCC

S2_A21
S2_RDY#
S2_A20

C254
0.1U_0402_10V6K

S2_WE#
S2_A19
S2_A14
S2_A18
S2_A13
S2_A17
S2_A8

S2_IOWR#
S2_A9
S2_IORD#
S2_A11
S2_VS1
S2_OE#
S2_CE2#
S2_A10
S2_D15
S2_CE1#
S2_D14
S2_D7
S2_D13
S2_D6
S2_D12
S2_D5
S2_D11
S2_D4
S2_CD1#
S2_D3

C302
1000P_0402_50V7K
A

PCMC150PIN

Compal Electronics, Inc.

Title
PROPRIETARY NOTE

T H I S S H E E T OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
Size
T R A D E S E C RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
D E P A R T M E N T EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
U S E D B Y OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
3

C A R D B U S & PCMCIA (2/2)

Document Number
LA-1841
Thursday, February 20, 2003

Rev
0.1
Sheet

28

of

57

PCI_AD[0..31]

PCI_AD[0..31]

23,26,27,30

+3V

MINI_PCI SOCKET

24,26,27,30,36,39
PM_CLKRUN#
23,26,27,30 PCI_SERR#
23,26,27,30
23,26,27,30

PCI_PERR#
PCI_C/BE#1

PCI_AD14
PCI_AD12
PCI_AD10
PCI_AD8
PCI_AD7

CLK_PCI_MINI
1

PCI_AD5

R449
@33_0402_5%

PCI_AD3
W=30mils

+5VS_MINIPCI
1 2

PCI_AD1

C593
@10P_0402_50V8K

+5VS

1
L31

2 W=30mils
0_0603_5%
0603

+5VS_MINIPCI

PCI_AD18
PCI_AD16

2 PCI_AD18
100_0402_5%
PCI_PAR

IDSEL : PCI_AD18

23,26,27,30

PCI_FRAME#
PCI_TRDY#
PCI_STOP#

PCI_DEVSEL#

23,26,27,30
23,26,27,30
23,26,27,30

23,26,27,30

PCI_AD15
PCI_AD13
PCI_AD11

+5VS_MINIPCI

C214
@1000P_0402_50V7K

C233
@0.1U_0402_16V4Z

C598
@0.1U_0402_16V4Z

C600
@10U_1206_16V4Z

PCI_AD9

PCI_C/BE#0

PCI_AD6
PCI_AD4
PCI_AD2
PCI_AD0

23,26,27,30

+3VS_MINIPCI
C304
0.1U_0402_16V4Z

W=20mils

C252
0.1U_0402_16V4Z

C255
0.1U_0402_16V4Z

C243
0.1U_0402_16V4Z

C288

PCI_C/BE#2
PCI_IRDY#

1
R440

0.1U_0402_16V4Z

C590
10U_1206_16V4Z

PCI_AD17
23,26,27,30
23,26,27,30

PCI_AD22
PCI_AD20

PCI_AD21
PCI_AD19

PCI_AD28
PCI_AD26
PCI_AD24
MINI_IDSEL

PCI_AD23

26,27,30,39

PCI_C/BE#3

+3V

0_0603_5%

23,26,27,30

WLANPME#
PCI_AD30

23

PCI_AD27
PCI_AD25

PCI_GNT#1

+3VS_MINIPCI
L30
1
2

PCI_AD31
PCI_AD29

W=40mils

PCI_REQ#1

+3V

23

+5VS_MINIPCI
PCI_PIRQC#
23,27

CLK_PCI_MINI

15 CLK_PCI_MINI

W=30mils
PCI_PIRQC#
W=40mils
PCIRST#

PCI_PIRQD#

W=40mils23,27 PCI_PIRQD#

L17

LAN RESERVED

0_0603_5%

4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124

PCIRST#

PCIRST#

RING

+3V

+3VS_MINIPCI

3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123

2
KEY
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124

D9
RB751V_SOD323
1
2

10,23,26,27,30,36,39

JP27
1
KEY
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123

LAN RESERVED

TIP

KILL_SW#

WL_OFF#

2
0.1U_0402_16V4Z

+3V

39
33,38,39

U10
TC7SH08FU_SSOP5

Mini-PCI SLOT

C289
0.1U_0402_16V4Z

Compal Electronics, Inc.

C346

Title

MINI_PCI
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.

Size
B

LA-1841

Date:

Document Number
Thursday, February 20, 2003

Rev
0.1
Sheet

29

of

57

+3VS
1
R526
1
R527
1
R524
1
R267
2
R269

+3VS

23,26,27,29 PCI_C/BE#3
23,26,27,29 PCI_C/BE#2
23,26,27,29 PCI_C/BE#1
23,26,27,29 PCI_C/BE#0
15 CLK_PCI_1394
23
PCI_GNT#0
23
PCI_REQ#0

23,26,27,29 PCI_FRAME#
23,26,27,29 PCI_IRDY#
23,26,27,29 PCI_TRDY#
23,26,27,29 PCI_DEVSEL#
23,26,27,29 PCI_STOP#
23,26,27,29 PCI_PERR#
16,23,27 PCI_PIRQA#
26,27,29,39 1394_PME#
23,26,27,29 PCI_SERR#
23,26,27,29 PCI_PAR
24,26,27,29,36,39
PM_CLKRUN#
10,23,26,27,29,36,39
PCIRST#

PCIRST#

14
CLK_PCI_1394

C696
@10P_0402_50V8K

G_RST

GPIO3
GPIO2

R523
220_0402_5%

C408

C409

C671

C410

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

0.1U_0402_16V4Z

86
96
10
11

CYCLEIN

CYCLEOUT/CARDBUS
CNA
TEST17
TEST16

20
35
48
62
78
VDDP
VDDP
VDDP
VDDP
VDDP

C685

0.1U_0402_16V4Z

PCI BUS INTERFACE

CPS
NC/(TPBIAS1)
NC/(TPA1+)
NC/(TPA1-)
NC/(TPB1+)
NC/(TPB1-)

BIAS CURRENT

R0

15
27
39
51
59
72
88
100
7
1
2
107
108
120
106

+3VS

1394_PLLVDD

0.01U_0402_25V4Z
C407

C403

C400

C396

C670

C672

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

L18
BLM21A601SPT_0805
1
2 +3VS
C404
4.7U_0805_10V4Z

1
R545

2
1K_0402_5%

125
124
123
122
121

118

R564
6.34K_0603_1%

R1

OSCILLATOR

X0

X1

119
6

C702
22P_0402_50V8J
X7
24.576MHz_16P_3XG-24576-43E1

FILTER0

FILTER

FILTER1

C694

0.1U_0402_16V4Z

EEPROM 2 WIRE BUS SDA 92

SCL

POWER CLASS

PC0
PC1
PC2

TPBIAS0
TPA0+
TPA0TPB0 +
TPB0 -

PHY PORT 1

91
99
98
97

116
115
114
113
112

1
R525
1
R521

2
220_0402_5%
2
220_0402_5%

TEST9
TEST8
TEST3
TEST2
TEST1
TEST0

C700
22P_0402_50V8J

R562
56.2_0603_1%

R561
56.2_0603_1%

4
3
2
1
R557
56.2_0603_1%

101
102
104
105

C681
220P_0402_50V8K

TSB43AB21_PQFP128

0.33U_0603_16V4Z
JP35

TPBIAS0
TPA0+
TPA0TPB0+
TPB0-

94
95

C684

R558
56.2_0603_1%

4
3
2
1

SUYIN_020204FR004S507ZL

R556
5.11K_0603_1%

R516
220_0402_5%
1

R583
@10_0402_5%

89
90

C683

0.1U_0402_16V4Z

2 1394_IDSEL
100_0402_5%

TSB43AB21
/(TSB43AB22)

DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
PLLVDD
AVDD
AVDD
AVDD
AVDD
AVDD

1
R563

C675

0.1U_0402_16V4Z

+3VS

PCI_AD16

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_C/BE3
PCI_C/BE2
PCI_C/BE1
PCI_C/BE0
PCI_CLK
PCI_GNT
PCI_REQ
PCI_IDSEL
PCI_FRAME
PCI_IRDY
PCI_TRDY
PCI_DEVSEL
PCI_STOP
PCI_PERR
PCI_INTA/CINT
PCI_PME/CSTSCHG
PCI_SERR
PCI_PAR
PCI_CLKRUN
PCI_RST

C676

IDSEL:PCI_AD16

84
82
81
80
79
77
76
74
71
70
69
67
66
65
63
61
46
45
43
42
41
40
38
37
32
31
29
28
26
25
24
22
34
47
60
73
16
18
19
36
49
50
52
53
54
56
13
21
57
58
12
85

+3VS

2
4.7K_0402_5%
2
10K_0402_5%
2
4.7K_0402_5%
2
4.7K_0402_5%
1
4.7K_0402_5%

PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_C/BE#3
PCI_C/BE#2
PCI_C/BE#1
PCI_C/BE#0
CLK_PCI_1394
PCI_GNT#0
PCI_REQ#0
1394_IDSEL
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_PERR#
PCI_PIRQA#
1394_PME#
PCI_SERR#
PCI_PAR

PLLGND1
REG_EN
AGND
AGND
AGND
AGND
AGND
AGND
AGND
DGND
DGND
REG18
DGND
DGND
DGND
DGND
DGND
DGND
DGND
REG18
DGND

PCI_AD[0..31]

U52

8
9
109
110
111
117
126
127
128
17
23
30
33
44
55
64
68
75
83
93
103

23,26,27,29

PCI_AD[0..31]

87

C695
0.1U_0402_16V4Z

C668
0.1U_0402_16V4Z

Compal Electronics, Inc.

Title

1394 Interface
PROPRIETARY NOTE

T H I S S H E E T OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
Size
T R A D E S E C RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
D E P A R T M E N T EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
U S E D B Y OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
C

Document Number

Rev
0.1

LA-1841
Thursday, February 20, 2003

Sheet
E

30

of

57

AC97 Codec

LINE_IN_L

33

LINE_IN_R

2
R624
2
R621
2
R623
2
R622

1
6.8K_0402_5%
1
6.8K_0402_5%
1
6.8K_0402_5%
1
6.8K_0402_5%

AdjustableOutput

+5VALW
4
LINEIN_L
1U_0603_10V6K
LINEIN_R
1U_0603_10V6K

C741
C738

T H I S S H E E T OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
T R A D E S E C RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
D E P A R T M E N T EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
U S E D B Y OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C432

C434

4.7U_0805_10V4Z

0.1U_0402_16V4Z

34,39,40,41,50,51

7
8

SUSP#

U22
VIN

VOUT

DELAY

SENSE or ADJ

ERROR

CNOISE

SD
SI9182DH-AD_MSOP8

GND

+VDDA

+VDDA

33

PROPRIETARY NOTE

R279

100K_0603_1%

C433

0.1U_0402_16V4Z

C431
4.7U_0805_10V4Z

R278
33K_0603_1%

+AVDD_AC97
1

L36
1

+VDDA

CHB2012U170_0805

+5VCD

+VDDC

+3VS

38

MD_SPK

2
R635

0.01U_0402_25V4Z
33
1
10K_0402_5%

2
R637

1
10K_0402_5%

MIC

CD_L_R
C746
CD_R_R
C744
CD_GNA
C745
MIC
C743

23

LINEIN_R

24

1U_0603_10V6K
1U_0603_10V6K
1U_0603_10V6K
C_MIC
1U_0603_10V6K

+AUD_VREF
C_MD_SPK
1U_0603_10V6K

C750
33

MONO_IN
2
R633

24,38 ICH_AC_RST#

18
20
19
21
22
13
12

1
11
100_0402_5%
10

24,38 ICH_AC_SYNC

24,38 ICH_AC_SDOUT

45
46

33

EAPD

47
48
4
7

LINE_OUT_R

VIDEO_L

MONO_OUT

VIDEO_R

TRUE_LOUT_L

LINE_IN_L

TRUE_LOUT_R

CD_R
CD_GND
MIC1
MIC2
PHONE
PC_BEEP

R627
@0_0402_5%

RESET#
SYNC

SDATA_OUT
NC
XTLSEL
EAPD

SPDIFO
DVSS1
DVSS2

2 CDROM_L

35

LINEL

36

LINER

37
39
41

13

C731

1000P_0402_50V7K

C732

1000P_0402_50V7K

C728

4.7U_0805_10V4Z

EQ_LEFT

C727

4.7U_0805_10V4Z

EQ_RIGHT

1
C752

BIT_CLK

SDATA_IN
XTL_IN

6
8
2

1
R632
1
R636

2
22_0402_5%
2
22_0402_5%

AFILT1
AFILT2

VREFOUT

1
R638

VREF

29

C734

30

VRDA

VRAD
DCVOL
VAUX
GPIO0
GPIO1

NC
AVSS1
AVSS2

27

ICH_AC_SDIN0

C733

1
R617

1000P_0402_50V7K

1000P_0402_50V7K

2
0_0402_5%

X1

40
26
42

35

INT_CD_R

14
11
7

R_INT_CD_R
1U_0603_10V6K

C690

10 CDROM_R

1
R616

DM_ON#
+5VCD

D I RECT PLAY PATH

24,38
2
R601

+2.5VOP_REF

24

22P_0402_25V8K

1
2

1
R_INT_CD_L
10K_0402_5%

C436

14
4
7

C736

C729

0.1U_0402_16V4Z

4.7U_0805_10V4Z

C735

C723

0.01U_0402_25V4Z

1U_0603_10V6K

1 R_INT_CD_R
10K_0402_5%

2
R581

+2.5VOP_REF

U53D
74HCT4066

14
8
7

+5VCD

1U_0603_10V6K

R579
100K_0402_5%

DM_ON#

AGND
1

1
R272
0_0805_5%

1
R277
0_0805_5%

+AUD_VREF

34

DM_ON

DM_ON

2
G

Q61
2N7002_SOT23

CD_GNA
C717

2
1
R628
20K_0402_5%
R472

R629

0_0402_5%

6.8K_0402_5%

0.1U_0402_16V4Z

DM_ON

DIRECT CD

DM_ON

SYSTEM ON

C726
4.7U_0805_10V4Z
Title

CD_AGND
1

35

1
R281
0_0805_5%

EQ_RIGHT

DM_ON

C724

AGND

EQ_LEFT

U53C
74HCT4066

+5VCD

22P_0402_25V8K

+AUD_VREF

2
@0_0402_5%

U53B
74HCT4066

1 24.576MHz_16P_3XG-24576-43E1
C435

32
31
33
34
43
44

32,33

ICH_AC_BITCLK

2
@10K_0402_5%

@1M_0402_5%

28

32,33

EQ_RIGHT

2
15P_0402_50V8J

R280

XTL_OUT

EQ_LEFT

+5VCD

ALC202_E_LQFP48

DGND

U53A
74HCT4066

12

LINE_OUT_L

AUX_R

CD_L

INT_CD_L

0.1U_0402_16V4Z

9
DVDD2

DVDD1

AUX_L

LINE_IN_R

35

C693
14
1
7

R_INT_CD_L

C751

1
20K_0402_5%
1
20K_0402_5%

LINEIN_L

10U_1206_16V4Z

C709
1U_0603_10V6K

CDROM_R

17

1
6.8K_0402_5%
1
6.8K_0402_5%

2
R630
2
R626

16

0.1U_0402_16V4Z

CDROM_L

15

C749

14

C748
0.1U_0402_16V4Z

2
R631
2
R625

38

AVDD1

R634
@0_0402_5%

U58

AVDD2

25

+AUD_VREF

C747

10U_1206_16V4Z

0.1U_0402_16V4Z

C742

POWER ON PATH

+VDDC

C737

Compal Electronics, Inc.

AC97 Codec

DGND

AGND

Size
B
Date:

Document Number

Rev
0.1

LA-1841
Thursday, February 20, 2003

Sheet
1

31

of

57

+5VCD

+5VCD
+5VCD
C423

C422

4.7U_0805_10V4Z

1
R598
2.87K_0603_1%

+5VCD

C701
1800P_0402_50V7K
1
2
R594
1.05K_0603_1%

+5VCD

C703

R618

EQ_L_OUT2

10

13

EQ_L_IN4

LMV824MT_TSSOP14

12

33

OUTPUT TO AMPLIFIER
LEFT CHANNEL

R589
162K_0603_1%
+2.5VOP_REF

AMP_LEFT

LMV824MT_TSSOP14

U56D

4
1200P_0603_50V7K

EQ_L_OUT3

+2.5VOP_REF

OUT

R590
162K_0603_1%

100K_0603_1%

U56C

4
9

EQ_L_IN3

LMV824MT_TSSOP14

11

2700P_0805_50V7K

AMP_LEFT

+5VCD

C705

EQ_L_IN2

AUDIO LEFT CHANNEL

U56B

3300P_0402_50V7K

14 EQ_L_OUT4

OUT

LMV824MT_TSSOP14

C720

+2.5VOP_REF

1000P_0402_50V7K
2

11

C704

4
1
2
R607
5.62K_0603_1%

0.056U_0402

C721

EQ_L_IN5

LMV824MT_TSSOP14

2
4.32K_0603_1%

11

1
R612

EQ_L_OUT1

R614
63.4K_0603_1%

11

+2.5VOP_REF

1
2
R619
2.26K_0603_1%

U57A

U56A

4
C718
0.018U_0603_16V7K

2
EQ_L_IN1#
19.6K_0603_1%
EQ_L_IN1

1
R613

11

EQ_LEFT

C725
0.018U_0603_16V7K

0.1U_0402_16V4Z

BTQ00 EQ Circuit

0.1U_0402_16V4Z

C730
100P_0402_50V8K

C425

B Y - PASS EQ CIRCUIT

+5VCD

0.1U_0402_16V4Z

4
-

12

LMV824MT_TSSOP14

U57D
OUT

11

11

R596

13

14

LMV824MT_TSSOP14
C722
100P_0402_50V8K

100K_0603_1%

1
2
R620
2.26K_0603_1%

1
2
R586
2.87K_0603_1%

C706
1800P_0402_50V7K
1
2
R597
1.05K_0603_1%

+5VCD

R615
100K_0603_1%

LMV824MT_TSSOP14

R585
162K_0603_1%
+2.5VOP_REF

EQ_R_IN3

10

OUT

EQ_R_OUT3

4
9

1200P_0603_50V7K

13

EQ_R_IN4

LMV824MT_TSSOP14

12

R584
162K_0603_1%
+2.5VOP_REF

AMP_RIGHT

AMP_RIGHT

33
B

OUTPUT TO AMPLIFIER
RIGHT CHANNEL

U54D
OUT

7EQ_R_OUT2

U54C

LMV824MT_TSSOP14

+5VCD

C707

2700P_0805_50V7K

U54B

11

EQ_R_IN2

C689

1000P_0402_50V7K

11

EQ_R_IN5

C688

U57B

0.056U_0402

+5VCD

3300P_0402_50V7K

+2.5VOP_REF

2
4.32K_0603_1%

C713

1
2
R602
5.62K_0603_1%

11

LMV824MT_TSSOP14

C712

AUDIO RIGHT CHANNEL

1
R600

EQ_R_OUT1

R606
63.4K_0603_1%

P
O

11

+5VCD

14 EQ_R_OUT4

LMV824MT_TSSOP14

U54A

4
+2.5VOP_REF

11

C710
0.018U_0603_16V7K

2
EQ_R_IN1#
19.6K_0603_1%
EQ_R_IN1
1

1
R603

C719
0.018U_0603_16V7K

OUT

M
C708

C420
0.1U_0402_16V4Z

EQ_RIGHT

4.7U_0805_10V4Z

C418

4.7U_0805_10V4Z

C421

10

+5VCD

U57C

100K_0603_1%
+5VCD

+5VCD

+2.5VOP_REF

R595

31,33 EQ_RIGHT

+5VCD

AMP_LEFT
1
@0_0402_5%
1
AMP_RIGHT
@0_0402_5%

2
R609
2
R608

EQ_RIGHT

EQ_LEFT

31,33 EQ_LEFT

Title
PROPRIETARY NOTE

T H I S S H E E T OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
Size
T R A D E S E C RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
D E P A R T M E N T EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
U S E D B Y OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
3

Compal Electronics, Inc.

HAREWARE EQ
Document Number

Rev
0.1

LA-1841
Thursday, February 20, 2003

Sheet

32

of

57

Audio AMP

+5VCD

+5VCD

R591
100K_0402_5%
SHUTDOWN#

C711

C415

0.1U_0402_16V4Z

4.7U_0805_10V4Z

W=40Mil

HIGH

P IN 6,20 ACTIVE

LOW

P IN 5,23 ACTIVE

2
G
R605
Q62
2N7002_SOT23

EAPD

0_0402_5%

31

NBA_PLUG

R604
@100K_0402_5%
1
2

32

AMP_LEFT

C430

0.47U_0603_16V4Z

C755

1U_0603_10V6K

C419

0.47U_0603_16V4Z

C756

1U_0603_10V6K

EQ_LEFT

C429

0.47U_0603_16V4Z

EQ_RIGHT

C414

0.47U_0603_16V4Z

31,32

EQ_LEFT
EQ_RIGHT

17

R649

BEEP#

C699
0.1U_0402_16V4Z

+3V POWER

R641
10K_0402_5%

2
B

+5VCD
+AVDD_AC97
+AUD_VREF

31
31

Q63

MONO_IN

MIC

MIC

LINE_IN_R
LINE_IN_L

LINE_IN_R
LINE_IN_L

29,38,39

31

2SC2411K_SOT23

KILL_SW#

INTSPK_R1
INTSPK_L2
INTSPK_L1
KILL_SW#

R639
2.4K_0402_5%

16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
JP10
ACES_85201-1605

1
4

C716

R611
560_0402_5%
1
2
1

U55B
1U_0603_10V6K
SN74LVC14APWLE_TSSOP14
+3V POWER

R642

D35
RB751V_SOD323

10K_0402_5%

Title
PROPRIETARY NOTE

NBA_PLUG
VOL_AMP

14
P
G

AUDIO Board Conn.

C754
10U_1206_16V4Z

+3V

1
2
MOLEX_53398-0290

R447
560_0402_5%
1
2

1U_0603_10V6K

JP9

INTSPK_R1
INTSPK_R2

31

C753
1U_0603_10V6K
MONO_IN

SN74LVC14APWLE_TSSOP14

PCM_SPK#

SPKR

1U_0603_10V6K

C587

24

0.47U_0603_16V4Z
1U_0603_10V6K
0.47U_0603_16V4Z

P
O

R610
560_0402_5%
1
2

C714

C715

0.22U_0603_16V4Z
28

C427

R640
10K_0402_5%

U51C
+3V POWER
SN74LVC125APWLE_TSSOP14

1
2
R599
8.2K_0402_5%

C426

14

U55A

10
OE#

* C428

+5VCD

+VDDA

100K_0402_5%

1
2
R592
100K_0402_5%

INTSPK_L2
INTSPK_R2

1
12
13
24

CLK
TPA0232PWP_TSSOP24

NBA_PLUG
0.1U_0402_16V4Z

R593

+3V

39
2

C417

+3V

GND
GND
GND
GND

22
15
14
11
9
16
10
8

1.2K_0603_0.5%
1

1.2K_0603_0.5%

HP/LINE#
VOLUME
LOUT+
ROUT+
LLINEIN
RLINEIN
LHPIN
RHPIN

SHUTDOWN#
SE/BTL#
PC-BEEP
BYPASS
LOUTROUTLIN
RIN

0.1U_0402_16V4Z

2
R648

PVDD
PVDD
VDD

C416
0.047U_0402_16V4Z

C424

U21

2
3
4
21
5
23
6
20

VOL_AMP
INTSPK_L1
INTSPK_R1

32 AMP_RIGHT

31,32

7
18
19

NBA_PLUG

T H I S S H E E T OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
Size
T R A D E S E C RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
D E P A R T M E N T EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
U S E D B Y OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
C

Compal Electronics, Inc.

AMP & Audio Jack
Document Number

Rev
0.1

LA-1841
Thursday, February 20, 2003

Sheet
E

33

of

57

35

CDD[0..15]

CDD[0..15]

L35
CHB1608G301_0603
1
2

+5VOZ

1
2
L34
CHB1608G301_0603

IDE_SDIOR#
IDE_SDIOW#

99
6
72
93

IDE_IRQ15
IDE_SDDREQ
IDE_SDDACK#

74
12
88

SIDE_RST#

24
59

24,35 IDE_SDIORDY

48
53
55
50
46

DM_ON
PLAYBTN#
FRDBTN#
REVBTN#
STOPBTN#

210U_1206_16V4Z

28
36
35
34
37

DM_ON

Q50
3 2N7002

5,39 EC_SMB_CK2

S
1

Q49
2N7002

R496

OSC1
OSC2

R497
100K_0402_5%
2

+5VCD

26
27

2
1
R498
10K_0402_5%
1
2
D31
1N4148_SOT23 5,39 EC_SMB_DA2

29
25
30

100K_0402_5%

CHINTRQ
CDMARQ
CHDMACK#

HRESET#
HDASPN

CRESET#
CDASPN

HSYNC
HBIT_CLK
HDATA_OUT
HDATA_IN
HACRSTN
PAV_EN
PLAY/PAUSE
FFORWARD
REWIND
STOP/EJECT
PCSYSTEM_OFF
INTN
RESET#

SSYNC
SBIT_CLK
SDATA_OUT
SDATA_IN
SACRSTN

31
32

CD_SBA0
CD_SBA1
CD_SBA2

64
62

CD_SCS1#
CD_SCS3#

CD_SCS1#
CD_SCS3#

35
35

100
5
73
94

CD_SIOR#
CD_SIOW#
CIOCS16#
CD_SIORDY

CD_SIOR#
CD_SIOW#

35
35

CD_IRQ
CD_DREQ
CD_DACK#

CD_IRQ
CD_DREQ
CD_DACK#

75
13
89
23
60
47
52
54
49
45

PWR_CTL

ISCDROM

GPIO[1]/VOL_UP
GPIO[0]/VOL_DN

51
80
39
40
56
57

MODE0
MODE1

SDATA

PAVMODE

SCLK

CSN
INCN
UDN

OSCI
OSCO

38
41
42
43

2
2
1

+5VCD

2
240K_0402_5%

2
C611

31,39,40,41,50,51

1
1U_0805_25V4Z

R538

1
R514
GPIO_1
GPIO_0

2
R235

Q46
@DTC124EK_SOT23

10U_1206_16V4Z

22K

C604
0.1U_0402_16V4Z

2 CD_PLAY

22K

CD_PLAY

39

22K
Q44
DTC124EK_SOT23

35
35
35

35

+5VCD

+5VCD

1
R518

2 ISCDROM
@0_0402_5%

R532 1
MODE1

C608

22K

35

CD_RSTDRV#

1
@10K_0402_5%
R539
1
10K_0402_5%

8
S
D 7
S
D 6
S
D 5
G
D
SI4425DY-T1_SO8

2
1
R469
10K_0402_5%

SUSP#

SUSP#

U43

1
R470

35
35
35

CD_SIORDY

CD_RSTDRV#
CDASPN

1
2
3
4

2
1

58

44

HINTRQ
HDMARQ
HDMACK#

CD_SBA0
CD_SBA1
CD_SBA2

2
0_0402_5%

MEDIA_DETECT

REVBTN#
FRDBTN#
PLAYBTN#
STOPBTN#

39

8
7
6
5

RP83

1
2
3
4

10K_8P4R_1206_5%
8
7
6
5

MODE1
CDASPN
ISCDROM

2 @1K_0402_5%

RP84

1
2
3
4

10K_8P4R_1206_5%

1
10K_0402_5%

GPIO_0
GPIO_1

R244
R237

2
2

1
1

10K_0402_5%
10K_0402_5%
+5VCD

+5VCD

CD_SIORDY

2
C365 1
+5VCD

C659
10P_0402_50V8K

CDIOR#
CDIOW#
CIOCS16#
CIORDY

1U_0805_25V4Z

+5VALW

69
71
67

1M_0402_5%
C651
10P_0402_50V8K

HDIOR#
HDIOW#
HIOCS16#
HIORDY

C609

+5VALW

R228
100K_0402_5%

SIDE_RST#

CCS0
CCS1

10U_1206_16V4Z

35

R510

HCS0
HCS1

C606

SUSP#

DM_ON
D

2
G

DM_ON

DIRECT CD

DM_ON

SYSTEM ON

CD_IRQ
CIOCS16#

DM_ON

CDD7

31

Q14

CD_DREQ

2N7002

R509
R534
R533
R506
R495

1K_0402_5%
4.7K_0402_5%
47K_0402_5%
10K_0402_5%
5.6K_0402_5%

S
3

23,35 IDE_IRQ15
24,35 IDE_SDDREQ
24,35 IDE_SDDACK#

CDA0
CDA1
CDA2

+5VALW

CDD0
CDD1
CDD2
CDD3
CDD4
CDD5
CDD6
CDD7
CDD8
CDD9
CDD10
CDD11
CDD12
CDD13
CDD14
CDD15

GND
GND
GND
GND
GND

X4
8MHZ_16PF_7D08000014
OSC1
OSC2

HDA0
HDA1
HDA2

77
79
82
84
87
91
96
98
1
3
7
10
14
17
19
21

24,35 IDE_SDIOR#
24,35 IDE_SDIOW#

CDD0
CDD1
CDD2
CDD3
CDD4
CDD5
CDD6
CDD7
CDD8
CDD9
CDD10
CDD11
CDD12
CDD13
CDD14
CDD15

63
61

+5VCD

0.1U_0402_16V4Z

IDE_SDCS1#
IDE_SDCS3#

C642

24,35 IDE_SDCS1#
24,35 IDE_SDCS3#

0.1U_0402_16V4Z

68
70
66

HDD0
HDD1
HDD2
HDD3
HDD4
HDD5
HDD6
HDD7
HDD8
HDD9
HDD10
HDD11
HDD12
HDD13
HDD14
HDD15

IDE_SDA0
IDE_SDA1
IDE_SDA2

24,35 IDE_SDA0
24,35 IDE_SDA1
24,35 IDE_SDA2

VDD

76
78
81
83
86
90
95
97
2
4
8
11
15
18
20
22

VDD

IDE_SDD0
IDE_SDD1
IDE_SDD2
IDE_SDD3
IDE_SDD4
IDE_SDD5
IDE_SDD6
IDE_SDD7
IDE_SDD8
IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15

0.1U_0402_16V4Z

C641

U46
OZ168T-A1_TQFP100

16
33
65
85
92

24,35 IDE_SDD[0..15]

VDD

0.1U_0402_16V4Z

C662

C673

+5VOZ

Compal Electronics, Inc.

Title

OZ-168 CD_PLAY
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.

Size
B

LA-1841

Date:

Document Number
Thursday, February 20, 2003

Rev
0.1
Sheet

34

of

57

IDE,CD-ROM Module CONN.

HDD CONNECTOR

Placea caps. near HDD

CONN.

IDE_PDD[0..15]

24 IDE_PDD[0..15]

+5VS

C645
0.1U_0402_16V4Z

+5VS

IDE_IRQ14
IDE_PDA1
IDE_PDA0
IDE_PDCS1#
2
100K_0402_5%

+5VS

PCSEL

1
R236

C654

C656

C657

C655

C653

1000P_0402_50V7K

10U_1206_16V4Z

10U_1206_16V4Z

1U_0805_25V4Z

0.1U_0402_16V4Z

B_PCIRST#

16,23 B_PCIRST#
23

4 PIDE_RST#

PIDERST#

IDE_PDA2
IDE_PDCS3#

EXTID1

IDE_PDA2
24
IDE_PDCS3#
24

+5VS

EXTID0

Module

CDROM

FDD

HDD

T V Tuner/No Module

B_PCIRST#
24

TC7SH08FU_SSOP5

+5VS

C652
0.1U_0402_16V4Z

2
470_0402_5%

U47

IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15

IDE_PDDREQ
IDE_PDIOW#
IDE_PDIOR#

IDE_PDDREQ
IDE_PDIOW#
IDE_PDIOR#
IDE_PDIORDY
IDE_PDDACK#
IDE_IRQ14
IDE_PDA1
IDE_PDA0
IDE_PDCS1#
PHDD_LED#
1
+5VS
R259

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44

U48

4 SIDE_RST#

SIDERST#

24
24
24
24
24
23
24
24
24
39

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43

JP34
PIDE_RST#
IDE_PDD7
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
IDE_PDD0

SIDE_RST#

34

TC7SH08FU_SSOP5

OCTEK AFH-22DC

EXTID2

Module

CDROM

FDD

EXTID3

1
1

Main Module Conn. (Master)

2
R471
36
36
36
36
36
36
36
36,39

RDATA#
WP#
TRACK0#
WDATA#
STEP#
MTR0#
DSKCHG#
DRV0#

RDATA#
WP#
TRACK0#
WDATA#
STEP#
MTR0#
DSKCHG#
DRV0#

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
SUYIN_100311MB060S106ZU

INT_CD_R
CD_AGND
CDD8
CDD9
CDD10
CDD11
CDD12
CDD13
CDD14
CDD15
CD_DREQ
CD_SIOR#
CD_DACK#
CD_SBA2
CD_SCS3#
EXTID0
EXTID1
HDSEL#
WGATE#
USBP7+
USBP7FDDIR#
3MODE#
INDEX#

INT_CD_R

31

CD_DREQ
CD_SIOR#
CD_DACK#
CD_SBA2
CD_SCS3#
EXTID0
EXTID1

34
34
34
34
34
39
39

HDSEL#
WGATE#

36
36

USBP7+
USBP7-

24
24

FDDIR#
3MODE#

36
36

INDEX#

36

SIDE_RST#
IDE_SDD7
IDE_SDD6
IDE_SDD5
IDE_SDD4
IDE_SDD3
IDE_SDD2
IDE_SDD1
IDE_SDD0

24,34 IDE_SDIOW#
24,34 IDE_SDIORDY
23,34 IDE_IRQ15
24,34 IDE_SDA1
24,34 IDE_SDA0
24,34 IDE_SDCS1#

+5VCD

+5VS
W=80mils

C610

C616

C613

1000P_0402_50V7K

10U_1206_16V4Z

1U_0805_25V4Z

0.1U_0402_16V4Z

P l a c e c o m p o n e n t ' s closely MODULE CONNECTOR.

+5VS
1
2
3
4

RP138

8
7
6
5

1K_8P4R_1206_5%

MTR0#
DSKCHG#
INDEX#
DRV0#

STEP#
WDATA#
FDDIR#
TRACK0#
+5VS

6
7
8
9
10

RP139

5
4
3
2
1

1K_10P8R_1206_5%

S
WP#
RDATA#
WGATE#
HDSEL#

+5VS

IDE_SDDREQ
24,34
IDE_SDIOR#
24,34
IDE_SDDACK#
24,34
IDE_SDA2
24,34
IDE_SDCS3#
24,34
EXTID2
39
EXTID3
39

+5VCD

R464
100K_0402_5%
USBP3+
USBP3-

USBP3+
USBP3-

24
24

SHDD_LED#

SHDD_LED#

1
R468
2
G
Q45
2N7002_SOT23

2 EXTCSEL2
470_0402_5%
EXTID0

39

+5VS

+3VALW
W=80mils

R467
100K_0402_5%
1

C612

IDE_SDD8
IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15
IDE_SDDREQ
IDE_SDIOR#
IDE_SDDACK#
IDE_SDA2
IDE_SDCS3#
EXTID2
EXTID3

+5VS

+5VCD

IDE_SDIOW#
IDE_SIORDY
IDE_IRQ15
IDE_SDA1
IDE_SDA0
IDE_SDCS1#
SHDD_LED#
EXTCSEL2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
SUYIN_100311MB060S106ZU

CD_SIOW#
CD_SIORDY
CD_IRQ
CD_SBA1
CD_SBA0
CD_SCS1#
SHDD_LED#
1 EXTCSEL1
470_0402_5%

JP29

JP28

CD_SIOW#
CD_SIORDY
CD_IRQ
CD_SBA1
CD_SBA0
CD_SCS1#

2nd Module Conn. (Slave)

34
34
34
34
34
34

T V Tuner/No Module

INT_CD_L
CD_AGND
CD_RSTDRV#
CDD7
CDD6
CDD5
CDD4
CDD3
CDD2
CDD1
CDD0

31
INT_CD_L
31
CD_AGND
34 CD_RSTDRV#

HDD

IDE_SDD[0..15]

24,34 IDE_SDD[0..15]

CDD[0..15]

CDD[0..15]

34

C615

C617

C620

C614

1000P_0402_50V7K

10U_1206_16V4Z

1U_0805_25V4Z

0.1U_0402_16V4Z

EXTID0
EXTID1
EXTID2
EXTID3

8
7
6
5

RP82

1
2
3
4

10K_8P4R_1206_5%

P l a c e c o m p o n e n t ' s closely MODULE CONNECTOR.

Compal Electronics, Inc.

Title

IDE/ FDDMODULECONN.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.

Size
B

LA-1841

Document Number

Date:

Thursday, February 20, 2003

Rev
0.1
Sheet

35

of

57

SUPER I/O SMsC FDC47N227

+3VS
1

R209
10K_0402_5%

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

20
21
22
23
24
25

24,39 LPC_FRAME#
24 LPC_DRQ#1
10,23,26,27,29,30,39

26
27

PCIRST#
R195
R212

+3VS
23,27,39 SERIRQ
24,26,27,29,30,39
PM_CLKRUN#
15 CLK_PCI_SIO

CLK_14M_SIO
R214
@10_0402_5%

22

11

15 CLK_14M_SIO

38

10K_0402_5%
10K_0402_5%

CLK_PCI_SIO

50
17
30
28
29

CLK_14M_SIO

19
PID0
PID1
PID2
PID3

48
54
55
56
57
58
59
6
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47

BT_DET#
1
R643

+3VS

1
1

PID[0..3]

PID[0..3]

C341
@15P_0402_50V8J

2
2

2
10K_0402_5%

CLK_PCI_SIO
2

37

FIR_EN#
1
R644

+3VS

2
10K_0402_5%

1 C330
@22P_0402_25V8K
2

2
R194
2
R192

1
10K_0402_5%
1
10K_0402_5%

51
52
64
18

+3VS

PD0/INDEX#
PD1/TRK0
PD2/WRTPRT#
PD3/RDATA#
PD4/DSKCHG#
PD5
PD6/MTR0#
PD7

LFRAME#
LDRQ#
PCIRST#
LPCPD#

BUSY/MTR1#
PE/WDATA#
SLCT/WGATE#
ERROR#/HDSEL#
ACK#/DS1#
INIT#/DIR#
AUTOFD#/DRVDEN0#
STROBE#/DS0#
SLCTIN#/STEP#

GPIO12/IO_SMI#
IO_PME#
SIRQ
CLKRUN#
PCICLK
CLK14
GPIO10
GPIO15
GPIO16
GPIO17
GPIO20
GPIO21
GPIO22
GPIO24
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO40
GPIO41
GPIO42
GPIO43
GPIO44
GPIO45
GPIO46
GPIO47

DTR2#
CTS2#
RTS2#
DSR2#
TXD2
RXD2
DCD2#
RI2#
DTR1#
CTS1#
RTS1#
DSR1#
TXD1
RXD1
DCD1#
RI1#

IRMODE/IRRX3
IRRX2
IRTX2

RDATA#
WDATA#
WGATE#
HDSEL#
DIR#
STEP#
DS0#
INDEX#
DSKCHG#
WRTPRT#
TRK0#
MTR0#
DRVDEN0

GPIO13/IRQIN1
GPIO14/IRQIN2
GPIO23/FDC_PP
VTR

VCC
VCC
VCC

N
1

C340

0.1U_0402_16V4Z

C286
0.1U_0402_16V4Z

C315

0.1U_0402_16V4Z
2

4.7U_0805_10V4Z

53
65
93

C285

LAD0
LAD1
LAD2
LAD3

68
69
70
71
72
73
74
75

LPD0
LPD1
LPD2
LPD3
LPD4
LPD5
LPD6
LPD7

79
78
77
81
80
66
82
83
67

LPTBUSY
LPTPE
LPTSLCT
LPTERR#
LPTACK#

100
99
98
97
96
95
94
92
89
88
87
86
85
84
91
90

R208
@33_0402_5%

LPD[0..7]

U8

7
31
60
76

LPD[0..7]

LPTBUSY
LPTPE
LPTSLCT
LPTERR#
LPTACK#
INIT#
LPTAFD#
LPTSTB#
SLCTIN#

VSS
VSS
VSS
VSS

DRVDEN1
GPIO11/SYSOPT

L P C 4 7 N227 TQFP100 SUPER I/O

63
61
62
16
10
11
12
8
9
5
13
4
15
14
3
1
2
49

38

38
38
38
38
38
38
38
38
38

DSR#1
CTS#1
RI#1
DCD#1

CTS#2
DSR#2

LPC_AD[0..3]

24,39 LPC_AD[0..3]

1
R206

DCD#2
RI#2
DTR#1
CTS#1
RTS#1
DSR#1
TXD1
RXD1
DCD#1
RI#1

1
R199

IRRX
RDATA#
WDATA#
WGATE#
HDSEL#
FDDIR#
STEP#
DRV0#
INDEX#
DSKCHG#
WP#
TRACK0#
MTR0#
2
R213
1
R198

8
7
6
5

RP112

+3VS
1
2
3
4

CTS#2
DSR#2
DCD#2
RI#2

4.7K_8P4R_1206_5%

1
2
3
4

RP113

+3VS
8
7
6
5

4.7K_8P4R_1206_5%

2
1K_0402_5%
+5V
JP32

2
1K_0402_5%
IRMODE
IRRX
IRTXOUT

37
37
37

RDATA#
WDATA#
WGATE#
HDSEL#
FDDIR#
STEP#
DRV0#
INDEX#
DSKCHG#
WP#
TRACK0#
MTR0#
3MODE#

35
35
35
35
35
35
35,39
35
35
35
35
35
35

1
10K_0402_5%
2
1K_0402_5%

IRRX

1
2
3
4
5
6
7
8
9
10

RXD1
TXD1
DSR#1
RTS#1
CTS#1
DTR#1
RI#1
DCD#1

1
2
R193
1K_0402_5%

1
2
3
4
5
6
7
8
9
10
@96212-1011S

+5VS

B ase I/O Address

* 0 = 02Eh
1 = 04Eh

Compal Electronics, Inc.

Title

SUPERI/O
PROPRIETARY NOTE

T H I S S H E E T OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
Size
T R A D E S E C RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
D E P A R T M E N T EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
U S E D B Y OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
C

Document Number

Rev
0.1

LA-1841
Thursday, February 20, 2003

Sheet
E

36

of

57

+USB_BS

+3VALW

+USB_AS

+USB_BS

+USB_AS
1

R173

R174

100K_0402_5%

100K_0402_5%

C250

1
2
R175
47_0402_5%
1
2
R176
47_0402_5%

0.1U_0402_16V4Z

8
7
6
5

2
USB_OC0#

USB_OC0#

24

USB_OC2#

USB_OC2#

24

C230

150U_D2_6.3VM

R44
0_0603_5%
1
1
R45
0_0603_5%

USBP0USBP0+

0.1U_0402_16V4Z

470P_0402_50V7K

2
2

1 C3

USB0USB0+

1
2
3
4

JP17
VCC
D0D0+
VSS

VCC
D1D1+
VSS

5
6
7
8

9
G2
G1 11
G4
G3
SUYIN_020122MR008S516ZU

C465

470P_0402_50V7K

R46
0_0603_5%
1
1
R47
0_0603_5%

USB2USB2+

10
12

150U_D2_6.3VM

2
2

USBP2USBP2+

24
24

2 USBEN#
@0_0402_5%

1
R182

USB_EN#

0.1U_0402_16V4Z

R177

(New)

0_0402_5%

+USB_DS
+USB_CS

+USB_CS

1
2
R240
47_0402_5%
1
2
R239
47_0402_5%

USB_OC4#
USB_OC6#

USB_OC4#
USB_OC6#

USBP4USBP4+

C375

0.1U_0402_16V4Z

+3VS

FIR Module

+3VS

470P_0402_50V7K

R247
0_0603_5%
1
1
R250
0_0603_5%

2
2

USB4USB4+

1
2
3
4

JP33
VCC
D0D0+
VSS

VCC
D1D1+
VSS

5
6
7
8

USB6USB6+

10
12

9
G2
G1 11
G4
G3
SUYIN_020122MR008S516ZU

C658

470P_0402_50V7K

R252
0_0603_5%
1
1
R256
0_0603_5%

150U_D2_6.3VM

2
2

USBP6USBP6+

24
24

C82

22U_1206_10V4Z

(New)

+IR_ANODE

1
2
R99
@3.3_1206_5%
1
2
R87
3.3_1206_5%

1
+ C81

R80

2
1
R85
10K_0402_5%

47_1206_5%
1

4.7U_0805_6.3VM

1 C64
2

24

24
24

1
C370

0.1U_0402_16V4Z

USBEN#

24

C376

150U_D2_6.3VM

C369

100K_0402_5%

100K_0402_5%

0.1U_0402_16V4Z

8
7
6
5

36

+IR_VCC

IRRX

C348

100P_0402_50V8J
2

+
C350
150U_D2_6.3VM

1
1

U12
GND
OC1#
IN
OUT1
EN1#
OUT2
EN2#
OC2#
TPS2042ADR_SO8

R242

+5V

R243

C660

1
2
3
4

+USB_DS

+3VALW

24

24
24

C231

1
+
C251
150U_D2_6.3VM

U4
GND
OC1#
IN
OUT1
EN1#
OUT2
EN2#
OC2#
TPS2042ADR_SO8

1
2
3
4

+5V

1 C11

C467

36

C63
0.1U_0402_16V4Z
+IR_GND

FIR_EN#

1
R645

2
10K_0402_5%

IRRX

U2
2
4
6
8

1
IRED_A 3
IRED_C
TXD 5
RXD
SD/MODE 7
VCC
MODE
GND
I R _ VISHAY_TFDU6101E-TR4_8P

+IR_ANODE
IRTXOUT
IRMODE

IRTXOUT
IRMODE

36
36

The component's most place

cloely IRDA MODULE.

LOW FIR Poped

H I GH FIR Un-Poped

Compal Electronics, Inc.

Title

FIR_EN#

USB Conn.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.

Size
B

LA-1841

Document Number

Date:

Thursday, February 20, 2003

Rev
0.1
Sheet

37

of

57

BlueTooth Interface
MDC CONN.

+5VS

R72
100K_0402_5%

1
R83

+3VS_MDC

3
ICH_AC_SDIN1

C80
1U_0805_25V4Z

BT_PWR

29,33,39

Q6

36

SLCTIN#

1
R2

+5V_PRN
LPTSLCTIN#
LPTINIT#
LPTERR#
AFD#/3M#

+5V_PRN

LPD0
LPD1
LPD2
LPD3

1
2
3
4

LPD7
LPD6
LPD5
LPD4

1
2
3
4

36

10
9
8
7
6

8
7
6
5

FD0
FD1
FD2
FD3

68_8P4R_1206_5%
8
FD7
7
FD6
FD5
6
5
FD4
RP1
68_8P4R_1206_5%

FD4
FD5
FD6
FD7

RP3
2.7K_10P8R_1206_5%

2
LPTSLCTIN#
33_0402_5%
RP2

LPD[0..7]

INIT#

1
2
3
4
5
FD3
FD2
FD1
FD0

+5VS

D21

USBP5+
USBP5-

USBP5+
USBP5-

R338
R333

0_0603_5%
0_0603_5%

36

LPTSTB#

LPTSTB#

R303
33_0402_5%
1
2

+BT_VCC
(MAX=200mA)

LPTAFD#

36

LPTERR#

1
FD0
R302
LPTERR#
FD1
LPTINIT#
FD2
LPTSLCTIN#
FD3

LPD[0..7]

FD4
FD5
FD6

36

LPTACK#

36

LPTBUSY

36
36

LPTPE
LPTSLCT

LPTACK#
LPTBUSY
LPTPE
LPTSLCT

C477

0.1U_0402_16V4Z

Bluetooth Connector

R304
2.2K_0402_5%

AFD#/3M#

36

USB5+
USB5-

PARALLEL PORT

RB420D_SOT23

FD7

+5V_PRN

24
24

+5V_PRN

36

LPTINIT#
2
33_0402_5%

2
0_0402_5%

BT_RESET#
BT_WAKE_UP

39 BT_DETACH

10
9
8
7
6

1
R344

1
R3

BT_DET#

39 BT_WAKE_UP

BT_RESET#

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
ACES_87153-2008
(Top Contact)

Module ID
Module_Detect

U30

BT_RST#

JP18
36

@TC7SH08FU_SSOP5

1
2
3
4
5

RP87
2.7K_10P8R_1206_5%

10U_1206_16V4Z

DTC124EK_SOT23

Module ID
I n d i cation for polarity of reset
R e s e t i nput High Active --> Low ,
R e s e t input Low Active --> Open

+3VS

KILL_SW#

39

LPTSLCT
LPTPE
LPTBUSY
LPTACK#

+BT_VCC
C25

24,31

C495
1U_0805_25V4Z

+5V_PRN

22K
22K

C489
@0.1U_0402_16V4Z

39

24

ICH_AC_BITCLK

+5VS_MDC

1
C98
1U_0805_25V4Z

1
2
R79
22_0402_5%
2

24,31

Q7
SI2301DS-T1_SOT23

C27
0.1U_0402_16V4Z

ICH_AC_SYNC

1
R78
22_0402_5%

ACES_88023-3010

+3V

1
2
+5VS
L23
CHB1608B121_0603
1
2
+3VS
R350
10K_0402_5%

2
0_0402_5%

0.1U_0402_16V4Z

+5VS_MDC

C76

31
1

MD_SPK

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30

AUDIO_PWDN
MONO_PHONE
Bluetooth Enable
GND
+5V
USB Data+
USB DataPRIMARY DN
5Vd
GND
AC97_SYNC
AC97_SDATA_IN1
AC97_SDATA_IN0
GND
AC97_BITCLK

+3VS
24,31 ICH_AC_SDOUT
24,31 ICH_AC_RST#

MONO_OUT/PC_BEEP
GND
AUXA_RIGHT
AUXA_LEFT
CD_GND
CD_RIGHT
CD_LEFT
GND
3.3Vaux
GND
3.3Vmain
AC97_SDATA_OUT
AC97_RESET#
GND
AC97_MSTRCLK

+3V

R100
0_0402_5%
1
2
L22
1
2 +3VS_MDC
CHB1608B121_0603

JP19
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29

+3VS

1
2
14
33_0402_5% 2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13

C452
1
2
220P_0402_50V8K

FD3
LPTSLCTIN#
FD2
LPTINIT#

8
7
6
5

CP11

1
2
3
4

220P_1206_8P4C_50V8_V1
CP9
8
1
7
2
6
3
5
4

LPTSLCT
LPTPE
LPTBUSY
LPTACK#

JP14
LPTCN-25

220P_1206_8P4C_50V8_V1
CP1
1
8
2
7
3
6
4
5

FD1
LPTERR#
FD0
AFD#/3M#

(BTS88)
FD7
FD6
FD5
FD4

220P_1206_8P4C_50V8_V1
CP10
8
1
7
2
6
3
5
4
220P_1206_8P4C_50V8_V1

Compal Electronics, Inc.

Title

PARALLEL/MDCPORT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.

Size

Document Number

Rev
0.1

LA-1841
Date:

Thursday, February 20, 2003

Sheet

38

of

57

C639

0.1U_0402_16V4Z
ECAGND

15 CLK_PCI_LPC

LPC_FRAME#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
2
R549

+3VALW

R548
@33_0402_5%
24

2
C682
@22P_0402_25V8 K

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
1 EC_RST#
4.7K_0402_5%

EC_SCI#

31

EC_GA20
EC_KBRST#

5
6

EC_SCI#

1
23
23

GATEA20
KBRST#

7
8
9
15
14
13
10
18
19
22
23

R494
100K_0402_5%
1
2
1
2
R478
100K_0402_5%

EMAIL#
INTERNET#

+3VALW

R535
10K_0402_5%

26,27,29,30 WLANPME#

26,27,29,30 1394_PME#

2
C649

EC_PME#

+3VALW
1
2
3
4

8
7
6
5

35
EXTID0
35
EXTID1
35
EXTID2
35
EXTID3
44
TP_CLK
44
TP_DATA
43
LID_SW#
34 MEDIA_DETECT

34
45
123
136
157
166

PWM
or PORTA

IOPB0/URXD
IOPB1/UTXD
IOPB2/USCLK
IOPB3/SCL1
IOPB4/SDA1
IOPB7/RING/PFAIL/RESET2

Key matrix scan

PORTB

KBSOUT0
KBSOUT1
KBSOUT2
KBSOUT3
KBSOUT4
KBSOUT5
KBSOUT6
KBSOUT7
KBSOUT8
KBSOUT9
KBSOUT10
KBSOUT11
KBSOUT12
KBSOUT13
KBSOUT14
KBSOUT15

IOPC0
IOPC1/SCL2
IOPC2/SDA2
IOPC3/TA1
IOPC4/TB1/EXWINT22
IOPC5/TA2
IOPC6/TB2/EXWINT23
IOPC7/CLKOUT

PORTC

TINT#
TCK
TDO
TDI
TMS

PORTD-1

IOPD0/RI1/EXWINT20
IOPD1/RI2/EXWINT21
IOPD2/EXWINT24/RESET2

PORTE

IOPE4/SWIN
IOPE5/EXWINT40
IOPE6/LPCPD/EXWIN45
IOPE7/CLKRUN/EXWINT46

JTAG debug port

CRY1

158

CRY2

160

PSCLK1/IOPF0
PSDAT1/IOPF1
PSCLK2/IOPF2
PSDAT2/IOPF3
PSCLK3/IOPF4
PSDAT3/IOPF5
PSCLK4/IOPF6
PSDAT4/IOPF7

IOPH0/A0/ENV0
IOPH1/A1/ENV1
IOPH2/A2/BADDR0
IOPH3/A3/BADDR1
IOPH4/A4/TRIS
IOPH5/A5/SHBM
IOPH6/A6
IOPH7/A7

PORTH

PS2 interface

IOPI0/D0
IOPI1/D1
IOPI2/D2
IOPI3/D3
IOPI4/D4
IOPI5/D5
IOPI6/D6
IOPI7/D7

PORTI

32KX1/32KCLKIN
32KX2

EC_SMB_DA2
EC_SMB_CK2
EC_SMB_DA1
EC_SMB_CK1

10K_1206_8P4R_5%

A n a l o g Board ID definition,
P l e ase see page 3.

24
42
29
24
38

EC_SMI#

EC_SMI#
S4_SATA
WL_OFF#
EC_SWI#
BT_RST#

SYSON
SUSP#
VR_ON

41,42,50 SYSON
31,34,40,41,50,51 SUSP#
53
VR_ON
27 PCM_SUSP#
24,45 EC_RSMRST#
35,36
DRV0#
16,22
ENBKL
22
BKOFF#
40

BKOFF#
FSEL#

FSEL#

+3VALW

IOPJ0/RD
IOPJ1/WR0

0.1U_0402_16V4Z

IOPJ2/BST0
IOPJ3/BST1
IOPJ4/BST2
IOPJ5/PFS
IOPJ6/PLI
IOPJ7/BRKL_RSTO
IOPM0/D8
IOPM1/D9
IOPM2/D10
IOPM3/D11
IOPM4/D12
IOPM5/D13
IOPM6/D14
IOPM7/D15

IOPD4
IOPD5
IOPD6
IOPD7

PORTD-2

PORTJ-2

PORTK

PORTM

IOPK0/A8
IOPK1/A9
IOPK2/A10
IOPK3/A11
IOPK4/A12
IOPK5/A13_BE0
IOPK6/A14_BE1
IOPK7/A15_CBRD
IOPL0/A16
IOPL1/A17
IOPL2/A18
IOPL3/A19
IOPL4/WR1#

PORTL

SEL0#
SEL1#
CLK

ECAGND

BATT_TEMPA 47

BATT_OVP

BATT_OVP 48

ALI/MH#
EMAIL#
MODE#
INTERNET#
AD_BID0

1
R499

ALI/MH# 47
EMAIL# 43
MODE# 44
INTERNET# 43

1
C644

2
100K_0402_5%
2
0.22U_0603_16V4 Z

99
100
101
102

DAC_BRIG
EN_DFAN2#
IREF
EN_DFAN1#

32
33
36
37
38
39
40
43

INVT_PWM
BEEP#

153
154
162
163
164
165

EC_URXD
EC_UTXD
EC_USCLK
EC_SMB_CK1
EC_SMB_DA1

168
169
170
171
172
175
176
1

PBTN_OUT#
EC_SMB_CK2
EC_SMB_DA2
FAN_SPEED1
EC_PME#
EC_THRM#
FAN_SPEED2

26
29
30

ACIN
CD_PLAY
PM_SLP_S3#

ACIN
24,44,46
CD_PLAY 34
PM_SLP_S3# 24

2
44
24
25

PM_SLP_S5#
BT_WAKE_UP

ON/OFF 43
PM_SLP_S5# 24
BT_WAKE_UP 38
PM_CLKRUN# 24,26,27,29,30,36

124
125
126
127
128
131
132
133

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7

138
139
140
141
144
145
146
147

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

150
151

FRD#
FWR#

FRD#
FWR#

40
40

152

SELIO#

SELIO#

40

41
42
54
55

NUM_LED#
CAPS_LED#
PADS_LED#

143
142
135
134
130
129
121
120

KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15

113
112
104
103
48

KBA16
KBA17
KBA18
KBA19
FSTCHG

DAC_BRIG 22
EN_DFAN2 42
IREF
48
EN_DFAN1 42

48,52

EC_URXD
EC_UTXD
EC_USCLK

@96212-1011S

KEYBOARD CONN.
(ACES_85201-2405_24P)

INVT_PWM 22
BEEP#
33
SHDD_LED# 35
ACOFF
48
KILL_SW# 29,33,38
EC_ON
43,45
EC_LID_OUT# 24
BT_DETACH 38

ACOFF
KILL_SW#
EC_ON
EC_LID_OUT#
BT_DETACH

ADP_I

+3VALW

EC_TINIT#
EC_TCK
EC_TDO
EC_TDI
EC_TMS

JP5

NUM_LED#
NUM_LED#
PADS_LED#
PADS_LED#
CAPS_LED#
CAPS_LED#
1
2
300_0402_5% +3VS
KSO15 R 2 1 9
KSO15
KSO14
KSO14
KSO10
KSO10
KSO11
KSO11
KSO8
KSO9
KSO13
KSO8
KSI7
KSO9
KSO3
KSO13
KSO7
KSI7
KSO12
KSI4
KSI6
KSO3
KSI5
KSO7
KSO6
KSO12
KSO5
KSI4
KSI3
KSI0
KSO0
KSI6
KSO1
KSI5
KSI1
KSO6
KSI2
KSO5
KSO2
KSO4
1
2
KSI3
+3VS
R218
300_0402_5%
KSI0
KSO0
KSO1

34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

EC_URXD 45
EC_UTXD 45
E C _ U S C L K 45
EC_SMB_CK1 40,47
EC_SMB_DA1 40,47
PCIRST# 10,23,26,27,29,30,36
PBTN_OUT# 24
EC_SMB_CK2 5,34
EC_SMB_DA2 5,34
FAN_SPEED1 42
EC_THRM# 24
FAN_SPEED2 42
BT_PWR 38

1
R217

6278-34P-KBCON

2
300_0402_5%

+3VS

KSI1
KSI2
KSO2
KSO4

CP8
1
2
3
4

@100P_1206_8P4C_50V8
8
7
6
5

CP7
1
2
3
4

@100P_1206_8P4C_50V8
8
7
6
5

CP6
1
2
3
4

@100P_1206_8P4C_50V8
8
7
6
5

CP5
1
2
3
4

@100P_1206_8P4C_50V8
8
7
6
5

CP4
1
2
3
4

@100P_1206_8P4C_50V8
8
7
6
5

CP3
1
2
3
4

@100P_1206_8P4C_50V8
8
7
6
5

CP2
1
2
3
4

@100P_1206_8P4C_50V8
8
7
6
5

(Need to check layout library with KB spec)

I/O Address
BADDR1(KBA3) BADDR0(KBA2)

PHDD_LED# 35

Index

IRE
* OBD
DEV
PROG

2F

4E

4F

(HCFGBAH, HCFGBAL)(HCFGBAH, HCFGBAL)+1

1
ENV0 (KBA0)

Data

2E

Reserved
ENV1 (KBA1) TRIS (KBA4)

0
0
1
1

0
1
0
1

0
0
0
0

SHBM(KBA5)=1: Enable shared memory with host BIOS

TRIS(KBA4)=1: While in IRE and OBD, float all the
signals for clip-on ISE use
+3VALW
+5VS
FSTCHG

1
R493
TP_DATA 1
R492
TP_CLK

48

2
4.7K_0402_5%
2
4.7K_0402_5%

KBA1
KBA2
KBA3
KBA5

PC87591L-VPCN01 A2_LQFP176

1
R491
1
R490
1
R489
1
R488

2
1K_0402_5%
2
@1K_0402_5%
2
1K_0402_5%
2
1K_0402_5%
A

L32 2

32.768KHz_12.5P_CM155

Compal Electronics, Inc.

FBM-L11-160808-800LMT_0603
C665
12P_0402_50V8J

173
174
47

R517
120K_0402_5%

C664
10P_0402_50V8 K

Rb

148
149
155
156
3
4
27
28

2 CRY2

20M_0603_5%

X5
2

C638
1

2 1

AD_BID0
R487
0_0402_5%

62
63
69
70
75
76

SELIO#

R481
100K_0402_5%

Ra

BATT_TEMP

1
2
3
4
5
6
7
8
9
10

1
2
3
4
5
6
7
8
9
10

1
100K_0402_5%

Title

EC PC87591

1
CRY1

R519

2
R553

NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10

1
2
3
4

AGND

RP85

11
12
20
21
85
86
91
92
97
98

8
7
6
5

For EC Tools

161
VBAT
IOPA0/PWM0
IOPA1/PWM1
IOPA2/PWM2
IOPA3/PWM3
IOPA4/PWM4
IOPA5/PWM5
IOPA6/PWM6
IOPA7/PWM7

PORTJ-1

+5VALW

GA20/IOPB5
KBRST/IOPB6
KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7

81
82
83
84
87
88
89
90
93
94

DA0
DA1
DA2
DA3

DA output

IOPD3/ECSCI#

10K_1206_8P4R_5%

110
111
114
115
116
117
118
119

TP_CLK
TP_DATA
LID_SW#

MODE#
FRD#
SELIO#
FSEL#

105
106
107
108
109

AD Input

96

RP145

1
BATT_TEMP
0.01U_0402_25V4 Z

KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15

49
50
51
52
53
56
57
58
59
60
61
64
65
66
67
68

MEDIA_DETECT

AD0
AD1
AD2
AD3
IOPE0AD4
IOPE1/AD5
IOPE2/AD6
IOPE3/AD7
DP/AD8
DN/AD9

Host interface

GND1
GND2
GND3
GND4
GND5
GND6
GND7

ECAGND

71
72
73
74
77
78
79
80

EC_TINIT#
EC_TCK
EC_TDO
EC_TDI
EC_TMS

26,27,29,30 PCM_PME#

26,27,29,30 LAN_PME#

KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7

SERIRQ
LDRQ#
LFRAME#
LAD0
LAD1
LAD2
LAD3
LCLK
RESET1#
SMI#
PWUREQ#

17
35
46
122
159
167
137

+3VALW

KSI0
KSI1
KSI2
KSI3
KSI4

KBA[0..19]
ADB[0..7]

44
44
44
44
43

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6

VDD

2
23,27,36 SERIRQ
24,36
24,36
24,36
24,36
24,36

40
40

+RTCVCC

+51AVCC

JP31

0.1U_0402_16V4Z
U50

16

+3VALW

C677

+3VALW
2
L33
FBM-L11-160808-800LMT_0603

0.1U_0402_16V4Z

0_0402_5%

KBA[0..19]
ADB[0..7]

+51AVCC

C666

R552

1000P_0402_50V7K

1
D

+3VS
C637
1000P_0402_50V7K

0.1U_0402_16V4Z

+RTCVCC

C643

C661

0.1U_0402_16V4Z

0.1U_0402_16V4 Z
C669

C678

0.1U_0402_16V4 Z
C674

+51VDD

95

+3VALW

AVCC

PROPRIETARY NOTE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
Document Number
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
Custom
LA-1841
USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
Thursday, February 20, 2003
3

Rev
0.1
1

Sheet

39

of

57

+5VALW

+5VALW

1
C351

SELIO#

A
B

U13A
O

CC
LARST#

11
1

D0
D1
D2
D3
D4
D5
D6
D7
CP
MR

U11

SN74HCT273PW_TSSOP20

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

10

S N74LVC32APWLE_TSSOP14

VCC

3
4
7
8
13
14
17
18

2
5
6
9
12
15
16
19

KSO16

KSO17
HDD_LED#

KSO17
43,44
HDD_LED#
43
WL_BT_LED#
43
S4_LATCH
42
EC_RCVEN
45
EC_RCRST#
45

EC_RCVEN
EC_RCRST#

SN74HCT273PW_TSSOP20

1U_0805_25V4Z

+3VALW

1
D

10
9

EC_FLASH#

14
P

31,34,39,41,50,51

24

Q15
2N7002_SOT23

U13C
S N74LVC32APWLE_TSSOP14

SUSP#

2
G

39

1MB Flash ROM

512KB Flash ROM

KBA[0..19]
ADB[0..7]

KBA[0..19]
ADB[0..7]

+3VALW

U15

39
39

FSEL#
FRD#

KBA0
KBA1
KBA2
KBA3
KBA4
KBA5
KBA6
KBA7
KBA8
KBA9
KBA10
KBA11
KBA12
KBA13
KBA14
KBA15
KBA16
KBA17
KBA18
KBA19

21
20
19
18
17
16
15
14
8
7
36
6
5
4
3
2
1
40
13
37

FSEL#
FRD#
FWE#

22
24
9

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
CE#
OE#
WE#

VCC0
VCC1
D0
D1
D2
D3
D4
D5
D6
D7
RP#
NC
READY/BUSY#
NC0
NC1

GND0
GND1

25
26
27
28
32
33
34
35
10
11
12
29
38

1 C380

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7
RESET#

1
2
R248
@100K_0402_5%

1
100K_0402_5%

1
VCC
A0 2
WP
A1 3
SCL
A2 4
SDA
GND
AT24C16N10SC-2.7_SO8

R263
100K_0402_5%

Flash ROM Socket Conn.

U16

31
30

R266

U18

C663
0.1U_0402_16V4Z
1
2

39
39

8
7
6
5

39,47 EC_SMB_CK1
39,47 EC_SMB_DA1

FWR#

R245
100K_0402_5%

C399
2 0.1U_0402_16V4Z

CC
+3VALW

+3VALW

+5VALW
+5VALW

2
100K_0402_5%
2
100K_0402_5%

1
R246
1
R238

AA

FWE#

to 3V

C352
1
2

1
2
R224
20K_0402_5%

+5VALW

KBA4

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

2
0.1U_0402_16V4Z

GND

20

CP
MR

0.1U_0402_16V4Z
14

11
1

VCC

AA
LARST#

CD_FDD_LED#

C366
1
2

CDON_LED#
44
MP3_LED#
44
EMAIL_LED#
44
PWR_LED#
44
PWR_SUSP_LED#
44
BATT_LOW_LED#
44
BATT_CHGI_LED#
44
CD_FDD_LED#
43

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

+3VALW

U13B
SN74LVC32APWLE_TSSOP14

D0
D1
D2
D3
D4
D5
D6
D7

2
5
6
9
12
15
16
19

GND

U14

10

SELIO#

SELIO#

3
4
7
8
13
14
17
18

39

KBA2

14

+3VALW

ADB0
ADB1
ADB2
ADB3
ADB4
ADB5
ADB6
ADB7

20

1
2
C367
0.1U_0402_16V4Z

0.1U_0402_16V4Z

+3VALW

KBA18
KBA16
KBA15
KBA12
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1
KBA0
ADB0
ADB1
ADB2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS

VCC
WE*
A17
A14
A13
A8
A9
A11
OE*
A10
CE*
DQ7
DQ6
DQ5
DQ4
DQ3

29F040/SST39VF040_PLCC

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

FWE#
KBA17
KBA14
KBA13
KBA8
KBA9
KBA11
FRD#
KBA10
FSEL#
ADB7
ADB6
ADB5
ADB4
ADB3

+3VALW

KBA16
KBA15
KBA14
KBA13
KBA12
KBA11
KBA9
KBA8
FWE#
RESET#
KBA18
KBA7
KBA6
KBA5
KBA4
KBA3
KBA2
KBA1

23
39

JP7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
@SUYIN-80065A-040G2T

KBA17
KBA19
KBA10
ADB7
ADB6
ADB5
ADB4
+3VALW
ADB3
ADB2
ADB1
ADB0
FRD#
FSEL#
KBA0

SST39VF080-70_TSOP40

Compal Electronics, Inc.

Title

BIOS & EXT.I/OPORT

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.

Size
B

LA-1841

Date:

Document Number
Thursday, February 20, 2003

Rev
0.1
Sheet

40

of

57

1
R426
100K_0402_5%
1
2

SYSON_ALW

2 SYSON#
G
Q39
@2N7002_SOT23

R427

0.1U_0402_16V4Z

@1M_0402_5%

2
1

C437

+3VS

0.1U_0402_16V4Z

+12VALW
1

R473

0.1U_0402_16V4Z

@1M_0402_5%

C342

2
SUSP
G
Q47
2N7002_SOT23

C647

4.7U_1206_16V4Z

C648

0.1U_0402_16V4Z

2
1

1
19

SUSP

SUSP

D
Q53
31,34,39,40,50,51
2N7002_SOT23

2
G

SUSP#

D
Q52
2N7002_SOT23

2
G

+2.5VS

8
7
6
5

U3
1
D
S 2
D
S 3
D
S 4
D
G
SI4800DY_SO8

1
2

SYSON

R501
10K_0402_5%

+2.5V TO +2.5VS

+2.5V

39,42,50

SYSON

+5VALW

R502
10K_0402_5%

SYSON#

M
1

+5VALW

1U_0805_25V4Z

5VS_GATE
2 C640

C646
4.7U_1206_16V4Z

+5VS
U45
1
D
S 2
D
S 3
D
S 4
D
G
SI4800DY_SO8

5VS_GATE

8
7
6
5

3
R474
100K_0402_5%
1
2

2 SUSP
G
Q54
@2N7002_SOT23

+5VALW

1U_0805_25V4Z

1 1

C343

2 SUSP
G
Q48
@2N7002_SOT23

10U_1206_16V4Z

C345

10U_1206_16V4Z

1
2
3
4

C344

R507
@470_0805_5%

+3VALW

+5VS

+5VALW TO +5VS

D
S
D
S
D
S
D
G
SI4800DY_SO8

2 SUSP
G
Q11
@2N7002_SOT23

SYSON_ALW

2 SYSON#
G
Q41
2N7002_SOT23

+3VS

1 1

C605

+3VALW TO +3VS

8
7
6
5

2 SYSON#
G
Q51
@2N7002_SOT23

R475
@470_0805_5%

U9

R184
@470_0805_5%

1U_0805_25V4Z

C441
4.7U_1206_16V4Z

1 C438

4.7U_1206_16V4Z

R505
@470_0805_5%

10U_1206_16V4Z

+12VALW

1 C440

R408
@470_0805_5%

1
D
S 2
D
S 3
D
S 4
D
G
SI4800DY_SO8

+5V

2
1U_0805_25V4Z

U23
1
D
S 2
D
S 3
D
S 4
D
G
SI4800DY_SO8

C599

U44

1 C635
2

8
7
6
5

10U_1206_16V4Z

8
7
6
5

+2.5VS

C601

+5V

+3VALW

+3V

+5VALW TO +5V

+3V
+5VALW

+3VALW TO +3V

C193

4.7U_1206_16V4Z

C194
1U_0805_25V4Z

C192
4.7U_1206_16V4Z

5VS_GATE

2
1

C170
0.1U_0402_16V4Z

Compal Electronics, Inc.

Title

POWER CONTROLCKT
T H I S S H E E T OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
Size
PROPRIETARY NOTE
T R A D E S E C RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
D E P A R T M E N T EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
U S E D B Y OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:
A

Document Number

Rev
0.1

LA-1841
Thursday, February 20, 2003

Sheet
E

41

of

57

Power ON Circuit

RTC Battery

+3VS
+3V

+3V

RTCBATT
SYS_PWROK

D27

7,24

R588

100K_0402_5%

CHGRTC
1
+12V_FAN

PAD-OPEN 4x4m

D
D
D
D

D7

1SS355_SOD323

FAN1

1
2
3
4
ACES_85205-0400

EN_FAN2

1
2
R200
100_0402_5%

2
B

2 C256

LM358A_SO8

0.1U_0402_16V4Z

FAN2

1
R541

40

39 FAN_SPEED2

39
+5VALW

S4_LATCH
RTCVREF

1
C

100_0402_5%

C260

2
B

FMMT619_SOT23
Q12

E
FAN2-1

D4

1 C413

S4_SATA

1
2
R276
10K_0402_5%

1U_0805_16V7K

1
2
3
4
5
6
7

1
CD1#
D1
CP1
SD1#
Q1
Q1#
GND

14
13
12
11
10
09
08

VCC
CD2#
D2
CP2
SD2#
Q2
Q2#

RTCVREF
C405

0.1U_0402_10V6K
2

74LCX74

D14
2

D_SET_S4

2
G

Q19
2N7002_SOT23
S

C257
10U_1206_16V4Z
4

1SS355_SOD323

D6

JP22

1N4148_SOT23

1
2
3
ACES_85205-0300

0.1U_0402_16V4Z

2
@1U_0805_16V7K

1
2
R274
10K_0402_5%

RB751V_SOD323

R205

1
C412

2
0_0402_5%

1
R207

1
2
R273
10K_0402_5%

RTCVREF

FAN CONN. 3

Q17
2N7002_SOT23
S

2
G

SYSON

Q16
2N7002_SOT23

+3VALW

EN_FAN2

39,41,50

U20

2
10K_0402_5%

2
G

Q18
2N7002_SOT23

1
2
3
ACES_85205-0300

1N4148_SOT23

+3VS

1SS355_SOD323

2
8.2K_0402_5%

1
2
R268
U19
10K_0402_5%
NC7SZ14M5X

RB751V_SOD323

D5
1
R201

2
G

JP23

Q10

C249
10U_1206_16V4Z

R202
10K_0402_5%

OUT

D3

Title

Compal Electronics, Inc.

Power OK/Reset/RTC battery/Lid Switch/Int. KB

Size

Document Number

Rev
0.1

LA-1841
A

43,45

-IN

FMMT619_SOT23

ON/OFFBTN#

2
1U_0805_16V7K

0.1U_0402_10V6K
2

1N4148_SOT23

+IN

C406

EN_DFAN2

EN_DFAN2

39

43 S4_LID_SW#

560K_0402_5%

1
C411

D15

U7B

100K_0402_5%

D13

+5VALW

FAN CONN. 2

R270

100K_0402_5%

R271

R275

39 FAN_SPEED1

RTCVREF

2
10K_0402_5%

RTCVREF

1
R529

RTCVREF

+3VS

* 5 V F a n : Ri = 100K_1%, Rf = 52.3K_1%
* 1 2 V F a n : Ri = 100K_1%, Rf = 267K_1%

RTCVREF

2
52.3K_0603_1%

1
R210

Rf

1N4148_SOT23

JP25

D8

LM358A_SO8

EN_FAN1

R211
100K_0603_1%

OUT

-IN

C287
10U_1206_16V4Z

+IN

4
3
2
1

Ri

U6
SI4800DY_SO8

G
S
S
S

U7A

8
2

5
6
7
8

1
2
C303
0.1U_0402_16V4Z

39 EN_DFAN1

0.1U_0402_16V4Z

2
1

VS

C607

JP3
1

+5VALW

BAS40-04_SOT23

+RTCVCC

FAN CONN. 1

EN_DFAN1

+RTCBATT

1 +RTCBATT

1U_0805_25V4Z

U55E
SN74LVC14APWLE_TSSOP14
10
O
+3V POWER

11

C692

8
O
+3V POWER

P
I
G

14

U55D
SN74LVC14APWLE_TSSOP14

14

R587
180K_0402_5%
1

BATT1
2

Date:

Thursday, February 20, 2003

Sheet

42

of

57

LID Switch
42 S4_LID_SW#
39

LID_SW#

LID_SW#

3 SW1

45 CIR_LID_SW#

INTERNET_BTN#

39

2 51ON#

39
40,44

JP6

TV_OUT_EN#
KSO17
EMIAL_BTN#
INTERNET_BTN#

KSI4
KSO17

1
2
3
4
5
6
ACES_85201-0605

+3VALW

HORNG CHIH
3

INTERNET#

DAN202U_SC70

D1
@DAN217_SOT23
2

1INTERNET#

DAN202U_SC70

Button FPC Conn.

D10

D2

D11

+3VALW

EMIAL_BTN#

(DIFFERENT BETWEEN MPU-101-81A)

EMAIL#

51ON#

EMAIL#

39

DAN202U_SC70

R560

100K_0402_5%

ON/OFF

39

2 51ON#

51ON#

44,46

2
1
2 2
R555
33K_0402_5%
Q58 22K
DTC124EK_SOT23

Q55

WL_BT_LED#

WL_BT_LED#

40

10K

1 CD_FDDLED#
200_0603_5%

2
R466

1 WL_BTLED#
200_0603_5%

Power FPC Conn.

2
G
S
3

2N7002_SOT23

40

+5VALW

E 47K

EC_ON

EC_ON

39,45

Q43
DTA114YKA_SOT23

RLZ20A_LL34

C
22K
B

1000P_0402_50V7K

D34

CD_FDD_LED#

47K

10K

2
R465

C687
R554
4.7K_0402_5%

CD_FDD_LED#

DAN202U_SC70

+3VALW

ON/OFFBTN#

42,45 ON/OFFBTN#

47K

D33

Q42
DTA114YKA_SOT23

J3

+5VALW
3

1
JOPEN

+5VALW

Power Button

+3VALW

1
JOPEN

Q13
DTA114YKA_SOT23
2

B
HDD_LED#

HDD_LED#

40

ACES_85201-1405

10K
2

+5VS

J2

2
R216

R215

200_0603_5%

1
HDDLED#
200_0603_5%

44 POWER_ON_LED

WL_BTLED#
SDLED#
CD_FDDLED#
HDDLED#
ON/OFFBTN#
POWER_ON_LED

14
13
12
11
10
9
8
7
6
5
4
3
2
1

14
13
12
11
10
9
8
7
6
5
4
3
2
1

JP4

SDLED#

27

SDLED

SDLED

2
G

Q56
2N7002_SOT23

Compal Electronics, Inc.

Title

Switchs & Connectors

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.
5

Size
B

LA-1841

Document Number

Date:

Thursday, February 20, 2003

Rev
0.1
Sheet
1

43

of

57

+5VALW

10K

47K

2R_PWR_SUSP_LED#

10K

R288

BATT_CHGI_LED#

40 BATT_CHGI_LED#

10K

PWR_SUSP_LED#

40

2
43 POWER_ON_LED

Q30
DTA114YKA_SOT23
B

BATT_LOW_LED#

BATT_LOW_LED#

47K

Q31
DTA114YKA_SOT23
B

2EMAIL_LED#

40

10K

EMAIL_LED#

40

10K

21
R294

R297

200_0603_5%
BATT_CHGILED#

R295

200_0603_5%

200_0603_5%

BATT_LOWLED#

EMAILLED#

200_0603_5%

BATTERY CHGI/LOW LED

PWRLED#

C439
@2.2U_0805_6.3V6F

200_0603_5%

R646

47K

21

R293
R296

0_0402_5%
1

200_0603_5%

21

47K E

47K

+5VALW

21

PWR_LED#

PWR_LED#

Q27
DTA114YKA_SOT23

40

Q28
DTA114YKA_SOT23

3
Q29
DTA114YKA_SOT23

+5VALW
3

+5VALW
3

+5VALW

EMAIL LED

PWR_SUSPLED#

POWER_ON_LED

LED FPC Conn.

POWER/SUSP LED
ACES_85201-1005
+5VALW

R298
200_0603_5%

ACINLED#
PWRLED#
PWR_SUSPLED#
BATT_LOWLED#
BATT_CHGILED#
EMAILLED#

10
9
8
7
6
5
4
3
2
1

ACINLED#

2 ACIN
G
Q32
2N7002_SOT23

ACIN

24,39,46

JP12

21

TP_CLK
TP_DATA

TP_CLK
TP_DATA

CDPLAY Board Conn.

43,46 51ON#

MODE#

39 MODE#

C347

14

1
2
3
4
5
6

12

+3VALW
D_MODE#

40,43
39
39
39
39

P
5

11

SN74LVC125APWLE_TSSOP14

ACES 85201-0602_6P

U55C

SN74LVC14APWLE_TSSOP14
+3V POWER

1U_0603_10V6K

KSO17
KSI0
KSI1
KSI2
KSI3

D_MODE#
R_CDON_LED#
R_MP3_LED#
KSO17
EC_PLAYBTN#
EC_STOPBTN#
EC_REVBTN#
EC_FRDBTN#

14
13
12
11
10
9
8
7
6
5
4
3
2
1

14
13
12
11
10
9
8
7
6
5
4
3
2
1

Compal Electronics, Inc.

Title

JP11

Switchs & Connectors

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.

U51D

ACES_85201-1405

1N4148_SOT23
A

1N4148_SOT23
D17

S N74LVC14APWLE_TSSOP14
+3V POWER

14

39
39

JP8

+5VS

D16

SN74LVC125APWLE_TSSOP14

R_MP3_LED#

12

U55F

+3V

R_CDON_LED#

13

200_0603_5%

200_0603_5%

51ON#

Touch Pad Connector

R283

R282

U51B

B
10K

MP3_LED#

40 MP3_LED#
C

OE#

B
10K

13

+3V

47K E

OE#

CDON_LED#

Q21
DTA114YKA_SOT23

47K E

21

40 CDON_LED#

Q20
DTA114YKA_SOT23

ACIN LED

+5VALW

+5VALW

Size
B

LA-1841

Document Number

Date:

Thursday, February 20, 2003

Rev
0.1
Sheet
1

44

of

57

Q33
SI2301DS 1P_SOT23

1U_0603_10V6K
1
C444
1
R299

H8
SCREW 8.5X2.8

H9
SCREW 8.5X2.8

H10
SCREW 8.5X2.8

H11
SCREW 8.5X2.8

H12
SCREW 8.5X2.8

H15
SCREW 8.5X2.8

H16
SCREW 8.5X2.8

H17
SCREW 8.5X2.8

H18
SCREW 8.5X2.8

H19
SCREW 8.5X2.8

H20
SCREW 8.5X2.8

2
1U_0603_10V6K
2
100K_0402_5%
1
2
3
4

1
2
R300
100K_0402_5%
1

43 CIR_LID_SW#

H14
SCREW 8.5X2.8

1
2

1
R289

+5VALW

EC_ON

C442
1U_0603_10V6K

2
10K_0402_5%

39,43

U24

P2

H13
SCREW 8.5X2.8

1
2
P2
R284
100K_0402_5%
2
24,39 EC_RSMRST#
G

8
7
6
5

P2
C443

Q22
DTC115EKA_SOT23

1U_0805_25V4Z

Q23
2N7002_SOT23

S
Q24
2N7002_SOT23

H28
SCREW 8.5x3.0

H29
SCREW 8.5x3.0

CIR_RCRST#

C447

0.1U_0402_16V4Z
2
+5V_CIR

H30
SCREW 8.5x3.0

1
2
3
4

Q25
2N7002_SOT23

2
0_0402_5%

M34501M4-XXXFP

+3VALW
+5VALW

39

1
1
R285

EC_UTXD

+3VALW

1
R287

EC_USCLK

1
10K_0402_5%

3
1
Q26
MMBT3904_SOT23

CIR_UTXD
40

EC_URXD

2
10K_0402_5%
EC_USCLK

1 CIR_RCVEN

Q64

MMBT3904_SOT23

+5VALW
2
D18

1 CIR_URXD

R651

RB751V_SOD323

10K_0402_5%

2
D19

1 CIR_USCLK

40

EC_RCRST#

1 CIR_RCRST#

Q65

RB751V_SOD323

MMBT3904_SOT23

Compal Electronics, Inc.

Title

EC_RCVEN

2
10K_0402_5%

1
R292

EC_UTXD

R650

10K_0402_5%

2
@10K_0402_5%

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, IN C.

EC_URXD

+3VALW

1
1

1
1

FD6
FIDUCAL

22

1
2
3
4
5
6
ACES_85201-0605

RCIRRX

1
1

FD5
FIDUCAL

2
G

0.1U_0402_16V4Z

+3VALW

39

1
1

FD4
FIDUCAL

1
1

FD1
FIDUCAL

VSS

1
R301

42,43

H35
SCREW 8.5x3.0

1
1
1

FD3
FIDUCAL

VDD

RC_ON/OFFBTN

ON/OFFBTN#
D

22

+5V_CIR

H34
SCREW 8.5x3.0

FD2
FIDUCAL

CNVSS

CIR_URXD
CIR_USCLK

2
+5V_CIR
@10K_0402_5%
2
0_0402_5%

22

CIR Reciever Board Conn.

CF21
CF27
CF23
CF24
CF22
CF26
CF25
CF28
CF2
CF4
CF12
CF17
CF1
CF3
SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80

D3/K
D2/C

CIR_UTXD

12
11

1
R290
1
R291

R286

39

D0
D1

16
15
14
13

8
7
6
5

CF5
CF11
CF8
CF20
CF7
CF14
CF6
CF9
CF13
CF10
CF15
CF18
CF16
CF19
SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80 SMD40M80

P21/AIN1
P20/AIN0

C446

H37
SCREW 8.5X2.8

RESET#

CIR_RCVEN
CIR_UTXD

10K_1206_8P4R_5%

H33
SCREW 8.5X2.8

9
10

JP13

H36
SCREW 8.5X2.8

P10
P11
P12/CNTR
P13/INT

CIR_RCVEN
CIR_RCRST#
CIR_URXD
CIR_USCLK

RCIRRX

H32
SCREW 8.5X2.8

XOUT

20
19
18
17

+5V_CIR

RP86

H31
SCREW 8.5X2.8

P00
P01
P02
P03

H27
SCREW 8.5x3.0

7
8

2
@10P_0402_50V8K

H26
SCREW 8.5x3.0

XIN

1
C758

H25
SCREW 8.5x3.0

U25
3
X2
4MHz

2
@10P_0402_50V8K

1
C757

H24
SCREW 8.5x3.0

H23
SCREW 8.5x3.0

H22
SCREW 8.5x3.0

H21
SCREW 8.5x3.0

IN
FB
TAP
ERR#

MIC2951

2
G

OUT
SNS
SHDN
GND

H7
SCREW 8.5X2.8

H6
SCREW 8.5X2.8

C445

3
1

100K

H4
SCREW 8.5X2.8
+5V_CIR

H5
SCREW 8.5X2.8

100K

H3
SCREW 8.5X2.8

H2
SCREW 8.5x3.0

H1
SCREW 8.5x3.0

CIR & Screws

Size
B

Document Number
LA-1841

Date:

Thursday, February 20, 2003

Rev
0.1
Sheet

45

of

57

VS

PC6

PACIN
PD2

RLZ4.3B_LL34

0.1U_0603_50V4Z

PR8

48,49

Vin Detector

RTCVREF

10K_0603_5%

VIN

PACIN

PR7
10K_0603_5%

LM393M_SO8

2
1000P_0603_50V7K

24,39,44
1

PR6

PC5

ACIN

1
2
PR4
1K_0603_5%

PU1A

8
2
22K_0603_5%

20K_0603_1%

5.6K_0603_5%

1
PR5

SINGA_2DC-S113L200

PR2

VS

100P_0603_50V8J
2

1000P_0603_50V7K

PC4
2

100P_0603_50V8J

1000P_0603_50V7K

PC3

PD1
EC10QS04

1
2

PC2

2
1M_0603_1%

84.5K_0603_1%

PC1

G
G
G
G

1
PR1
PR3

VIN

PCN1
6
5
4
3

VIN

PL1
CHT_C8BBPH853025_13A
1
2

PF1
12A_65VDC_451012
1
2

3.3V

High 18.764 17.901 17.063

Low 17.745 16.903 16.038

PD3

RB751V_SOD323

PR9

1
PQ1
TP0610T_SOT23
1

PJP2

+2.5V

PAD-OPEN 4x4m
+1.25VSP

PJP4

(12A,480mils ,Via NO.=24)

PJP3

+5VALWP

+1.25VS

(3A,120mils ,Via NO.= 6)

(6A,240mils ,Via NO.= 12)

+CPUVIDP

PJP5
1

+CPUVID

(150mA,40mils ,Via NO.= 2)

+3VALWP

PJP7

+1.5VS

(6A,240mils ,Via NO.= 12)

PAD-OPEN 4x4m
+12VALWP

+12V_FANP

+VGA_COREP

1
2
1
1

PJP8

RLZ6.2C_LL34

PC11

499K_0603_1%

PR23
215K_0603_1%

1000P_0603_50V7K

1000P_0603_50V7K

PR21

2
PR22

0.1U_0603_16V7K

RTCVREF

3.3V
PQ2
2N7002_SOT23

Precharge detector
15.34
15.90
16.48
13.13
13.71
14.20

2
G

2
PR24

1
PACIN
47K_0603_5%

PQ3
DTC115EKA_SOT23

+3VALW

100K

+5VALWP

100K

+VGA_CORE

PAD-OPEN 4x4m

+12VALW

(300mA,20mils ,Via NO.= 1)

PAD-OPEN 2x2m
PJP11

10K_0603_5%
PC13

(6A,240mils ,Via NO.= 12)

PJP9

PAD-OPEN 4x4m

PAD-OPEN 2x2m
+1.5VSP

PC12

+5VALW

PAD-OPEN 4x4m

PAD-OPEN 4x4m
PJP6

PD8

+2.5VP

PAD-OPEN 4x4m

RB715F_SOT323

PR19
499K_0603_1%

LM393M_SO8

PJP1

PD7

ACON

PU1B

PON

1
1M_0603_1%

48

47,4 9 MAINPWON

2
PR18

RLZ16B_LL34

6.0V

PD6

1U_0805_25V4Z

2
10K_0603_5%

PC9

N2

1
PR17

PC10
10U_1206_10V4Z

B+

VS

200_0603_5%

200_0603_5%

PR16

2
1

CHGRTC

1
2
PR12
1K_1206_5%

1
2
PR15
1K_1206_5%

PU2
S-81233SGUP-T1_SOT89

3.3V

N3

2
22K_0603_5%

RTCVREF

PR20

1
PR14

51ON#

0.22U_1206_25V7M

PD5

1N4148_SOD80

43,44

VIN

PC8
0.1U_0603_25V7K

100K_0603_5%

PC7

PR13

N1

1
2
PR11
200_0603_5%

1
2
PR10
1K_1206_5%

CHGRTCP

VS

33_1206_5%

BATT+

PD4

1N4148_SOD80
2

(5A,200mils ,Via NO.= 10)

PJP10
1

+VTT_GMCHP
1

+12V_FAN

PAD-OPEN 2x2m

(0.5A,60mils ,Via NO.= 2)

+VTT_GMCH

PAD-OPEN 3x3m

(1.2A,60mils ,Via NO.= 3)

T H I S S H E E T O F E N G I N E E R I N G D R A W I N G I S T H E PROPRIETARY PROPERTY
O F C O M P A L E L E C T R O N I C S , I N C . A N D C O N T A I N S C O NFIDENTIAL AND TRADE
S E C R E T I N F O R M A T I O N . T H I S S H E E T M A Y N O T BE TRANSFERRED FROM THE
C U S T O D Y O F T H E C O M P E T E N T D I V I S I O N O F R&D DEPARTMENT EXCEPT AS
A U T H O R I Z E D B Y C O M P A L E L E C T R O N I C S , I N C . N E ITHER THIS SHEET NOR
T H E I N F O R M A T I O N I T C O N T A I N S M A Y B E U S E D BY OR DISCLOSED TO ANY
T H I R D P A R T Y W I T H O U T P R I O R W R I T T E N C O N S E N T OF COMPAL ELECTRONICS,
INC.
C

Title

Compal Electronics, Inc.

DCIN&DETECTOR

Size

Document Number

Rev
0.1

LA-1841
Date:

Thursday, February 20, 2003

Sheet
D

46

of

57

PH1 under CPU botten side :

CPU thermal protection at 84 degree C
Recovery at 45 degree C
1

1K_0603_5%

47K_0603_1%

0.01U_0603_50V7K

PR31
1
2
16.9K_0603_1%
TM_REF1

PD9
@BAS40-04

8
3
2

+
-

MAINPWON

46,49

1
2
PR28
47K_0603_1%
PU3A
1
O

PC16

100_0603_5%

PQ4

PD10

2 100K

DTC115EKA_SOT23

1SS355_SOD323

LM393M_SO8

100K

0.22U_0805_16V7K_V2

2
25.5K_0603_1%

PR33

39

VL

+3VALWP

PR34
2
1
100K_0603_1%

3.32K_0603_1%

1
PR35

PC17
ALI/MH#

100_0603_5%

1000P_0603_50V7K

PR32

PR25

PC14
0.1U_0603_50V4Z

PR30

PC15

VL

10KB_0603_1%_TH11-3H103FT
PH1

BATT+

PR29

2
47K_0603_5%

1
PR27

2
15A_65VDC_451012
+3VALWP

1
PF2

1
1K_0603_5%

VS

PR26

SUYIN_200275MR009G130ZL

ALI/NIMH#
AB/I
TS_A
EC_SMDA
EC_SMCA
1

1
2
3
4
5
6
7
8
9

BATT+
BATT+
ID
B/I
TS
SMD
SMC
GND
GND

VL
PL2
CHT_C8BBPH853025_13A
1
2

VMB

PCN2

PC18

PH2 near main Battery CONN :

B A T. thermal protection at 84 degree C
Recovery at 45 degree C

39,40

VL

PH2

PR38
47K_0603_1%

10KB_0603_1%_TH11-3H103FT

PU3B

PR39
1
2
47K_0603_1%

1
PR40

2
16.9K_0603_1%
TM_REF2

5
6

+
-

PD14

1SS355_SOD323

LM393M_SO8

+5VALWP

VL
2

EC_SMB_CK1

39,40

EC_SMB_DA1

PD13
@BAS40-04

PD12
@BAS40-04

39

BATT_TEMPA

1000P_0603_50V7K

PD11
@BAS40-04

3
1

100K_0603_1%

PR37
1K_0603_5%

PR36

PR42

PC19

3.32K_0603_1%

2
PC20

PR43
100K_0603_1%

PR41

VL

100K_0603_1%

1000P_0603_50V7K

0.22U_0805_16V7K_V2

T H I S S H E E T O F E N G I N E E R I N G D R A W I N G I S T H E PROPRIETARY PROPERTY
O F C O M P A L E L E C T R O N I C S , I N C . A N D C O N T A I N S C O NFIDENTIAL AND TRADE
S E C R E T I N F O R M A T I O N . T H I S S H E E T M A Y N O T BE TRANSFERRED FROM THE
C U S T O D Y O F T H E C O M P E T E N T D I V I S I O N O F R&D DEPARTMENT EXCEPT AS
A U T H O R I Z E D B Y C O M P A L E L E C T R O N I C S , I N C . N E ITHER THIS SHEET NOR
T H E I N F O R M A T I O N I T C O N T A I N S M A Y B E U S E D BY OR DISCLOSED TO ANY
T H I R D P A R T Y W I T H O U T P R I O R W R I T T E N C O N S E N T OF COMPAL ELECTRONICS,
INC.
A

Title

Compal Electronics, Inc.

BATTERYCONN/OTP

Size

Document Number

Rev
0.1

LA-1841
Date:

Thursday, February 20, 2003

Sheet
D

47

of

57

1
2
PL3
HCB4532K-800T90_1812

0.01_2512_1%

4.7U_1210_25V6K

SI4825DY_SO8

11

0.1U_0603_16V7K
2

100K_0603_1%

PC33

1
10
10K_0603_5%

VREF

OUT
VH

FB1

VCC

-INE1

RT

+INE1

-INE3

18

OUTC1

FB3

OUTD

CTL

17
16
15
14

100K

-INC1

+INC1

100K

PR64

1
2
PC28
0.1U_0603_50V4Z

3
2
1

39

LXCHRG
1
2
PC31
0.1U_0603_25V7K
2

1
PR57
68K_0603_5%

CC=0.5~2.7A
CV=16.8V(12 CELLS LI-ION)
PL4
22UH_SPC-1205P-220A
1
2

PR61
PC32
1
2
1
2
47K_0603_5%
1500P_0603_50V7K
ACON

PR59

4.7U_1210_25V6K

BATT+

0.02_2512_1%

13

PD16

PC34

RB051L-40_SOD106

PC35

PC36

4.7U_1210_25V6K

4.2V

47.5K_0603_0.1%

PR65

4.7U_1210_25V6K

143K_0603_0.1%
3

ACOFF

100K

MB3887_SSOP24

2 100K

PQ9
DTC115EKA_SOT23
100K 2

0.1U_0603_25V7K

20
19

PQ8
SI4835DY_SO8

PC25
1
2

21

12

FB2

N18

VCC(o)

CS

PC24
0.022U_0603_25V7K
1
2

2
PR60

1
1

PQ11
DTC115EKA_SOT23

PR62

CS

2
7
1K_0603_5%

-INE2

0_0603_5%

23
22

VIN

PR50

24

1000P_0603_50V7K

100K
PQ12
DTC115EKA_SOT23
FSTCHG

PC30
PR56
1
2 1

2
205K_0603_1%

+3VALWP
PR63
47K_0603_5%

CS

47K_0603_5%

PC29

2
1
PR58

2
5
10K_0603_5%

4700P_0603_50V7K

+INE2

PR48

33.2K_0603_1%

10K_0603_1%

0.1U_0603_16V7K

IREF

PC27
PR55
1
2 1

GND

5
6
7
8

PR53

PR54

2N7002_SOT23

OUTC2

+INC2

PQ10

2
G

-INC2

PR47

10K_0603_5%

PC26

39

IREF=1.31*Icharge
IREF=0.73~3.3V

1
2
PR52
3K_0603_5%

1
100K_0603_5%

PU4

ADP_I
2
PR51

ACON

ACON

39,52

150K_0603_1%

1
PACIN

PACIN

4.7U_1210_25V6K

2
1

0.1U_0603_16V7K

39

4.7U_1210_25V6K

1
2
3

PC23

ACOFF#

PR49

PD15

1SS355_SOD323

46

PC22

200K_0603_1%

ACOFF# 1

46,49

PC21

SI4825DY_SO8

10K_0603_5%

PR46

8
7
6
5

D
D
D
D

S
S
S
G

1
2
3
4

PQ7
SI7447DP_SO8

PR45

1
2
3
4

S
S
S
G

PR44

1
1

D
D
D
D

8
7
6
5

PQ6

B++

B+

PQ5
VIN

Iadp=0~5.8A

P3

P2

VMB

PR66
340K_0603_1%

OVP voltage : LI

4S3P : 17.4V--> BATT_OVP= 1.935V

(BAT_OVP=0.1111 *VMB)

PR67
499K_0603_1%

PU5A
3
+
2
LM358A_SO8

39 BATT_OVP

+5VALWP

PC38
0.01U_0603_50V7K

105K_0603_0.5%
2

2.2K_0603_5%
2

0.1U_0603_16V7K

PR69

PR68

PC37

T H I S S H E E T O F E N G I N E E R I N G D R A W I N G I S T H E PROPRIETARY PROPERTY
O F C O M P A L E L E C T R O N I C S , I N C . A N D C O N T A I N S C O NFIDENTIAL AND TRADE
S E C R E T I N F O R M A T I O N . T H I S S H E E T M A Y N O T BE TRANSFERRED FROM THE
C U S T O D Y O F T H E C O M P E T E N T D I V I S I O N O F R&D DEPARTMENT EXCEPT AS
A U T H O R I Z E D B Y C O M P A L E L E C T R O N I C S , I N C . N E ITHER THIS SHEET NOR
T H E I N F O R M A T I O N I T C O N T A I N S M A Y B E U S E D BY OR DISCLOSED TO ANY
T H I R D P A R T Y W I T H O U T P R I O R W R I T T E N C O N S E N T OF COMPAL ELECTRONICS,
INC.
B

Title

Compal Electronics, Inc.

CHARGER

Size

Document Number

Rev
0.1

LA-1841
Date:

Thursday, February 20, 2003

Sheet
D

48

of

57

PC39
4.7U_1210_25V6K
1
2
2

N4

PC41
BST51

VS

PD18

PC44
1
2

DAP202U_SOT323

PD19

VL

1SS355_SOD323

0.1U_0603_25V7K

PC47
4.7U_1206_16V4Z

PC45

1
2

4.7U_1210_25V6K

PC49

PDH5

PR72

2 PDH51

1
2
3
4

47K_0603_5%

2
1
PR83
47K_0603_1%

PC60

0.047U_0603_16V7K

21

2
1

CSH5

PR76

2M_0603_5%
2

0.012_2512_1%

PC55

+5VALWP

4.7U_1206_16V4Z
1

PR79

PC57

100P_0603_50V8J

150U_D_6.3VM

1
+

1
PC58
+

PD21
EP10QY03

10.5K_0603_1%

PC59

VL

47P_0603_50V8J

PR75

PR82

VL

MAINPWON

PC51

150U_D_6.3VM

10K_0603_1%
2

+3.3V Ipeak = 6.66A ~ 10A

PDL5

2.5VREF

RUN/ON3

8
D1
G1 7
D1 S1/D2 6
G2 S1/D2 5
S2 S1/D2
SI4814DY_SO8~D

1
2
PR81

10K_0603_1%

TIME/ON5

PC56
680P_0603_50V8J

PON
1

2
PR80

MAX1632

M
7

28

100P_0603_50V8J

CSH3
CSL3
FB3
SKIP#
SHDN#

PQ14

PLX5

GND

PC54

PU6

LX3
DL3

4
5
18
16
17
19
20
14
13
12
15
9
6
11

1
2
PR77
10K_0603_5%

PACIN

DH3

12OUT
VDD
BST5
DH5
LX5
DL5
PGND
CSH5
CSL5
FB5
SEQ
REF
SYNC
RST#

PR78

1
2
3
10
23

EP10QY03
2

PC53
150U_D_6.3VM

46,48
1

PD20

3.57K_0603_1%
2

CSH3

PC52
150U_D_6.3VM

1M_0603_1%

0.012_2512_1%

26
24

+3VALWP

27

BST3

V+

22

2
1

25

PR73

PC46

0_0603_5%

PR74

+12VALWP

4.7U_1206_16V4Z

47P_0603_50V8J

PT1
SDT-1205P-100

B+++

1
1

PC48
0.1U_0603_25V7K
PDH3

SPC-1205P-100

4.7U_1210_25V6K

PDL3
PC50

PL6

1 FLYBACK
22_1206_5%

1
PR71
0_0603_5%
PLX3

2
PR70

D1
G1
D1 S1/D2
G2 S1/D2
S2 S1/D2
SI4814DY_SO8~D

PDH31

8
7
6
5

4.7U_1210_25V6K

PQ13

1
2
3
4

4.7U_1210_25V6K

PC43

PC42

HCB4532K-800T90_1812

SNB

BST31

0.1U_0603_25V7K

PD17

EC11FS2_SOD106

B+

B+++

PL5
1

470P_0805_100V7K

PC40

46,47

+5V Ipeak = 6.66A ~ 10A

PC61

0.047U_0603_16V7K

T H I S S H E E T O F E N G I N E E R I N G D R A W I N G I S T H E PROPRIETARY PROPERTY
O F C O M P A L E L E C T R O N I C S , I N C . A N D C O N T A I N S C ONFIDENTIAL AND TRADE
S E C R E T I N F O R M A T I O N . T H I S S H E E T M A Y N O T BE TRANSFERRED FROM THE
C U S T O D Y O F T H E C O M P E T E N T D I V I S I O N O F R&D DEPARTMENT EXCEPT AS
A U T H O R I Z E D B Y C O M P A L E L E C T R O N I C S , I N C . N EITHER THIS SHEET NOR
T H E I N F O R M A T I O N I T C O N T A I N S M A Y B E U S E D BY OR DISCLOSED TO ANY
T H I R D P A R T Y W I T H O U T P R I O R W R I T T E N C O N S E N T OF COMPAL ELECTRONICS,
INC.
2

Title

Compal Electronics, Inc.

5V/3.3V/12V

Size

Document Number

Rev
0.1

LA-1841
Date:

Thursday, February 20, 2003

Sheet

49

of

57

PC63

PC62

PC64

PL7 2

PR84
51_1206_5%

B+

HCB4532K-800T90_1812

4.7U_1210_25V6K

+5VALWP

4.7U_1210_25V6K
2

4.7U_1210_25V6K

PGND1

PGND2

11

VOUT1
VSEN1
EN1
PG1

OCSET1

VOUT2
VSEN2
EN2
PG2/REF

PR98

1
2

2
1K_0603_1%

+5VALWP

D1
G1
D1 S1/D2
G2 S1/D2
S2 S1/D2
SI4814DY_SO8~D

8
7
6
5

20
19
21
16

+1.25VSP

PL9
1 .5U_TPRH6D38-1R5M_4A_20%
1
2
PR93
@100_0603_5%

PC76

26

2
PR95

OCSET2
ISL6225BCA-T_SSOP28

1
PR92

PQ17

21

27

18

150K_0603_1%

22

1
2
3
4

220U_D2_4VM

PC77
@1000P_0603_50V7K

28

LGATE2

VCC

VIN

14

ISEN2

LGATE1

25

@ 0_0603_5%

1
0_0603_5%

+1.25V

24

1
0_0603_5%

SUSP#

31,34,39,40,41,51

PC78
@ 10U_1206_10V4Z

10K_0603_1%

9
10
8
15

ISEN1

DDR

PR97

2
PR94

PHASE2

PR96

SYSON

PHASE1

PC69
4.7U_1206_16V4Z

2
1
PC71
0.1U_0603_25V7K

39,41,42

PR87
0_0603_5%
23 1
2

@1000P_0603_50V7K

UGATE2

17 2

PC79

SOFT2

0.01U_0603_16V7K

UGATE1

13

EC31QS04

1
PR91
1.43K_0603_1%
1
2

PQ16
FDS6672A_SO8
1
2
3

PC75

4
PD23

PR90
0_0603_5%

PR88
@100_0603_5%

220U_D2_4VM
PR89
18.2K_0603_1%

1
1

PC74

220U_D2_4VM

PC68
0.01U_0603_50V7K

BOOT2

GND

8
7
6
5

PC73

12

8
7
6
5
D
D
D
D
0.01U_0603_50V7K
PC72

PC67
0.01U_0603_50V7K
PU7
2
1
12
SOFT1
PR86
PC70
0_0603_5%
2
1
1
2
6
BOOT1
0.1U_0603_25V7K

1
2
3
4

PL8
4.7U_SPC-1205P-4R7B_+40-20%~D
1
2

+2.5VP

DDR Termination Voltage

PQ15
IRF7811A_SO8

S
S
S
G

+2.5VP

PC66
2.2U_0805_10V6K

0.1U_0603_25V7K

DAP202U_SOT323

+2.5V

+2.5V/+1.25V

PR85
2.2_0603_5%
1

PD22

PC65

2
1
PR99
10K_0603_0.1%

PR100
10K_0603_0.1%
2
1
+2.5VP

T H I S S H E E T O F E N G I N E E R I N G D R A W I N G I S T H E PROPRIETARY PROPERTY
O F C O M P A L E L E C T R O N I C S , I N C . A N D C O N T A I N S C O NFIDENTIAL AND TRADE
S E C R E T I N F O R M A T I O N . T H I S S H E E T M A Y N O T BE TRANSFERRED FROM THE
C U S T O D Y O F T H E C O M P E T E N T D I V I S I O N O F R&D DEPARTMENT EXCEPT AS
A U T H O R I Z E D B Y C O M P A L E L E C T R O N I C S , I N C . N E ITHER THIS SHEET NOR
T H E I N F O R M A T I O N I T C O N T A I N S M A Y B E U S E D BY OR DISCLOSED TO ANY
T H I R D P A R T Y W I T H O U T P R I O R W R I T T E N C O N S E N T OF COMPAL ELECTRONICS,
INC.
A

Title

Compal Electronics, Inc.

DDR/2.5V/1.25V

Size

Document Number

Rev
0.1

LA-1841
Date:

Thursday, February 20, 2003

Sheet
D

50

of

57

51_1206_5%

4.7U_1210_25V6K

+5VALWP

PC83

PL10

B+

HCB4532K-800T90_1812

4.7U_1210_25V6K
2

PC82

PR101

PC81
4.7U_1210_25V6K

4.7U_1210_25V6K

PC80

FIX 1.2V

DDR

OCSET1

PR118
107K_0603_1%

2
PR112

PR110
6.8K_0603_1%

1
+ PC94

220U_D2_4VM

@ 220U_D2_4VM

PR113
10K_0603_1%

PR117
PR119
124K_0603_1%

1
+ PC93

@10K_0603_1%

NV31

POWER_SEL=1

VOUT=1.2V

POWER_SEL=1

VOUT=1.0V

POWER_SEL=0

VOUT=1.0V

POWER_SEL=0

VOUT=0.95V

PR105=3.4K_0603_1%

PR105=1.1K_0603_0.5%

PR105=1.1K_0603_0.5%

PR115=10K_0603_1%

PR114=4.87K_0603_1%

PR114=20.5K_0603_1%

UNPOP PR114

PR115=10K_0603_1%

PR115=19.6K_0603_1%

UNPOP PQ20

POP PQ20

POP PQ20

T H I S S H E E T O F E N G I N E E R I N G D R A W I N G I S T H E PROPRIETARY PROPERTY
O F C O M P A L E L E C T R O N I C S , I N C . A N D C O N T A I N S C O NFIDENTIAL AND TRADE
S E C R E T I N F O R M A T I O N . T H I S S H E E T M A Y N O T BE TRANSFERRED FROM THE
C U S T O D Y O F T H E C O M P E T E N T D I V I S I O N O F R&D DEPARTMENT EXCEPT AS
A U T H O R I Z E D B Y C O M P A L E L E C T R O N I C S , I N C . N E ITHER THIS SHEET NOR
T H E I N F O R M A T I O N I T C O N T A I N S M A Y B E U S E D BY OR DISCLOSED TO ANY
T H I R D P A R T Y W I T H O U T P R I O R W R I T T E N C O N S E N T OF COMPAL ELECTRONICS,
INC.
A

0.01U_0603_50V7K

1SUSP#
0_0603_5%

18

OCSET2
ISL6225BCA-T_SSOP28

PC95

VOUT2
VSEN2
EN2
PG2/REF

0_0603_5%

VOUT1
VSEN1
EN1
PG1

PR109

26
20
19
21
16

+1.5VSP

PL12
4.7U_SPC-1205P-4R7B_+40-20%~D
2

PGND2

PGND1

27

8
D1
G1 7
D1 S1/D2 6
G2 S1/D2 5
S2 S1/D2
SI4814DY_SO8~D

28
VCC

VIN

14

ISEN2

LGATE2

22

1
2
3
4

PR108
1.96K_0603_1%
1
2

25

+1.5V
PQ19

11

1
2
2
1
PR104
0_0603_5% PC89
0.1U_0603_25V7K

NV18/NV34

24

PHASE2

@ 0.01U_0603_50V7K

1
0_0603_5%

PHASE1

@10K_0603_1%

9
10
8
15

PC96

10K_0603_1%
2

PR116

UGATE2

POWER_SEL

PR115

16

2
G
PQ20
2N7002_SOT23

2
PR111

1
12

PR114
4.87K_0603_1%

SUSP#

UGATE1

23

SUSP#

BOOT2

PR107
2
7
ISEN1
1.65K_0603_1%
2
LGATE1

31,34,39,40,41,50

BOOT1

17 2

0_0603_5%

0_0603_5%
2

SOFT2

PC87
0.01U_0603_50V7K

PR106

PR105
1.1K_0603_0.5%

1
PR103

@220U_D2_4VM
2

PC88
2
1
0.1U_0603_25V7K

13

PC91

1
2
3
4

GND

G1
D1
S1/D2 D1
S1/D2 G2
S1/D2 S2
SI4814DY_SO8~D

PC92

8
7
6
5

PC86
PU8
2
1
12
SOFT1
0.01U_0603_50V7K

220U_D2_4VM

PQ18

PC90

PL11
4 .7U_SPC-1205P-4R7B_+40-20%~D
0.01U_0603_50V7K
1
2

DAP202U_SOT323

+1.2V
+VGA_COREP

PC85
2.2U_0805_10V6K

2.2_0603_5%

0.1U_0603_25V7K

PR102

PC84

PD24

Title

Compal Electronics, Inc.

VGA_CORE/1.5V

Size

Document Number

Rev
0.1

LA-1841
Date:

Thursday, February 20, 2003

Sheet
D

51

of

57

1
PR120

2
1M_0603_1%

VL

2
-

O
PU9A
LM393M_SO8

PQ21
2N7002_SOT23
S

PC99
1000P_0603_50V7K

2
G

PC98
1000P_0603_50V7K

100K_0603_1%

5,7
D

PR124

H_PROCHOT#

47K_0603_1%

2
200K_0603_1%

1
PR123

2
3
84.5K_0603_1%
2

VL

1
PR122

PR121

PC97
0.1U_0603_50V4Z

ADP_I

39,48

VS

PU9B
O

+5VS

LM393M_SO8

PR125
0_1206_5%

PD25

PU10

1
2
3
4

PQ22

8
D1
G1 7
D1 S1/D2 6
G2 S1/D2 5
S2 S1/D2
SI4814DY_SO8~D

PL13
5 U_SPC_06704_5R0_2.9A_30%~D
2
PR126
8.2K_0603_0.5%

1
+

PC103
220U_D2_4VM

PR128

29.4K_0603_1%

PR129
15.4K_0603_1%

12

FB

GND

+VTT_GMCHP

PGND

33P_0603_50V8J

0.1U_0603_16V7K

21

PC104

PC105
1200P_0603_50V7K

100K_0603_5%

PC102

DL

PR127

COMP

LX

10

BST

DH

PC101
22U_1210_6.3V6M

HSD

11

IN

10U_1206_10V4Z

PC100

EP10QY03

MAX1954

2
G
PQ23
2N7002_SOT23

GMCH_SEL

53

GMCH_SEL=1

VOUT=1.225V FOR PRESCOTT

GMCH_SEL=0

VOUT=1.45V FOR NORTHWOOD

T H I S S H E E T O F E N G I N E E R I N G D R A W I N G I S T H E PROPRIETARY PROPERTY
O F C O M P A L E L E C T R O N I C S , I N C . A N D C O N T A I N S C ONFIDENTIAL AND TRADE
S E C R E T I N F O R M A T I O N . T H I S S H E E T M A Y N O T BE TRANSFERRED FROM THE
C U S T O D Y O F T H E C O M P E T E N T D I V I S I O N O F R&D DEPARTMENT EXCEPT AS
A U T H O R I Z E D B Y C O M P A L E L E C T R O N I C S , I N C . N EITHER THIS SHEET NOR
T H E I N F O R M A T I O N I T C O N T A I N S M A Y B E U S E D BY OR DISCLOSED TO ANY
T H I R D P A R T Y W I T H O U T P R I O R W R I T T E N C O N S E N T OF COMPAL ELECTRONICS,
INC.
2

Title

Compal Electronics, Inc.

VTT_GMCH/CLOCKTHROTTLING

Size

Document Number

Rev
0.1

LA-1841
Date:

Thursday, February 20, 2003

Sheet

52

of

57

D i f f e r e n t P in Definition for ISL6561 in PU9

#7

GND

#11

REF

#33

EN

#38

OVP

#9

TCOMP

#14

IDROOP

#35

GND

#40

GND

#18

RGND

#37

GND

B+

+5VALWP

PR130
80.6K_0603_1%

Battery Feed
Forward

1
ENLL

33

35

PR165
0_0603_5%

55

ISEN3-

55

PWM4

55

ISEN4+

55

ISEN4-

55

2 PR139 1
@ 0_0603_5%

GND

+5VALWP

VR-TT#

16
17
18

VDIFF
VSEN
VRTN

GND

GND
ISL6247_MLFP40

PR146
2
0_0603_5%

14

NC

NTC

PR152
1.2M_0603_5%

1
1
PR158

GMCH_SEL

PR167

0.1U_0603_16V7K
PC113

PR148
@ 0_0603_5%
2
1
PC111
@ 1000P_0603_50V7K
1
PR150

3
PQ24
2N7002_SOT23
PC114
1U_0603_10V6K

2
1
PR164
22K_0603_5%

PR157
5.1K_0603_1%

27K_0603_5%

340K_0603_1%

4 BOOTSELECT

Place close to IC

PR156

52

PR144
20K_0603_1%
1
1
2
1000P_0603_50V7K
2
1
PC110
@ 1000P_0603_50V7K

+5VALWP

OFS

PC116
4.7U_1206_16V4Z

2
PC108

13

CM2843ACIM25_SOT23-5

ISEN3+

+CPUVIDP

PG
EN

55

21
22

15

FB

PQ26
2N7002_SOT23
2
G

PWM3

30
29

COMP

DRSV

VR_ON

OUT

FS

39

VIN

54

20

31

PWM4

ISEN4+
ISEN4-

DSV

SOFT

PC115
4.7U_1206_16V4Z

54

ISEN2-

Panasonic ERTJ0EV334J (0402) PQ25

Locate this NTC resistor on TP0610T_SOT23
PCB between phase 2 and 3
1
for thermal compensation.
2

2
1.2VDD

330K_0402_5%
PH3
12

1
1
2
1
1

0_0603_5%

38

19

PU12

VID_PWRGD
PR161

37

40

220P_0603_50V8J

@ 10K_0603_5%

ISEN2+

2
1.91K_0603_1%
PR153
1
2

16.2K_0603_1%
G

PR154
3.24K_0603_1%

54

27
28

+3VALWP

PC112

PR151

PWM2

PR145
@ 0_0603_5%
2

+3VALWP

PR147
100K_0603_5%

PR149

54

26

54

ISEN1-

LM358A_SO8

1K_0603_1%

ISEN3+
ISEN3-

36

OCSET

ISEN1+

PU5B
5
+
6
-

17.4K_0603_1%

PR155
4.22K_0603_1%

11

PC109
100P_0603_50V8J

PWM3

0.033U_0603_25V7M

Frequency Select
PR143

DSEN#

ISEN2+
ISEN2-

54

24
23

0_0603_5%

PWM2

24

PWM1

PR138
1K_0603_1%

DRSEN

VGATE

25

301_0603_1%

10

@ 0_0603_5%

1
PR141

PC107
2
1

PR142

PR140

PR137
@ 0_0603_5%

+5VALWP

STP_CPU#

15,24

0_0603_5%
2
1
PR136
@ 0_0603_5%

PWM1
ISEN1+
ISEN1-

ENLL

PR132
1
10K_0603_5%

39

PGOOD

RAMPS

VID4
VID3
VID2
VID1
VID0
VID12.5

PR135

34

VCC

1
PR134
0_0603_5%

1
2
3
4
5
6

H_VID4
H_VID3
H_VID2
H_VID1
H_VID0
H_VID5

PU11

2
5
5
5
5
5
5

0_0603_5%

24 PM_DPRSLPVR

32

PC106
1U_0603_10V

@ 0_0603_5%
PR133
1

PR131

PR162
2
1
PQ27
0_0603_5%
2N7002_SOT23
2 PR163 1

2
G
S
1
PQ28
3MMBT3904_SOT23
3

#10 DAC

2
1
PR159
0_0603_5%
PR160
2
1
@ 0_0603_5%

+CPU_CORE
VCCSENSE

Remote
Sensing
5

Place near +VCC_CORE

output capacitor
VSSSENSE

@ 0_0603_5%

PR166
100K_0603_5%

100K_0603_5%

1 . W h e n mode control signal is

h i g h / l o w, the VR will operate to
N o r t h w o od/ Prescott load line.
2 . V I D 5 (12.5) should be pulled
h i g h , when the VR operates to
N o t hwood load line.

BOOTSELECT=1 PRESCOTT
BOOTSELECT=0 NORTHWOOD
A

T H I S S H E E T O F E N G I N E E R I N G D R A W I N G I S T H E PROPRIETARY PROPERTY
O F C O M P A L E L E C T R O N I C S , I N C . A N D C O N T A I N S C O NFIDENTIAL AND TRADE
S E C R E T I N F O R M A T I O N . T H I S S H E E T M A Y N O T BE TRANSFERRED FROM THE
C U S T O D Y O F T H E C O M P E T E N T D I V I S I O N O F R&D DEPARTMENT EXCEPT AS
A U T H O R I Z E D B Y C O M P A L E L E C T R O N I C S , I N C . N E ITHER THIS SHEET NOR
T H E I N F O R M A T I O N I T C O N T A I N S M A Y B E U S E D BY OR DISCLOSED TO ANY
T H I R D P A R T Y W I T H O U T P R I O R W R I T T E N C O N S E N T OF COMPAL ELECTRONICS,
INC.
C

Title
Size

Compal Electronics, Inc.

Document Number

CPU_CORE_Controller

Rev
0.1

LA-1841
Date:

Thursday, February 20, 2003

Sheet
D

53

of

57

PL14
CHT_C8BBPH853025_13A
1
2

CPU_B+

G
S
S
S
4
3
2
1

N6

PHASE1

5
PQ31
SI4362DY_SO8

G
S
S
S

PR172
@68_0805_5%
PC126
@220P_0603_50V8J

0.6U_HK_AE26A0R6_26A_25%

PR173
2

32.4K_0603_1%

4
3
2
1

CPU_DRIVE_EN

PQ32
SI4362DY_SO8

PL15

Snubber
1

PR169
1N5 2
0_0603_5%
8

21

GND
LGATE
ISL6207CB-T_SO8

100U_25V_M
2

PQ30

5
6
7
8

PHASE

B+

PC119

PC124
1U_0805_25V4Z

EN

2
100U_25V_M

1
+

IRF7811A_SO8

G
S
S
S

0.1U_0603_16V7K

UGATE

D
D
D
D

BOOT

PWM

4.7U_1210_25V6K
4.7U_1210_25V6K

PC118

4
3
2
1

PC123

@ 499K_0603_1%

VCC

5
6
7
8

PR171

PR170
2
0_0603_5%

PWM1

PU13

D
D
D
D

6
53

4
3
2
1

5
6
7
8

IRF7811A_SO8

1
+

4.7U_1210_25V6K
PC121
PC122

PC120

PQ29

0.15U_0805_16V7K

G
S
S
S

PR168
0_0603_5%

D
D
D
D

5
6
7
8

D
D
D
D

+5VALWP

PC117

PC125
1
0.01U_0603_16V7K

N7
PH4

ISEN1ISEN1+

2
CPU_B+
PC128

C
1

G
S
S
S

4
3
2
1

PHASE2

+CPU_CORE

0.6U_HK_AE26A0R6_26A_25%

PR177
@68_0805_5%
PR178

12

PQ35

SI4362DY_SO8

PQ36
SI4362DY_SO8

PL16

PC132
@220P_0603_50V8J
2

N9

L o cal Transistor
S w tich Decoupling

PC130
4.7U_1210_25V6K

GND
LGATE
ISL6207CB-T_SO8

1
820_0603_1%~D

5
6
7
8

PQ34
IRF7811A_SO8
4.7U_1210_25V6K

PC129
4.7U_1210_25V6K

5
6
7
8

PHASE

PR175
1N8 2
0_0603_5%
8

D
D
D
D

EN

5
6
7
8

UGATE

4
3
2
1

PC131
1U_0805_25V4Z

BOOT

PWM

G
S
S
S

PR176
@ 499K_0603_1%

VCC

D
D
D
D

PU14

G
S
S
S

PWM2
2

53

4
3
2
1

PQ33
IRF7811A_SO8

D
D
D
D

5
6
7
8

0.15U_0805_16V7K

G
S
S
S

PR174
0_0603_5%

D
D
D
D

PC127
1
2

4
3
2
1

53
53
2

PC133
1

32.4K_0603_1%

1
0.01U_0603_16V7K
3

53
53

ISEN2ISEN2+

N10

PH5
2

1
820_0603_1%~D

L ocal Transistor
S w tich Decoupling

T H I S S H E E T O F E N G I N E E R I N G D R A W I N G I S T H E PROPRIETARY PROPERTY
O F C O M P A L E L E C T R O N I C S , I N C . A N D C O N T A I N S C O NFIDENTIAL AND TRADE
S E C R E T I N F O R M A T I O N . T H I S S H E E T M A Y N O T BE TRANSFERRED FROM THE
C U S T O D Y O F T H E C O M P E T E N T D I V I S I O N O F R&D DEPARTMENT EXCEPT AS
A U T H O R I Z E D B Y C O M P A L E L E C T R O N I C S , I N C . N E ITHER THIS SHEET NOR
T H E I N F O R M A T I O N I T C O N T A I N S M A Y B E U S E D BY OR DISCLOSED TO ANY
T H I R D P A R T Y W I T H O U T P R I O R W R I T T E N C O N S E N T OF COMPAL ELECTRONICS,
INC.
A

Title

Compal Electronics, Inc.

CPU_CORE_Powerstage1

Size

Document Number

Rev
0.1

LA-1841
Date:

Thursday, February 20, 2003

Sheet
D

54

of

57

UGTE

EN

PHSE

PR180
1N11 2
1
0_0603_5%
8
PHASE3

5
GND
LGTE
ISL6207CB-T_SO8~D

N12

3
2
1

PWM

PL17
2
PQ40

PQ39
SI4362DY_SO8~D
4

1
0.6U_HK_AE26A0R6_26A_25%

SI4362DY_SO8~D

PR182
@68_0805_5%

PR183
2

PC140
@220P_0603_50V8J

PC139
1

32.4K_0603_1%

1
0.01U_0603_16V7K

3
2
1

3
2
1

PC138
1U_0805_25V4Z

BOOT

@ 499K_0603_1%

4.7U_1210_25V6K
4.7U_1210_25V6K

5
6
7
8

PR181

VCC

3
2
1

PWM3
2

53

5
6
7
8
PQ38
IRF7811A_SO8~D

PU15

5
6
7
8

PC137

4.7U_1210_25V6K

PC136

0.15U_0805_16V7K

PR179
0_0603_5%

PC135

PQ37
IRF7811A_SO8~D

+5VALWP

CPU_B+

PC134
2

5
6
7
8

N13
ISEN3ISEN3+

PR185
1N14 2
1
0_0603_5%
8
PHASE4

5
GND
LGTE
ISL6207CB-T_SO8~D

N15

PQ43

1
2

SI4362DY_SO8~D

SI4362DY_SO8~D
4

3
2
1

PQ44

PL18

0.6U_HK_AE26A0R6_26A_25%

PHSE

L ocal Transistor
S w tich Decoupling

PR187
@68_0805_5%
12

EN

4.7U_1210_25V6K

PQ42
IRF7811A_SO8~D

UGTE

PC144

PC147
@220P_0603_50V8J
2

2
1

PC145
1U_0805_25V4Z

@ 499K_0603_1%

PR186

BOOT

PWM

PC143

4.7U_1210_25V6K

VCC

PC142

3
2
1

5
6
7
8

6
PWM4

3
2
1

53

4.7U_1210_25V6K

IRF7811A_SO8~D

PU16

PR188
2

32.4K_0603_1%

ISEN4ISEN4+

PC146
1
0.01U_0603_16V7K

N16

53
53

+CPU_CORE

5
6
7
8

5
6
7
8

PQ41

0.15U_0805_16V7K

1
820_0603_1%~D

5
6
7
8

PC141
1
2
PR184
0_0603_5%

PH6
2

CPU_B+

3
2
1

53
53

CPU_DRIVE_EN

PH7
820_0603_1%~D
1

T H I S S H E E T O F E N G I N E E R I N G D R A W I N G I S T H E PROPRIETARY PROPERTY
O F C O M P A L E L E C T R O N I C S , I N C . A N D C O N T A I N S C O NFIDENTIAL AND TRADE
S E C R E T I N F O R M A T I O N . T H I S S H E E T M A Y N O T BE TRANSFERRED FROM THE
C U S T O D Y O F T H E C O M P E T E N T D I V I S I O N O F R&D DEPARTMENT EXCEPT AS
A U T H O R I Z E D B Y C O M P A L E L E C T R O N I C S , I N C . N E ITHER THIS SHEET NOR
T H E I N F O R M A T I O N I T C O N T A I N S M A Y B E U S E D BY OR DISCLOSED TO ANY
T H I R D P A R T Y W I T H O U T P R I O R W R I T T E N C O N S E N T OF COMPAL ELECTRONICS,
INC.
A

Title

Compal Electronics, Inc.

CPU_CORE_Powerstage2

Size

Document Number

Rev
0.1

LA-1841
Date:

Thursday, February 20, 2003

Sheet
D

55

of

57

+5VALWP

PC148
2

PR189
0_1206_5%

+12V_FANP

270P_0603_16V8K

3K_0603_0.5%

PC154

10U_1210_25V6K
2

PR193

PC153

PC150

PC151
10U_1210_25V6K

0.1U_0603_25V7K

S PQ45
SI2302_SOT23

390_0603_5%

0.1U_0603_25V7K

2
G

PR192

8
7
6
5

1.2K_0603_0.5%

PC152

PD26

EP10QY03

-IN
FB
SCP
OSC
VCC
GND
BR/CTL
OUT
PJ3800_SOP8

1
1

PU17

1
2
32.4K_0603_1%

1
2
4.7U_1206_10V7K

PR190

1
2
3
4

PR191

1
2
PL19
0 . 56U_ETQP4LR56WFC_21A_20%~D

PC149

1000P_0603_50V7K

T H I S S H E E T O F E N G I N E E R I N G D R A W I N G I S T H E PROPRIETARY PROPERTY
O F C O M P A L E L E C T R O N I C S , I N C . A N D C O N T A I N S C ONFIDENTIAL AND TRADE
S E C R E T I N F O R M A T I O N . T H I S S H E E T M A Y N O T BE TRANSFERRED FROM THE
C U S T O D Y O F T H E C O M P E T E N T D I V I S I O N O F R&D DEPARTMENT EXCEPT AS
A U T H O R I Z E D B Y C O M P A L E L E C T R O N I C S , I N C . N EITHER THIS SHEET NOR
T H E I N F O R M A T I O N I T C O N T A I N S M A Y B E U S E D BY OR DISCLOSED TO ANY
T H I R D P A R T Y W I T H O U T P R I O R W R I T T E N C O N S E N T OF COMPAL ELECTRONICS,
INC.
2

Title

Compal Electronics, Inc.

12V_FAN

Size

Document Number

Rev
0.1

LA-1841
Date:

Thursday, February 20, 2003

Sheet

56

of

57

BTQ00 PIR LIST

* * *********** Rev0.1 PIR List **************

Compal Electronics, Inc.

Title
PROPRIETARY NOTE

T H I S S H E E T OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND
Size
T R A D E S E C RET INFORMATION. THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
D E P A R T M E N T EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE
U S E D B Y OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date:

B T Q 0 0 PIR LIST
Document Number

LA-1841

Thursday, February 20, 2003

Rev
0.1
Sheet

57

of

57