CS 1013 Advance Computer Architecture UNITI What are embedded computers? List their characteristics. Embedded computers are computers that are lodged into other devices where the presence of the computer is not immediately obvious. These devices range from everyday machine to handheld digital devices, They have a wide range of processing power and cost. Define Response time and Throughput. Response time is the time between the start and the completion of the event, Also referred to as execution time or latency. Throughput is the total amount of work done in a given amount of time. Mention the use of transaction processing benchmarks Tt measures the ability of system to handle transactions, which consists of database accesses and updates. An airline reservation system and bank ATM are the examples of TP system. State Amdalh’s law. ‘Amdalh’ s law states that the performance improvement to be gained from using some faster mode of execution is limited by the fraction of time the mode can be used. What are toy benchmarks? Toy benchmarks are typically between 10 and 100 lines of code and produce result the user already knows before running the toy program. E,g puzzle. What is profile based static modeling? In this technique, 2 dynamic execution profile of the program, which indicates how often each instruction is executed, is maintained. Suppose that we are considering an enhancement to the processor of a server system used for web serving. The new CPU is 10 times faster on computation in the web serving application than the original processor. Assuming that the original CPU is busy with computation 40% of the time and is waiting for /O 60% of the time, What is the overall speedup gained by incorporating the enhancement? Fractionesnanc Speedupeaicas = 10 Speeduporeran = 1/(0.640.4/10) =1/0.64 = Explain the different types of locality. Temporal locality, states that recently accessed items are likely to be accessed in the near future.Spatial locality, says that items whose addresses are near one another tend to be referenced close together in time. 9. Name the addressing modes used for signal processing? Modulo or circular addressing mode Bit reverse addressing mode. 10. Specify the CPU performance equation. CPU time = Instruction Count x Clock cycle Time x cycles per instruction 11. Explain the hybrid approach for encoding an instruction set? The hybrid approach reduces the variability in size and work of the variable architecture but provide multiple instruction lengths to reduce code size 12. What are the registers used for MIPS processors. MIPS has 34, 64-bit general purpose registers (GPRs), named RO, R1...R31, GPRs are sometimes called as integer registers. There are also a set of 32 floating point registers (FPRs), named FO,F1....F31, which can hold 32 single precision values and 32 double precision values. 13. Explain the concept behind pipelining. Pipelining is an implementation (echnique whereby multiple instructions are overlapped in execution. It takes advantage of parallelism that exists among actions needed to execute an instruction. 14, Write about pipe stages and processor cycle. Different steps in an instruction are completed in different parts of different instruction is parallel. Each of these steps is called a pipe stage or pipe segment. The time required between moving an instruction one step down the pipeline is called processor cycle. 15, Explain pipeline hazard and mention the different hazards in pipeline Hazards are situations that prevent the next instruction in the instruction stream from executing during its designated clock cycle, Hazards reduce the overall performance from the ideal speedup gained by pipelining. The three classes of hazards are, © Structural hazards. © Data hazards. * Control hazards. 16. Explain the concept of forwarding. Forwarding can be generalized to include passing a result directly to the functional unit that fetches it. The result is forwarded from the pipeline register corresponding to the output of one unit to the input of the same unit 17. Mention the different schemes to reduce pipeline branch penalties. a. Freeze or flush the pipeline b, Treat every branch as not takenc every branch as taken 4. Delayed branch 18. Consider an unpipelined processor. Assume that it has a Ins clock cycle and that it uses 4 cycles for ALU operations and branches and 5 cycles for memory operations. Assume that the relative frequencies of these operations are 40%, 20% and 40% respectively. Suppose that due to clock skew and setup, pipelining the processor adds 0.2 ns of overhead to the clock. Ignoring any latency impact, how much speedup in the instruction execution rate will we gain from a pipeline? The average instruction execution time on an unpipelined processor is, = clock cycle x Average CPI ns x ((40% x 4)+(20 x 4)+(40 x 5) 4 ns. The average instruction execution time on an pipelined processor is = 140.2ns = 1.2ns Speedup = Avg. instruction time unpipelined/ Avg. instruction time pipelined = 4.4/1.2 = 3.7 times. 19. Briefly explain the different conventions for ordering the bytes within a larger object? Little endian byte order puts the byte whose address is “x....x000” at the least significant position in the double word. Big endian byte order puts the byte whose address is ““x....x000" at the ‘most significant position in the double word. 20. When do data hazards arise? Data hazards arise when an instruction depends on the results of a previous instruction in a way that is expressed by the overlapping of instructions in the pipeline. UNIT 1. List the various data dependence. Data dependence Name dependence Control Dependence 2. What is Instruction Level Parallelism? Pipelining is used to overlap the execution of instructions and improve performance. This potential overlap among instructions is called instruction level parallelism (ILP) since the instruetion can be evaluated in parallel. 3. Give an example of control dependence? ifpl {sls} if p2 {s2:}