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Tom Fitzpatrick
Verification Evangelist DVT
A Guiding Methodology
Provides Freedom From Choice Avoids Chaos and Repetition Ease of Use APIs Not just for Super-heroes!
2011 Mentor Graphics Corp. Company Confidential
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UVM Foundations
Objective
Separation of stimulus generation from delivery Raise the abstraction level of stimulus and checking Test bench configuration Interoperability Reuse
Standard class library & API VIP Testbench components Stimulus
Justification
Several people can develop stimulus Increase productivity Avoid expensive recompilation Important for intra and inter company development Key to productivity
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APB
DUT
SPI I/F
IRQ
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UVC(agent)
Configuration Object Monitor
Sequencer
seq_item
Driver
DUT
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UVC(agent)
Configuration Object Monitor
UVC(agent)
Configuration Object Monitor
Sequencer Driver
Sequencer
DUT
Driver
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UVC(agent)
Configuration Object Monitor
RegSeq
Sequencer
Driver
DUT
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31:14 R
Reserved
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ASS
12
IE
11
10
7 R
6:0 R/W
Char_Len
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SQR
Also provides means to access registers A block can have > 1 map
SQR
Sequencer
Driver
DUT
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i.e. Set this bit in this register rather than write x to address y If the bus agent changes, the stimulus still works Front door is via an agent Back door is directly to the hardware via the simulator database
Configuration
Register model reflects hardware programmable registers Set up desired configuration in register model then dump to DUT
Randomization with configuration constraints
Analysis Mirror
Current state of the register model matches the DUT hardware Useful for scoreboards and functional coverage monitors
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function new(string name = "spi_reg_block"); super.new(name, build_coverage(UVM_CVR_ADDR_MAP)); endfunction virtual function void build(); divider_reg = divider::type_id::create("divider"); divider_reg.build(); divider_reg.configure(this, null, ""); divider_reg.add_hdl_path_slice("divider", 0, 16); APB_map = create_map("APB_map", 'h800, 4, UVM_LITTLE_ENDIAN); APB_map.add_reg(divider_reg, 32'h00000014, "RW"); add_hdl_path("DUT", "RTL"); lock_model(); endfunction: build endclass: spi_reg_block
11 TF - UVM Recipe of the Month 10/11
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UVC(agent)
Template-Generated
RegSeq Sequencer
Monitor
Driver
DUT
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Customer Example
Register Definitions
Early in project:
335 Registers
Final project:
1,000 Registers
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Control File
Reg. Definitions
Documentation
Blocks
A Readers P I
Datamodel
A P I
Writers
RTL
Block Map
OVM/UVM Pkg.
Checks
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UVM Coverage
You can specify the coverage model you wish to generate for instances in a block Simply add a column to your spreadsheet
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Access the hardware register and update the register database Can specify front or back door access
Front door access takes time and may create side effects
Uses bus agent and consumes clock cycles Uses simulation database and access API (VPI)
Back door access is instant and does not cause side effects
For back door accesses, register model updated with result Can be used for individual fields Desired value
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Good news most of these fields have defaults! A typical register access only needs a few of these:
spi_rm.ctrl.write(status, wdata, .parent(this));
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// SPI Register model: spi_reg_block spi_rm; // SPI env config object (contains register model handle) spi_env_config m_cfg;
Sequence base class contains variables common to all register sequences: data, status register model handle
// Properties used by the various register access methods: rand uvm_reg_data_t data; // For passing data uvm_status_e status; // Returning access status // Common functionality: // Getting a handle to the register model task body; m_cfg = spi_env_config::get_config(m_sequencer); spi_rm = m_cfg.spi_rm; endtask: body endclass: spi_bus_base_seq
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Extends base sequence Randomizes data value with specific constraint Writes data to divider register
// Interesting divisor values: constraint div_values {data[15:0] inside {16'h0, 16'h1, 16'h2, 16'h4, 16'h8, 16'h10, 16'h20, 16'h40, 16'h80};} task body; super.body; // Randomize the local data value assert(this.randomize()); // Write to the divider register spi_rm.divider_reg.write(status, data, .parent(this)); endtask: body endclass: div_load_seq
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task body; super.body; // Set up the data register handle array data_regs = '{spi_rm.rxtx0_reg, spi_rm.rxtx1_reg, spi_rm.rxtx2_reg, spi_rm.rxtx3_reg}; // Randomize order data_regs.shuffle(); foreach(data_regs[i]) begin // Randomize register content and then update assert(data_regs[i].randomize()); data_regs[i].update(status, .path(UVM_FRONTDOOR), .parent(this)); end endtask: body endclass: data_load_seq
Extends the base class Gets an array of register handles Randomizes the array index order Foreach reg in the array: Randomize the content Updates the register
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UVC(agent)
Monitor
Reg
Sequencer
Driver
DUT
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reg2bus() converts register item to bus item note single access only
virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); ahb_seq_item ahb = ahb_seq_item::type_id::create("ahb"); ahb.HWRITE = (rw.kind == UVM_READ) ? AHB_READ : AHB_WRITE; ahb.HADDR = rw.addr; bus2reg() converts bus item ahb.DATA = rw.data; to reg item return ahb; endfunction virtual function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw); ahb_seq_item ahb; if (!$cast(ahb, bus_item)) begin `uvm_fatal("NOT_AHB_TYPE","Provided bus_item is not of the correct type") return; end rw.kind = (ahb.HWRITE == AHB_READ) ? UVM_READ : UVM_WRITE; rw.addr = ahb.HADDR; rw.data = ahb.DATA; rw.status = UVM_IS_OK; endfunction endclass: reg2ahb_adapter
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Two ways:
Register model updates based on value written or read back OK in simple situations where only one way to access the DUT registers Requires no additional components
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Auto Prediction
For simple scenarios:
Only sequences accessing the bus agent are register sequences Register can only be accessed via one bus Based on value read or written to the register
UVC(agent)
Monitor RegSeq Sequencer
Reg
Driver
reg
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UVC(agent)
Predictor RegSeq Monitor
Reg
Sequencer Breq
Driver
Breq
reg
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SQR
UVC(agent)
Predictor RegSeq Sequencer Driver Monitor
reg
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SQR
reg
UVC(agent)
Predictor RegSeq Sequencer Driver Monitor
reg
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function void spi_env::connect_phase(uvm_phase phase); if(m_cfg.m_apb_agent_cfg.active == UVM_ACTIVE) begin reg2apb = reg2apb_adapter::type_id::create("reg2apb"); // Register sequencer layering part: m_cfg.ss_rm.TOP_map.set_sequencer(m_apb_agent.m_sequencer, reg2apb); // Set the predictor map: apb2reg_predictor.map = m_cfg.ss_rm.TOP_map; Predictor is integrated during // Set the predictor adapter: the connect phase apb2reg_predictor.adapter = reg2apb; // Connect the predictor to the bus agent monitor analysis port m_apb_agent.ap.connect(apb2reg_predictor.bus_in); end endfunction: connect
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After
mirrored value
desired value
desired value
hardware value
hardware value Mirrored and desired value updated at the end of the bus read cycle
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During
mirrored value
After
mirrored value
desired value
desired value
desired value
hardware value
hardware value Mirrored and desired value updated at the end of the write cycle
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reg.get(), reg.set(),
reg.reset(), reg.get_reset()
reg.update()
Cause the hardware to be updated if register model content has changed via reg.set(), reg.reset() or reg.randomize() Can specify front or back door access
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set()
mirrored value
update()
mirrored value
After
mirrored value
desired value
desired value
desired value
desired value
hardware value
hardware value
hardware value Update() transfers desired value to HW via a write bus cycle
hardware value Mirrored value updated at the end of the write cycle
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Built-In Sequences
Sequences are automatic
Low overhead to use Useful for initial sanity checks on bus connectivity
e.g. Read only registers are not bit bashed Read only memories are not tested
e.g. Clock enable bit Mechanism is to use the uvm_resource_db to set an attribute for the register
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SPI Master
APB
SPI
Another DUT
Another DUT
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SPI Master
APB
SPI
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class sys_env extends uvm_env; axi_agent m_axi_agent; sys_env_config m_cfg; // Register layering adapter: reg2ahb_adapter reg2axi; // Register predictor: uvm_reg_predictor #(axi_seq_item) axi2reg_predictor; function void spi_env::connect_phase(uvm_phase phase); if(m_cfg.m_axi_agent_cfg.active == UVM_ACTIVE) begin reg2axi = reg2axi_adapter::type_id::create("reg2axi"); // Register sequencer layering part: m_cfg.sys_rm.TOP_map.set_sequencer(m_axi_agent.m_sequencer, reg2axi); // Set the predictor map: axi2reg_predictor.map = m_cfg.sys_rm.TOP_map; // Set the predictor adapter: axi2reg_predictor.adapter = reg2axi; // Connect the predictor to the bus agent monitor analysis port m_axi_agent.ap.connect(axi2reg_predictor.bus_in); end endfunction: connect
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Use explicit prediction Built in sequences available for initial testing Works with OVM
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Verification Academy
Verification AcademyProvide the necessary skills that enable you to take advantage of todays latest, advanced functional verification techniques.
Wide Variety of Topics Verification Planning ABV CDC FPGA Verification
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Transactions
Transistors
Questa
Veloce
ESL
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Emulation
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Register at http://www.mentor.com/products/fv/series/uvm-ovm-series
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Thank you
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