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vru

tu

qr

op

mn

|~

z{|}

|~

z{|}

wxy

xy

0/1

0
0
1

00
1/1

2 level-sensitive
latches

1/0

0/0

01

1
0

10

1/0

Comb.
Logic

Clk

0
1

0/0

1/1
11

0/1

Correct State Transition Using Level-Sensitive Latches

Comb.
Logic

Transition for the darkened arrow:

1

1
0
Clk

Clk

0
1

Comb.
Logic

Clk

0
1
0

Clk

0
0

0/1

00
1/1

1/0

0/0

01

10

1/0

Comb.
Logic

1/1

0/0

0
1 (fast)
1
(slow)

1
0
0

0/1

11

Clk

Comb.
Logic

1
1

0
1
1

Comb.
Logic

Clk

1
0

Inorrect State Transition or Race Condition Using Level-Sensitive Latches

Comb.
Logic
1

1
0
Clk

Comb.
Logic

1
1

Required transition for the darkened arrow becomes incorrect transition

corresponding to the dashed arrow:
1

1
0
Clk

2 level-sensitive
latches

0
0
Clk

Clk

0/1

1/1

00
1/0

0/0

01

10

1/0
0/0

1/1
11

0/1

No Race Conditions Using M-S or Edge-Trigerred FFs

Comb.
Logic

0
0
1

1
0

0
1

0
1 (fast)
1
(slow)

Comb.
Logic

Comb.
Logic

Clk

0
1

1
0

Clk

Comb.
Logic

Correct transition for the darkened arrow irrespective of the relative speed
of different excitation (next state) outputs:
1

1
0
Clk

2 M-S or edgetrigerred FFs

Period Between
State Transitions
(also clock period)

Clk

1
0

0
1
1

Comb.
Logic

Clk

0
1

1
0

Comb.
Logic

Phi2 Phi1

0
0
1

T1-2

00
1/1

1/0

0/0

01

1
0

10

1/0

Comb.
Logic

1/1

0/0

0
1 (fast)
1
(slow)

Phi2 Phi1

0/1

11

1
0

Comb.
Logic

0
1

0
(slow)

0
(slow)

0
1

Phi2 Phi1

Comb.
Logic

Tgap > Tskew, T2-1 >= Tp,ff + Tp,logic + Tsu + Tskew

T1-2 >= Tp,ff + Tsu + Tskew

Phi2 Phi1

0
1

Correct transition for the darkened arrow irrespective of the relative speed
of different excitation (next state) outputs:

0/1

No Race Conditions Using

2-phase clocking and
level-sensitive latches

Phi2

Phi1
T2-1

Tgap

r3
r1

r1=17

r3=7

Reg. File (level-sensitive FFs)

s
u

ns

op

vru

tu

qr
y

op

mn

Clk

r1
r3

r1=10 alu
r1=3 alu
r3=7 o/p=10 r3=7 o/p=17

Control signals: read r1, r3, write r1 valid

Execution of ADD r1 r1 r3
: Level sensitive Reg. File; Single-cc Race Condition

ALU

wx

Clk

r3
r3

Reg. File (edge-triggered FFs)

r1

r1

r1=3 alu
r3=7 o/p=10

r1=10
r3=7

Previous control signals invalid

Execution of ADD r1 r1 r3
: Edge-Triggered Reg. File; No Single-cc Race Condition

Control signals: read r1, r3, write r1 valid

ALU

phi1
phi2

r1=3
r3=7

r1=10

phi2

r1

phi1

r3

r3=7

r1=10

phi2

r3

Reg. File (2-phase clocking)

r1

phi1

alu
o/p=10

r1

r3

Previous control signals invalid

Execution of ADD r1 r1 r3
: 2-Phase Clocked Reg. File; No Single-cc Race Condition

Control signals: read r1, r3, write r1 valid

ALU