Scribd Logo
Carica

Benvenuto in Scribd!

  • ELEN 127 - Lab 4

    Caricato da

    ajaypal
    83 visualizzazioni1 pagina
    This document provides instructions for a lab assignment on simulating examples from an advanced logic design book. Students are asked to simulate two examples from the book, providing state tables, state diagrams and circuit designs for each, as well as comparing generated waveforms to those in the book. The submission requires the Verilog code typed, along with the requested diagrams, circuits and waveforms.

    Descrizione originale:

    Titolo originale

    ELEN_127_-_Lab_4

    Copyright

    © Attribution Non-Commercial (BY-NC)

    Formati disponibili

    PDF, TXT o leggi online da Scribd

    Hai trovato utile questo documento?

    Questo contenuto è inappropriato?

    Segnala questo documento
    This document provides instructions for a lab assignment on simulating examples from an advanced logic design book. Students are asked to simulate two examples from the book, providing state tables, state diagrams and circuit designs for each, as well as comparing generated waveforms to those in the book. The submission requires the Verilog code typed, along with the requested diagrams, circuits and waveforms.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Scarica in formato PDF, TXT o leggi online su Scribd
    Segnala contenuti inappropriati
    83 visualizzazioni1 pagina

    ELEN 127 - Lab 4

    Caricato da

    ajaypal
    This document provides instructions for a lab assignment on simulating examples from an advanced logic design book. Students are asked to simulate two examples from the book, providing state tables, state diagrams and circuit designs for each, as well as comparing generated waveforms to those in the book. The submission requires the Verilog code typed, along with the requested diagrams, circuits and waveforms.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Scarica in formato PDF, TXT o leggi online su Scribd
    Segnala contenuti inappropriati
    di 1

    SANTA CLARA UNIVERSITY

    DEPARTMENT OF ELECTRICAL ENGINEERING ELEN 127 / COEN 127 Advanced Logic Design Lab 4: Simulating Examples from the Book
    Objective: Simulate HDL Example 5.5 and HDL Example 5.7 Special Thanks: Thomas Pham Prelab: No pre-lab Specification: For Example 5.5: Provide State Table State Diagram Circuit

    For HDL Example 5.7: Provide State Table State Diagram Circuit Also compare the waveforms you obtained in Xilinx to the one in the book. Procedure: Listen to the book Submission: For both Examples: Provide the verilog code you typed in Provide waveforms And everything required in the specifications

    Potrebbero piacerti anche