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COE/EE 244 Logic Circuit Lab

Lab #4; Page 1/11 Spring 2003

Implementing Combinational Circuits

Due: By 6:00pm on Wednesday April 9. While Multiplexers are primarily thought of as “data selectors” because they select one of several inputs to be logically connected to the output, they can also be used to implement Boolean functions. Similarly, while n -bit Decoders are primarily thought of as n -bit binary to 1 of 2 n code converters or as Demultiplexers, they can also be used to implement Boolean functions of n variables.

1 Multiplexers Used in Boolean Functions

Consider the following truth table that describes a function of 4 Boolean variables.

ABCD
F
0000
0
0001
0
0010
1
0011
1
0100
0
0101
1
0110
0
0111
1
1000
0
1001
0
1010
1
1011
1
1100
0
1101
0
1110
0
1111
1
MUX 16:1
Vcc
D
0
}
C
1
0
G
B
2
15
A
3
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

F

Figure 1: A 16 to 1 Multiplexer Implementation

A 16 to 1 Multiplexer with A, B, C , and D applied to its S 3 , S 2 , S 1 , and S 0 inputs respectively would select one of its 16 inputs for each of the 16 possible combinations of A, B, C , and D . We can implement the function described by the truth table by connecting a voltage source for logic level 1 or ground for a logic level 0 to each of the Multiplexer inputs corresponding to the required value of the function associated with the combination of A, B, C , and D that selected the input. Therefore, the inputs to the Multiplexer will be the same as the F entries in the truth table provided A, B, C , and D are connected to the Multiplexer select inputs in the right order. Consider what happens when, instead of using a 16 to 1 Multiplexer, we use an 8 to 1 Mux. If we choose to connect A, B, and C to the inputs of the Multiplexer, then for each combination of A, B and C ,

COE/EE 244 Logic Circuit Lab

Lab #4; Page 2/11 Spring 2003

although only one Mux input is selected, we need to realize two potentially different values of F . If they are different, they will be functions of D (either D or D ). To see this, we partition the truth table into sections where A, B and C have the same value. This is shown in Figure 2.

ABC
D
F
000
0
0
0
000
1
0
001
0
1
1
001
1
1
010
0
0
D
010
1
1
011
0
0
D
011
1
1
100
0
0
0
100
1
0
101
0
1
1
101
1
1
110
0
0
0
110
1
0
111
0
0
D
111
1
1
MUX 8:1
C
0
}
B
1
G 0
7
A
2
0
1
2
3
4
5
6
7

Vcc

D

F

Figure 2: An 8 to 1 Multiplexer Implementation

This idea can be extended to a 4 to 1 Mux implementation. In this case we partition the table into sections for which A and B have the same value. This is shown in Figure 3. Now Multiplexer inputs will be either 1, 0 or some function of C and D . K-maps may be used to simplify the functions of C and D for each of the table partitions, but in the case of two variables, the functions are usually obvious. The nal possibility, shown in Figure 4, is a 2 to 1 Mux implementation. In this case only A is used as a select input and the table is partitioned into two parts based on A. Inputs to the Mux will be functions of B, C and D . Here it is more likely that you will need to use K-maps to simplify the functions. It should be apparent that there is no explicit importance to the order of A, B, C and D in the truth table. If we rearranged them, we would have chosen different variables as Mux select inputs, and we might end up using less logic in the rest of the circuit. Consider rearranging the table so that B is the Mux select input. Using this approach, the realization shown in Figure 5 uses less hardware.

2 Multiplexers as Data Selectors

In larger designs you may want to perform the same operations on signals coming from a number of different sources, or share a resource, such as a Seven-Segment display or an ALU (Arithmetic Logical Unit). If this is the case Multiplexers and Decoders can be used to route data. When used in this fashion

COE/EE 244 Logic Circuit Lab

Lab #4; Page 3/11 Spring 2003

A
B
C
D
F
0
0
0
0
0
0
0
0
1
0
C
0
0
1
0
1
0
0
1
1
1
0
1
0
0
0
0
1
0
1
1
D
0
1
1
0
0
0
1
1
1
1
1
0
0
0
0
1
0
0
1
0
C
1
0
1
0
1
1
0
1
1
1
1
1
0
0
0
1
1
0
1
0 CD
1
1
1
0
0
1
1
1
1
1
 B MUX 4:1 0 A 1 } G 0 3 C 0 F D 1 C 2 C 3 D

Figure 3: A 4 to 1 Multiplexer Implementation

the inputs to a Multiplexer are split between control signals and data signals (also known as “control path” and “data path”). In the design process the two are designed independently of each other with separate truth tables and K-maps. That is when designing the control path you are not concerned with the values on the data path. Similarly when designing the data path you assume the correct values are on the control path without being concerned with how they are generated. Several Multiplexers can be combined to create Multiplexer congurations of different path widths and numbers of inputs. In Figure 6(a) two 74157s (a quadruple 2-to-1 Multiplexer with common select and active-low enable) are used to create an octal (8-bit) 2-to-1 Multiplexer by controlling the select line S on both modules with the same select signal. Figure 6(b) shows a quad 4-to-1 Multiplexer realized with two 74157 modules. Select signal S 1 enables one of the two modules and disables the output of the other. Signal S 0 is used as the select signal for both modules.

COE/EE 244 Logic Circuit Lab

Lab #4; Page 4/11 Spring 2003

A
BCD
F
0
000
0
0
001
0
0
010
1
BC BD
0
011
1
0
100
0
0
101
1
0
110
0
0
111
1
1
000
0
1
001
0
1
010
1
BC CD
1
011
1
1
100
0
1
101
0
1
110
0
1
111
1

B

D

B

C

C

D

MUX 2:1
A
0}G 0
1
0
1

F

Figure 4: A 2 to 1 Multiplexer Implementation

B
CDA
F
0
000
0
0
001
0
0
010
0
C
0
011
0
0
100
1
0
101
1
0
110
1
0
111
1
1
000
0
1
001
0
1
010
1
D A C
1
011
0
1
100
0
1
101
0
1
110
1
1
111
1

C

A

D

MUX 2:1

0}G 0

1

0

1

B

C

F

Figure 5: Another 2 to 1 Multiplexer Implementation