ALU

AIM: To implement the ALU by using verilog.

BLOCK DIAGRAM:

[3:0]s [7:0]a [7:0]b clk

[15:0]f

ALU

PROGRAM: module alu(s,clk,a,b,f); input[3:0]s;

input [7:0]a; input [7:0]b; output[15:0]f; reg[15:0]f; always@(s or a or b) begin begin case (s) 4'b0000: f<= a&b; 4'b0000: f<= a|b; 4'b0000: f<= a^b; 4'b0000: f<= ~(a^b); 4'b0000: f<= a; 4'b0000: f<= a+b; 4'b0000: f<= (a+(~b)+1); 4'b0000: f<= a+(~b); 4'b0000: f<= b+1; 4'b0000: f<= b-1; 4'b0000: f<= a*b; endcase end endmodule WAVEFORMS:

RESULT: By using verilog HDL simulation we implemented the ALU.

COMPARATOR

AIM:

To implement a general comparator by using verilog

BLOCKDIAGRAM:
a-gt-b a

comparator

a-lt-b a-eq-b

PROGRAM: module comp(a,b,a_gt_b,a_lt_b,a_eq_b); parameter bus =8; parameter eq=5,lt=8,gt=8; input [bus-1:0]a,b; output a_gt_b,a_lt_b,a_eq_b; assign a_eq_b = a==b; assign a_gt_b = a>b; assign a_lt_b = a<b ; endmodule

WAVE FORMS:

RESULT: BY using verilog HDL simulation we implemented the comparator.

PRIORITY ENCODER

AIM: To implement the Priority encoder by using verilog BLOCKDIAGRAM:

Priority Encoder [3:0]w [1:0]y z

PROGRAM: module priorityen(w,y,z); input [3:0]w; output [1:0]y; reg [1:0]y; output z ; reg z; always @ (w) begin if(w==0) y=0; else if (w[0]==1) y=2'b00; else if (w[1]==1) y=2'b01; else if (w[2]==1) y=2'b10; else y=2'b11; if (w==0) z=1'b0; else z=1'b1; end endmodule

WAVE FORMS:

RESULT:

By using verilog HDL simulation we implemented the Priority Encoder

ENCODER

AIM: To implement the Encoder by using verilog BLOCKDIAGRAM: [8:3] Encoder [7:0]data PROGRAM: module encoder (code,data); output [2:0] code; input [7:0] data; reg [2:0] code; always @(data) begin if (data==8'b00000001) code=0;else if (data==8'b00000010) code=1;else if (data==8'b00000100) code=2;else if (data==8'b00001000) code=3;else if (data==8'b00010000) code=4;else if (data==8'b00100000) code=5;else if (data==8'b01000000) code=6;else if (data==8'b10000000) code=7; else code=3'bxxx; end endmodule WAVE FORMS:

[2:0]code

RESULT:

By using verilog HDL simulation we have implemented the Encoder.

DECODER

AIM: To implement 3to 8 Decoder by using verilog.

BLOCKDIAGRAM:

[0]a [1]a [2]a PROGRAM: module deco(a,en,y); input [2:0]a; input en; output [7:0]y; reg [7:0]y; begin always@(a) if(en==0) y=8'b00000000; else case(a) 0:y=8'b10000000; 1:y=8'b01000000; 2:y=8'b00100000; 3:y=8'b00010000; 4:y=8'b00001000; 5:y=8'b00000100; 6:y=8'b00000010; 7:y=8'b00000001; endcase end endmodule

3 to 8 DECODER

y[7:0]

WAVE FORMS:

RESULT: BY using verilog HDL simulation we implemented the 3 to 8 decoder.

HALF ADDER
AIM: To implement the half adder by using verilog.

BLOCKDIAGRAM: a b Sum HALF ADDER carry

PROGRAM:
module ha(a,b,s,c); input a,b; output s,c; assign s=a^b; assign c=a&b; endmodule

WAVEFORMS:

RESUlT: By using verilog HDL simulation we implemented the half adder.

FULLADDER
AIM: To implement Full adder by using verilog. BLOCKDIAGRAM: a b cin FULL ADDER Sum cout

PROGRAM: module fa(a,b,cin,s,cout); input a,b,cin; output s,cout; assign s=a^b^cin; assign cout=(a&b)|(b&cin)|(cin&a); endmodule

WAVEFORMS:

RESULT: By using verilog HDL simulation we implemented the full adder.

DEMULTIPLEXER
AIM: To implement Demultiplexer by using verilog. BLOCKDIAGRAM:

1 to 4 DEMUX

[0]y [1]y [2]y [3]y

PROGRAM: module demux (a,s,y); input a; input [1:0]s; output [3:0]y; reg [3:0]y; always @ (a or s) begin case (s)

S0

S1

2'b00 : y[0]=a; 2'b01 : y[1]=a; 2'b10 : y[2]=a; 2'b11 : y[3]=a; default y=4'bxxxx; endcase end endmodule

WAVEFORMS:

RESULT: By using verilog HDL simulation we implemented demultiplexer

MULTIPLEXER.
AIM: To implement multiplexer by using verilog. BLOCKDIAGRAM: X0 X1 X2 X3 4 to 1 MUX

S0 PROGRAM: module mux4to1(x,s,y); input [0:3]x; input [1:0]s; output y; reg y; always @ (x or s) begin case (s) 2'b00 :y=x[0]; 2'b01 :y=x[1]; 2'b10 :y=x[2]; 2'b11 :y=x[3]; endcase end endmodule WAVEFORMS:

S1

RESULT: By using verilog HDL simulation we implement Multiplexer.

HALF SUBTRACTOR

AIM: To implement half subtractor by using verilog BLOCKDIAGRAM:

A B

Half Subtractor

Diff Barrow

PROGRAM: module hs(a,b,diff,barr); input a,b; output diff,barr; assign diff=a^b; assign barr=(~(a)&b); endmodule WAVE FORMS:

RESULT: By using verilog HDL simulation we implement half subtractor.

FULL SUBTRACTOR
AIM: To implement Fullsubtractor by using verilog BLOCKDIAGRAM: A B Bin PROGRAM: module fs(a,b,bin,diff,bout); input a,b,bin; output diff,bout; assign diff=a^b^bin; assign bout=(~bin&b)|(~bin&a)|(a&b); endmodule WAVEFORMS: FULL SUBTRAC TOR Diff Bout

RESULT:

By using verilog HDLsimulation we implement fullsubtractor.

UP-DOWN COUNTER
AIM: To implement up-down counter using verilog. PROGRAM: module counter (clk, clr, up_down, q); input clk, clr, up_down; output [3:0] q; reg [3:0] tmp; always @(posedge clk or posedge clr) begin if (clr) tmp <= 4'b0000; else if (up_down) tmp <= tmp + 1'b1; else tmp <= tmp - 1'b1; end assign q = tmp; endmodule

WAVEFORMS:

RESULT: By using verilogHDL simulation Up-down counter is implemented .

BCD TO GRAY CODE CONVERSION

AIM: To implement BCD to Gray code conversion by using verilog.

BLOCKDIAGRAM:

I bo b1 b2 b3 go g1 g2 g3

BCD to Gray

PROGRAM: module btog (b, g); input [3:0] b; output [3:0] g; assign g [3] = b [3]; xor (g[2], b[2], b[3]); xor (g[1], b[1], b[2]); xor (g[0], b[0], b[1]); endmodule WAVEFORMS:

RESULT: BCD to Gray code conversion is implemented using HDL simulation.

GRAY TO BCD CODE CONVERSION

AIM: To implement Gray to BCD code conversion by using verilog. BLOCKDIAGRAM:

I go g1 g2 g3 bo b1 b2 b3

Gray to BCD

PROGRAM: module gtob (b, g); input [3:0] g; output [3:0] b; assign b[3] = g[3]; xor (b[2], g[2], g[3]); xor (b[1], g[1], g[2]); xor (b[0], g[0], g[1]); endmodule WAVEFORMS:

RESULT: By using verilog HDL simulation Gray to BCD code conversion is implemented.

TRI-STATE BUFFER-BUFIF0
AIM: To implement tri-state buffer (bufif0) by using verilog. BLOCKDIAGRAM:

Bufi f0

in

out

ctrl PROGRAM: module tri_state1 (t, i, o); input t, i; output o; reg o; always @(t or i) begin if (~ t) o = i; else o = 1'bz; end endmodule WAVEFORMS:

RESULT: By using verilog HDL simulation Tri-state buffer(bufif0) is implemented.

TRI-STATE BUFFER-BUFIF1

AIM: To implement tri-state buffer (bufif1) by using verilog. BLOCKDIAGRAM:

Bufi f1

in

out

ctrl PROGRAM: module tri_st_if1 (t, i, o); input t, i; output o; reg o; always @(t or i) begin if ( t) o = i; else o = 1'bz; end endmodule

WAVEFORMS:

RESULT: By using verilog HDL simulation Tri-state buffer(Bufif1) is implemented.

PARITY CHECKER
AIM: To implement the parity checker in verilog. BLOCKDIAGRAM: Parity Checker I[1:9] PROGRAM: module parity(i,even,odd); input[1:9]i; output even,odd; reg p,even,odd; integer j; always@(i) begin p=1'b0; for(j=1;j<=9;j=j+1) if(i[j])p=~p; else p=p; odd =p; even=~p; end endmodule Even Odd

WAVEFORMS:

RESULT: : By using verilog HDL simulation Parity Checker is implemented.