Sei sulla pagina 1di 1
--Flip-Flop D com reset assíncrono e enable --Caveira: Não fazer and entre clock e outra
--Flip-Flop D com reset assíncrono e enable
--Caveira: Não fazer and entre clock e outra --
entrada, como o rst por exemplo.
ENTITY FFD IS
PORT(
clk: IN STD_LOGIC;
rst: IN STD_LOGIC;
enb: IN STD_LOGIC;
d: IN STD_LOGIC;
--Registrador de 16 bits.
--Sem comentarios: reg com incremento.
ENTITY reg_16 IS
PORT (
clk: IN STD_LOGIC;
rst: IN STD_LOGIC;
load: IN STD_LOGIC;
inc: IN STD_LOGIC;
--Registrador com selecao de entrada
ENTITY sisa IS
PORT (
clk: IN STD_LOGIC;
rst: IN STD_LOGIC;
a,b,c: IN STD_LOGIC_VECTOR (15 downto 0);
x: OUT STD_LOGIC_VECTOR (15 downto 0);
op: IN STD_LOGIC_VECTOR (1 downto 0);
--Contador
ENTITY contador IS
GENERIC (N: integer := 16);
PORT (
clk: IN STD_LOGIC;
rst: IN STD_LOGIC;
inc: IN STD_LOGIC;
dec: IN STD_LOGIC;
-----Detector de Quadratura--------
ENTITY DetectorQuadratura IS
PORT (clk: IN STD_LOGIC;
rst: IN STD_LOGIC;
a: IN STD_LOGIC;
b: IN STD_LOGIC;
dec: OUT STD_LOGIC;
inc: OUT STD_LOGIC
entrada: IN STD_LOGIC_VECTOR (15 downto 0);
saida: OUT STD_LOGIC_VECTOR (15 downto 0)
);
END ENTITY sisa;
load: IN STD_LOGIC;
q:
OUT STD_LOGIC
);
END ENTITY FFD;
);
END ENTITY reg_16;
ent: IN STD_LOGIC_VECTOR (N-1 downto 0);
cnt: OUT STD_LOGIC_VECTOR (N-1 downto 0));
END ENTITY contador;
);
END ENTITY DetectorQuadratura;
ARCHITECTURE a OF FFD IS
BEGIN
PROCESS (clk,rst)
BEGIN
IF rst = '1' THEN
ARCHITECTURE super OF reg_16 IS
SIGNAL s: std_logic_vector(15 downto 0);
BEGIN
saida <= s;
PROCESS (clk,rst)
q
<= '0';
BEGIN
IF rst = '1' THEN
ARCHITECTURE a OF sisa IS
SIGNAL xmt,e: STD_LOGIC_VECTOR (15 downto 0);
BEGIN
x <= xmt;
PROCESS (clk,rst)
BEGIN
IF rst = '1' THEN
xmt <= (OTHERS => '0');
ELSIF rising_edge (clk) THEN
ARCHITECTURE a OF contador IS
SIGNAL cont: UNSIGNED (N-1 downto 0);
BEGIN
cnt <= STD_LOGIC_VECTOR (cont);
PROCESS (clk,rst)
BEGIN
ARCHITECTURE A of DetectorQuadratura IS
TYPE tipoestado IS (q0,q1,q2,q3);
SIGNAL estado: tipoestado;
BEGIN
PROCESS (clk,rst)
BEGIN
IF (rst = '1') THEN
estado <= q0;
ELSIF rising_edge (clk) THEN
IF rst = '1' THEN
ELSIF (rising_edge(clk)) THEN
-- com enable
if enb = '1' then
s
<= (OTHERS => '0');
IF op /= "00" THEN
xmt <= e;
cont <= (OTHERS => 0);
CASE estado IS
q
<= 'd';
ELSIF rising_edge(clk) THEN
ELSIF rising_edge(clk) THEN
WHEN q0 =>
--
END IF;
IF
load = '1' THEN
END IF;
--Continuação Detector Quadratura
WHEN q2 =>
IF a = '0' AND b = '1' THEN
estado <= q3;
ELSIF a = '1' AND b = '0' THEN
estado <= q1;
END IF;
WHEN q3 =>
IF a = '0' AND b = '0' THEN
estado <= q0;
ELSIF a = '1' AND b = '1' THEN
estado <= q2;
END IF;
END CASE;
END IF;
END PROCESS;
-------------Maneira 1-------------------------
inc <= '1' WHEN (estado = q0 AND a = '1'
AND b = '0')
OR (estado = q1 AND a = '1' AND b = '1')
OR (estado = q2 AND a = '0' AND b = '1')
OR (estado = q3 AND a = '0' AND b = '0')
ELSE '0';
END IF;
s
<= entrada;
END PROCESS;
END ARCHITECTURE a;
ELSIF inc = '1' THEN
END IF;
END PROCESS;
<= STD_LOGIC_VECTOR (UNSIGNED(s) + 1);
END IF;
END IF;
END PROCESS;
END ARCHITECTURE super;
s
PROCESS (op,a,b,c)
BEGIN
CASE op IS
WHEN "01" => e <= a;
WHEN "10" => e <= b;
WHEN "11" => e <= c;
WHEN OTHERS => e <= (OTHERS => '0');
END CASE;
END PROCESS;
END ARCHITECTURE a;
IF load = '1' THEN
cont <= ent;
ELSIF inc = '1' THEN
cont <= cont + 1;
ELSIF dec = '1' THEN
cont <= cont - 1;
END IF
END IF
END PROCESS;
END ARCHITECTURE a;
IF a = '1' AND b = '0' THEN
estado <= q1;
ELSIF a = '0' AND b = '1' THEN
estado <= q3;
END IF;
WHEN q1 =>
IF a = '1' AND b = '1' THEN
estado <= q2;
ELSIF a = '0' AND b = '0' THEN
estado <= q0;
END IF;
dec <= '1' WHEN ( estado = q0 AND a = '0'
AND b = '1')
OR (estado = q3 AND a = '1' AND b = '1')
OR (estado = q2 AND a = '1' AND b = '0')
OR (estado = q1 AND a = '0' AND b = '0')
ELSE '0';
END ARCHITECTURE A;
-
-----------Sincronizar um sinal assíncrono
ENTITY sincronizador IS
PORT (
------filtro ( DEBOUNCE )
ENTITY filtro IS
PORT (
-------------Sistema Detector
ENTITY sistemaDetector IS
PORT (
--- finalidade: implementar um modulo MESTRE para
uma interface spi
TYPE
tipoestado IS (parado,funcionando);
SIGNAL estado: tipoestado;
clk: IN STD_LOGIC;
clk: IN STD_LOGIC;
clk:
IN STD_LOGIC;
ENTITY mestre IS
GENERIC (
CONSTANT DIV: INTEGER := 100;
BEGIN
x: IN STD_LOGIC;
xsinc: OUT STD_LOGIC);
END sincronizador;
x: IN STD_LOGIC;
xout: OUT STD_LOGIC);
END ENTITY filtro;
rst:
IN STD_LOGIC;
N
: natural := 8; -- tamanho da palavra
a:
IN STD_LOGIC;
M: natural := 16; -- numero de escravos
b:
IN STD_LOGIC;
ARCHITECTURE a OF sincronizador IS
SIGNAL x1: STD_LOGIC;
BEGIN
PROCESS (clk)
BEGIN
IF (rising_edge(clk)) THEN
ARCHITECTURE a OF filtro IS
SIGNAL e: STD_LOGIC_VECTOR (3
downto 0);
BEGIN
PROCESS (clk)
BEGIN
contador: OUT STD_LOGIC_VECTOR (15 downto 0));
END ENTITY sistemaDetector;
);
PORT (
clk: IN std_logic;
rst: IN std_logic;
-- interface com processador
data: INOUT std_logic_vector(N-1 DOWNTO 0);
rd: IN std_logic; -- ativo quando leitura
mclk <= mclkint;
PROCESS(instruction_reg,state_reg)
BEGIN
ssx<= (OTHERS => '0');
IF (state_reg =working) THEN
ssx(TO_INTEGER(UNSIGNED(instruction_reg(3
ARCHITECTURE a OF sistemaDetector IS
SIGNAL asinc, bsinc, afilt, bfilt, xinc, xdec: STD_LOGIC;
BEGIN
a1: ENTITY WORK.sincronizador
DOWNTO 0))))<='1';
END IF;
END PROCESS;
x1
<= x;
wr: IN std_logic; -- ativo quando escrita
addr: IN std_logic;-- 0 = dados, 1 = endereco
PROCESS(clk,rst)
BEGIN
xsinc <= x1;
END IF;
END PROCESS;
END ARCHITECTURE a;
IF (rising_edge(clk)) THEN
e <= e(2 downto 0) & x;
END IF;
END PROCESS;
PORT MAP (clk, a, asinc);
b1: ENTITY WORK.sincronizador
PORT MAP (clk, b, bsinc);
a2: ENTITY WORK.filtro
PORT MAP (clk, asinc, afilt);
cs:
IN std_logic; -- se o mestre for selecionado
PROCESS (clk)
b2: ENTITY WORK.filtro
-- interface spi
mosi: OUT std_logic;-- master output slave input
miso: IN std_logic;-- master input slave output
mclk: OUT std_logic;-- master clock
IF rst = '1' THEN
estado <= parado;
mclkint <= '0';
ELSIF rising_edge(clk) THEN
CASE estado IS
WHEN funcionando =>
IF ccnt /= 0 THEN
ccnt <= ccnt - 1;
ELSE
ccnt <= DIV;
IF mclkint = '0' THEN
mclkint <= '1';
dados <= miso &
dados(7 downto 1);
bcnt <= bcnt - 1;
ELSE
mclkint <= '0';
mosi <= dados(0);
IF bcnt = 0 THEN
estado <= parado;
END IF;
END IF;
END IF;
END CASE;
END IF;
BEGIN
IF e = "1111" THEN
xout <= '1';
ELSE
xout <= '0';
END IF;
END PROCESS;
END ARCHITECTURE a;
PORT MAP (clk, bsinc, bfilt);
d1: ENTITY WORK.detectorQuadratura
PORT MAP (clk, rst, afilt, bfilt, xinc, xdec);
c1: ENTITY WORK.contador
GENERIC MAP (n => 32)
PORT MAP (clk, rst, xinc, xdec, contador);
END ARCHITECTURE a;
ss:
OUT std_logic_vector(M-1 DOWNTO 0) -- slave
WHEN parado =>
select
);
END ENTITY mestre;
ARCHITECTURE a OF mestre IS
SIGNAL instrucao, dados, r: STD_LOGIC_VECTOR (N-1
downto 0);
SIGNAL mclkint: STD_LOGIC;
SIGNAL bcnt: INTEGER RANGE 0 to N-1;
SIGNAL ccnt: INTEGER RANGE 0 to DIV-1;
IF addr = '0' AND cs = '1' AND wr = '1' THEN
dados <= data;
mclkint <= '0';
ELSIF addr = '1' AND cs= '1' AND wr = '1' THEN
instrucao <= data;
estado <= funcionando;
bcnt <= 7;
ccnt <= DIV;
mosi <= dados(0);
mclkint <= '0';
END IF;
END PROCESS;
END ARCHITECTURE a;
-
--- finalidade: implementar um modulo
WHEN parado =>
IF ss = '1' THEN
-------------Comunicação Assincrona
PROCESS(rst,clk)
WHEN data_bit =>
ESCRAVO para uma interface spi
------------TRANSMISSOR
BEGIN
IF (div /= 0) THEN
------------------------RECEPTOR
ENTITY receptor0 IS
ENTITY escravo IS
PORT(
bcnt <= 7;
estado <= funcionando;
ENTITY transmissor0 IS
GENERIC(N: INTEGER := 8);
IF (rst = '1') THEN
div
<= div - 1;
ELSIF (bitcnt /= 0) THEN
clk
:IN STD_LOGIC;
miso <= dados(0);
PORT(
estado <= parado;
ELSIF (rising_edge(clk)) THEN
bitcnt <= bitcnt - 1;
GENERIC (N: INTEGER := 8);
PORT(
clk,rst: IN STD_LOGIC;
rst
:IN STD_LOGIC;
END IF;
WHEN funcionando =>
IF ss = '0' THEN
clk,rst: IN STD_LOGIC;
wr,cs: IN STD_LOGIC;
data: IN STD_LOGIC_VECTOR(n-1 DOWNTO
CASE estado IS
WHEN parado =>
IF (wr = '1' AND cs = '1') THEN
estado <= start_bit;
div
<= DIVMAX;
rx: IN STD_LOGIC;
mosi :IN STD_LOGIC;
sr
<= '1' & sr(N-1 DOWNTO 1);
mclk :IN STD_LOGIC;
ss :IN STD_LOGIC;
miso :OUT STD_LOGIC
estado <= parado;
ELSE
0);
p <= p XOR sr(0);
ELSE
dp: OUT STD_LOGIC;
data: OUT STD_LOGIC_VECTOR (N-1
DOWNTO 0)
busy: OUT STD_LOGIC;
div
<= DIVMAX;
estado <= parity_bit;
);
);
END ENTITY escravo;
IF
mclk = '1' AND mclkant = '0' THEN
tx: OUT STD_LOGIC
p <= '0';
div
<= DIVMAX;
END ENTITY receptor0;
);
END ENTITY transmissor0;
sr
<= data;
END IF;
ARCHITECTURE a OF escravo IS
dados <= mosi & dados (7 downto 1);
bcnt <= bcnt - 1;
ELSIF mclk = '0' AND mclkant = '1' THEN
END IF;
WHEN start_bit =>
WHEN parity_bit =>
IF (div /= 0) THEN
ARCHITECTURE a OF receptor0 IS
TYPE tipoestado IS (parado, start_bit,
TYPE tipoestado IS (parado,funcionando);
miso <= dados(0);
ARCHITECTURE a OF transmissor0 IS
IF (div /= 0) THEN
div
<= div - 1;
data_bit, parity_bit, stop_bit);
SIGNAL estado: tipoestado;
SIGNAL mclkant: STD_LOGIC;
SIGNAL bcnt: integer RANGE 0 TO 7;
SIGNAL dados: STD_LOGIC_VECTOR (N-1
downto 0);
IF bcnt = '0' THEN
bcnt <= 7;
TYPE tipoestado IS (parado, start_bit, data_bit,
parity_bit, stop_bit);
SIGNAL estado: tipoestado;
CONSTANT DIVMAX: INTEGER := 1041;
SIGNAL div: INTEGER RANGE 0 TO 1064;
div
<= div - 1;
ELSE
SIGNAL estado: tipoestado;
ELSE
div
<= DIVMAX;
END IF;
END IF;
END IF;
estado <= data_bit;
bitcnt <= 7;
estado <= stop_bit;
END IF;
CONSTANT DIVMAX: INTEGER := 1041;
SIGNAL div: INTEGER RANGE 0 TO 1064;
SIGNAL bitcnt: INTEGER RANGE 0 TO 7;
div
<= DIVMAX;
BEGIN
END CASE;
SIGNAL bitcnt: INTEGER RANGE 0 TO 7;
END IF;
WHEN stop_bit =>
IF (div /= 0) THEN
SIGNAL p: STD_LOGIC;
SIGNAL sr: STD_LOGIC_VECTOR (N-1
PROCESS(clk,rst)
END IF;
SIGNAL p: STD_LOGIC;
SIGNAL sr: STD_LOGIC_VECTOR(N-1 DOWNTO
div
<= div - 1;
BEGIN
END PROCESS;
END ARCHITECTURE a;
ELSE
DOWNTO 0);
BEGIN
IF rst = '1' THEN
estado <= parado;
ELSIF rising_edge(clk) THEN
mclkant <= mclk;
CASE estado IS
0);
div
<= DIVMAX;
BEGIN
estado <= parado;
END IF;
END CASE;
END IF;
END PROCESS;
--output logic
tx <= '1' WHEN estado = parado
ELSE
PROCESS(rst,clk)
BEGIN
IF (rst = '1') THEN
estado <= parado;
ELSIF (rising_edge(clk)) THEN
CASE estado IS
WHEN parado =>
IF (rx = '0') THEN
'0'
WHEN estado = start_bit
ELSE
sr(0) WHEN estado = data_bit ELSE
estado <= start_bit;
div <= DIVMAX;
p
WHEN estado = parity_bit
ELSE
END IF;
'1'
WHEN OTHERS;
busy <= '0' WHEN estado = parado ELSE
'1';
END ARCHITECTURE a;
-
WHEN start_bit =>
WHEN parity_bit =>
IF (div /= 0) THEN
--Conversor DA PWM
ENTITY conversordapwm IS
--Conversor AD
ENTITY name IS
div
<= div - 1;
IF (div /= 0) THEN
GENERIC(N: INTEGER := 8);
--Comparador do conversor AD
ENTITY comparador IS
PORT(
GENERIC(N: INTEGER := 8);
ELSE
div
<= div - 1;
PORT(
IF
(rx = '0') THEN
estado <= data_bit;
ELSE
clk: IN STD_LOGIC;
va,vb: IN VOLTAGE;--input analog signals
comp: OUT STD_LOGIC--comparation result.
PORT (
clk,start: IN STD_LOGIC;--clock and start
WHEN counting =>
IF (aux_eoc = '0') THEN
cnt <= cnt + 1;
ELSE
estado <= stop;
dp
<= p XOR rx;
wr: IN STD_LOGIC;
div
<= DIVMAX;
bitcnt <= 7;
p <= '0';
--erro -> dp = 1 ;certo dp = 0
estado <= stop_bit;
v: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
saida: OUT STD_LOGIC
);
END ENTITY comparador;
ARCHITECTURE a OF comparador IS
v_an: IN VOLTAGE;--analog signal
eoc: OUT STD_LOGIC; output will be available
value: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0)
div
<= DIVMAX;
);
ELSE
END ENTITY conversordapwm;
);
END ENTITY name;
estado <= parado;
END IF;
WHEN stop_bit =>
BEGIN
comp <= '1' WHEN va < vb ELSE '0';
END ARCHITECTURE a;
END IF;
END CASE;
END IF;
END PROCESS;
END ARCHITECTURE a;
END
IF;
IF (div /= 0) THEN
ARCHITECTURE a OF conversordapwm IS
END IF;
div
<= div-1;
WHEN data_bit =>
IF (div /= 0) THEN
ELSE
estado <= parado;
END IF;
SIGNAL cnt: INTEGER RANGE 0 TO (2**N -1);
SIGNAL vi: INTEGER RANGE 0 TO (2**N -1);
BEGIN
--output logic
--Biblioteca para o conversor AD
PACKAGE analog IS
TYPE VOLTAGE IS RANGE 0 TO 1000
ARCHITECTURE a OF name IS
TYPE tipoestado IS (stop, counting);
SIGNAL estado: tipoestado;
SIGNAL cnt: UNSIGNED(N-1 DOWNTO 0);
div
<=
div - 1;
UNITS
mV; --millivolts
SIGNAL v: VOLTAGE;
SIGNAL aux_eoc: STD_LOGIC;
ELSE
END CASE;
END IF;
saida <= '1' WHEN cnt < vi ELSE '0';
PROCESS(clk)
V
= 1000 mV;
--volts
SIGNAL s: STD_LOGIC_VECTOR(N-1 DOWNTO 0);
p
<= p XOR rx;
END PROCESS;
BEGIN
END UNITS;
sr
<= rx & sr(N-1 DOWNTO 1);
--output logic
IF (rising_edge(clk)) THEN
END PACKAGE;
IF
(bitcnt /= 0) THEN
bitcnt <= bitcnt - 1;
data <= sr;
END ARCHITECTURE a;
IF (cnt < (2**N-1)) THEN
cnt <= cnt + 1;
ELSE
--Conversor DA do conversor AD
ENTITY conversorda IS
BEGIN
dut0: ENTITY work.conversorda
PORT MAP(s_di=>s, s_an=>v);
dut1: ENTITY work.comparador
PORT MAP(va=>v_an, vb=>v, comp=>aux_eoc);
estado <= parity_bit;
ELSE
cnt <= 0;
GENERIC(N: INTEGER := 8);
eoc <= aux_eoc;
div
<= DIVMAX;
END IF;
END
IF;
END IF;
END IF;
END PROCESS;
PORT (
s_di: IN STD_LOGIC_VECTOR (N-1 DOWNTO 0);
s_an: OUT VOLTAGE
s <= STD_LOGIC_VECTOR(cnt);
value <= s;
--state register
PROCESS(clk)
PROCESS(clk)
);
END ENTITY conversorda;
BEGIN
BEGIN
IF (rising_edge(clk)) THEN
IF (wr = '1') THEN
vi <= TO_INTEGER(UNSIGNED(v));
END IF;
END IF;
END PROCESS;
END ARCHITECTURE a;
-- 0
====>
255
-- 0 mV ====>
10000mV
ARCHITECTURE a OF conversorda IS
--NOT SYNTHESIZABLE--
CONSTANT VMAX: INTEGER := 2**n - 1;
BEGIN
s_an <= TO_INTEGER(UNSIGNED(s_di))*10000
mV/VMAX;
IF (rising_edge(clk)) THEN
CASE estado IS
WHEN stop =>
IF (start = '1') THEN
estado <= counting;
cnt <= (OTHERS=>'0');
END IF;
END ARCHITECTURE a;