Debussy 5.0 and Modelsim 5.

X
Windows-Based
Shao-Sheng Yang

2001/08/06
 Before Simulation
• Copy
X:\Novas\Debussy\share\PLI\modelsim_pli\WINNT\nova
s.dll to X:\modelsim\win32\
• Edit X:\modelsim\modelsim.ini and add block box text

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 Simulation
• To add 2 Debussy system tasks to
stimulation file( or call testbench file)

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 In the Modelsim (1)
• 1. Change working directory to directory of source
code (ex: File->Change Directory, f:\temp\)

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 In the Modelsim (2)
• 2. Create a new library for this work (ex: Design
-> Create a New Library)

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 In the Modelsim (3)
• Compile Source Code (ex: Design ->
Compile)

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 In the Modelsim (4)
• Load the top module to modelsim for this work (ex:
the top module is test, Design -> Load Design -> test)

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 In the Modelsim (5)
• View the sub-window, Wave, Structure, and Signals (ex:
View -> Wave, View -> Structure, and View -> Signals)

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 In the Modelsim (6)
• Add selected signals to Wave-window

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 In the Modelsim (7)
• Before • After change display Properties
(ex: Edit-> Display Properties)

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 In the Modelsim (8)
• To Run, In Main window or Wave window press run –all.
(In the red circle)

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 In the Modelsim (9)
• DON’T Finish it when the Finish Vsim is
popped. Press “NO” button

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 In the Modelsim (10)
• Zoom in, Zoom out, or Zoom Full

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 In the Debussy(1)
• Call the nWave from Debussy, or type:
C:\Novas\Debussy\bin\Debussy -nWave

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 In the Debussy(2)
• Open the data base from *.fsdb (ex:reg_bus.fsdb)

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 In the Debussy(3)
• Get selected signals (ex: Signal -> Get Signals)

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 In the Debussy(4)
• The WaveForm

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 //
Appendix-Example
Register Bus Example1
// Din address is 11_1111_1111, are Write or Read
// Dout address is 11_1111_1111, is Read only
// Written by Shao-Sheng Yang

module counter(reg_data,reg_addr,reg_wr,reg_rd,/*reg_en*/dout,load,clk,rst);
inout [15:0] reg_data;
input [9:0] reg_addr;
input reg_wr;
input reg_rd;
input load;
//input reg_en;
output [15:0] dout;
input clk,rst;
wire [15:0] reg_data;
reg [15:0] dout;
reg [15:0] din;
reg [15:0] reg_data_tmp;

assign reg_data=reg_data_tmp;

always @(posedge clk or posedge rst)

begin
if (rst)
begin
din<=16'b0;
end
else
begin
// To write register din from register data bus
if (reg_wr==1'b1)
begin
2001/08/06 case (reg_addr)//synopsys parallel_case 18
10'b11_1111_1111: din <= reg_data;
endcase
 end
else
begin
din <= din;
end
end
end
always @(posedge clk or posedge rst)
begin
if (rst)
begin
reg_data_tmp<=16'b0;
end
else
begin
// TO read register din to register data bus
if (reg_rd==1'b1)
begin
case(reg_addr) //synopsys parallel_case
10'b11_1111_1111:reg_data_tmp<=din;
10'b11_1111_1110:reg_data_tmp<=dout;
default:reg_data_tmp<=16'bz;
endcase
end
else
reg_data_tmp<=16'bz;
end
end
always @(posedge clk or posedge rst)
begin
if (rst)
dout <= 16'b0;
else if (load)
dout <= din;
else
dout <= dout +1'b1;
end
endmodule

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 Appendix-Testbench initial
//Testbench for Register Bus begin
module test; #0
wire [15:0] reg_data; rst=1'b0;
reg [9:0] reg_addr; clk=1'b0;
load=1'b0;
reg [15:0] reg_data_tmp; reg_rd=1'b0;
reg reg_wr; reg_wr=1'b0; @(negedge clk)
reg reg_rd; reg_addr=10'b0; reg_rd=1'b0;
reg load; #10 @(negedge clk)
wire [15:0] dout; rst=1'b1; @(negedge clk)
#12 reg_addr=10'h3fe;
rst=1'b0; reg_rd=1'b1;
reg clk,rst; @(negedge clk) @(negedge clk)
reg_wr=1'b1; reg_rd=1'b1;
counter U1(reg_data,reg_addr,reg_wr reg_data_tmp=16'ha0a0; @(negedge clk)
,reg_rd,dout,load,clk,rst); reg_addr=10'h3ff; reg_addr=10'h3fe;
@(negedge clk) reg_rd=1'b1;
assign reg_data=reg_data_tmp; reg_wr=1'b0; @(negedge clk)
reg_data_tmp=16'ha1a1; reg_rd=1'b0;
initial @(negedge clk) @(negedge clk)
load=1'b1; @(negedge clk)
begin @(negedge clk) $finish;
load=1'b0; end
$fsdbDumpfile("reg_bus.fsdb"); reg_data_tmp=16'hz; always #5 clk=~clk;
//Debussy system task @(negedge clk) endmodule
$fsdbDumpvars; reg_rd=1'b1;
//Debussy system task,dump variables to file .fsdb
end

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