FGMOS BASED WIDE RANGE LOW VOLTAGE CURRENT MIRROR AND ITS ‘APPLICATIONS Susheel Sharma’, 8. S. Rajput™, L. K. Magotra’, and S. S. Jamuar "Department of Physics and Electronics, University of Jammu, Jammu-180006, India **National Physical Laboratory, DKS. Krishnan Mar Department of Elecial Fgincering, Indian Insite of Technology, Hauz Khas, DELHI "New Delhi-140012, India 110016 Presently wth Department of Electeal and Eleronc Engineering, Faculty of Engineering, ‘University Putra Malaysia, 43400 UPM Serdang, Selangor, Malaysia +» Email ssiamuar@eng upm.edu my Abstract Low vollage current mirror (LVCM) based om floating ‘gate MOSFET (FCMOS) has been presented in this Duper The LVCM has ouput ewrent range of 100 410 ‘500 4, high ouput resistance (135 MA at $00 4), high bandwidth 300 Mis) and fow input compliance vollage (2.4 ¥ at 20 yt inpu current and 0.5 V af 300 pt Input eurren) The LYCM design hasbeen ered wing P-Spice for 0Sum technology and the error in current ‘nansfer is observed tobe less than #0.1% Simulations Ihave also been cared ou for P-ppe LCM and Bipolar eM, L Introduction ‘The wage of low voltage civeutin portable and mobile ‘equipment is well established now Tn ponsnobile ‘equipment, the applications of low voltage low power ‘ots re increasing because it reduces the equipment Weight and power consumpdon. ‘The current mio (CMs) ate wed a5 basic element forthe design of lo voltage circuit statues and many low vollage curt Imimor suetres have been developed [1-4], Most of ‘hose structures have low compliance vole at output node but any of tem have high compliance volage at the iput node [1-4]. There are few cleats, which have Jow input and ouput compliance volages. However they have high offset curen, hus imiting the operating ange [U+6), To increase their operating range, adaptation of ‘muliple inputs fosting gate (MIFG) technology (a promising technique in low voltage design), needs tobe amined Tn 2 ruhiple inputs floating gate (MIF) transistor the gate is loting. The frst peysicon layer forms the ‘osting gate (FG) over the n-channel while the second polyilicon lyer forme the male input gate (MIG). ‘The FG is capactvely coupled tothe MIG [7-11], 'A tworinput MIFG MOSFET is shown in Fig. 1 where a de voltage (Vs) is applied at one of the gates called bias gate while the signal is applied atsecond wate temed as signal gate (SG), The resultant threshold 0-7803-7690-002/517.00 2002 IEEE ‘oltage (Va (od) ofthe MOSFET wth epect to 56, Aspens on the theshold voltage of the FG, (a), ad i sven (7,8) Fok) Wa Yale) = Pa o where k= Cyt Cl Cua C) and Ce represent the capacitances between FG and SGs respectively. Cau is the sum of all the capacitances between SGs and FG, capacitance between FO to drain, capacitance between FG to source and capacitance between FG to blk : ae so wat ac A "Is Fig. 1 MIFG Transistor structure ‘We find from eon. (1) that Vg (mod) i desided by Fy 4 and y and hence itis possible to program the Fa according tthe requirements of given application. In this paper we present low vollage CM structures, which ae bit using MIFG MOSFETs. These transistors te avallable in sundard CMOS technology. It needs 4 Supply voltage of 1 V. MLV Current Mirrors using FEMOS A.Negpe LV Current Mirror ‘A conveagonal CM structure ie shown in Fig. 2 (0), which requires input voltage (Va) ofa least one Va. Tis (CM has high compliance voltage at input end and is ‘unsuitable fr low voltage applications, The equivalent of this circuit in MIFG technology is shown in Fig. 2 (0)2(0) OM based on MIFG MOSFETS To this cre, one ofthe gat input tenminals has been wed to program the threshold vollage ofthe MOSFET. ‘The varation of input voltage versus the input eurent a) is shown in Fig. 3. We find thatthe use of de bis Woltage (V7) has dereased the tnesbold voltage but the Ve sharacerstei simile o conventional CM of Fig 2(@) This circuit has Tow compliance voltage at low curens but snot suitable fr high input curent Fig. 3 Input characteristics for various values of 7, However in his ciguit the threshold voltage can be ‘made programmable if the input volage canbe made to change proportional tof This is achieved by feeding back ft produce a voltage proportional othe Jy Ths vag is obtained by passing through a esstance. The voltage drop across the resistance wil be high thigh Jy while it wil be Tow at low Iq, A circuit, which Jmplement thi behavior, shown in Fi.) where Ix fs fed back ough cure mirror formed by Mand MS. 382 ‘To have complete CMOS implementation, 2 MOSFET MG as shown in Fig. 4() has replaced the resistance. The tse of ME reduces the thesbold sufficiently at high Ja However, a low , almost negligible cient flows through M6, whch provide very Low bas voltage (F)-In i mode, the input voltage i almost simile to a simple 7M, To deceate this voltage further, «constant curent ‘ow has to be maintained through the MOSFET M6. The ouput impedance of this stuctue is ow. Using MOSFET M7 as shown in Fig. § increases the ouput impedance. To bias MD, tansitors MB and MO ae sed. Fig. 4 (6) OM using MIFG with resistor ‘The circuit shown in Fig. 5 obtains a futher Improvement over the structure shown in fg. (8). We hive added MOSFETS M7 and MB and the ouput is taken from the drain of M7. This suucture is similar to the one given in (78). The use of MT and MB has given aed advantage of low output compliance voltage high ‘output impedance. MS. This circuit uses feedback ferns at two places. One for programming the threshold Voge, which is higher at higher input currents ‘hereby reducing the input compliance voltage at high input currents. Seconlly the current is fed back to bias the tansisor Mf, which increases the ouput impedance ‘ofthe resultant trent itor. Fig. 4 (0) CM using MIFG MOSFET ‘The CM crcits have been simulated sing level 3 P- Spice parameters for 0.Sum technology. with supply voliages of 40.75V. IL ratios for various MOSFET are Chosen 25 200mm for Mand M2, SOwn/Ium for(MB, 100umi0.Sum for Mand MS, 3S,/1 4m for ME, 200yw0.Sum for M7, Summ for MB. and ‘Surw0.Sum for MO. The ino port characteristics ofthe ‘yanous CMs are shown in Fig. 6. We find from tis plat that the LVCM propoted in Fig, 5 hat the best perfomance. The power consumption is 1 26nW. te Fig 5 Proposed fn! structure for MIFG Miror tc ik Fig. 6 Comparative Vac curves for vious CMs () Conventional CM (i) EM ih resistor (i) CM "with MOSFET (v) Proposed LVM “The LY characterises of proposed LVCM are shown in Fig. 7. The offset curent is found to be SENA and urent transfer ratio i almost equal to wn (Fig. 8), with emor less than 20.1%. The frequeney response of ‘proposed CM is shown in Fig. 9 and the bandwidth is found as $00 MER. BPppe LYCM ‘A Patgpe LVCM can be built by replacing NMOS by PMOS ia Fig. 5. The power dissipated ie found to be 48mW. The resulting circuit has been simulated which shows current transfer error less than # 015% and the bandit i ofthe order of250 Mi ‘Bitterat Curren Mirror A bilateral. CM can be constructed sing the proposed ‘ruts forthe mirs in MIFG technology. The resltant structure i shown in Fig 10, sett Fig. 7. charsctersis ofthe proposed mite Opec and tear hi ig. 8 Current transfer characteristics i: 3 Fig, 9 Frequency response ofthe proposed mizor Fig. 10 Propose bilateral CM. ‘The circuit hasbeen simulated and it was found that the circuit offers input resistance of 2000, output resistance LIMA, and bandwidth of 398 Miz, The eror in the curent ansfer err is found les than 0.3%. The Ve eharactersties ae shown in ig 1