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INTRODUCTION
INTRODUCTION
I-1
University of California Berkeley
College of Engineering Department of Electrical Engineering and Computer Science
Required Text
Analysis and Design of Analog Integrated Circuits, 4th Edition, P.R. Gray, P. Hurst, S. Lewis and R.G. Meyer, John Wiley and Sons, 2001
Supplemental Texts
B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001. Thomas Lee, The Design of CMOS Radio Frequency Integrated Circuits, Cambridge University Press, 1998 The SPICE Book, Andre Vladimirescu, John Wiley and Sons, 1994
Prerequisites
EECS 105: Microelectronic Devices and Circuits
ROBERT W. BRODERSEN
LECTURE 1
ROBERT W. BRODERSEN
LECTURE 1
INTRODUCTION
I-2
University of California Berkeley
College of Engineering Department of Electrical Engineering and Computer Science
EE142 Non-Linear
EE141 Digital
Sensors, Transducers
Interface Circuits
ROBERT W. BRODERSEN
LECTURE 1
ROBERT W. BRODERSEN
LECTURE 2
i in
+
+ -
b) Voltage, Current Dividers c) Thevenin, Norton Equivalents d) 2-Port Equivalents e) Phasors, Frequency Response
Vs
+ a i n
out
RL
R S = i n = 0
out A = ------in
RL
i in
+
i out in1
Rin1
+ -
out1 in2 + a 1 i n 1
-
R out1
R out2 Rin2
+ a 2 in2
out
-
M-3 Cutoff :
V GS < V T
M-4
V DSAT I DS Saturation
Linear :
V GS > V T V D S < V D S A T = VG S V T VD I D S = k' W V G S V T -------S V D S --2 L
Linear
Saturated :
V GS > V T V D S > V D S A T = VG S V T
ROBERT W. BRODERSEN
LECTURE 2
M-5
M-6
(VSB > 0 ) V T o Threshold Voltage @ V S B = 0 f Fermi Potential 0.3 Body Effect Factor Short Channel Effect W Width of Device L Length k' = C ox
Oxide Capacitance mobility E VBS E = V DS/L VT S n G ++++++++ n D
1 = ------ C ox
2 q NA
VTo
0
ROBERT W. BRODERSEN
LECTURE 2
ROBERT W. BRODERSEN
LECTURE 2
M-7
M-8
Modeled as
k' W I (DB) = --- --- ( V G S V T )2 ( 1 + V D S) -2 L
I (DB) = I DS V DS
( A) k' W ID 2 dL = --- -------- ( V G S V T ) E F F VD S 2 L2 FF d VD S E
L = L drawn 2 L D LE F F = L X D X D = f ( VD S )
ROBERT W. BRODERSEN
LECTURE 2
ROBERT W. BRODERSEN
LECTURE 3
M-9
I DS Ideal
I D S
S
Longer Channel (Increasing L)
W L
C G W L COX
ROBERT W. BRODERSEN
LECTURE 3
ROBERT W. BRODERSEN
LECTURE 3
M-10 M-11
M-12
gm gs gmbs bs V SB B ro
gm =
What is VDSAT ? G bs + dI D S ds dV DS k' I D S = --- W ( V G S V T ) 2 = k' W V 2 S A T ------ ---D 2 L 2 L W g m = k' --- V D S A T so, -L 2 ID S 2 V D S A T = -------------------- k' W L
LECTURE 3
1 -
gm
ROBERT W. BRODERSEN
gmbs
LECTURE 3
dID S dID S gs + d VG S d V BS
+ S
1/ro
V G S = VT + V D S A T
ROBERT W. BRODERSEN
M-13
M-14
C js 0V
Q c h a n n e lduetovgs C o x g s Q c h a n n e ld u e t o v b s C j s b s C js = -----C ox
g mbs ------- = gm
ROBERT W. BRODERSEN
LECTURE 3
M-15
M-16
ROBERT W. BRODERSEN
LECTURE 3
ROBERT W. BRODERSEN
LECTURE 3
LECTURES ON SPICE
LECTURES ON SPICE
Robert W. Brodersen
EECS140
Lectures on SPICE
ROBERT W. BRODERSEN
LECTURE 4
ROBERT W. BRODERSEN
LECTURE 4
LECTURES ON SPICE
LECTURES ON SPICE
SP-1 Spice Transistor Model : M1 1 2 3 4 nch L=1 W=10 AD=( ) AS=( ) PD=( ) PS=( ) NRD=( ) parasitic resistors
G
SPICE Initial Operationg Point DC currents and Voltages Linearize Around OP Point Solve Eqn. New Operating Point No DC Converge? Yes Increment Time No End of Time Interval
LECTURE 4
SP-2
area of drain 1
S L
2 3
Yes
STOP
ROBERT W. BRODERSEN
LECTURE 4
ROBERT W. BRODERSEN
LECTURES ON SPICE
LECTURES ON SPICE
4 + R4 1 I1 + VB R1
VA I4 G i = 1/Ri 3 R2 R3
SP-4
( G 1 + G 4 ) V1
G1 V 2
G 4 V 4 + I1 = 0
= 0
G 1 V 1 + ( G 1 + G 2 + G 3 ) V2 G 3 V3 G 3 V2 + G 3 V3 G4 V 1 V1 V 3 V 4
Current src G B F R V = I E C Total # of EQNS N=n + n v + nl n = # of circuit nodes nv= # of independent voltage srcs nl= # of inductors
LECTURE 4
I4 = 0 G 4 V 4 + I4 = 0
= VB = VA
Votlage src
ROBERT W. BRODERSEN
ROBERT W. BRODERSEN
LECTURE 4
LECTURES ON SPICE
LECTURES ON SPICE
b (10 ) b2
(0)
b (10 ) b2
(1 )
b (32 )
b (30 )
Eliminate a 21,a 31
e (11 ) = e (10) a e (21) = e (20) ------) e (10 ) (0 a 11
(0 ) 21
(0 ) 31
x x x 0 x x 0 x x
Solution
ROBERT W. BRODERSEN
LECTURE 4
ROBERT W. BRODERSEN
LECTURE 4
LECTURES ON SPICE
LECTURES ON SPICE
Accuracy Cant divide by 0 or small numbers, so pivoting is used to reorder eqns (Basically renumbering nodes). Puts maximum values on diagonal. R 1 =1
1 1 1 1.0001 V1 = V2 1 0
1 1 - --------- = G 1 + G 2 1 10 k
SP-7 To control accuracy .options PIVTOL = <values> (1018) This sets the allowable range of conductance values. *ERROR* : Maximum entry ......at STEP ....... is less than PIVTOL -Probably means you have an incorrect element or floating node
SP-8
1A
R 2=10k
Actually,
V 1 = 10 , 001V V 2 = 10 , 000V
ROBERT W. BRODERSEN
LECTURE 4
ROBERT W. BRODERSEN
LECTURE 4
LECTURES ON SPICE
LECTURES ON SPICE
SP-10 Newton-Raphson Iteration : - Make guess of next operation point in iteration Start at initial guess and linearize diode eqn.
+ IA G VD IG ID ID,G
IA
IG
+ V D(0) ID0
ROBERT W. BRODERSEN
LECTURE 4
ROBERT W. BRODERSEN
LECTURE 4
LECTURES ON SPICE
LECTURES ON SPICE
SP-11 Convergence Keep iterating until all voltages and currents are within a a tolerance value.
V (ni) = node voltage n at iteration i Vn = R E L ( V ) m a x ( V (ni + 1 ) , V (ni) ) + A B S ( V)
SP-12
A B S ( V ) 10 6 (Default 50V )
ABS(V) should be at least two orders of magnitude below required accuracy. These values would give 1 part in 104 accuracy down to 100V resolution
ROBERT W. BRODERSEN LECTURE 4
ROBERT W. BRODERSEN
LECTURE 4
SP-13 Current convergence is broken into two types; MOS and NOT MOS
MOS A B S M O S A B S O L U T E ( 10 6 ) R E L M O S RELATIVE ( 0.5 ) ABSI A B S O L U T E ( 10 9) R E L I RELATIVE ( 0.01 )
NOTMOS
ITL = # of steps in iteration (200) When you get *ERROR* no convergence in DC analysis and the last node voltages Then it hasnt converged in 200 times - something is probably wrong with your netlist
ROBERT W. BRODERSEN LECTURE 2