Code No: NR411905 NR

IV B.Tech I Semester Supplementary Examinations, November 2006

VLSI TECHNOLOGY
(Electronics & Computer Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
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1. (a) Explain in detail the p-well process for CMOS fabrication indicating the masks
used.
(b) Draw a neat sketch of CMOS inverter fabricated using n-well process. [12+4]

2. (a) Derive the relation ship between drain to source current Ids verses drain to
source voltage Vds in non saturated and saturated region.
(b) Draw graphs of Ids vs Vds for depletion and enhancement mode MOS tran-
sistors. [8+8]

3. Using block schematics, explain the terms

(a) PLDs
(b) CPLDs
(c) FPGAs
(d) PALs [16]

4. Explain about the design approaches for full custom and semi custom Devices [16]

5. Briefly explain the following verification tools:

(a) timing verifiers

(b) design rule checkers
(c) layout extractions and
(d) test vectors. [4+4+4+4]

6. Discuss the following types of simulations

(a) circuit level [4]

(b) logic level [3]
(c) switch level [3]
(d) mixed mode and [3]
(e) timing simulations. [3]

7. (a) Explain the wire bonding.

(b) Compare through hole and ceramic packages. [8+8]

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Code No: NR411905 NR
8. (a) Prove that the combination of BJT and MOS technology offers the best per-
formance in Analog VLSI design.
(b) Draw the block diagram of D/A converter suitable for VLSI Analog Circuits
and explain. [8+8]

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