PART I: SOLUTIONS CHAPTER L (Components of a computer: ALU and Control Unit (CPU), Memory, Input, and Output. Functions of various components: CPU: It processes and stores binary data, wansfers data from and to memory and VO devices, and provides timing to all the operations. It includes ALU, register arrays, and control unit. ‘The ALU perfonns the arithmetic and logic operations, and the control unit provides timing. ‘Input - provides binary data as an input to the CPU. Output - accepts binary data from the CPU. A microprocessor functions as the CPU of a microcomputer, and includes the ALU, register arrays, and the control unit on one chip; itis manufactured using the LSL technology. On the other hand, the CPU is designed with various discret boards, Functionally, beth are similay however, technology and processes used for designing is different A microprocessor is one component of a microcomputer, and the microcomputer is ‘complete computer consists of a microprocessor, memory, input, and output ‘See Summary: Scale oF Totagration Four bytes. ‘The machine language of the 8085 are the comamands to the microprocessor given in binary. ‘These are the binary instructions the processor can understand and execute. ‘The assembly language comprise of mnemonics (group of letiers to represent commands) assigned by the ‘manufacturer for the convenience of the users, 9, 10, 11, See Summary: Computer Languages 2. ‘The assembly language mnemonics represent instructions to the microprocessor: therefore. when they are wanslated into machine language, there is one-to-one correspondences between the mnemonics and the machine code. The assembly language programs are compact, require less memory space, and are efficient. ‘The high level languages arc written, in English- like statements, and when these statements are translated in machine language, the ‘object code tends to be large. and requires large memory. ‘The execution of the programs ‘written in high level languages is less efficient than that of assembly language programs13, 14. See Summary: Computer Languages 15. 16, ASCII codes in Hex: A= a1, 5A, and m=6D s Summary: Computer Languages CHAPTER? 1 2 10 12, Memory Read, Memory Write, VO Read, and U0 Wate, A bus is group of ines (wires or conductors) which cary digital informasion, “The function ofthe address busi to camy’a binary address of'a memory jcation or an YO device. ‘The address bus is unidirectional, and dhe information flows from the MPU t9 ‘peripherals and memory _A microprocessor with 14addreas lines is capable of addressing 16K (2) memory locations 21 adress tines. ‘Data bytes are transferred in both dizetions between the MPU and memory/perpheral. TOR (VO Read), 1OW (VO Write), MEMR (Memory Read), end MEMW (Memory Writ). In memory write operation, the control siznal required is MEMW, and the dirotion of the data flow is fom the MPU to memory. ‘The accumulators an 8-bitregister and itiea partof the ALU. All8-bt arithmetic and logic ‘operations are performed in relation to the accumulator content, and theresult i storedin the steurnulator (with a few exceptions) A fing i the output of a given Mip-flop to indieate certain data conditions. ‘The program counter and the stack pointer store memory sddresses of 16 bits. ‘The program counter always points to the next memory Tocation; therefore, the content of the program counter will be 2055H. 128 registers and 128 X4 = 512 memory cells. 1024 bits are can be stored by this chip; however, it can not be specified as 2 128-byte _memary chip because the byte indicates § bit memory registers; this chip has 4-bit registers.15, 16. v7. 18. 18. 21 2, 2 2, 2s. 26 21, 28, 29, 30, 3 32. 33. 34 .bit wort size, 8 chips. 4 chips 32 chips ‘The WR signal enables the input buffer of a memory chip co that information can be stored (orien) in the selected memory register 1 address tines, ‘The staring address is FBOOH, and the memory map is FSO0H to FBFFH. “The staring adress ie: BOOOH. ‘The address ranges fom FFOOH to FFFFH. “The address ofthe selected register: 1000 0000 0100 0111 = $0474 ‘The memory map ranges fora 2000H to 23FFH. “The address of the selected register: 0010 0000 1111 1000 = 20F8H4 8 address lines are required for a peripheral UO port, aad 16 address lines are required fr a memory-mapped VO por ‘Tri-state devices ae logie devices with tee states; the third state is high impedance, In a ‘bus-orlented system, devices are connected in parallel, and the buses are capable of diving fone TTL logic device. The MPU communicates with one peripheral at a time, snd other peripherals are placed in high impedance to avoid bus loading High impedance state. From B10 A. None. The decoder is not enabled: all output lines will be hi “The line 6 (00, 001 (Complement of 1 10)