Exp.No: 1 BASIC GATES Date : 30.01.10 __________________________________________________________________________________ Aim : 1. To write source code in VHDL for a basic gates 2.

To compile and simulate the programs using Modelsim simulator 3. To verify the functionality of the various modules by obtaining test bench waveforms Program Dataflow model Or2.vhd LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY OR2 IS PORT(A,B:IN STD_LOGIC; C:OUT STD_LOGIC); END OR2; ARCHITECTURE OR2_ARCH OF OR2 IS BEGIN C<=(A OR B); END OR2_ARCH; and2.vhd LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY AND2 IS PORT(A,B:IN STD_LOGIC; C:OUT STD_LOGIC); END AND2; ARCHITECTURE AND2_ARCH OF AND2 IS BEGIN C<=(A AND B); END AND2_ARCH; Not2.vhd LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY NOT2 IS PORT(A:IN STD_LOGIC; B:OUT STD_LOGIC); END NOT2; ARCHITECTURE NOT2_ARCH OF NOT2 IS BEGIN B<=(NOT A); END NOT2_ARCH; xor2.vhd LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY XOR2 IS PORT(A,B:IN STD_LOGIC; C:OUT STD_LOGIC); END XOR2;

ARCHITECTURE XOR2_ARCH OF XOR2 IS BEGIN C<=(A XOR B); END XOR2_ARCH; Test Bench Waveforms For XOR Gate

Result : The source code in VHDL For basic gates have been written,compiled and simulated using Modelsim simulator.The functionality of the various modules was verified by obtaining test bench waveforms.

Exp.No: 2 ADDERS Date : 30.01.10 __________________________________________________________________________________ Aim :

1. To write source code in VHDL for Half-adder and Full-adder 2. To compile and simulate the programs using Modelsim simulator 3. To verify the functionality of the various modules by obtaining test bench waveforms Program: Half-Adder Dataflow Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY HA_DAT IS PORT(A,B:IN STD_LOGIC; SUM,COUT:OUT STD_LOGIC); END HA_DAT; ARCHITECTURE HA_DAT_ARCH OF HA_DAT IS BEGIN SUM<=(A XOR B); COUT<=(A AND B); END HA_DAT_ARCH; Structural Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY HA_STD IS PORT(X,Y:IN STD_LOGIC; SUM,COUT:OUT STD_LOGIC); END HA_STD; ARCHITECTURE HA_STD_ARCH OF HA_STD IS COMPONENT XOR2 IS PORT(A,B:IN STD_LOGIC; C:OUT STD_LOGIC); END COMPONENT; COMPONENT AND2 IS PORT(A,B:IN STD_LOGIC; C:OUT STD_LOGIC); END COMPONENT; BEGIN X1:XOR2 PORT MAP(X,Y,SUM); X2:AND2 PORT MAP(X,Y,COUT); END HA_STD_ARCH; Behavioral Model LIBRARY IEEE; USE IEEE.STD_LOGIC.1164.ALL; ENTITY HA_BEH IS PORT(X,Y:IN STD_LOGIC; SUM,COUT:OUT STD_LOGIC); END HA_BEH; ARCHITECTURE HA_BEH_ARCH OF HA_BEH IS BEGIN PROCESS(X,Y) BEGIN IF(X='0' AND Y='0') THEN SUM<='0'; COUT<='0'; ELSIF(X='0' AND Y='1') OR (X='1' AND Y='0') THEN

SUM<='1'; COUT<='0'; ELSIF(X='1' AND Y='1') THEN SUM<='0'; COUT<='1'; END IF; END PROCESS; END HA_BEH_ARCH; Full-Adder Dataflow Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY FA_DAT IS PORT(A,B,CIN:IN STD_LOGIC; SUM,COUT:OUT STD_LOGIC); END FA_DAT; ARCHITECTURE FA_DAT_ARCH OF FA_DAT IS BEGIN SUM<=(A XOR B XOR CIN); COUT<=((A AND B) OR ( B AND CIN) OR (A AND CIN)); END FA_DAT_ARCH; Structural Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY FA_STD IS PORT(X,Y,CIN:IN STD_LOGIC; SUM,COUT:OUT STD_LOGIC); END FA_STD; ARCHITECTURE FA_STD_ARCH OF FA_STD IS SIGNAL SUM1,C2,C3,C4,C5:STD_LOGIC; COMPONENT XOR2 PORT(A,B:IN STD_LOGIC; C:OUT STD_LOGIC); END COMPONENT; COMPONENT AND2 PORT(A,B:IN STD_LOGIC; C:OUT STD_LOGIC); END COMPONENT; COMPONENT OR2 PORT(A,B:IN STD_LOGIC; C:OUT STD_LOGIC); END COMPONENT; BEGIN X1:XOR2 PORT MAP(X,Y,SUM1); X2:XOR2 PORT MAP(CIN,SUM1,SUM); X3:AND2 PORT MAP(Y,CIN,C2); X4:AND2 PORT MAP(X,CIN,C3); X5:AND2 PORT MAP(X,Y,C4); X6:AND2 PORT MAP(C2,C3,C5); X7:AND2 PORT MAP(C4,C5,COUT); END FA_STD_ARCH; Behavioral Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY FA_BEH IS PORT(A,B,CIN:IN STD_LOGIC;

SUM,COUT:OUT STD_LOGIC); END FA_BEH ; ARCHITECTURE FA_BEH_ARCH OF FA_BEH IS BEGIN PROCESS(X,Y,CIN) BEGIN IF(A='0' AND B='0' AND CIN='0') THEN SUM<='0';COUT<='0'; ELSIF(A='0' AND B='0' AND CIN='1') OR (A='0' AND B='1' AND CIN='0') OR (A='1' AND B='0' AND CIN='0') THEN SUM<='1';COUT<='0'; ELSIF(A='0' AND B='1' AND CIN='1') OR (A='1' AND B='0' AND CIN='1') OR (A='1' AND B='1' AND CIN='0') THEN SUM<='0';COUT<='1'; ELSIF(A='1' AND B='1' AND CIN='1') THEN SUM<='1';COUT<='1'; END IF; END PROCESS; END FA_BEH_ARCH; 4BIT Full Adder Structural Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY FA4_STD IS PORT(A,B:IN STD_LOGIC_VECOTR(3 DOWNTO 0); CIN:IN STD_LOGIC; SUM:OUT STD_LOGIC_VECOTR(3 DOWNTO 0); COUT:OUT STD_LOGIC); END FA4_STD; ARCHITECTURE FA4_STD_ARCH OF FA4_STD IS SIGNAL C1,C2,C3:STD_LOGIC; COMPONENT FA_STD IS PORT(A,B,C:IN STD_LOGIC; S,CO:OUT STD_LOGIC); END COMPONENT; BEGIN X1:FA_STD PORT MAP(A(0),B(0),CIN,SUM(0),C1); X2:FA_STD PORT MAP(A(1),B(1),C1,SUM(1),C2); X3:FA_STD PORT MAP(A(2),B(2),C2,SUM(2),C3); X4:FA_STD PORT MAP(A(3),B(3),C3,SUM(3),COUT); END FA4_STD_ARCH; Test Bench Waveforms For Half-Adder

Test Bench Waveforms For Full-Adder

Test Bench Waveforms For 4BIT Full-Adder

Result : The source code in VHDL For Half-Adder and Full-Adder have been written,compiled and simulated using Modelsim simulator.The functionality of the various modules was verified by obtaining test bench waveforms. Exp.No: 3 SUBTRACTORS Date : 30.01.10 __________________________________________________________________________________ Aim :

1. To write source code in VHDL for Half-subtractor and Full-subtractor 2. To compile and simulate the programs using Modelsim simulator 3. To verify the functionality of the various modules by obtaining test bench waveforms Program: Half-Subtractor DataFlow Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY HS_DAT IS PORT(A,B:IN STD_LOGIC; D,BOUT:OUT STD_LOGIC); END HS_DAT; ARCHITECTURE HS_DAT_ARCH OF HS_DAT IS BEGIN D<=(A XOR B); BOUT<=((NOT A) AND B); END HS_DAT_ARCH; Structural Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY HS_STD IS PORT(X,Y:IN STD_LOGIC; D,BOUT:OUT STD_LOGIC); END HS_STD; ARCHITECTURE HS_STD_ARCH OF HS_STD IS SIGNAL C:STD_LOGIC; COMPONENT XOR2 IS PORT(A,B:IN STD_LOGIC; C:OUT STD_LOGIC); END COMPONENT; COMPONENT AND2 IS PORT(A,B:IN STD_LOGIC; C:OUT STD_LOGIC); END COMPONENT; COMPONENT NOT2 IS PORT(A:IN STD_LOGIC; B:OUT STD_LOGIC); END COMPONENT; BEGIN X1:XOR2 PORT MAP(X,Y,D); X2:NOT2 PORT MAP(X,C); X3:AND2 PORT MAP(C,Y,BOUT); END HS_STD_ARCH;

Behavioral Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY HS_BEH IS PORT(X,Y:IN STD_LOGIC; D,BOUT:OUT STD_LOGIC);

END HS_BEH; ARCHITECTURE HS_BEH_ARCH OF HS_BEH IS BEGIN PROCESS(X,Y) BEGIN IF(X='0' AND Y='0') OR (X='1' AND Y='1') THEN D<='0'; BOUT<='0'; ELSIF(X='0' AND Y='1') THEN D<='0'; BOUT<='1'; ELSIF(X='1' AND Y='0') THEN D<='1'; BOUT<='0'; END IF; END PROCESS; END HS_BEH_ARCH; Full-Subtractor Dataflow Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY FS_DAT IS PORT(A,B,BIN:IN STD_LOGIC; D,BOUT:OUT STD_LOGIC); END FS_DAT; ARCHITECTURE FS_DAT_ARCH OF FS_DAT IS BEGIN D<=(A XOR B XOR BIN); BOUT<=(((NOT A) AND B) OR ( (NOT A) AND BIN) OR (B AND BIN)); END FS_DAT_ARCH; Structural Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY FS_STD IS PORT(A,B,BIN:IN STD_LOGIC; D,BOUT:OUT STD_LOGIC); END FS_STD; ARCHITECTURE FS_STD_ARCH OF FS_STD IS SIGNAL D1,C1,C2,C3,C4,C5:STD_LOGIC; COMPONENT XOR2 PORT(A,B:IN STD_LOGIC; C:OUT STD_LOGIC); END COMPONENT; COMPONENT AND2 PORT(A,B:IN STD_LOGIC; C:OUT STD_LOGIC); END COMPONENT; COMPONENT OR2 PORT(A,B:IN STD_LOGIC; C:OUT STD_LOGIC); END COMPONENT; COMPONENT NOT2 PORT(A:IN STD_LOGIC; C:OUT STD_LOGIC); END COMPONENT; BEGIN

X1:XOR2 PORT MAP(X,Y,D1); X2:XOR2 PORT MAP(BIN,D1,D); X3:NOT2 PORT MAP(X,C1)L X4:AND2 PORT MAP(C,Y,C2); X5:AND2 PORT MAP(C1,BIN,C3); X6:AND2 PORT MAP(Y,BIN,C4); X7:OR2 PORT MAP(C2,C3,C5); X8:OR2 PORT MAP(C5,C4,BOUT); END FS_STD_ARCH; Behavioral Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY FS_BEH IS PORT(A,B,CIN:IN STD_LOGIC; SUM,COUT:OUT STD_LOGIC); END FS_BEH ; ARCHITECTURE FS_BEH_ARCH OF FS_BEH IS BEGIN PROCESS(X,Y,CIN) BEGIN IF(A='0' AND B='0' AND CIN='0') OR (A='1' AND B='0' AND CIN='1') OR (A='1' AND B='1' AND CIN='0') THEN SUM<='0';COUT<='0'; ELSIF(A='0' AND B='0' AND CIN='1') OR (A='0' AND B='1' AND CIN='0') OR (A='1' AND B='1' AND CIN='1') THEN SUM<='1';COUT<='1'; ELSIF(A='0' AND B='1' AND CIN='1') THEN SUM<='0';COUT<='1'; ELSIF(A='1' AND B='0' AND CIN='0') THEN SUM<='1';COUT<='0'; END IF; END PROCESS; END FS_BEH_ARCH;

Test Bench Waveform For Half-Subtractor

Test Bench Waveform For Full-Subtractor

Result : Thus source code in VHDL for Half-Subtractor and Full-Subtractor and Have been written,compiled and simulated using Modelsim simulator.The functionality of the various modules was verified by obtaining test bench waveforms.

Exp.No: 4 Date : 06.02.10

MULTIPLEXER AND DEMULTIPLEXER

__________________________________________________________________________________ Aim : 1. To write source code in VHDL for Multiplexer and Demultiplexer 2. To compile and simulate the programs using Modelsim simulator 3. To verify the functionality of the various modules by obtaining test bench waveforms Program Multiplexer Dataflow Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MUX4_DAT IS PORT(S0,S1,D0,D1,D2,D3:IN STD_LOGIC; Y:OUT STD_LOGIC); END MUX4_DAT; ARCHITECTURE MUX4_DAT_ARCH OF MUX4_DAT IS BEGIN Y<= (D0 AND (NOT S1) AND (NOT S0)) OR (D1 AND (NOT S1) AND S0) OR (D2 AND S1 AND (NOT S0)) OR (D3 AND S1 AND S0); END MUX4_DAT_ARCH; Structural model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MUX4_STD IS PORT(S0,S1,D0,D1,D2,D3:IN STD_LOGIC; Y:OUT STD_LOGIC); END MUX4_STD; ARCHITECTURE MUX4_STD_ARCH OF MUX4_STD IS SIGNAL V0,V1,A0,A1,A2,A3:STD_LOGIC; COMPONENT AND3 IS PORT(A,B,C:IN STD_LOGIC; D:OUT STD_LOGIC); END COMPONENT; COMPONENT OR4 IS PORT(A,B,C,D:IN STD_LOGIC; E:OUT STD_LOGIC); END COMPONENT; COMPONENT NOT2 PORT(A:IN STD_LOGIC; B:OUT STD_LOGIC); END COMPONENT; BEGIN X1:NOT2 PORT MAP(S0,V0); X2:NOT2 PORT MAP(S1,V1); X3:AND3 PORT MAP(D0,V0,V1,A0); X4:AND3 PORT MAP(D1,V0,S1,A1); X5:AND3 PORT MAP(D2,S0,V1,A2); X6:AND3 PORT MAP(D3,S0,S1,A3); X7:OR4 PORT MAP(A0,A1,A2,A3,Y); END MUX4_STD_ARCH; Behavioral Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MUX4_BEH IS

PORT(S0,S1,D0,D1,D2,D3:IN STD_LOGIC; Y:OUT STD_LOGIC); END MUX4_BEH; ARCHITECTURE MUX4_BEH_ARCH OF MUX4_BEH IS BEGIN PROCESS(S0,S1,D0,D1,D2,D3) BEGIN IF(S0='0' AND S1='0') THEN Y<=D0; ELSIF(S0='0' AND S1='1') THEN Y<=D1; ELSIF(S0='1' AND S1='0') THEN Y<=D2; ELSIF(S0='1' AND S1='1') THEN Y<=D3; END IF; END PROCESS; END MUX4_BEH_ARCH; DeMultiplexer Dataflow Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DMUX4_DAT IS PORT(S0,S1,D:IN STD_LOGIC; Y0,Y1,Y2,Y3:OUT STD_LOGIC); END DMUX4_DAT; ARCHITECTURE DMUX4_DAT_ARCH OF DMUX4_DAT IS BEGIN Y0<=(D AND (NOT S0) AND (NOT S1)); Y1<=(D AND (NOT S0) AND S1); Y2<=(D AND S0 AND (NOT S1)); Y3<=(D AND S0 AND S1); END DMUX4_DAT_ARCH; Structural Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DMUX4_STD IS PORT(S0,S1,D:IN STD_LOGIC; Y0,Y1,Y2,Y3:OUT STD_LOGIC); END DMUX4_STD; ARCHITECTURE DMUX4_STD_ARCH OF DMUX4_STD IS SIGNAL V0,V1:STD_LOGIC; COMPONENT AND3 IS PORT(A,B,C:IN STD_LOGIC; D:OUT STD_LOGIC); END COMPONENT; COMPONENT NOT2 PORT(A:IN STD_LOGIC; B:OUT STD_LOGIC); END COMPONENT; BEGIN X1:NOT2 PORT MAP(S0,V0); X2:NOT2 PORT MAP(S1,V1);

X3:AND3 PORT MAP(D,V0,V1,Y0); X4:AND3 PORT MAP(D,V0,S1,Y1); X5:AND3 PORT MAP(D,S0,V1,Y2); X6:AND3 PORT MAP(D,S0,S1,Y3); END DMUX4_STD_ARCH; Behavioral Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DMUX4_BEH IS PORT(S0,S1,D:IN STD_LOGIC; Y0,Y1,Y2,Y3:OUT STD_LOGIC); END DMUX4_BEH; ARCHITECTURE DMUX4_BEH_ARCH OF DMUX4_BEH IS BEGIN PROCESS(S0,S1,D) BEGIN IF(S0='0' AND S1='0') THEN Y0<=D;Y1<='0';Y2<='0';Y3<='0'; ELSIF(S0='0' AND S1='1') THEN Y1<=D;Y2<='0';Y3<='0';Y0<='0'; ELSIF(S0='1' AND S1='0') THEN Y2<=D;Y1<='0';Y0<='0';Y2<='0'; ELSIF(S0='1' AND S1='1') THEN Y3<=D;Y1<='0';Y2<='0';Y0<='0'; END IF; END PROCESS; END DMUX4_BEH_ARCH; Test Bench Waveform For Multiplexer

Test Bench Waveform For DeMultiplexer

Result : Thus source code in VHDL for Multiplexer and DeMultiplexer and Have been written,compiled and simulated using Modelsim simulator.The functionality of the various modules was verified by obtaining test bench waveforms.

Exp.No: 5 ENCODER AND DECODER Date : 13.02.10 __________________________________________________________________________________ Aim : 1. To write source code in VHDL for Encoder and Decoder 2. To compile and simulate the programs using Modelsim simulator

3. To verify the functionality of the various modules by obtaining test bench waveforms Program : Encoder Dataflow Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ENC8TO3_DAT IS PORT(D0,D1,D2,D3,D4,D5,D6,D7:IN STD_LOGIC; Y0,Y1,Y2:OUT STD_LOGIC); END ENC8TO3_DAT; ARCHITECTURE ENC8TO3_DAT_ARCH OF ENC8TO3_DAT IS BEGIN Y0<=( D1 OR D3 OR D5 OR D7 ); Y1<=( D2 OR D3 OR D6 OR D7 ); Y2<=( D4 OR D5 OR D6 OR D7 ); END ENC8TO3_DAT_ARCH; Structural Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ENC8TO3_STD IS PORT(D0,D1,D2,D3,D4,D5,D6,D7:IN STD_LOGIC; Y0,Y1,Y2:OUT STD_LOGIC); END ENC8TO3_STD; ARCHITECTURE ENC8TO3_STD_ARCH OF ENC8TO3_STD IS COMPONENT OR4 IS PORT(A,B,C,D:IN STD_LOGIC; E:OUT STD_LOGIC); END COMPONENT; BEGIN X1:OR4 PORT MAP(D1,D3,D5,D7,Y0); X2:OR4 PORT MAP(D2,D3,D6,D7,Y1); X3:OR4 PORT MAP(D4,D5,D6,D7,Y2); END ENC8TO3_STD_ARCH; Behavioral Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY ENC8TO3_BEH IS PORT(D0,D1,D2,D3,D4,D5,D6,D7:IN STD_LOGIC; Y0,Y1,Y2:OUT STD_LOGIC); END ENC8TO3_BEH; ARCHITECTURE ENC8TO3_BEH_ARCH OF ENC8TO3_BEH IS BEGIN PROCESS(D0,D1,D2,D3,D4,D5,D6,D7) BEGIN IF (D1='1' OR D3='1' OR D5='1' OR D7='1') THEN Y0<='1'; END IF; IF (D2='1' OR D3='1' OR D6='1' OR D7='1') THEN Y1<='1'; END IF; IF (D4='1' OR D5='1' OR D6='1' OR D7='1') THEN

Y2<='1'; END IF; END PROCESS; END ENC8TO3_BEH_ARCH; Decoder Dataflow Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DEC3TO8_DAT IS PORT(A,B,C:IN STD_LOGIC; D0,D1,D2,D3,D4,D5,D6,D7:OUT STD_LOGIC); END DEC3TO8_DAT; ARCHITECTURE DEC3TO8_DAT_ARCH OF DEC3TO8_DAT IS BEGIN D0<=( (NOT A) AND (NOT B) AND (NOT C)); D1<=( (NOT A) AND (NOT B) AND C); D2<=( (NOT A) AND B AND (NOT C)); D3<=( (NOT A) AND B AND C); D4<=( A AND (NOT B) AND (NOT C)); D5<=( A AND (NOT B) AND C); D6<=( A AND B AND (NOT C)); D7<=( A AND B AND C); END DEC3TO8_DAT_ARCH; Structural Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DEC3TO8_STD IS PORT(A,B,C:IN STD_LOGIC; D0,D1,D2,D3,D4,D5,D6,D7:OUT STD_LOGIC); END DEC3TO8_STD; ARCHITECTURE DEC3TO8_STD_ARCH OF DEC3TO8_STD IS SIGNAL N1,N2,N3:STD_LOGIC; COMPONENT AND3 IS PORT(A,B,C:IN STD_LOGIC; D:OUT STD_LOGIC); END COMPONENT; COMPONENT NOT2 IS PORT(A:IN STD_LOGIC; B:OUT STD_LOGIC); END COMPONENT; BEGIN X1:NOT2 PORT MAP(A,N1); X2:NOT2 PORT MAP(B,N2); X3:NOT2 PORT MAP(C,N3); X4:AND3 PORT MAP(N1,N2,N3,D0); X5:AND3 PORT MAP(N1,N2,C,D1); X6:AND3 PORT MAP(N1,B,N3,D2); X7:AND3 PORT MAP(N1,B,C,D3); X8:AND3 PORT MAP(A,N2,N3,D4); X9:AND3 PORT MAP(A,N2,C,D5); X10:AND3 PORT MAP(A,B,N3,D6); X11:AND3 PORT MAP(A,B,C,D7);

END DEC3TO8_STD_ARCH; Behavioral Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DEC3TO8_BEH IS PORT(A,B,C:IN STD_LOGIC; D0,D1,D2,D3,D4,D5,D6,D7:OUT STD_LOGIC); END DEC3TO8_BEH; ARCHITECTURE DEC3TO8_BEH_ARCH OF DEC3TO8_BEH IS BEGIN PROCESS(A,B,C) BEGIN IF(A='0' AND B='0' AND C='0') THEN D0<='1';D1<='0';D2<='0';D3<='0';D4<='0';D5<='0';D6<='0';D7<='0'; ELSIF(A='0' AND B='0' AND C='1') THEN D0<='0';D1<='1';D2<='0';D3<='0';D4<='0';D5<='0';D6<='0';D7<='0'; ELSIF(A='0' AND B='1' AND C='0') THEN D0<='0';D1<='0';D2<='1';D3<='0';D4<='0';D5<='0';D6<='0';D7<='0'; ELSIF(A='0' AND B='1' AND C='1') THEN D0<='0';D1<='0';D2<='0';D3<='1';D4<='0';D5<='0';D6<='0';D7<='0'; ELSIF(A='1' AND B='0' AND C='0') THEN D0<='0';D1<='0';D2<='0';D3<='0';D4<='1';D5<='0';D6<='0';D7<='0'; ELSIF(A='1' AND B='0' AND C='1') THEN D0<='0';D1<='0';D2<='0';D3<='0';D4<='0';D5<='1';D6<='0';D7<='0'; ELSIF(A='1' AND B='1' AND C='0') THEN D0<='0';D1<='0';D2<='0';D3<='0';D4<='0';D5<='0';D6<='1';D7<='0'; ELSIF(A='1' AND B='1' AND C='1') THEN D0<='0';D1<='0';D2<='0';D3<='0';D4<='0';D5<='0';D6<='0';D7<='1'; END IF; END PROCESS; END DEC3TO8_BEH_ARCH;

Test Bench Waveform For Encoder

Test Bench Waveform For Decoder

Result : Thus source code in VHDL for Encoder and Decoder and Have been written, compiled and simulated using Modelsim simulator. The functionality of the various modules was verified by obtaining test bench waveforms.

Exp.No: 6 COMPARATOR Date : 20.02.10 __________________________________________________________________________________ Aim : 1. To write source code in VHDL for 4BIT Comparator

2. To compile and simulate the programs using Modelsim simulator 3. To verify the functionality of the various modules by obtaining test bench waveforms Program Behavioral Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY comp4b_beh IS PORT(A,B:IN std_logic_VECTOR(3 DOWNTO 0); F1,F2,F3:OUT std_logic); END ENTITY; ARCHITECTURE comp4b_beh_arch OF comp4b_beh IS BEGIN PROCESS(A,B) BEGIN IF(A(3)='0' AND B(3)='1')THEN F3<='1';F2<='0';F1<='0'; ELSIF(A(3)='1' AND B(3)='0')THEN F1<='1';F2<='0';F3<='0'; ELSE IF(A(2)='0' AND B(2)='1')THEN F3<='1';F2<='0';F1<='0'; ELSIF(A(2)='1' AND B(2)='0')THEN F1<='1';F2<='0';F3<='0'; ELSE IF(A(1)='0' AND B(1)='1')THEN F3<='1';F2<='0';F1<='0'; ELSIF(A(1)='1' AND B(1)='0')THEN F1<='1';F2<='0';F3<='0'; ELSE IF(A(0)='0' AND B(0)='1')THEN F3<='1';F2<='0';F1<='0'; ELSIF(A(0)='1' AND B(0)='0')THEN F1<='1';F2<='0';F3<='0'; ELSE F2<='1';F1<='0';F3<='0'; END IF; END IF; END IF; END IF; END PROCESS; END comp4b_beh_arch;

Test Bench Waveform For 4Bit Comparator

Result : Thus source code in VHDL for 4BitComparator and Have been written, compiled and simulated using Modelsim simulator. The functionality of the various modules was verified by obtaining test bench waveforms.

Exp.No: 7 FLIP FLOPS Date : 27.02.10 __________________________________________________________________________________ Aim : 1. To write source code in VHDL for FlipFlop(JK,D and T) 2. To compile and simulate the programs using Modelsim simulator 3. To verify the functionality of the various modules by obtaining test bench waveforms Program

JK FlipFlop Behavioral Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY FFJK_BEH IS PORT(SET,RESET,J,K,CLK:IN STD_LOGIC; Q:INOUT STD_LOGIC:='1'; QN:OUT STD_LOGIC:='1'); END FFJK_BEH; ARCHITECTURE FFJK_BEH_ARCH OF FFJK_BEH IS BEGIN PROCESS(SET,RESET,CLK,J,K) BEGIN IF RESET='1' THEN Q<='0'; ELSIF SET='1' THEN Q<='1'; ELSIF (CLK='1' AND CLK'EVENT) THEN Q<=(J AND NOT Q) OR (NOT K AND Q); END IF; END PROCESS; QN<=NOT Q; END FFJK_BEH_ARCH; D FlipFlop Behavioral Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY FFD_BEH IS PORT(D,CLK,RESET:IN BIT; Q,QINV:OUT BIT); END FFD_BEH; ARCHITECTURE FFD_BEH_ARCH OF FFD_BEH IS BEGIN PROCESS BEGIN WAIT UNTIL CLK='1' AND CLK 'EVENT; IF(RESET='1') THEN Q<='0';QINV<='1'; ELSIF D='1' THEN Q<='1';QINV<='0'; ELSE Q<='0'; QINV<='1'; END IF; END PROCESS; END FFD_BEH_ARCH ;

T FlipFlop Behavioral Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY FFT_BEH IS PORT(T,CLK,RESET:IN BIT; Q,QINV:OUT BIT); END FFT_BEH; ARCHITECTURE FFT_BEH_ARCH OF FFT_BEH IS SIGNAL S:BIT; BEGIN PROCESS BEGIN WAIT UNTIL CLK='1' AND CLK 'EVENT; IF(RESET='1')THEN S<='0'; ELSIF T='1' THEN S<=NOT S; END IF; END PROCESS; Q<=S; QINV<=NOT S; END FFT_BEH_ARCH; Test Bench Waveform For JK FlipFlop

Test Bench Waveform For D FlipFlop

Test Bench Waveform For T FlipFlop

Result : Thus source code in VHDL for FlipFlops(JK,D and T) and Have been written, compiled and simulated using Modelsim simulator. The functionality of the various modules was verified by obtaining test bench waveforms.

Exp.No: 8 COUNTERS Date : 06.03.10 __________________________________________________________________________________ Aim : 1. To write source code in VHDL for Counters a) 4 BIT Asynchronous updown counter b) 4 BIT Synchronous updown counter

2. To compile and simulate the programs using Modelsim simulator 3. To verify the functionality of the various modules by obtaining test bench waveforms Program 4 BIT Asynchronous updown counter Structural Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY BIT4_ASYN_UD_COUNTER_STRUC IS PORT(S,CLK:IN STD_LOGIC;Q:INOUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END BIT4_ASYN_UD_COUNTER_STRUC; ARCHITECTURE BIT4_ASYN_UD_COUNTER_STRUC_ARCH OF BIT4_ASYN_UD_COUNTER_STRUC IS COMPONENT MUX21 PORT(A,B,S:IN STD_LOGIC;Y:OUT STD_LOGIC); END COMPONENT; COMPONENT FFT PORT(T,CLK,RESET:IN STD_LOGIC;Q,Q_INV:INOUT STD_LOGIC); END COMPONENT; SIGNAL M:STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL Q_INV:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN T0:FFT PORT MAP('1',CLK,'0',Q(0),Q_INV(0)); M0:MUX21 PORT MAP(Q(0),Q_INV(0),S,M(0)); T1:FFT PORT MAP('1',M(0),'0',Q(1),Q_INV(1)); M1:MUX21 PORT MAP(Q(1),Q_INV(1),S,M(1)); T2:FFT PORT MAP('1',M(1),'0',Q(2),Q_INV(2)); M2:MUX21 PORT MAP(Q(2),Q_INV(2),S,M(2)); T3:FFT PORT MAP('1',M(2),'0',Q(3),Q_INV(3)); END BIT4_ASYN_UD_COUNTER_STRUC_ARCH 4 BIT Synchronous updown counter Structural Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY BIT4_SYN_UD_COUNTER_STRUC IS PORT(CLK,S:IN BIT; M:OUT BIT_VECTOR(3 DOWNTO 0));//i/p and o/p declaration END BIT4_SYN_UD_COUNTER_STRUC; ARCHITECTURE BIT4_SYN_UD_COUNTER_STRUC_ARCH OF BIT4_SYN_UD_COUNTER_STRUC IS COMPONENT fft_beh PORT (T,CLK,RESET:IN BIT;Q,QINV:OUT BIT); END COMPONENT; COMPONENT mux2_std IS PORT(A,B,S:IN BIT;Q:OUT BIT); END COMPONENT;

COMPONENT and2 PORT(A,B:IN BIT;C:OUT BIT); END COMPONENT; SIGNAL Q_INV,Q:BIT_VECTOR(3 DOWNTO 0); SIGNAL A:BIT_VECTOR(2 DOWNTO 0); BEGIN T0:fft_beh PORT MAP('1',CLK,'0',Q(0),Q_INV(0)); A0:and2 PORT MAP('1',Q(0),A(0)); T1:fft_beh PORT MAP(A(0),CLK,'0',Q(1),Q_INV(1)); A1:and2 PORT MAP(A(0),Q(1),A(1)); T2:fft_beh PORT MAP(A(1),CLK,'0',Q(2),Q_INV(2)); A2:and2 PORT MAP(A(1),Q(2),A(2)); T3:fft_beh PORT MAP(A(2),CLK,'0',Q(3),Q_INV(3)); MO:mux2_std PORT MAP(Q(0),Q_INV(0),S,M(0)); M1:mux2_std PORT MAP(Q(1),Q_INV(1),S,M(1)); M2:mux2_std PORT MAP(Q(2),Q_INV(2),S,M(2)); M3:mux2_std PORT MAP(Q(3),Q_INV(3),S,M(3)); END BIT4_SYN_UD_COUNTER_STRUC_ARCH;

Test Bench Waveform For 4 BIT ASynchronous updown counter

Result : Thus source code in VHDL for Counters (4 BIT ASynchronous updown counter And 4 BIT Synchronous updown counter ) and Have been written, compiled and simulated using Modelsim simulator. The functionality of the various modules was verified by obtaining test bench waveforms.

Exp.No: 9 REGISTER Date : 13.03.10 __________________________________________________________________________________ Aim : 1. To write source code in VHDL for 4BIT shift register 2. To compile and simulate the programs using Modelsim simulator 3. To verify the functionality of the various modules by obtaining test bench waveforms Program Behavioral Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY 4BITSHIFTREG_BEH IS PORT(DATA:IN STD_LOGIC_VECTOR(3 DOWNTO 0); LOAD,ENABLE,CLOCK:IN STD_LOGIC;

MODE:IN STD_LOGIC_VECTOR(1 DONWTO 0); Y:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END 4BITSHIFTREG_BEH; ARCHITECTURE 4BITSHIFTREG_BEH_ARCH OF 4BITSHIFTREG_BEH IS SIGNAL Z:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(CLOCK) BEGIN IF(CLOCK='1' AND CLOCK'EVENT) THEN IF(ENABLE='0') THEN IF(LOAD='0') THEN Z<=DATA; ELSE IF(MODE="00") THEN Z<=Z(2 DOWNTO 0) & '0'; ELSIF(MODE="01") THEN Z<='0' & Z(3 DOWNTO 1); ELSIF(MODE="10") THEN Z<=Z('0') & Z(3 DOWNTO 1); ELSIF(MODE="11") THEN Z<=Z(2 DOWNTO ) & Z(3); ELSE Z<="0000"; END IF; END IF; ELSE Z<="0000"; END IF; END IF; END PROCESS; Y<=Z; END 4BITSHIFTREG_BEH_ARCH;

Test Bench Waveform For 4 BIT Shift Register

Result : Thus source code in VHDL for 4BIT Shift Register and Have been written, compiled and simulated using Modelsim simulator. The functionality of the various modules was verified by obtaining test bench waveforms.

Exp.No: 10 MULTIPLIER Date : 20.03.10 __________________________________________________________________________________ Aim : 1. To write source code in VHDL for 4BIT Systolic Array multiplier 2. To compile and simulate the programs using Modelsim simulator 3. To verify the functionality of the various modules by obtaining test bench waveforms Program Dataflow Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY BASIC_CELL IS PORT(A,B,SIN,CIN:IN STD_LOGIC; SOUT,COUT:OUT STD_LOGIC); END BASIC_CELL; ARCHITECTURE BASIC_CELL OF BASIC_CELL IS SIGNAL W:STD_LOGIC; BEGIN W<=A AND B; SOUT<=W XOR SIN XOR CIN; COUT<=(W AND SIN) OR (SIN AND CIN) OR (WW AND CIN); END BASIC_CELL;

4BIT Systolic Array multiplier Structure Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY 4BIT_SYSTOLIC_ARRAY_MUL_STD IS PORT(A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0); P:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); END 4BIT_SYSTOLIC_ARRAY_MUL_STD; ARCHITECTURE 4BIT_SYSTOLIC_ARRAY_MUL_STD_ARCH OF 4BIT_SYSTOLIC_ARRAY_MUL_STD IS SIGNAL C0,C1,C2,C3,S0,S1,S2,S3:STD_LOGIC_VECTOR(3 DOWNTO 0); COMPONENT BASIC_CELL PORT(A,B,SIN,CIN:IN STD_LOGIC;SOUT,COUT:OUT STD_LOGIC); END COMPONENT; BEGIN B1: BASIC_CELL PORT MAP(A(0),B(0),'0','0',P(0),C0(0)); B2: BASIC_CELL PORT MAP(A(1),B(0),'0',C0(0),S0(1),C0(1)); B3: BASIC_CELL PORT MAP(A(2),B(0),'0',C0(1),S0(2),C0(2)); B4: BASIC_CELL PORT MAP(A(3),B(0),'0',C0(2),S0(3),C0(3)); B5: B6: B7: B8: BASIC_CELL BASIC_CELL BASIC_CELL BASIC_CELL PORT PORT PORT PORT MAP(A(0),B(1),S0(1),'0',P(1),C1(0)); MAP(A(1),B(1),S0(2),C1(0),S1(1),C1(1)); MAP(A(2),B(1),S0(3),C1(1),S1(2),C1(2)); MAP(A(3),B(1),'0',C1(2),S1(3),C1(3));

B9: BASIC_CELL PORT MAP(A(0),B(2),S1(1),'0',P(2),C2(0)); B10: BASIC_CELL PORT MAP(A(1),B(2),S1(2),C2(0),S2(1),C2(1)); B11: BASIC_CELL PORT MAP(A(2),B(2),S1(3),C2(1),S2(2),C2(2)); B12: BASIC_CELL PORT MAP(A(3),B(2),'0',C2(2),S2(3),C2(3)); B13: BASIC_CELL PORT MAP(A(0),B(3),S2(1),'0',P(3),C3(0)); B14: BASIC_CELL PORT MAP(A(1),B(3),S2(2),C3(0),P(4),C3(1)); B15: BASIC_CELL PORT MAP(A(2),B(3),S2(3),C3(1),P(5),C3(2)); B16: BASIC_CELL PORT MAP(A(3),B(3),'0',C3(2),P(6),P(7)); END 4BIT_SYSTOLIC_ARRAY_MUL_STD_ARCH; Test Bench Waveform For 4BIT Systolic Array multiplier

Result : Thus source code in VHDL 4BIT Systolic Array multiplier and Have been written, compiled and simulated using Modelsim simulator. The functionality of the various modules was verified by obtaining test bench waveforms.

Exp.No: 11 RANDOM ACCESS MEMORY Date : 27.03.10 __________________________________________________________________________________ Aim : 1. To write source code in VHDL for Random Access Memory 2. To compile and simulate the programs using Modelsim simulator 3. To verify the functionality of the various modules by obtaining test bench waveforms Program Behavioral Model LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY RAM_8X8_BEH IS PORT(ADDRESS:IN STD_LOGIC_VECTOR(2 DOWNTO 0); CHIP_ENABLE:IN STD_LOGIC; READ_WRITE:IN STD_LOGIC; CLK:IN STD_LOGIC; DATA_IN:IN STD_LOGIC_VECTOR(7 DOWNTO 0); DATA_OUT:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END RAM_8X8_BEH; ARCHITECTURE RAM_8X8_BEH_ARCH OF RAM_8X8_BEH IS TYPE ARR IS ARRAY (7 DOWNTO 0) OF STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL REG:ARR; BEGIN

PROCESS(ADDRESS,CHIP_ENABLE,READ_WRITE,CLK,DATA_IN) BEGIN IF(CLK='1' AND CLK'EVENT) THEN IF(CHIP_ENABLE='0') THEN IF(READ_WRITE='0') THEN CASE ADDRESS IS WHEN "000" => DATA_OUT<= WHEN "001" => DATA_OUT<= WHEN "010" => DATA_OUT<= WHEN "011" => DATA_OUT<= WHEN "100" => DATA_OUT<= WHEN "101" => DATA_OUT<= WHEN "110" => DATA_OUT<= WHEN "111" => DATA_OUT<= WHEN OTHERS => NULL; END CASE; END IF; ELSE DATA_OUT<="ZZZZZZZZ"; END IF; END IF; END PROCESS; END RAM_8X8_BEH_ARCH; Test Bench Waveform For Random Access Memory(8*8)

REG(0); REG(1); REG(2); REG(3); REG(4); REG(5); REG(6); REG(7);

Result : Thus source code in VHDL Random Access Memory and Have been written, compiled and simulated using Modelsim simulator. The functionality of the various modules was verified by obtaining test bench waveforms.