VLSI Design Lecture 4: Wires and Vias, Parasitics

Shaahin Hessabi Department of Computer Engineering Sharif University of Technology Adapted, with modifications, from lecture notes prepared by the author (from Prentice Hall PTR)

Topics
Wire and via structures Wire parasitics
Capacitance Resistance

Transistor parasitics

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Wires and vias

metal 3

metal 2

vias
metal 1 poly n+ p-tub n+ poly

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Metal migration
Current-carrying capacity of metal wire depends on cross-section. Height is fixed, so width determines current limit. Metal migration: when current is too high, electron flow pushes around metal grains. Higher resistance increases metal migration, leading to destruction of wire.

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Metal migration problems and solutions

Marginal wires will fail after a small operating periodinfant mortality. Normal wires must be sized to accommodate maximum current flow:
Imax = 1.5 mA/m of metal width.

Mainly applies to VDD/VSS lines.

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Diffusion wire capacitance

Capacitances formed by p-n junctions:
sidewall capacitances n+ (ND)

depletion region

substrate (NA)
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bottomwall capacitance
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Typical 0.5 micron diffusion capacitance values

n-type:
bottomwall: 0.6 fF/m2 sidewall: 0.2 fF/m

p-type:
bottomwall: 0.9 fF/m2 sidewall: 0.3 fF/m

In 0.5 micron process, = 0.25 m

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Diffusion capacitance example

Perimeter = 32 area = 52 2 sidewall/bottomwall capacitances = ? total capacitance = ?

12 3 4

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Depletion region capacitance

Zero-bias depletion capacitance:
Cj0 = si/xd.

Depletion region width (zero bias):

xd0 = sqrt[(1/NA + 1/ND)2siVbi/q].

Junction capacitance is function of voltage across junction:

Cj(Vr) = Cj0/sqrt(1 + Vr/Vbi)

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Poly/metal wire capacitance

Two components:
parallel plate; fringe.

fringe plate

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Typical poly/metal capacitance values for 0.5 micron process

poly:
plate: 0.09 fF/m2 fringe: 0.04 fF/m

metal 2:
plate: 0.02 fF/m2 fringe: 0.06 fF/m

metal 1:
plate: 0.04 fF/m2 fringe: 0.09 fF/m

metal 3:
plate: 0.009 fF/m2 fringe: 0.02 fF/m

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Metal coupling capacitances

Can couple to adjacent wires on same layer, and to wires on above/below layers:

metal 2

metal 1

metal 1

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Example: parasitic capacitance measurement

n-diffusion: bottomwall=2 fF, sidewall=2 fF. metal: plate=0.15 fF, fringe=0.72 fF.
3 m 0.75 m 1 m 2.5 m

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1.5 m

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Wire resistance
Resistance of any size square is constant:

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Typical resistance values for our 0.5 micron process

Poly: 4 ohms/square metal 1: 0.08 ohms/square metal 2: 0.07 ohms/square metal 3: 0.03 ohms/square ndiff: 2 ohms/square pdiff: 2 ohms/square

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Calculating resistance
Determine current flow, then aspect ratio:
20 2 vs. 20 2
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I
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Current around corners

Resistance at corner of two equal-width wires is approximately 1/2 square:

1/2 square

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Via resistance
Determined by current flow through via cut. Typical metal1-poly contact: 2.5 ohms. Typical metal1-metal2 contact: 0.5 ohms.

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Skin effect
At low frequencies, most of copper conductors cross section carries current. As frequency increases, current moves to skin of conductor.
Back EMF induces counter-current in body of conductor.

Skin effect most important at gigahertz frequencies.

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Transistor gate parasitics

Gate-source/drain overlap capacitance:

gate source drain

overlap

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Transistor source/drain parasitics

Source/drain have significant capacitance, resistance.
Significant effect on circuit performance.

Measured same way as for wires. Source/drain R, C may be included in Spice model rather than as separate parasitics.

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