Computer System Architecture © Pipelining Part IIT Chalermek Intanagonwiwat QQ ‘Shdes courtesy of Devid Patterson Data Hazards si Mehopmned + Avoid some “by design’ iminate WAR by always fetching operands early (DCD) inpipe ~~ (last stage, static) 5 + Detect and resolve remaining ones Er] - stall or forward (if possible) Greate bier SP (el an pa Pipeline Hazards Again iFetch Wem if OpFetch [Exec | Store n [p00] *** | RONITH, Jassyoigny iF |-ocol ex [Mem|wo-] Raw (read after write) Data Hazard | bcof Ex J mem 19 | waw Date Hazard (ie [oct ex wen we] (wre after write } [pep or [ex] wed (ae [ocol of [ex [Rs war Date Hazard (write after read) vari, Hazard Detection + Suppose instruction / is about to be issued and a predecessor instruction j is in the instruction pipeline. pe | + ARAW hazard exists on register p if p « Rregs( 7) Wregs( j) - - Keep @'record of pending writes (for inst's in the pipe) and compare with operand regs of current instruction. - When instruction issues, reserve its result | - When on operation completes, remove its write reservation. |Hazard Detection (cont.) + A WAW hazard exists on register p if p< Wregs( / )> Wregs( /) + A WAR hazard exists on register p if p Wregs( / > Rregs( j) + Detect nearest valid write op operand register ‘and forward into op latches, bypassing remainder of the pipe + Increase muxes to add paths from pipeline registers Forwarding = Data Bypassing Record of Pending Writes + Current operand registers Wey BR 8 | Sbctoseds nwt dow (5 == Puy & tet i Bp 8 F Sain 99 Sided wien What about memory operations?.’ * Tf instructions are initiated in _| order and operations always [a5 RURARB| i accur in the same stage, there Ley can be no hasanés betecen memory operations! * What does delaying WB on arithmetic operations cost? ~ cycles ? = hardware 2 * What about data dependence on loads? Ri<- R4+R5 2 Mem[R2 +1} R3«R2+Rt 5 asa yield em (usoseer mnide heaerk ring thaviOmddemmrgayne AH Mnuwss canpiler c Lagorsifstite Compiler Avoiding Load Stalls: 5 s:s‘¥ ovo [PB scheduiea Ml unscheduled ] ibn outa 54% gee ate 42% spice "4% Synswiy 65% ri tex _ fous o% = am % loads stalling pipeline Exception Handling aU. detec! bad instruction address. Catchy etect bad instruction (decwe im detect verfow (eyetey a oh a Allow exception to take effect & hee OS icerog mer What about Interrupts, Traps, Faults? + External Interrupts: - Allow pipeline to drain, + Faults (within instruction, restartable) - Force trap instruction into IF - disable writes till trap hits WB - must save multiple PCs or PC + state Refer to MIPS solution Exception Problem Exceptions/Interrupts: 5 instructions executing in 5 stage pipeline -How to stop the pipeline? Restart? - wos i‘ at — silent aueh EO et Sate}