VLSI 1.

Simulation + Steiner tree Different types of simulation (logic/functional) Weste & Wsragian Pg,440 (theory only) Xerox simulation 3.6 event driven simulation pg 49 Smith ch 13 different types. Pg 670 logic simulation works (4 types. 2nd paragraph) 13.4

Steiner tree Sarafzade ch 3 pg 97 (exact steiner tree is np completeproof) Wrst algorithm pg 101 104 (prob + algo) Mst, smt(defn only) pg 96 97 2. Technology mapping (logic systhesis) Srinivas 3 basic steps pg 6 Pg 9 flowchart Pg 11 technology mapping (defn) Pg 185 7.7 tech mapping concept Pg 187 gate library (picture) Pg 218 problem 13 ref image pg 113 Similar problems on pg 273, 194 Tree mapping steps pg 190 7.8 3. Floorplanning Sarafzade ch 2 pg 47 63 (exclude simulated annealing) hierarchical floorplan sizing algo on pg 63 Paper by bhaskar + sahani First page 3 pts Related algorithm from class note

4. Partitioning + placement Sarafzade ch 2 pg 34 39 (F_m , K_L)

Placement Sarafzade ch 2 pg 70 74 Cost function Force directed/constraints/iterative Simulated annealing Partitioning placement(optional)

5. Channel routing Xerox by mam (typed Xerox) (problems using figures) Revised godleg (amar mukherjee pg 320) sherwani pg 330 334 merging of nets, YK algo

6. Downscaling + nano technology Hiroshi iwai paper art 3 (limit for integration) theory only + table (4 pts) Paper tutorial on emerging nao tech devices Introduction 3 bullets Art 2 nanoscale mosfets 2.2.1 to 2.2.6 Art 3.6 carbon nanotube Rakshit chattopadhyay pg 506 art 19.3 scaling on VLSI device (theory only, summary. No formula)

7. Fpga Sarafzade ch 3 pg 140 145

Problem on diagonal s box and general architechture Sherwani ch 13 art 13.1 LUT & MUX Problem given by mam in class

8. Asic soc + fault Fault --Kohavi ch 8 pg 214 223 fig on pg 223 Smith ch 13 fault models art 14.3.2 pg 751 752 Lee full Xerox Pg 350 369

Asic soc Comparision between asic and soc Defn and modules of asic