ECE569 Analog IC Ch 8

8장 전류원 및 바이어스 회로

8.2 바이어스 회로

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High Speed CMOS IC LAB, POSTECH
ECE569 Analog IC Ch 8

8.2 바이어스 회로

Ideal voltage or current source : no PVT dependence

(PVT: process voltage temperature)

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ECE569 Analog IC 8.2.1 공급전압 의존성 Ch 8

Simple current source (use VDD as reference voltage):

VDD increase Î Iout increase

VDD VDD

R M3 (W/L)3

Iref Iout Iref Iout

M1(W/L)1 M2(W/L)1 M1(W/L)1 M2

(W/L)1

(a) (b)
그림8.2.1 간단한 전류 바이어스 회로
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ECE569 Analog IC Self-bias circuit Ch 8

A simple self-bias circuit

Iout can be any value (including 0),

Cannot be used
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ECE569 Analog IC Self-bias circuit Ch 8

Iout determined to be a single value

M3, M4 Î Iref = Iout

M1, M2, Rs Î
VGS1 = VGS2 + Iout x Rs

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ECE569 Analog IC Self-bias circuit Ch 8

Iout can be 0 Î needs start-up ckt

Body effect on M2 Î inaccuracy

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ECE569 Analog IC Self-bias circuit Ch 8

Body effect eliminated

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ECE569 Analog IC Self-bias circuit with start-up Ch 8

Eliminate the operating point of Iout=0

Constraints:
(1) VTH 1 + VTH 5 + | VTH 3 | < VDD
Î Not a good start-up ckt
(2) VGS1 + VTH 5 + | VGS 3 | > VDD
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High Speed CMOS IC LAB, POSTECH Razavi
ECE569 Analog IC 공급전압 의존성 Ch 8

Supply-insensitive biasing :

cannot use VDD as reference

Use one of the following three as reference instead

(1) BJT VBE

(2) MOS threshold voltage

(3) Thermal voltage VT

Î self bias circuit

Band gap reference : PVT insensitive voltage source(~1.2V)

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ECE569 Analog IC 8.2.2 VBE referenced CMOS self-bias ckt Ch 8

VDD

M M4 M9
3

M7 M8 M10

I1 Iout
I2

M5 M6 VR = VEB1
 I1 
M1 M2 I 2 ⋅ R = VT ⋅ ln 
 I S1 
+
Q1 VR R 1  I1 
I2 = ⋅ VT ⋅ ln 
- R  I S1 
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ECE569 Analog IC 8.2.2 VBE referenced CMOS self-bias ckt Ch 8

C E B C

p+ p+ n+ p+

n-well

p-sub

그림8.2.2 N-well CMOS 공정에서의 substrate PNP 트랜지스터

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ECE569 Analog IC 8.2.2 VBE referenced CMOS self-bias ckt Ch 8
VDD V EB1
I1 = I2 = I out =
M3 M4 M9 R
∂I out ∂VEB1 ∂R
M7 M8 M10 ∂T = ∂T − ∂T Î Large negative TC
I out VEB1 R
I1 Iout
I2
I1 = I 2 (curve 1)
M5 M6
I2
노이즈 in I 1
M1 M2
B VT ⋅ ln(I1 I S1 )
C I2 =
+ ③ R
Q1 VR R ④ (curve2)
- ①
ⓒ ②

ⓐ ⓑ

A I1
노이즈 in I1
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ECE569 Analog IC 8.2.3 문턱전압 기준(threshold voltage referenced) CMOS self-bias 회로 Ch 8

VDD

M4
M3 M7

M5 M8
I1 M6
Iout
I2
R in
M2 2 I1
VTH +
VGS1 µ nCox (W L)1
I2 = =
M1 R R

R VTH
I1 = I2 = I out ≈
R
VSS for large (W/L)1
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ECE569 Analog IC 8.2.3 문턱전압 기준(threshold voltage referenced) CMOS self-bias 회로 Ch 8

VDD

M4
M3 M7

M5 M8
M6
I1
Iout
I2
R in
M2 I2 I1 = I2
M1
 2I1 
R I2 = VTH +  R
동작점  µnCox (W L)1 
VTH / R
VSS

I1
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ECE569 Analog IC 8.2.4 열전압 기준(thermal voltage referenced) CMOS self-bias 회로 Ch 8

VDD

M4
M3 M9 I1 = I 2
M8 M10
M7
VEB1 = VEB 2 + I 2 ⋅ R
I1 Iout
I2

M5 I 2 ⋅ R + VT ⋅ ln(I 2 ) = VT ⋅ ln(n) + VT ⋅ ln(I1 )

M6

 I2 ⋅ R 
M1 M2 I2 ⋅ exp  = n ⋅ I1
 VT 
R
VT ⋅ ln(n)
I2 ≈
R
Q1 1 : n Q2 VT ⋅ ln(n)
I out = I1 = I2 ≈
R
∂I out ∂R
VSS
∂T 1 ∂T Î moderate TC 15
= −
High Speed CMOS IC LAB, POSTECH I out T R
ECE569 Analog IC 8.2.4 열전압 기준(thermal voltage referenced) CMOS self-bias 회로 Ch 8
VDD
VT ⋅ ln(n)
M3
M4
M9 I out = I1 = I2 ≈
R
M8 M10
M7
∂I out ∂R
Iout
I1 I2
∂T 1 ∂T
= − Î moderate TC
M5 M6 I out T R
M1 M2
I2
I1 = I2
R

I2R
Q1 1 : n Q2
I2 ⋅ e VT
= n ⋅ I1
VT ⋅ ln( n ) B
VSS
R

A I1
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High Speed CMOS IC LAB, POSTECH
ECE569 Analog IC 8.2.5 CMOS band gap reference Ch 8

VDD
Vout = VBE + K ⋅ VT
∂Vout ∂VBE K ⋅ VT
= +
IDC ∂T ∂T T

K = (1.65 mV †
C ) (0.083 mV C )
†
= 19.9
VBE Î 0 TC

전압
Vout =VBE + K⋅VT
VT KVT 합산기
VT K
생성기 PTAT

그림 8.2.9 Band gap reference 전압원의 개략도

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 VBE
ECE569 Analog IC BJT 베이스-에미터 전압 의 온도 의존성 Ch 8

 I DC  ÎAssumed DC collector current

VBE (T ) = VT ⋅ ln  (constant, PVT independent)
 I S (T ) 
3
2  2πk m∗ m∗  −
EG
qA E D n
n i ni2
 n p  3 kT
IS = = 4⋅  ⋅T ⋅ e
N ⋅W B  h2 
A  

3 E G (T ) E G (300)
− +
 T 
ni2 (T ) = (1.45 × 10 )10 2
⋅   ⋅ e
kT
⋅ e 300 k
 300 

4+ m EG ( T ) EG ( 300 )
 T  − +
I S (T ) = I S (300) ⋅   ⋅e kT
⋅e 300 k

 300 
M = -1.5 due to Temperature dependence of mobility (un) 18
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 VBE
ECE569 Analog IC BJT 베이스-에미터 전압 의 온도 의존성 Ch 8

 
 
I   IDC 
VBE(T ) = VT ⋅ ln DC  = VT ⋅ ln 4+ m EG (T ) EG (300) 
 IS (T )   I (300) ⋅  T  ⋅ e k T ⋅ e 300k 
− +

 S   
 300
 I   T  EG (T ) EG (300)
= VT ⋅ ln DC  − (4 + m) ⋅ VT ⋅ ln  + − VT ⋅
I
 S (300)   300  q 300 k

T  E (300)  T  300 EG (T ) 
= ⋅ VBE (300) − G − (4 + m) ⋅ VT 300 ⋅ ln  + ⋅ 
300  q  300  T q 

∂VBE (T ) 1  EG (300)  T  300 ∂EG (T ) 

= V
 BE (300 ) − − ( 4 + m ) ⋅ V ⋅
T 300  ln + 1+ ⋅ 
∂T 300  q  300  q ∂ T 

∂VBE (T ) 1
= (0.75 − 1.12 − 0.0625 − 0.051) = − 1.61 mV †
C
∂T T =300 K 300 †

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High Speed CMOS IC LAB, POSTECH
 VBE
ECE569 Analog IC BJT 베이스-에미터 전압 의 온도 의존성 Ch 8

∂VBE (T ) 1  EG (300)  T  300 ∂EG (T ) 

= V
 BE (300 ) − − ( 4 + m ) ⋅ V ⋅
T 300  ln + 1+ ⋅ 
∂T 300  q  300  q ∂ T 

Razavi

Constant IC assumed

Curvature in temperature characteristics

Of Vout ( = VBE + K T )

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High Speed CMOS IC LAB, POSTECH
ECE569 Analog IC CMOS band gap reference 회로 Ch 8

VDD

M3 M4 M5

M8 M9 M10

I1 I2 I3 Iout.2
Iout.1
(sourcing전류원)
M6 M7 (sinking전류원)
+
-
M1 M2
R2
+
R xR VSS
Vo VDD
1 : n : n
-
Q1 Q2 Q3 - +
VSS Vout 전압원

그림 8.2.10 CMOS band gap reference 회로

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High Speed CMOS IC LAB, POSTECH
ECE569 Analog IC CMOS band gap reference 회로 Ch 8

VDD

M3 M4 M5

M8 M9 M10

I1 I2 I3 Iout.2
Iout.1
(sourcing전류원)
M6 M7 (sinking전류원)
+
-
M1 M2
R2
+
R xR VSS
Vo VDD
1 : n : n
-
Q1 Q2 Q3 - +
VSS Vout 전압원
VT ⋅ ln(n)
I1 = I 2 I3 = I2 I3 = I2 = I1 ≈
R

Vo = I 3 ⋅ xR + VEB 3 = VT ⋅ x ⋅ ln(n) + VEB 3

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High Speed CMOS IC LAB, POSTECH
ECE569 Analog IC CMOS band gap reference : revisited Ch 8

PTAT voltage (PTAT : proportional to absolute temperature)

PTAT voltage

PTAT voltage : difference between 2 VBEs of PN junctions

with different current density
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High Speed CMOS IC LAB, POSTECH Razavi
ECE569 Analog IC CMOS band gap reference : revisited Ch 8

Bandgap reference : Vref = VBE + K VT

Close to bandgap of silicon

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High Speed CMOS IC LAB, POSTECH Razavi
ECE569 Analog IC CMOS band gap reference : revisited Ch 8

For 0 TC

Close to bandgap

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High Speed CMOS IC LAB, POSTECH
ECE569 Analog IC CMOS band gap reference : revisited Ch 8

Conceptual band gap reference :

enforce Vo1 and Vo2 to be the same

Vo 2 = R I + VBE 2
= VT ⋅ ln n + VBE 2
ln (n) = 17.2 Î n=2.95e7 (too large, impractical)
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High Speed CMOS IC LAB, POSTECH Razavi
ECE569 Analog IC CMOS band gap reference : revisited Ch 8

Basic band gap reference ckt

VX and VY: kept the same

by a negative feedback OP amp ckt
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High Speed CMOS IC LAB, POSTECH Razavi
ECE569 Analog IC CMOS band gap reference : revisited Ch 8

Basic band gap reference ckt

R2
R1=R2 Î the same current at Q1, Q2 ln n ⋅ (1 + ) = 17.2
R2 > R3 to decrease n R3

Example: R1=R2, R2/R3=4, n=31

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High Speed CMOS IC LAB, POSTECH Razavi
ECE569 Analog IC CMOS band gap reference : revisited Ch 8

Basic band gap reference ckt

PTAT IC

Constant IC
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High Speed CMOS IC LAB, POSTECH Razavi
ECE569 Analog IC CMOS band gap reference : revisited Ch 8

Effect of Vos (input offset voltage)

VBE1 − VOS ≈ VBE 2 + I C 2 ⋅ R3

I C 2 = (VBE1 − VBE 2 − VOS ) / R3

= (VT ⋅ ln n − VOS ) / R3

Vos amplified, Vos varies with temperature

Razavi
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