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EE 560 CHIP INPUT AND OUTPUT (I/0) CIRCUITS

Kenneth R. Laker, University of Pennsylvania

-> ESD PROTECTION CIRCUITS (INPUT PADS) -> ON-CHIP CLOCK GENERATION & DISTRIBUTION -> TRANSLATION BETWEEN OFF & ON-CHIP LOGIC LEVELS -> OUTPUT PADS -> ON-CHIP NOISE DUE TO PARASITIC INDUCTANCE -> LATCH-UP PHENOMENON

Kenneth R. Laker, University of Pennsylvania

ESD PROTECTION
HUMAN BODY MODEL 1 M + Vesd 1.5 k DUT 100 pF + Vesd MACHINE MODEL 1 M DUT 200 pF

Simulates the touch from a charged humans finger.

Since in MM body resistance is absent, contact with machines can be higher stress.

CC

Kenneth R. Laker, University of Pennsylvania

ESD TESTERS: LUMPED ELEMENT MODEL CS LS Component HBM I CC (pF) 100 + RS RS () 1500 Ct DUT V LS () 5 CS (pF) 1 Ct (pF) 10

MM 200 25 2.5 0 10

VDD input pin 1 - 3 k

PROTECTION NETWORK (PN) VA to circuits on die

-0.7 V < VA < VDD + 0.7 V Effective protection networks can withstand up to 8 kV HBM ESD stress.

Kenneth R. Laker, University of Pennsylvania

INPUT SERIES TRANSMISSION GATE CIRCUIT

A A E TG X E

PN

VDD

A -> EXTERNAL (OFF-CHIP) input signal E -> INTERNAL (ON-CHIP) enable signal X -> INTERNAL (ON-CHIP) output signal X = A, when E = 0 X = HIGH-IMPEDANCE STATE when E = 1 NOTE: ANY UNUSED INPUT TERMINALS SHOULD BE TIED TO VDD OR GND USING WEAK PULL-UP OR PULL-DOWN TRANSISTORS RATHER THAN FLOAT
Kenneth R. Laker, University of Pennsylvania

INVERTING INPUT CIRCUIT

VDD

PN

X=A LEVEL SHIFTING FROM TTL TO CMOS Vin = A VOH = 2.0 V VOL = 0.8 V NMH NML CMOS VOL = 0 Vin = A 0.8 VIL Vth VIH 2.0 VIH VIL VOH = VDD Vth Vout = Vin Vout = X

TTL NML = VIL - VOL NMH = VOH - VIH

DESIGN FOR Vth = 0.8 V + (2.0 V - 0.8 V)/2 = 1.4 V

Kenneth R. Laker, University of Pennsylvania

VARIATIONS IN LEVEL SHIFT VTC DUE TO PRCESS VARIATIONS 7 Vout = X VOH = VDD PM-NM PH-NL PL-NH VOL = 0 0.8 VIL Vth VIH 2.0 Vin = A

PM-NM => nominal processing PH-NL => strong pMOS, weak nMOS process corner PL-NH => weak pMOS, strong nMOS process corner IN ADDITION: Strong (fast) nMOS, pMOS -> low VTn0, low |VT0p|; high kn, high kp Weak (slow) nMOS, pMOS -> high VTn0, high |VT0p|; low kn, low kp
Kenneth R. Laker, University of Pennsylvania

Worst Case Simulation Method

Models are first partitioned into their main types, that is NMOS, PMOS, R, and C. All possible combinations of these types are then run. However, in practice, in order to reduce the number of simulation runs R and C are grouped together. For example, if a design contained NMOS and PMOS, the following sets would be run: 1. weak nmos, weak pmos, weak temp. 2. weak nmos, nominal pmos, weak temp. 3. weak nmos, strong pmos, weak temp. 4. nominal nmos, weak pmos, nominal temp. 5. nominal nmos, nominal pmos, nominal temp. 6. nominal nmos, strong pmos, nominal temp. 7. strong nmos, weak pmos, high temp. 8. strong nmos, nominal pmos, high temp. 9. strong nmos, strong pmos, high temp. A total of 9 runs.
Kenneth R. Laker, University of Pennsylvania

If R and C are included, the number of runs would increase to 27.

DIFFERENTIAL SIGNALING (LOGIC LEVELS) FOR GBPS SYSTEMS LVPECL (low-voltage positive referenced emitter coupled logic) LVDS (low-voltage differential signals) HSTL (highspeed transceiver logic) CML (current-mode logic)

Kenneth R. Laker, University of Pennsylvania

OUTPUT CIRCUITS AND L(di/dt) NOISE TRISTABLE OUTPUT CIRCUIT CK D D Z CK CK D 1 1 1 0 P 0 1 CK N 0 1 Z 1=D 0=D 6 transistors D VDD Large W/L Z or super buffer 12 transistors
P

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VDD

Large W/L Z or super buffer

Z = D for CK = 1 Z = HIGH IMP for CK = 0

LARGE W/L -> Sufficent current sink, source -> Reduce delay times CK

Kenneth R. Laker, University of Pennsylvania

LARGE W/L -> Sufficient current sink, source => LARGE di/dt -> Reduce delay times L (di/dt) VOLTAGE DROP ACROSS BONDING WIRE CONNECTING PAD TO PACKAGE PIN VOH Vin, Vout Imax iC(t)

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VOL

T/2 iC nMOS ON pMOS ON

T nMOS ON

t 0 ts/2 ts t

Kenneth R. Laker, University of Pennsylvania

I max 2 I max di = dt max t s / 2 ts 4 Cload VDD ( t s )2 0.1 to 10 A/ns

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4 C loadVDD di dt max ( ts )2 LET Cload = 1 pF, L = 1 nH, VDD = 3.5 V and ts = 1 ns

HIGH-END MICROPROCESSOR CHIPS WITH 32 BITS OR 64 BIT DATA BUS LINES - ALL OTPUT DRIVERS SWITCHING AT THE SAME TIME! For 32 bits switching simulataneously: PROBLEM!
Kenneth R. Laker, University of Pennsylvania

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REDUCE L(di/dt) NOISE VDD D

CK = 0, VDD VDD/2

Z
(dVout/dt)max = VDD/2

CK
CK = 0, 0 V

ST = 1 PRECHARGES INVERTER OUTPUT Z TO VDD/2 WHEN ST = 1 AND CK = 0 (JUST PRIOR TO CK -> 1) ALSO, STAGGER SWITCHING TIMES OF 32 OUTPUT DRIVERS BY USING BULT-IN DELAYS IN THE CLOCK DISTRIBUTION NET.
Kenneth R. Laker, University of Pennsylvania

DIFFERENTIAL DRIVER CIRCUIT VDD B 2ZO IN A

VDD/2

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O 2ZO

To a Z0 transmission line

IN A B C O
VDD/2
DIFFERENTIAL SIGNAL wrt VDD/2 NEG. PULSE ON RISE OF IN ONLY POS. PULSE ON FALL OF IN ONLY

Kenneth R. Laker, University of Pennsylvania

BIDRECTIONAL BUFFER CIRCUIT WITH TTL INPUT CAPABILITY VDD Tri-state Output D E D TS E DI TTL DI E Z VDD PN

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TTL Level Shift

Kenneth R. Laker, University of Pennsylvania

ON-CHIP CLOCK GENERATION AND DISTRIBUTION SIMPLE ON-CHIP CLOCK CIRCUIT RING OSCILLATOR CK CK

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CK FREQUENCY -> PROCESS DEPENDENT -> UNSTABLE FREQUENCY Rbias

PIERCE CRYSTAL OSCILLATOR CIRCUIT C1 Crystal C2 -> GOOD FREQUENCY STABILITY

Kenneth R. Laker, University of Pennsylvania

TWO-PHASE CLOCKING SCHEMES Tc phi1 phi2

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clk

phi1 phi2

PRIMARY CLOCKS FROM XTAL CONTROLLED OSCILLATOR

Kenneth R. Laker, University of Pennsylvania

CLOCK DECODER

CK1 CK2 CK3 CK4

GENERAL LAYOUT OF H-TREE CLOCK DISTRIBUTION NETWORK FOR UNIFORM CLOCK DISTRIBUTION

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CLOCK GEN

C AD Techniques to automate the generation of optimum clock distribution networks.

Kenneth R. Laker, University of Pennsylvania

clk chip

PLL CLOCKING SCHEMES

chip clk pad buffer PLL

clk clk pad

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R C

clk-out output pad ddata = dclk-buf + dRC +dout-reg+ dpad clk d clk-out clk data out clk Phase Detector Filter n WHY USE PLL IN SYSTEM CLOCKS?

output register

R clk-out output pad ddata = dout-reg + dpad clk dclk clk-out data out output - clk C

VCO

+ To syncronize the internal clock of a chip to an external clock - reduce skew. + To operate an internal clock at a higher rate than the external clock input.
Kenneth R. Laker, University of Pennsylvania

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clk chip PLL 4 C output pad clk clk-out ddata = dout-reg + dpad clk pad Generates an internal fclk-out = 4 fclk synchronized to clk

Kenneth R. Laker, University of Pennsylvania

LATCHUP IN CMOS CIRCUITS

Vin latch-up susceptability proportional to p+ n+ Vout n+ NPN VDD IRwell Rwell VB-pnp Q2 (NPN) IE2 I
Kenneth R. Laker, University of Pennsylvania

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VDD p+ n+ Rwell PNP Rwell n-well VDD

p+

Rsub I + 2.0 mA V IH p-sub I

IE1 Q1 (PNP) VB-npn Rsub IRsub

slope = 1/RT trigger point 0 VH = 1.5 V V

RT

IH VH

SCR EQIV CKT in Latch-up

VDD IRwell Rwell VB-pnp Q2 (NPN) IE2 I At the on-set of latch-up I > IH = (VDD - VH)/RT LATCH-UP CONDITION I IE1 Q1 (PNP) VB-npn Rsub IRsub V + I 2.0 mA IH slope = 1/RT trigger point 0 VH = 1.5 V V

VDD RT IH VH SCR EQIV CKT in Latch-up

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Kenneth R. Laker, University of Pennsylvania

LATCH-UP PREVENTION

make large LATCHUP OCCURS IF SATISFIED-

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make small

TO PREVENT LATCH-UP: Insure Latchup Condition is Violated! Reduce npn, pnp; Reduce Rsub, Rwell
A. Use a latchup resistant process. Latchup Prevention LAYOUT Guidelines: B. Use p+ guard rings connected to GND around nMOS transistors and n+quard rings connected to VDD around the pMOS transistors to reduce Rwell and Rsub and to weaken BJTs. C. Place sub, well contacts close to the nMOS, pMOS source connections to supply rails (i.e. GND for nMOS, VDD for pMOS) to reduce Rwell and Rsub. CONSERVATIVE RULE: One sub contact per source connection to a supply, or GND. LESS CONSERVATIVE: One sub contact per 5-10 transistors. D. Layout nMOS, pMOS transistors close to GND, VDD rails, respectively and maintain space between nMOS, pMOS transistors.
Kenneth R. Laker, University of Pennsylvania

INVERTER AND I/O BUFFER CELL LAYOUT USING LATCH-UP GUIDELINES (a) (b)
Latchup Protection Using

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n-well (c)

n-well

n+ guard ring to VDD

p+ guard ring to GND

n-well
Kenneth R. Laker, University of Pennsylvania