Digital Circuits & Fundamentals of Microprocessor

Nagpur Institute of Technology, Nagpur
Department of Computer Science & Engineering

Question Bank with Solutions
Digital Circuits & Fundamentals of Micro Processor (III Sem-CSE)

Compiled By
Ms. Shital Tiwaskar
Email: shitaltiwaskar@nitengg.edu.in
QuestionBank:DCFMIIISemCSE
Q.1) Perform the following conversions. I] (110101.011) binary = (?) decimal Solutions: = 1 2 5 + 1 2 4 + 0 2 3 + 1 2 2 + 0 2 1 + 1 2 0 + 0 2 1 + 1 2 2 + 1 2 3 + 1 2 4 Ans: (53.4375)decimal
a] ( . 73 15 Solutions:
22 7
2 .5
O =
(? )D
(15.73) octal
= 1 81 + 5 8 0 + 7 8 1 + 3 8 2 = (13.92136) decimal = 2 81 + 2 8 0 = (18) decimal =7 80 = (7) decimal = 2 8 0 + 5 8 1 =(2.653)decimal

2 . 653
(22) octal
(7) octal
(2.5)octal
18 Ans: 13 . 92136 7
b] 110 Solutions:
decimal
(2 A
)DC
= (?)
(110)H = (1 16 2 + 1 16 1 + 0 16 = (272) decimal (2A) H = (2 16 1 + A 16 0 ) = (42)D (DC)H = (D 16 1 + C 16 = (220)D

220
0
Ans: (272 ) (42 )
decimal
NagpurInstituteofTechnology,Nagpur
IV] (243.62) D = (?) octal Solutions: Decimal no
243 30 3
Base (8)
Quotient
Remainder
8 8 8
= = =
30 3 0
3 6 3
Ans: (363.4753)O
c]
(9310 .25 )10 = (? )H

Decimal no
Solutions:
9310 581 36 2
Base (8)
Quotient
Remainder 14 5 4 2
Quotient result
16 16 16 16
= = = =
581 36 2 0 = =
Decimal no
Base (8)
0.25
Ans: (245 E . 4 )H
16
4.0
VI] (273 . 45 )O = (? )H Solutions:
( )O = ( )B = ( )H
10 11 1011 . 1001 01)
(273.45) = (0 Ans: (0 BB.94 )H
d] (10110111) gray = (?)B Solutions: NagpurInstituteofTechnology,Nagpur
Decimal no
Base (8)
= = = = =
0.62 0.96 0.68 0.44

Ans: (10100101)B e) i] BCD Additions:
8 8 8 8
Quotient result 4.96 7.68 5.44 3.52
(256.2)D + (743.9)D
Solutions: 0 0 1 0 0 1 0 1 0 1 1 0 . 0 0 1 0 0 1 1 1 0 1 0 0 0 0 1 1 . 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 . 1 0 1 1 (invalid BCD) 0 0 0 0 0 0 0 0 0 0 0 0 . 0 1 1 0
1 0 0 1 1 0 0 1 1 0 1 0 . 0 0 0 1 (invalid BCD) 0 0 0 0 0 0 0 0 0 1 1 0 . 0 0 0 0 1 0 0 1 1 0 1 0 0 0 0 0 . 0 0 0 1 (invalid BCD) 0 0 0 0 0 1 1 0 0 0 0 0 . 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 . 0 0 0 1 (invalid BCD) 0 1 1 0 0 0 0 0 0 0 0 0 . 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 . 0 0 0 1 (Valid BCD) Ans: (10001.1)
f] BCD Subtraction (76.53)D (59.27)D Solutions: 0 1 1 1 0 1 1 0 . 0 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 . 0 0 1 0 0 1 1 1 0 0 0 1 1 1 0 1 . 0 0 1 0 1 1 0 0 (invalid BCD) 0 0 0 0 0 1 1 0 . 0 0 0 0 0 1 1 0 0 0 0 1 0 1 1 1 . 0 0 1 0 0 1 1 0 (valid BCD) Ans: (17.26 )decimal g] (253) D (315) D Solutions:
(253)D + (315)D (?)D (253)D = (128 + 64 + 32 + 16 + 8 + 4 + 1) =(11111101)B (315)D= 256 + 32 + 16 + 8 + 2 +1 =(100111011)B (+253) (+315) 0 0 011111101 100111011
1s Compliment of (315)D = ( 1 0 1 1 0 0 0 1 0 0 ) + 1
2s Compliment of (315)D = ( 1 0 1 1 0 0 0 1 0 1 )B = (-315)D (+253)D + (-315)D = 0 1 1 011111101 011000101 111000010
Verification:- (z)=
1 0
111000010 000111101 + 1
1s Compliment =
000111110
h] Excess 3 Code Additions i] (956.2) D + (873.4)D (?)D Solutions: 1100 1000 1001 . 1010 1011 1010 0110 . 0111 1000 0010 1111.1100 0011 0011 0011 0011.0011 0100 1011 1101.1100 1001 1 8 2 . 9 6
i] Excess 3 code Subtractions (47.59)D (28.38)D (?)D Solutions:
0111 1010 . 1000 1100 0101 1011 . 0110 1011 0001 1111 . 0010 0001 0011 0011 . 0011 0011 0000 0000 . 1111 0100
Q.2) a] Why NAND gate and NOR gates are called universal gates? Answer: all the logical ckt. are made by using basic 3 logic gates OR, AND, NOT gates, by using only NAND gate . We can design these 3 basic gates OR, AND, NOT gates. Hence any logical ckt. can be completely by using only NAND gate. So NAND gate is called UNIVERSAL gate. Similarly, OR, AND, NOT gate can be designed by using only NOR gats, so any logical ckt. can be completely designed by using only NOR gates. Hence NOR gate is also universal gate. (a) NAND gate as universal gate: 1] Not gate using NAND gate. Input Y = A. A = A NOT gate is obtained by shorting by both the input of NAND gate as shown in fig.
2] AND gate using NAND gate:
AND gate is opposite of NAND gate. So, AND gate is Obtained by Connecting NOT at the output of NAND gate as shown in fig. 3] OR gate using NAND gate:
The output of NOR gate is Y = A + B = A + B = A . B [de-morgans 1st thermo then].. (1) The logical ckt. og eg.(1) can be obtained by using NAND gate. OR, AND, NOT gate are designed by using only NAND gate. So, NAND gate is Universal.
(a) NOR gate as universal gate: 1] NOT gate using NOR gate:
i/p Y = A+ A= A NOT gate is obtained from NOR gate by shorting both inputs as shown in fig. 2] OR gate using NOR gate:
OR gate is opposite of NOR gate. So, gate is obtained by connecting NOT gate at the output of NOR gate as shown in Fig. 3] AND gate using NOR gate:
The output of 2 input AND gate is Y = A.B = A + B [De- morgans 2nd theorem]..(2) The logical ckt. of eg.(2) can be obtained by using NOR gate as shown in fig.
Q.2) b] Prove that:

A.B + A.B + A.B = A + B L . H .S = A . B + A . B + A . B
= ( A . 1 ) + (B . 1 ) = A+ B = R . H .S .
[(A.B + A.B )]+ [(A.B + A.B )] = [A .(B + B )] + [(A + A ). B ]

=
2) X Y Z + XYZ + XY Z + XYZ = 1
L . H .S = X Y Z + XYZ + XY Z + XYZ = ( XYZ + XYZ ) + Y Z X + X = 1 + Y Z [XYZ + XYZ = 1] A + A = 1 = 1[ 1 PLUSANYTHI NG = 1] = R . H .S
Q.2 ) c] State principal of duality. Answer: Principal of duality is used for writing dual equations or for designing dual ckt. for a given local equations, replace each term on L.H.S. and R.H.S. by the corresponding dual terms. The equations obtained will be dual equation of the given equations. Similarly, if any logical ckt. is given then replace each gate by corresponding dual gate. The logical ckt.obtained will be dual of the given ckt. In dual logical ckt. the output will be dual of each other. The different dual terms and dual gates are given in the table below,
0 OR gate + NOR gate X-OR gate
1 AND gate . NAND gate X-NOR gate
(+) De-morgans 1st theorem Product term(.) SOP equations
(.) Demorgans 2nd theorem Sum term (+) POS equations
Q.2) d] Prove that De-morgans theorem. Answer: DEMORGANS FIRST THEROM: The logical equations of De-morgans 1st theorem for two input is, Y = A + B = A . B ..(1) Similarly for 3 inputs is, Y = A + B + C = A . B .C (2) STATEMENT: De-morgans first theorem state that complement of ORing will be equal to the ANDing of complements. PROOF: De-morgans first theorem can be proved by using truth table. Truth table: Inputs (A+B) A .B A B A+B (R.H.S) A B (L.H.S)
0 0 1 1
0 1 0 1
1 1 0 0
1 0 1 0
0 1 1 1
1 0 0 0
1 0 0 0
As L.H.S. =R.H.S. of equations (1) hence 1st theorem is proved that. The logical Ckt. of L.H.S. and R.H.S. is shown in fig. below.
=
Y = A+ B
A + B = A.B
NOR gate L.H.S
Bubbled input AND gate R.H.S
DE-MORGANS SECOND THEROM: The logical equations of De-morgans 2nd theorem for two input is, Y = A . B = A + B ..(3) Similarly for 3 inputs is, Y = A . B .C = A + B + C ..(4) STATEMENT: De-morgans second theorem state that complement of ANDing will be equal to the ORing of complements. PROOF: De-morgans second theorem can be proved by using truth table.
Que estionBan nk:DCFM MIIISem CSE

Truth tab ble: Inp puts A 0 0 1 1 B 0 1 0 1
A B
B) (A.B 0 1 1 1
(A.B )
(L.H.S) 1 0 0 0
A + B + C
(R.H H.S) 1 0 0 0
1 1 0 0
1 0 1 0
As L L.H.S. =R.H.S of equation (3) hence 2nd theorem is proved tha S. ns at. The logical Ckt. o L.H.S. and R.H.S. is s of d shown in fig. below.
=
Y = A.B A.B = A + B
NAND gate L.H.S
Bu ubbled input OR gate R.H H.S
Q.3 a design a s a] squaring ckt Which will generate squ t. uare of the 3 bit no. appli at the i/p ied p? Solu ution: as i/p is a 3 bits so the max imum vale be (ABC) = (111) = (7 B i n a r y p 7) Henc the maxi ce imum value of o/p will be, 7*7= (49) = 32+ = +16+1 (11 10001) B in a ry y As o is of 6 b o/p bits so we ha to desig a logical ckt. In whi i/p will be of 3 bits and o/p wi be of 6 ave gn ich s ill bits as given in the truth ta able. Dec. no. Inputs Output Binary outpu ut A B C X X2 Y5 Y Y3 Y2 Y Y0 Y4 Y1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 1 2 0 1 0 4 0 0 0 1 0 0 3 0 1 1 9 0 0 1 0 0 1 4 1 0 0 16 0 1 0 0 0 0 5 1 0 1 25 0 1 1 0 0 1 6 1 1 0 36 1 0 0 1 0 0 7 1 1 1 49 1 1 0 0 0 1 If a logical ckt is designed using k ma then we w get onl one bit ou d ap will ly utput. Henc for obtain ce ning o/p of ts, ogical ckt. F each o/ p bit separa For ately. 6 bit we have to design lo Desi ign for Y5
A
BC
BC
BC
BC
BC
A
A
0 m0 0 0 m4 4
0 m1 0 m5
0 m3 1 m7
0 m2 m 1 m6 m
Y 5 = A.B
purInstituteo ofTechnolog gy,Nagpur Nagp
Design for Y4
A
BC
BC
BC
BC
BC
0 m0 1
0 m1 1 m5
0 m3 1 m7
0 m2 0 m6
Y 4 = AB
+ AC
m4
Design for Y3
A
A
BC
BC
BC
BC
BC
0 mo 0 m5
0 m1 1 m6
1 m3 0 m7
0 m4 0 m6
Y 3 = A BC + A B C
Design for Y2
A
A
BC
BC
BC
BC
BC
0 mo 0 m5
0 m1 0 m6
0 m3 0 m7
1 m4 1 m6
Y 2 = BC
Design for Y1
A
BC
BC
BC
BC
BC
A
Design for Y0
A
BC
0 mo 0 m5
0 m1 0 m6
0 m3 0 m7
0 m4 0 m6
Y1 = 0
BC
BC
BC
BC
0 mo 0 m5
1 m1 1 m6
1 m3 1 m7
0 m4 0 m6
Y0 = C

Logi ckt. ical Obta aining from eq (1) to (6) an it is shown in the fig. be q. nd n elow. A
Y5 Y
Y4
Y3S
Y2 Y Y1 Y Gnd. Y0 Y
Gnd.

Q.3. Design a Code Con .b] nverter Wh hich Will C onvert 3 Bi Binary N Applie s at the Inp into its N0. put equi ivalent Gra Code. ay Solu utions: The i/p w be 3 bit binary no. ABC . so, the o/p gray code will also be of 3 bits i.e., G G1 G0 . will t . y G2 INPUT A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 OUTP PUT G2 0 0 0 0 1 1 1 1 G1 1 0 0 1 1 1 1 0 0 G0 0 1 1 0 0 1 1 0 Design for G1 D 1
A
Design for G0 D 0
A
BC C
BC
BC
BC
BC
0 mo 0 m4
1 m1 1 1 m5 5
0 m3 0 m7
1 m2 1 m6
G 0 = BC + B C
BC
BC
BC
BC
BC
A
A
0 mo m 1 m4 m
0 m1 1 m5
1 m3 0 m7
1 m2 0 m6
G 1 = AB + A B
gn Desig for G2
A
BC
BC
BC
BC
BC
0 mo 1 m5
0 m1 1 m6
0 m3 1 m7
0 m4 m 1 m6 m
G2 = A
Logi Ckt: ical

Q.3 C] Design a NAND ga ckt. To convert 3 b gray co de into equ ate bit uivalent 3 b binary n bit numbers. Solu utions : INP PUT GRAY CODE G2 G1 G G0
0 0 0 0 1 1 1 1
A
OUTPUT BI O INARY NUM MBER B2

0 0 0 0 1 1 1 1
B1 B0
0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
BC
0 0 1 1 1 1 0 0
BC
0 1 1 0 0 1 1 0
BC
BC
Desig for B2 gn
BC
0 mo m 1 m5 m
0 m1 1 m6
0 m3 1 m7
0 m4 1 m6
B2 = A
gn Desig for G1
A
BC
BC C
BC
BC
BC
A
gn Desig for G0
A
0 mo o 1 m4 4
0 m1 1 m5
1 m3 0 m7
1 m2 0 m6
B1 = AB + A B
BC
BC
BC
BC
BC
A
Logi Ckt: ical
0 mo 1 m4
1 m1 m 0 m5 m
0 m3 1 m7
1 m2 0 m6
B0 = ABC + ABC + AB + ABC BC
Q.3 d] Design a NAND gate ckt. To detect illegal or invalid BCD number applied at the input. Solutions: if 4 bit number ABCD applied at the input is valid BCD(0000 to 1001)then output Y should be zero. If input ABCD is invalid BCD (1010 to 1111) then output should be 1. Truth Table: Inputs Output Symbol of Output A B C D Y 0 0 0 0 0 m0 0 0 0 1 0 m1 0 0 1 0 0 m2 Valid BCD 0 0 1 1 0 m3 0 1 0 0 0 m4 0 1 0 1 0 m5 0 1 1 0 0 m6 0 1 1 1 0 m7 1 0 0 0 0 m8 1 0 0 1 0 m9 1 0 1 0 1 m10 1 0 1 1 1 m11 Invalid BCD 1 1 0 0 1 m12 1 1 0 1 1 m13 1 1 1 0 1 m14 1 1 1 1 1 m15 Design k-map :
AB
AB
CD
CD
CD
CD
C D
AB
AB
A B
0 mo 0 m4 1 m12 0 m8
0 m1 0 m5 1 m13 0 m9
0 m3 0 m7 1 m15 1 m11
0 m2 0 m6 1 m14 1 m10
Y = AC + AB
Logi Ckt: ical

A B C D
Y = AC + AB
Q.3. E] Design a code con . nverter whi ich convert 4 bit BCD input num t mber into co orrespondi ng X-S3 code e. Solu utions: The truth table showing de ecimal digit , BCD num ber input an required X-S3 code given nd belo w. BCD Input D A B C 0 0 0 0 1 0 0 0 2 0 0 1 3 0 0 1 4 0 1 0 5 0 1 0 ber 1 As 4 bit input ill be BCD 0 numb from 6 1 7 0 1 1 8 1 0 0 9 1 0 0 Deci mal digit X- S3 output D Y3 Y 2 Y1 Y0 0 0 0 1 1 1 0 1 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 1 1 1 0 0 0 00 00 to 1 1001 , heance1 res o set 0 0 0 1 1 0 1 0 0 1 0 1 1 1 1 1 0 0
e mber from 1 010 to 111 1 will not b e applied at the input. So have to take the t f the , 4 bit num corr esponding o output bits. m 10 to m 15= X(don care). t Desig k-map for Y3: gn r
AB
AB
CD
CD
C D
CD
C D
AB
AB
A B
0 m0 0 m4 X m12 1 m8
0 m1 1 m5 X m13 1 m9
0 m3 m 1 m7 m X m15 m X m11 m
0 m2 2 1 m6 6 X m14 X m10
Y 3 = A + BD + BC C
Design k-map for Y2:
AB
AB
CD
CD
C D
CD
C D
AB
AB
AB
0 m0 1 m4 m12 0 m8
1 m1 0 m5 X m13 1 m9
1 m3 0 m7 X m15 X m11
1 m2 0 m6 X m14 X m10
Y 2 = B CD + B D + B C

AB
AB
CD
CD
CD
CD
C D
AB
AB
AB
1 m0 1 m4 X m12 1 m8
0 m1 0 m5 X m13 0 m9
1 m3 1 m7 X m15 X m11
0 m2 0 m6 X m14 X m10
Y 1 = CD + CD

AB
AB
CD
CD
CD
CD
C D
AB
AB
A B
1 m0 1 m4 X m12 1 m8
0 m1 0 m5 X m13 0 m9
0 m3 0 m7 X m15 X m11
1 m2 1 m6 X m14 X m10
Y0 = D
Logi Ckt: ical
NAND gate ckt. To ob e btain 9s co ompliment of the 4 bit BCD num t mber applied at the d Q.3 F] Design N ut. inpu Solu ution: Input BCD D number A 0 0 0 0 0 0 0 0 1 1 B 0 0 0 0 1 1 1 1 0 0 C 0 0 1 1 0 0 1 1 0 0 D 0 1 0 1 0 1 0 1 0 1 Decim mal dig git X 0 1 2 3 4 5 6 7 8 9 9s com mpliment 9-X 9 8 7 6 5 4 3 2 1 0 9s com mpliment o output Y3 1 1 0 0 0 0 0 0 0 0 Y2 0 0 1 1 1 1 0 0 0 0 Y1 0 0 1 1 0 0 1 1 0 0 Y0 1 0 1 0 1 0 1 0 1 0
0 X(DONT CARE) C m10 TO m15=X
AB
AB
CD
CD
CD
CD
CD
AB
AB AB
1 m0 0 m4 X m12 0 m8
1 m1 0 m5 X m13 0 m9
0 m3 0 m7 X m15 X m11
0 m2 0 m6 X m14 X m10
Y 3 = ABC

AB
CD
CD
CD
CD
CD
AB
0 m0 1 m4 X m12 0 m8
0 m1 1 m5 X m13 0 m9
1 m3 0 m7 X m15 X m11
1 m2 0 m6 X m14 X m10
AB
AB
AB
Y 2 = B C + BC

AB
CD
CD
CD
CD
CD
AB
AB
AB
AB
0 m0 0 m4 X m12 0 m8
0 m1 0 m5 X m13 0 m9
1 m3 1 m7 X m15 X m11
1 m2 1 m6 X m14 X m10
Y1 = C

AB CD
CD CD
CD
CD
AB
AB
AB
AB
1 m0 1 m4 X m12 1 m8
0 m1 0 m5 X m13 0 m9
0 m3 0 m7 X m15 X m11
1 m2 1 m6 X m14 X m10
Y0 = D
Logi Ckt: ical
Q.3 G] Design NAND gate ckt. For t e the function f= n Solu utions:
AB CD
CD CD
CD D
0,1,5,9,12 )+ d(3,7,11,1 + 15) m(0
CD
AB
AB
AB AB
1 m0 0 m4 1 m12 0 m8
1 m1 m 1 m5 m 0 m13 m 1 m9 m
X m3 X m7 X m15 5 X m11
0 m2 0 m6 0 m14 0 m10
F = AB C + ABC + B D + A D CD
Logi Ckt: ical
NAND gate ckt. For t he function f= e n Q.3 h] Design N on For the functio f.
ND m(1,,2,7,9,15 ) + d(0,8,12) design NAN ckt.
utions: the f functions f is opposi of f. H f ite Hence logic zero of fun c nction. f w be logic input in will c Solu f. But dont c cares will re emain uncha anged. Henc f= (3,4, 5,6,10,11,1 3,14) + d(0 ,8,12) ce k-ma for funct ap tions f is, Desig k-map: gn
AB CD
AB
CD
CD
CD D
CD
AB
AB
AB
X m0 1 m4 X m12 X m8
0 m1 1 m5 1 m13 0 m9
1 m3 m 0 m7 m 0 m15 m 1 m11 m
0 m2 2 1 m6 6 1 m14 4 1 m10 0
f = B D + B C + A BC + BCD
Logi Ckt: ical
Q.3 i] Design a multiplier ckt. which will mult iply 2 num ber A1A0* B1B0 r h Solu utions: The maximum value of inp 2 bit num v put mber will b e A1A0 = ( (11)B =(3)D D=B1B0. He ence the max imum value of output result will b (A1A0)* (B1B0)=3* 3=9=(1001) So we h e r be )B. have to desi gn the ckt for 4 bit output . nput Binary res sult in Decimal result A1 A 0 B1 B0 Y3 Y2 Y1 1Y0 (A1A0) *(B1B0) (A) (B) (C) (D) )
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 * * * * * * * * * * * * * * * * 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 = = = = = = = = = = = = = = = = 0 0 0 0 0 1 2 3 0 2 4 6 0 3 6 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 m0 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 m15
AB CD
AB
CD
CD
CD
CD
AB
AB
AB
0 m0 0 m4 0 m12 0 m8
0 m1 0 m5 0 m13 0 m9
0 m3 0 m7 1 m15 0 m11
0 m2 0 m6 0 m14 0 m10
Y 3 = ABCD

AB CD
AB
CD
CD
CD
CD
AB
AB
AB
0 m0 0 m4 0 m12 0 m8
0 m1 0 m5 0 m13 0 m9
0 m3 0 m7 0 m15 1 m11
0 m2 0 m6 1 m14 1 m10
Y 2 = AC D + A B C

AB CD
AB
CD
CD
CD
CD
AB
AB
AB
0 m0 0 m4 0 m12 0 m8
0 m1 0 m5 1 m13 1 m9
0 m3 1 m7 0 m15 1 m11
0 m2 1 m6 1 m14 0 m10
Y 1 = A BD + AC D + BC D + ABC

AB CD
AB
CD
CD
CD
CD
AB
AB
0 m0 0 m4 0 m12 0 m8
0 m1 1 m5 1 m13 0 m9
0 m3 1 m7 1 m15 0 m11
0 m2 0 m6 0 m14 0 m10
AB
Y 3 = BD
Logi Ckt: ical
) in it Q.4) a] Design and explai of two bi compara tor. Solu utions: Com mparator is a device w which will c compare th e given two input num o mber and g ives 3 bit outp result. put (a) ( One bit for A B (c) ( One bit for A = B
Onebit co omparator
AB A=B B
DES SIGN OF SI INGLE BIT COMPAR T RATOR The truth table showing two single b number A and B a e t bit r and the corr responding output of g com parator is given below w,
2 i/p nu umber A 0 0 1 1 B 0 1 0 1 AB 0 0 1 0
Usin two inpu K-map , we have to design th ng uts o hree differe nt ckt. For 3 bit outp ut. r Desig k-map for (A < B) gn r
A. B
A (A B) gn r

A. B
0 1
0 0
(A
> B)= AB
Logi Ckt: ical
Q.4 b] Design a and explain of two bit comparat or. n t utions: Two bit compar o rator is used to compar two numb d re bers of two bits each. Solu Lets first numb er A=A1 A0 and secon number B 0 nd B=B1B0. he econd bit nu umber B=B 1 B0,then th MSBs A he A1,B1are If th first two bit number is A=A1 A 0 and the se appl ied first on e bit compa arator and L LSBs A0,B 0 are applie to second one bit co ed d omparator. T The cond ditions for t three bit out tput of com mparator are given below w. AB B:)OR [(A1=B AND (A B1) A0>B0)] (A1>B1) So, ( (A>B) = (A A1>B1) + [(A A1=B1). (A A0>B0)] . (3 ) Two bit compar o rator using one bit com mparator is o obtaining fr rom equatio ns 1,2,3 an d it is show in below, wn ,
Onebit purInstituteo ofTechnolog gy,Nagpur Nagp compara ator
A1 < B1
Onebit O com mparator
A0 < B0

A1 A1=B1 B1 A1>B1 B0 0 A0 > B0 A0 0 A0 = B0
A1 (A) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
2 i/p n number A0 B1 (B) (C) 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1
B0 (D) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
AB B 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0
gn r Desig k-map for (A < B)

AB
AB
CD D
CD
CD
CD
CD
AB
AB
AB
0 m0 0 m4 0 m12 0 m8
1 m1 0 m5 0 m13 0 m9
1 m3 1 m7 0 m15 m 1 m11 m
1 m2 m 1 m6 m 0 m14 m 0 m10 m
( A < B ) = AC + AB D + BCD D
Design k-map for (A=B)

AB
AB
CD
CD
CD
CD
CD
AB
AB
AB
1 m0 0 m4 0 m12 0 m8
CD
0 m1 1 m5 0 m13 0 m9
CD
0 m3 0 m7 1 m15 0 m11
CD
0 m2 0 m6 0 m14 1 m10
CD
( A = B) = ABCD + ABCD + ABCD + ABC D
Design k-map for (A > B)

AB
AB
CD
AB
AB
AB
0 m0 1 m4 1 m12 1 m8
0 m1 0 m5 1 m13 1 m9
0 m3 0 m7 0 m15 0 m11
0 m2 0 m6 1 m14 0 m10
( A > B) = AC + BCD + AB D
Logical Ckt:

Q.5] what is a pa arity generato Explain t diagram even and od parity gen or? the dd nerator. Solut tions: In n bits data, the count of num mber of ones bit is called a parity. If th count of nu as he umber of once bit in n bit da is odd no. then it is call odd parity data.X-OR g is used to detect the p ata led y gate o parity of n b data. bits (a) ( If the pari of input da of X-OR g is always zero. ity ata gate s (b) ( If the pari of input da of X-OR g is odd then output of X ity ata gate X_OR gate is always zero. s . (1)th truth table s he showing 3 bit input numbe X-OR gate, then parity o input data a the corres t er , of and sponding outp of X-OR put gate is given below w. bits and writ the sum neg te glecting the carry for 3 I/P X-or gate. Add all the input b Inpu number ut B 0 0 1 1 0 0 1 1 R X-OR gate O/P O 0 1 1 0 1 0 0 1 Parity of output y I/P Even E Odd O Odd O Even E Odd O Even E Even E Odd O
A 0 0 0 0 1 1 1 1
C 0 1 0 1 0 1 0 1
ty Parit generator Parity generator is used to gene y s erate n bits no. of a parti icular parity. T There are two types of par generator. o rity (a a)Even parity generator y (b b)Odd parity generator y (a) E Even parity g generator: Even parity generator is used to gen i nerate even pa arity number. The 8 bit num mber D7 to D is applied a the i/p of D0 at even parity genera ator. The pari generator g ity generates one parity bit Dp So, the outp number o even parity generator e p. put of will b of 9 bits (D and D7 to D0) .The par of this 9 b output wi be always e be Dp rity bits ill even. 1] If the parity of 8 bit input nu umber D7 to D is already even parity b output will be always ev output da will D0 bit l ven ata ain rema even. 2] If the parity of 8 bit input da (D7 to D0) odd then parity bit Dp=1. So parity of 9 bits output data will bec ata ) f t come even.

(b)O parity ge Odd enerator: Odd parity genera is used to generate odd parity numb The 8 bit number D7 to D0 is applie at the inpu odd parity ator d ber. o ed ut rator. The par genaerato generates o parity bit Dp. Hence th output parit generator w be of 9 bits. (Dp and rity or one he ty will gener D7 to D0). The pa o arity of this 9 bits output w be always odd. will (1) If the p parity of inpu number D7 to D0 is already odd then parity bit Dp ut 7 p=0, So, the p parity of 9 bit output will s rema odd. ain parity of 8 bit input numbe D7 to D0 is even then parity bit Dp=1. So the pari of 9 bits ou t er s ity utput will (2) If the p becom odd. me
ssification of logic familie and properties of logic families. f es Q.6] Explain clas tions: Depen nding upon the main compo e onents which are used to fa fabricate logic gate. Logic g c gates families are divided s Solut into f following typ pes. (1)RTL [resistance transistor logic] family r y: The logic gates of RTL family are m L made by using resistance an transistor as main comp g nd ponents. (2)DTL [diode tr ransistor logi family: ic] The main components of DTL family gates are d diodes and tra ansistors. (3)TT [transisto transistor logic] family TL or y: The logic gates of TTL family are o L obtained from logic gates o DTL family by replacing diodes with transistors. m of y g h (4) E ECL [emitter couple logic family: r c] The logic gates of ECL family are m L made emitter c coupled trans sistor as main components. n . (5)CM MOSEFET ( (complement tary MOSEF FET) logic: The logic gates of CMO OSFET logic family are m c made by using complement g tary pair of M MOSFET i.e., one P chann and one channel MOSFET. nel n M

Prop perties or cha aracteristics of logic fami ilies (1)PROP POGATION DELAY TIM [TD OR T D ME TP]:
I/P A P
O/P Y P
The t time differenc between th install at w ce he which i/p is app plied and the installed at w which o/p is o obtained is cal as lled propa agation delay time: if prop y pagation time is less then lo gates is f and vice v ogic fast versa the prop pagation dela time is ay meas sured between the instant at which 50% of the i/p sig is applied (a) and the i n a gnal d instant at which 50% of the o/p signals e obtai ined (b). (2)POWE DISSIPA ER ATION (PD): The p power that is obtained in one gate is cal ad power dissipation p gate. If po o lled r per ower dissipation per gate is less then s logic gate is better and vice ver c r rsa. (3)PROD DUCT OF TD OR PD D For b better logic ga the value of propagatio delay time as well as po ates e on e ower dissipation should be small be. Bu in some e ut logic gates Td is s c small and Pd is large and v versa. So for selecting logic gates, t product of propagation delay time i vice the f n (td) a power dis and ssipation(Pd)i obtained. T logic fami in which t products ( * pd) is m is The ily this (td minimum is the family and vice versa. (4) FAN I IN maximum number of o/p of gates which can be conn o h nected to a sin i/p of one gate is calle as FAN IN if FAN IN ngle e ed N. The m is mo than logic gates is bette and vice ve ore c er ersa.
OUT (5) FAN O The m maximum number of input of other ga which can be connecte to output of one gate is c ts ates n ed f called as FAN OUT. If N FAN OUT is more than logic gates is better and vice vers N e g sa. purInstituteo ofTechnolog gy,Nagpur Nagp
(6) NOISE MARGIN gic a gnals are in th form of vol he ltage which is denoted by l s logic 1. If noi voltage is ise In log gates, the gates input and output sig super rimposed on o voltage of logic gates t o/p f then the value of o/p voltag will chang The maxim e ge ge. mum value of noise f volta which can be superpose on o/p bec age n ed cause of which the o/p logi remains unchanged is ca h ic alled ad noise voltage e marg gin. Q. 9] a] Explain h adder Ckt. ] half C Solut tions: a logic ckt. Which performs add c ditions of only two binary b is called a half adder. The two binary bit A and y bits as . d B are applies ti the input of Haft Adder. HA performs the addition (A+ and gives 2 bit o/p resu e e A e +B ult. B A (a) ( One bit fo sum (S) and or d HalfAdd der (b) ( One bit fo carry gener or rated (Co). (A+B) Co Table of half adder: f The Truth T Input (A + B) A 0 0 1 1 B 0 1 0 1 m Sum S 0 1 1 0 Co 0 0 0 1 S Car rry
logical ckt. of half adder can be designe using K-M f ed Map: The l Desig for Sum(S gn S): A B 0 m0 1 m2
B
1
B
m1 0 m3
S = AB + A B
A A
Design for Carry (Co): A B 0 m0 0 m2
B
0
B
m1 1 m3
A
A
Co = AB
Logical Circuit
A B
S = AB + A B
Co = AB
Q. 9] b] Explain Full Adder Ckt. Solutions: when we perform additions of two multibit number then we have to perfume additions of 3 bits. A logical ckt. Which is used to perform additions of 3 binary bits is called as full adder. The 3 binary bits A, B, C in applied of the i/p of Full adder. So, gives 2 bit output result. (1) One bit for sum(A + B + Cin) A B (2) One bit for carry out(Co.)
FullAdder
(A+B+ Cin)
Cin
Co The truth able for full adder ckt. Inputs (A + B + Cin) A B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Design K Map For Full Adder Ckt.
Sum So 0 1 1 0 1 0 0 1
S
Carry Co 0 0 0 1 0 1 1 1
Cin 0 1 0 1 0 1 0 1
Design for Sum(S): A BC 0 m0 1 m4 Design for Sum(S): A BC 0 m0 0 m4 1 m5 0 m5
BC
1
BC
0 m1 1
BC
1 m3 0 m7 m6 m2
BC
S = ABC + ABC + ABC + ABC BC

0 m1 1 m7
BC
1
BC
0 m3 1
BC
m2
A
m6
Co = AC + AB + BC
The logical ckt of full adder
Q. 9] c] Explain Half Subtractor Ckt. Solutions: A logic ckt. Which performs Subtractions of only two binary bits is called as half Subtractor. The two binary bit (A B). Is called as Half Subtractor A B (a) One bit for Difference (D) and (b) One bit for Borrow Required to perfume the subtraction Half (A-B) i.e., borrow out (Bo). Subtractor The truth table of half Subtractor: (AB) Input (A - B) A B 0 0 0 1 1 0 1 1 Difference Borrow D Bo 0 0 1 1 1 0 0 0
Bo
The logical ckt. of half Subtractor can be designed using K-Map:
Design for Difference (D): A B 0 m0 1 m2
B
1
B
m1 0 m3
A
A
D = AB + A B
Design for Borrow (Bo): A B 0 m0 0 m2
B
1
B
m1 0 m3
A
A
Co = AB
A
D = AB + A B
Bo = A B
Q. 9] d] Explain Full Subtractor Ckt. Solutions: when we perform Subtractions of two multibit number then we have to perfume Subtractions of 3 bits. A logical ckt. Which is used to perform Subtractions of 3 binary bits is called as full Subtractor. The 3 binary bits A, B, C in applied of the i/p of Full Subtracto. So, gives 2 bit output result. (1) One bit for Difference(A - B - Cin) (2) One bit for Borrow out(Bo.) A B
Full Subtractor (ABCin)
Cin
The truth able for full Subtracto ckt. Inputs (A - B - Cin) Difference A B Cin D 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0
Bo
Borrow Bo 0 1 1 1 0 0

1 1 0 1 1 1 Desig K Map Fo Full Adder Ckt. gn or Desig for Sum(S gn S): A BC C 0 m0 1 m4 gn ow(Bo): Desig for Borro A BC C 0 m0 0 m4 0 m5 0 m5 0 1 0 1
BC
1
BC
0 m1 1
BC
1 m3 0 m7 m6 m2
BC
ABC D = ABC + ABC + ABC + A BC

1 m1 1 m7
BC
1
BC
1 m3 0
BC
m2
A
m6
Bo = AC + AB + BC
Ckt. ubtractor Logical C of Full Su CS A B
Difference
Borrow
0] n nary adder. Q. 10 Explain in parallel bin Solut tions: A2 A3 A B3
B2
A1
B1
A0
B0 0
Fu Adder ull 3
Full A Adder 2
Full Add der 1
Full Adder
0
C3
S3
C2 2
S2
C1
S1
C0
S0 S
k l r m of The block diagram of 4 bits parallel binary adder is shown in figure; it is used to perform additions o two 4 bit number w without carry B are ry orms the addi itions as given n If A3 A2 A1 A0 and B3 B2 B1 B0 a two 4 bit number then parallel binar adder perfo below,
Carry generated 1st number 2nd number Result C3 C2 A3 B3 S3 FA3 C1 A2 B2 S2 FA2 CO A1 B1 S1 FA1 A0 BO S0 FA0
The 4 bit parallel binary adder performs the additions of two 4 bit number and given 5 bit result of additions. To performs additions of two C1 bit number with carry. We have to replace half adder HA0 by Full adder FA0.
Q.11] explain parallel binary subtractor. Solutions: A3 B3 A2 B2
A1
B1
A0
B0
Full Subtractor 3
Full Subtractor 2
Full Subtractor 1
Full Subtractor
0
B3
D3
B2
D2
B1
D1
B0
Do
The block diagram of 4 bits parallel binary Subtractor is shown in figure; it is used to perform subtractions of two 4 bit numbers. If A3 A2 A1 A0 and B3 B2 B1 B0 are two 4 bit number then parallel binary Subtractor performs the Subtractions as given below,
FA3 1st number 2nd number Borrow Required Result A3 B3 B2 D3
FA2 A2 B2 B1 D2
FA1 A1 B1 B0 D1
FA0 A0 BO
B3 If the last borrow B3=1 then it indicates that the result is ve represented in 2s compliment from. If the last borrow B3=0 then it indicates that result is either zero or +ve. This 4 bit parallel binary subtractor performs subtractions of two 4 bit number without borrows. To performs subtractions of two 4 bit numbers with borrow, we have to replace half subtractor HDo by full Subtractor FSo.
D0

Q. 12 design and explain 1s compliment ckt or contr 2] d t rolled inverto ors. Solut tions: B3 B B2 B1 Bo I Control Input
Y3
Y2
Y1
Y0
logical ckt of 4 bit controll inverter is shown in fig f led s g. The l Oper rations: (1) ( B3 B2 B1 Bo is 4 bit number appl 1 n lied at the inp .if contro input I i made zero then in X-OR gate; 0 (+) put ol is ) B = B. e t Henc the 4 bit output will be Y3 Y2 Y1 Yo = B3 B2 B1 Bo i.e., output = inp 1 put. (2) ( If control input I is made 1, the in X-OR g l s en gate, 1 (+) B = B Hence the 4 bit outpu will be, e ut Y3 Y2 Y1 Yo = B3B2 B1Bo 1 That is; o output = 1s compliment of input. c If log 1 is added to this 1s co gic d ompliment the we will ge 2s complim of B3 B2 B1 Bo and it will represe its ve en et ment 2 ent value i.e. (-B3 B2 B1 Bo) e
3] d metic unit or e element. Q. 13 Design and explain parallel arithm Solut tions:
A3B3 3A2B B2A1B1AoBo I/O I ControlI/P
oYo A3Y3A2Y2A1Y1Ao B3 Bo B2 B B1 C2 C1 Co I/O dder Full Ad ull Fu Adder Full Adde er Full Adder 3 0 2 1
C3S3C2S2 2C1S1C CoSo
The bloc diagram of 4 bit parallel arithmetic unit is shown in fig. it can additions as well as subtractions using 2s compliment method. OPERATIONS: (1)Additions operations: The two 4 bit binary numbers A3 A2 A1 Ao and B3 B2 B1 Bo are applied at the i/p and control input is made zero. So output of X-OR gate will be Y3 Y2 Y1 Yo = B3 B2 B1 Bo. Hence 4 bit parallel binary adder performs the following additions. Carry generated C2 C1 CO 1st number 2nd number Controlled i/p Result C3 S3 S2 S1 A3 B3 A2 B2 A1 B1 Ao Bo 0 S0
FA3 FA2 FA1 FAo (2)Subtraction operations: To perfoms the subtraction A3 A2 A1 Ao minus (-) B3 B2 B1 Bo the two number applied at the i/p and control i/p I is made. So, output of X-OR gate will be 1s compliment of the input that is; Y3 Y2 Y1 Yo = B3B 2 B1Bo Hence the 4 bit parallel binary adder performs the following additions. Carry generated C2 C1 CO 1st number 2nd number Controlled i/p Result C3 A3 B3 A2 B2 A1 B1 Ao Bo 0 S3 S2 S1 S0 FAo (2s compliment)
FA3 FA2 FA1 If the last carry C3 is neglected then we will get 4 bit result of subtractions i.e., S3, S2, S1, So.
Q.14] Design and explain BCD ADDER or 8421 ADDER or SINGLE DIGIT DECIMAL ADDER. Solutions: the block diagram of 4 bit or single adder is shown in fig.(1) OPERATIONS: (1) If A3 A2 A1 Ao and B3 B2 B1 Bo are two 4 bit BCD number, then using FAs. FAo to FA3. These two BCD number are added with carry (Cin). To performs additions without carry Cin is made zero. The additions of BCD number with carry is perfomed as given below,
A A3B3A2B B2A1 1B1 AoBo o Full Ful ll Full F Full Add der Adder 3 Add 2 der Adder 1 C3S S3C2 S2C C1S1 1CoSo
Full Adder 3
ut Cou (Car rryOut)
Full F Add 2 der
Y
Full Adder 1
C3Z3C C2Z2C1Z1 1Zo
(2) T logical ck to detect 4 LSBs of res S3 S2 S1 So for invalid BCD can de The kt sult d esigning using K-map as g given below.
s3s 2 s1so s1so s1so s3s 2 0 0

m0 m1 0 m4 1 m12 0 m8 0 m9 1 m13 m5
s1so
0 m3 0 m7 1 m15 1 m11 1 1 0 0
s so s1
m2 m6 m14 m10
s3s2
s 3s 2
s 3s 2
Y = s 2s3.s3s1
LSBs of resu S3 S2 S1 So is greater th 9 (invalid BCD)OR la carry C3=1 ult S han d ast 1then we have to add 6(0110)to the 4 If 4 L LSBs of result S3 S2 S1 So . the logical ckt To check th 3 t t. hese two cond ditions is obta ained using th equations. he ) .(1) Y= (S3 S2 S1 S0) + (C3) Of OR AND-NAND gate. D This logical ckt. O eq. (1) can be designed using AND-O gate or NA Using HAo, H HA1,FA4 ,(0 Y Y 0)number is added to the 4 LSBs of result S3 S S1 So, as given below. o S2 (3) U HA1 FA4 Carr generated ry Ao C2 C1 HA 4 LS SBS of Resul lt S1 1 S3 S2 S0 Num mber 0YY0 (6 6) Y Y Y 0 Corr BCD res rect sult Z3 Z2 Z1 1 Z0
If 4 LSBs of result is greater than, 9 or last carry C3=1 then Y= 1. So, 0 Y Y 0=0 1 1 0=6. Hence 6 is added to the 4 LSBs of result S3 S2 S1 S0 and the final result obtained Z3 Z2 Z1 Z0 is correct BCD result, the last carry out will be equal to Y.
Q.15] Obtain using MUX the logical ckt. For the SOP eq. Y = AB + AC + ABC Solutions: the standard form of given eq. is;
Y = ABC + ABC + ABC + ABC + ABC (1)

The given SOP equations can be expressed.
+ve D0 D1 D2 D3 D4 D5 D6 D7 0 ve A B C Control Inputs 8 to 1 MUX Output Y
F= m (2, 3, 4, 6, 7).. (2)
Q. 15) B] using 8 to 1 MUX implement the eq. Y = ABC + ABD + AC . Assume ABD as control inputs. Solutions:
Y = ABCD + ABC D + ABCD + ABCD + ABC + ABC Y = ABCD + ABC D + ABCD + ABCD + ABCD + ABC D + ABCD + ABC D
(0 0 1 1, 0 0 1 0 , 1 1 1 1 , 1 1 0 1 ,
INPUTS A 0 0 0 0 0 0 B 0 0 0 0 1 1 D 0 0 1 1 0 0 C 0 1 0 1 0 1
1100,1001,1000)
OUTPUT Y SYMBOL OF O/P RELATION OF Y&C
0 0 1 1 0 0
m0 m1 m2 m3 m4 m5 Y=0=D2 Y=1=D1 Y=0=Do
0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 + 5ve
Do D1 D2 D38TO1 D4 D5 D6 D7 MUX
0 0 1 1 0 0 1 1 0 1
m6 m7 m8 m9 m10 m11 m12 m13 m14 m15 Y=B=D7 Y=1=D6 Y=0=D5 Y=1=D4 Y=0=D3
0 ve

Q.15 E] Obtain 8 to 1 MUX Using 4 to 1 MUX. 5) Solut tions: (1) ( We have t use 2 Ics of 4 to 1 MUX to o X. (2) ( One IC of 2 to 1 MUX f X. Do D14 4TO1 Y1 D2MUX D3 B C D4 Y1 1 2:1 Y2 2MUX
OutputY
TO1 D54T MUX D6M D7
Y2
5) ent tions f = m (1,2,5,7 ) using 1:8 DE-MUX having low level ac g ctive output. . Q. 15 f] impleme the funct Solut tions: As ou utput DE-MUX is low lev active, he vel ence in De-M MUX , instead of AND gat NAND gat is used. So the d te te corre esponding ou utput of De=MUX will be connected t NAND gat instead of OR gate, tha is we get N e to te at NANDNAN gate ckt. ND Y0 Y1
Di1TO8 Y4 DEMUXY5 D Y6 Y7
OutputF O

Q.15 G] Design Full Adder using DE-Mu 5) u ultiplexer. Solut tions: Full ad dder will perfo forms addition of 3 bit bina bits as giv in the trut table. n ary ven th Inpu ut A + B + C 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Outpu ut Su um(S) Ca arry (Co) 0 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1 m0 m1 m2 m3 m4 m5 m6 m7
For s sum m1 = m2 = m4 = m7= 2 =1 So w have to con we nnect Y1, Y2, Y4, Y7 outp of De-Mux , put x. For c carry out m3 = m5 = m6 = m7 = 1. So, w have to co we onnect Y3, Y5 Y6, Y7 out 5, tput of De-Mu ux.
Yo Y1 1TO8 Y2 Di D xY3 DeMux Y4 Y5 Y6 Y7 Carry Sum
6) tion f = Q.16 A] implement the funct
r output. m (1, 2 , 4 , 6 ) using decoder having low level active o
Solut tions: as outp of decoders low level active, hence the decoder consist of NA put e AND gates. So, instead of OR gate we have to connect N NAND hate. In the given functi e ion; m1 = m2 = m4 = m = 0 m6 So.m = m3 = m5 = m7 = 1 m0 5 So w have to cor we rrect the o/ps Y0, Y3, Y5, Y7 of decod to NAND gate. s der purInstituteo ofTechnolog gy,Nagpur Nagp

Yo o 3to8 Y1 1 Y2 2
D DecoderY3 3 InputDi Y4 4 Y5 5 Y6 6 Y7 7 Q.16 B] design f Subtracto using deco 6) full or oder. Solut tions: Truth Ta able Input A - B - C 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Outpu ut Diffe erence(D) Borrow (Bo) ) 0 1 1 0 1 0 0 1 0 1 1 1 0 0 0 1 m0 m1 m2 m3 m4 m5 m6 m7
outputf
Yo o Y1 1 Y2 2 Borrow
3to8
De ecoderY3 3 Y4 4
Y5 5 InputDi Y6 6 Y7 7 purInstituteo ofTechnolog gy,Nagpur Nagp
Difference e
Q. 18) A] Explain BCD to 7 Segment Decode. Solutions: (a) Segment display: 7 segment display consist of LEDs a to g in the form of segment . these 7 segments are physically arranged like decimal digit 8. There is one circular LED for a decimal point (dp).these 8 LEDs are connected either in common cathode configuration (Fig 2)or in common anode configuration (fig3) in fig(2) by giving logic 1/0 to the anode. LED can be made on/off resp. similarly in fig (3) by giving logic 0/1 to the cathode LED can be made on/off resp. a abc fb 0ve (Commoncathodeconnection)Fig(2) ec +5ve d (Commonanodeconnection)Fig(3) (b) Design of BCD to 7 segment decode: When 4 bit no is applied to the input of decoder then decoder will give corresponding will give corresponding 7 bit output Ya to Yg, if these 7 bits are applied to the 7 Leds a to g of 7 segment display then the decimal digit corresponding to the BCD input is displayed on 7 segment display. If 7 segment display is connected in common cathode configuration then to make the LED on/off , decode will give logic input to the anode it LED. Ya A Yb Yc Yd Ye Yf Yg
BBCD Cto D7segment Decoder
(Physicalstructure)(7segmentdisplayin commoncathodeconfiguration) NagpurInstituteofTechnology,Nagpur
The truth table showing BCD input and the required output of decoder for displaying equivalent decimal digit to given below. Input 7 segment output Equation Decimal A B C D Ya Yb Yc Yd Ye Yf Yg Digit
0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 1 1 1 0 0
0 0 1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1 0 1
0 1 2 3 4 5 6 7 8 9
1 0 1 1 0 1 1 1 1 1
1 1 1 1 1 0 0 1 1 1
1 1 0 1 1 1 1 1 1 1
1 0 1 1 0 1 1 0 1 1
1 0 1 0 0 0 1 0 1 0
1 0 0 0 1 1 1 0 1 1
0 0 1 1 1 1 1 0 1 1
The logical ckt. Of decoder can be designed using K-Map,DRAW 4 INPUT K- MAP
AB CD
AB
CD
CD
CD
CD
m0
m1 m5 m13 m9
m3 m7 m15 m11
m2 m6 m14 m10
AB
m4
AB
AB
m12 m8
As inputs BCD, So, m10 to m15=X (Dont care); Design for Ya

AB CD CD
CD
0 1 X 1 1 1 X X
CD
1 1 X X
CD
AB
1 0 X 1
AB
AB AB
Ya = A + C + BD + BD
Design K-Map Yb
AB CD CD
AB
1 1 X 1 1 0 X X
CD
1 1 X X
CD
1 0 X X
CD
AB
AB
AB
Yb = CD + CD + B
Design K-Map for Yc:

AB CD CD
CD
CD
CD
AB
1 1 X 1
1 1 X 1
1 1 X X
0 1 X X
AB
AB AB
Yc = C + D + B
Design K-Map for Yd:
AB CD CD
CD
CD
CD
AB
1 0 X 1
0 1 X 1
1 0 X X
1 1 X X
AB
AB
AB
Yd = C D + A + BC + BCD + BD
Design for Ye:
AB CD CD
AB
AB
CD
0 0 X 0
CD
0 0 X X
CD
1 1 X X
1 0 X 1
AB AB
Ye = BD + C D
Design for Yf:
AB CD CD
AB
1 1 X 1
CD
0 1 X 1 0 0 X X
CD
0 1 X X
CD
AB
AB
A B Yf = A + BC + CD + B D
Design for Yg:
AB CD CD
AB
0 1 X 1
CD
0 1 X 1 1 0 X 1
CD
1 1 X X
CD
AB
AB A B Yg = A + B D + C D + BC
Q.18 b] Expla binary to 7 segmen decoder. 8) ain t nt Solu utions: A B C D BCD to 7 segment Decoder Ya Yb c Yc Yd Ye Yf Yg
ysical structure) (Phy
(7 segm display i ment in com mmon cathode configuration e n)
When 4 bit binary no. is applie of the input of decoder, then decoder will gate corr n y ed t responding 7 bits output Y to Yg. If Ya these 7 bits are ap e pplied to the anode of 7 LE a EDs a to g t then the hexa adecimal digit correspondin to the bina input is t ng ary displ layed on 7 seg gment display .the table sh y howing 4 bit b binary input a the required output of d and decoder for displaying equiv valent hexade ecimal digit is given below s w.
A Input B C D Equation Decimal Digit Ya 1 0 1 1 0 1 1 1 1 1 1 0 1 0 1 1 7 segment output Yb Yc Yd Ye 1 1 1 1 1 0 0 1 1 1 1 0 0 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 0 1 0 1 0 0 0 1 0 1 0 1 1 1 1 1 1 Yf 1 0 0 0 1 1 1 0 1 1 1 1 1 0 1 1 Yg 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 1 2 3 4 5 6 7 8 9 10(A) 11(B) 12(C) 13(D) 14(E) 15(F)
Design for Ya
AB CD CD
CD
CD
CD
AB AB
AB
1 0 1 1
0 1 0 1
1 1 1 0
1 1 1 1
AB
Ya = BD + AC + BC + AD + AB + ABD
Design K-Map Yb
AB CD CD
AB
1 1 0 1 1 0 1 1
CD
CD
1 1 0 0
CD
1 0 0 1
AB
AB AB
Yb = AB + ACD + ACD + BD + ACD
Design K-Map for Yc:
AB CD CD
AB
1 1 0 1 1 1 1 1
CD
1 1 0 1
CD
0 1 0 1
CD
AB
AB AB
Yc = AC + AD + AB + AB + CD
Design K-Map for Yd
AB CD CD
AB
1 0 1 1
CD
0 1 1 1
CD
1 0 0 1
CD
1 1 1 0
AB
AB AB
Yd = BCD + AC + BCD + BCD + BC D + AC D
Design for Ye
AB CD CD
AB
1 0 1 1
CD
0 0 1 0
CD
0 0 1 1
CD
1 1 1 1
AB
AB AB
Ye = BD + AB + AC + C D
Design for Yf
AB CD CD
AB
1 1 1 1
CD
0 1 0 1
CD
0 0 1 1
CD
0 1 1 1
AB
AB AB
Yf = CD + AB + AB + AB + BC D
Design for Yg
AB CD CD
AB
CD
0 1 1 1
CD
1 0 1 1
CD
1 1 1 1
0 1 0 1
AB
AB
AB
Yg = BC + C D + AB + AD + ABC
Logical Ckt.
Q.23) Conversions: Solutions: Excitations Table of different Flip Flop. Previous O/P Qn 0 0 1 1 Next Required O/P Qn+1 0 1 0 1 Inputs to Flip/ Flop K S R D X 0 X 0 X 1 0 1 1 0 1 0 0 X 0 1
J 0 1 X X
T 0 1 1 0
1) Convert J-K Flip Flop into S-R Flip Flops. Solutions: Flip Flop available=> J-K Flip Flop. Flip Flop => S-R Flip Flop. Inputs S R 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Truth table Design for J Next Required O/P Qn+1 0 1 0 0 1 1 X X Inputs to Flip/ Flop Available J K 0 X X 0 0 X X 1 1 X X 0 X X X X Excitation Table
Qn 0 1 0 1 0 1 0 1
Pr
S
RQn RQ
RQ
RQ
RQ
S
S
0 1
X X
X X
0 X
J =S
K Q
Clr
Design for K
S
RQn RQ
RQ
RQ
RQ
S
S
X X
0 0
1 X
X X
K=R
2) Convert S-R Flip Flop into J-K Flip Flops. Solutions: Flip Flop available=> S-R Flip Flop. Flip Flop => J-K Flip Flop. Inputs J K 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Truth table Design for S
J
Qn 0 1 0 1 0 1 0 1
Next Required O/P Qn+1 0 1 0 0 1 1 1 0
Inputs to Flip/ Flop Available S R 0 X X 0 0 X 0 1 1 0 X 0 1 0 0 1 Excitation Table
KQn KQ
KQ
KQ
KQ
J
J
0 1
X X
0 0
0 1
S = JQ
Design for K
J
KQn KQ
KQ
KQ
KQ
J
J
X 0
0 0
1 1
X 0
R = KQ
Logical Circuit
3) Convert S-R Flip Flop into D Flip Flops. Solutions: Flip Flop available=> S-R Flip Flop. Flip Flop => J-K Flip Flop. Inputs Qn 0 1 0 1 Next Required O/P Qn+1 0 0 1 1 Inputs to Flip/ Flop Available S R 0 X 0 1 1 0 X 0 Excitation table
D 0 0 1 1 Design for S
D
0
D
0 X
S=D
Design for R
D
X
D
1 0
R=D
Logical Ckt.
4) Convert T Flip Flop into S-R Flip Flops. Solutions: Flip Flop available=> T Flip Flop. Flip Flop Required => S-R Flip Flop. Inputs S 0 0 0 0 1 1 1 1 Truth table Design for T
S
Next Required O/P Qn+1 Qn 0 1 0 1 0 1 0 1
R 0 0 1 1 0 0 1 1
0 1 0 0 1 1 1 0
Inputs to Flip Flop Available T 0 0 0 1 1 0 X X Excitation Table
RQn RQ
RQ
RQ
RQ
S
S
0 1
0 0
1 X
0 X
T = RQ + S Q
5) Convert T Flip Flop into D Flip Flops. Solutions: Flip Flop available=> D Flip Flop. Flip Flop Required => T Flip Flop. Inputs D 0 0 1 1 Design for T
D
Next Required O/P Qn+1
Qn 0 1 0 1
0 0 1 1
Inputs to Flip Flop Available T 0 1 1 0
D
D
0 1
1 0
T = DQ + DQ
Logical Circuit.
6) Convert D Flip Flop into J-K Flip Flops. Solutions: Flip Flop available=> D Flip Flop. Flip Flop Required => J-K Flip Flop. Inputs J K 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Truth table Design for D
J
Next Required O/P Qn+1 Qn 0 1 0 1 0 1 0 1
0 1 0 0 1 1 1 0
Inputs to Flip Flop Available D 0 1 0 1 0 1 0 1 excitation table
KQn KQ
KQ
KQ
KQ
J
J
0 0
1 1
1 1
0 0
D =Q
Logical Circuit:
7) Convert D Flip Flop into T Flip Flops. Solutions: Flip Flop available=> D Flip Flop. Flip Flop Required => T Flip Flop. Inputs T 0 0 1 1 Design for D
T
Next Required O/P Qn+1
Qn 0 1 0 1
0 1 1 0
Inputs to Flip Flop Available D 0 1 1 0
0
T
T
1 0
D = TQ + T Q
Logical Circuit
Q. 24) Explain various types of shift register. Solutions: n bits are read together then it is called parallel output. So, depending upon the type of input and output, shift register are divides into following types. A) SERIAL INPUT SERIAL OUTPUT (SISO) SHIFT REGISTER. B) SERIAL INPUT PARALLEL OUTPUT (SIPO) SHIFT REGISTER. C) PARALLEL INPUT SERIAL OUTPUT (PISO) SHIFT REGISTER. D) PARALLEL INPUT PARALLEL OUTPUT (PIPO) SHIFT REGISTER. A) SERIAL INPUT SERIAL OUTPUT (SISO) SHIFT REGISTER: 4bitSISO
Serial I/P
Shift Register
Serial O/P
The logical ckt. Of 4 bits SISO shift register using D-type flip flop is shown in Fig. (1) and using S-R/ J-K Flip Flop is shown in fig. (2). Operations: (1) Initially Clr =0 So, Q3 Q2 Q1 Q0=0 0 0 0. During the operations Clr =1. (2) If ABCD=1011 is 4 bit number to br stored in 4 bit register , then initially MSB A=1 is applied at serial input Do. After +ve edge of point clk cycle , as Do=1 . So, Qo become . (3) As Qo=1, so, D1=1. Hence after +ve edge if 2nd clk cycle Q1=1 and so on. (4) Finally after 4 clk cycles. 4 bit number ABCD=1011 is stored in the 4 flip flops i.e., Q3 Q2 Q1 Q0=1011 (5) As input binary bit applied as well as output binary bt read is serial hence it is called SISO shift register.
B) SERIAL INPUT PARALLEL OUTPUT (SIPO) SHIFT REGISTER: 4bitSIPO
Q3 Q2 Q1 Qo Parallel O/P
Serial I/P
Shift Register
The logical ckt. of 4 bit serial input parallel O/P shift register is shown in fig.(1). Operations: (1) Initially Clr=0 So, Q3 Q2 Q1 Q0=0 0 0 0. During the operations Clr=1. (2) If ABCD=1011 is 4 bit number to br stored in 4 bit register , then initially MSB A=1 is applied at serial input Do. So, Do = A = 1. Hence after +ve edge of 1st clk cycle, Q0 = A= 1.
(3) As Qo =A= 1, So, D1= A=1and the next bit B=0 is applied at serial input Do. Hence sfter +ve edge of 2nd clk cycle, Q1 = A= 1 and Qo =B= 0. In this way the binary bit goes on shifting from one flip flop to another towards right and finally in 4 clk cycles, the 4 bit number is stored I the register i.e., Q3 Q2 Q1 Qo = A B C D = 1 0 1 1. (4) All these 4 bits are read together in parallel. As input is serial and output is parallel, so, it is called SIPO shift register.
C) PARALLEL INPUT SERIAL OUTPUT (PISO) SHIFT REGISTER.
Do Parallel I/P D1 D2 D3
4bitPISO Shift Register
Serial I/P
The logical ckt. Of 4 bit PISO shift register is shown in fig.(1).

Operations:
(1) Initially Clr=0 . So, Q3 Q2 Q1 Qo= 0 0 0 0, during the operation clr=1. (2) If ABCD is 4 bit number to be stored then these 4 bits are applied to the corresponding 4 parallel input pins x and control signal I is made zero(0). When I=0 the And gates number 0 are enabled, AND gates number 1 are disables. So, the inputs ABCD are applied through gates 0, 2 ti the inputs of flip flop i.e., D3 D2 D1 Do= A B C D, at the positive edge if 1st clk cycle, all these 4 bits are stored in the 4 flip flop i.e., Q3 Q2 Q1 Qo= A B C D. (3) As output is serial hence for obtaining serial output at Q3, we have to performs shift operations. the control input I is made 1. So, AND gates number 0 are disabled, And gats number 1 are enabled. Hence the output of one flip flop gets connected to the input of next flip flop through gates 1, @ i.e., D3=q2. D2=Q1, D1= Q0. At +ve edge of each clk cycle the binary data goes on shifting from one flip flop to another towards right and we get serial output at Q3.
D) PARALLEL INPUT PARALLEL OUTPUT (PIPO) SHIFT REGISTER. D1 D2 D3 D4 4bitPIPO Shift Register
DESCRIPTIONS: (1) INITIALLY Clr=0. So, Q3, Q2, Q1,Qo=0 0 0 0. During the operation Clr=1.
(2) If ABCD is 4 bit number to be stored then initially MSB A is applied at serial input.D3. At the +ve edge of 1st clk cycle ,as input D3=A, So Q3=A. (3) As D3=A. So,input D2=A and at the +ve edge of 2nd clk cycle Q2=A and so on. Hence the binary bit goes on shifting from 1 flip flop to another towards left i.e., Q3= Q2, Q1 and Qo. And Q1, Q0. Hence it is called shift register.
Q. 25) a] Design MOD 8 Synchronous Counter. Solutions: MOD 8 counters will count 8 numbers from 0 to 7. (7) decimal = (111)binary i.e. Maximum 8 bit binary number. So, we have to design 8 flip flop counter. Given synchronous counter. Clk input Output Q1 0 0 1 1 0 Clk input Qo 0 1 0 1 0 Output Q1 0 1 1 0
1 2nd 3rd 4th 5th
st
Q2 0 0 0 0 1
6 7th 8th 9th
th
Q2 1 1 1 0
Qo 1 0 1 0
e] Design a counter for the following sequence. 0 5 7
Solutions: (7) decimal = (111) binary Previous flip flop Next required output (n+1) output (n) Q2n Q1n Qon Q2(n+1) Q1(n+1) Qo(n+1)
Input to flip flop J2 K2 J1 K1 Jo Ko
0 1 1 1 1
Design for J2
Q2
0 0 1 0 1
0 1 1 0 0
1 1 1 1 0
0 1 0 1 0
1 1 0 0 0
1 X X X X
X 0 0 0 1
0 1 X 1 X
X X 1 X 1
1 X X 0 0
X 0 1 X X
m0 m5 m7 m4 m6
Q1Qo Q 1 Q o
Q 1Q 0
Q 1Q 0
Q 1Q 0
Q2
1 X
X X
X X
X X
Q 2
J2 =1
Design for K2
Q2
Q1Qo Q 1 Q o
Q 1Q 0
Q 1Q 0
Q 1Q 0
Q2
X 0
X 0
X 0
X 1
Q 2
K 2 = Q 1Q o
Design for J1
Q2
Q1Qo Q 1 Q o
Q 1Q 0
Q 1Q 0
Q 1Q 0
Q2
0 1
X 1
X X
X X
Q 2
J1 = Q 2

Desi ign for K1
Q2
Q1Q Q 1 Q o Qo
Q 1Q 0
Q 1Q 0
Q 1Q 0
Q2
X
Q 2
X X
X 1
X 1
K1 = 1
Desi ign for J0
Q2
Q1Qo Q 1 Q o 1
Q 1Q 0
Q 1Q 0
Q 1Q 0
Q2
1 0
X X
X X
X 0
Q 2
Jo = Q 2
Desi ign for Ko
Q2
Q1Qo Q 1 Q o 1
Q 1Q 0
Q 1Q 0
Q 1Q 0
Q2
X X
X 0
X 1
X X
Q 2
Ko = Q1
Q.25) g] Design lock free or lock out counter to count in the following sequence. 0 5 2
4 6 Solutions: in lock free counter or lock out counter if due to any error the counter enters into any unused state (1, 3, 7) then in the next clk cycle the output of counter should charge from unused state to the used state. 1 0 5 2 Unused state 3 7 4 6 TRANSITION TABLE Previous flip flop output (n) Q2n Q1n Qon
Next required output (n+1) Q2(n+1) Q1(n+1) Qo(n+1) J2 K2
Input to flip flop J1 K1 Jo Ko
0 1 0 1 1
0 0 1 Design for J2
Q2
0 0 1 1 0
0 1 1
0 1 0 0 0
1 1 1
1 0 1 1 0
0 0 0
0 1 1 0 0
0 0 0
1 0 0 0 0
0 0 0
1 X 1 X X
0 0 X
X 1 X 0 1
X X 1
0 1 X X 0
0 X X
X X 0 1 X
X 1 1
1 X 0 0 0
X X X
X 1 X X X
1 1 1
0 5 2 6 4
1 3 7
Q1Qo Q 1 Q o
Q 1Q 0
Q 1Q 0
Q 1Q 0
Q2
1
Q 2
0 X
0 X
1 X
J2 = Q0
Design for K2
Q2
Q1Qo Q 1 Q o
Q 1Q 0
Q 1Q 0
Q 1Q 0
Q2
X 1
X 1
X 1
X 0
Q 2
K 2 = Q 1 + Qo
Design for J1
Q2
Q1Qo Q 1 Q o
Q 1Q 0
Q 1Q 0
Q 1Q 0
Q2
0 0
0 1
X X
X X
Q 2
J1 = Q2
Design for K1
Q2
Q1Qo Q 1 Q o
Q 1Q 0
Q 1Q 0
Q 1Q 0
Q2
X X
X X
1 1
0 1
Q 2
K1 = Q 2 + Qo
Design for Jo
Q2
Q1Qo Q 1 Q o
Q 1Q 0
Q 1Q 0
Q 1Q 0
Q2
1 0
X X
X X
0 0
Q 2
JO = Q 2Q1
Design for Ko
Q2
Q1Qo Q 1 Q o
Q 1Q 0
Q 1Q 0
Q 1Q 0
Q2
X X
1 1
1 1
X X
Q 2
Ko = 1
esign MOD 6 lock free co ounter for th following s he sequence. h] De 2 7 1
If the counter cen e nters into un nused state th the next o hen output shoul be 5 ld tions: Solut 2 7 1 0 6 Previous flip flop ut outpu (n) Q2n Q1 1n Qon 0 1 0 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 1 1 0 0 0 1 4 5 3 ut p Inpu to flip flop J2 2 1 X 1 X X X 1 1 K2 X 1 X 0 0 0 X X J1 J X X 0 0 1 X 0 X K1 0 1 X X X 0 X 1 Jo 1 X X X 0 1 1 X Ko X 0 0 1 X X X 0 2 7 1 5 4 6 0 3
ired output (n+1) Next requi Q2(n+1) Q 1 0 1 1 1 0 1 1 Q1(n+1) Q 1 0 0 0 1 1 0 0 Qo(n+1) 1 1 1 0 0 0 1 1
Design for J2
Q2
Q1Qo Q 1 Q o
Q 1Q 0
Q 1Q 0
Q 1Q 0
Q2
X X
1 1
1 1
X X
Q 2
J2 =1
Design for K2
Q2
Q1Qo Q 1 Q o
Q 1Q 0
Q 1Q 0
Q 1Q 0
Q2
X 0
X 0
X 1
X 0
Q 2
K 2 = Q 1Q 0
Design for K1
Q2
Q1Qo Q 1 Q o
Q 1Q 0
Q 1Q 0
Q 1Q 0
Q2
X X
X X
1 1
0 0
Q 2
K1 = Q0
Design for J1
Q2
Q1Qo Q 1 Q o
Q 1Q 0
Q 1Q 0
Q 1Q 0
Q2
0 1
0 0
X X
X X
Q 2
J 1 = Q 2 Qo

Desi ign for Jo
Q2
Q1Qo Q 1 Q o 1
Q 1Q 0
Q 1Q 0
Q 1Q 0
Q2
1 0
X X
X X
1 1
Q 2
Jo = Q 2 + Q1
ign for Ko Desi
Qo Q 2 Q1Q Q 1 Q o
Q2
Q 1Q 0
Q 1Q 0
Q 1Q 0
X X
0 1
0 0
X X
Q 2
Ko = Q2Q1
i] Design 3 bit gray code counter. Solutions: The sequence of 3 bit gray code number is, INPUT A B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 1
C 0 1 0 1 0 1 0 1
G2 0 0 0 0 1 1 1 1 3
OUTPUT G1 0 0 1 1 1 1 0 0 2
G0 0 1 1 0 0 1 1 0
4 Previous flip flop output (n) Q2n Q1n Qon 0 0 0 0 1 1 1 1 Design for J2
Q 2 Q1Qo Q 1 Q o
Q 1Q 0
Next required output (n+1) Q2(n+1) 0 0 0 1 1 1 1 0 Q1(n+1) 0 1 1 1 1 0 0 0 Qo(n+1) 1 1 0 0 1 1 0 0 J2 0 0 0 1 X X X X K2 X X X X 0 0 0 1
Input to flip flop J1 0 1 X X X X 0 0 K1 X X 0 0 0 1 X X Jo 1 X X 0 1 X X 0 Ko X 0 1 X X 0 1 X 0 1 3 2 6 7 5 4
0 0 1 1 1 1 0 0
0 1 1 0 0 1 1 0
Q 1Q 0
Q 1Q 0
Q2
0 X
0 X
0 X
1 X
Q 2
J 2 = Q1Qo
Design for K2
Q 2 Q1Qo Q 1 Q o
Q 1Q 0
Q 1Q 0
Q 1Q 0
Q2
X 1
X 0
X 0
X 0
Q 2
K 2 = Q1Qo
Design for J1
Q 2 Q1Qo Q 1 Q o
Q 1Q 0
Q 1Q 0
Q 1Q 0
Q2
0 0
1 0
X X
X X
Q 2
J1= Q2Qo
Design for K1
Q 2 Q1Qo Q 1 Q o
Q 1Q 0
Q 1Q 0
Q 1Q 0
Q2
X X
X X
0 1
0 0
Q 2
K 1 = Q 2 Qo
Design for Jo
Q 2 Q1Qo Q 1 Q o
Q 1Q 0
Q 1Q 0
Q 1Q 0
Q2
1
Q 2
X X
X X
0 1
Jo = Q2Q1 + Q2Q1

Desi ign for Ko
Qo Q 2 Q1Q Q 1 Q o
Q2
Q 1Q 0
Q 1Q 0
Q 1Q 0
X X
0 1
1 0
X X
Q 2
Ko = Q 2 Q 1 + Q 2 1 2Q
k] De esign Ex-3 co counter. ode Solut tions: INPUT A 0 0 0 0 0 0 0 0 1 1 B 0 0 0 0 1 1 1 1 0 0 C 0 0 1 1 0 0 1 1 0 0 D 0 1 0 1 0 1 0 1 0 1 Y3 0 0 0 0 0 0 1 1 1 1 OUTPUT ( (Ex-3 code) Y2 Y1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 Y0 1 0 1 0 1 0 1 0 1 0
Example: (7)ex-3 = (10) decimal= (1010)binary Previous flip flop Next required output (n+1) output (n) Q3n Q2n Q1n Qon Q3(n+1) Q2(n+1) Q1(n+1) Qo(n+1) 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Input to flip flop J3 0 0 0 0 1 X X X X X K3 X X X X X 0 0 0 0 1 J2 1 X X X X 0 0 0 1 X K2 X 0 0 0 1 X X X X 0 J1 X 0 1 X X 0 1 X X 1 K1 1 X X 0 1 X X 0 1 X Jo X 1 X 1 X 1 X 1 X 1 Ko 1 X 1 X 1 X 1 X 1 X 3 4 5 6 7 8 9 10 11 12
Design for J3
Q 3Q 2 Q1Qo Q 1 Q o
Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
X 0 X
X 0 X X
0 1 X X
X 0 X X
Q 3Q 2
Q 3Q 2
Q 3Q 2
J3 = Q2Q Q0 1
Design for K3
Q 3Q 2 Q1Qo Q 1 Q o
Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
X X 1
X X X 0
X X X 0
X X X 0
Q 3Q 2
Q 3Q 2
0
Q 3Q 2
K 3 = Q2
Design for J2
Q 3Q 2 Q1Qo Q 1 Q o
Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
X X
X X X 0
1 X X 1
X X X 0
Q 3Q 2
Q 3Q 2
Q 3Q 2
X 0
J 2 = Q 1Q 0
Design for K2
Q 3Q 2 Q1Qo Q 1 Q o
Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
X 0
X 0 X X
X 1 X X
X 0 X X
Q 3Q 2
Q 3Q 2
Q 3Q 2
0 X
K 2 = Q 1Q 0
Design for J1
Q 3Q 2 Q1Qo Q 1 Q o
Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
X 0
X 1 X 1
X X X X
X X X X
Q 3Q 2
Q 3Q 2
Q 3Q 2
1 0
J 1 = Q 0 + Q 3Q 2
Design for K1
Q 3Q 2 Q1Qo Q 1 Q o
Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
X X X
X X X X
1 1 X 1
X 0 X 0
Q 3Q 2
Q 3Q 2
X
Q 3Q 2
K1 = Q0
Design for Jo
Q 3Q 2 Q1Qo Q 1 Q o
Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
X 1
X X X X
X X X X
X 1 X 1
Q 3Q 2
Q 3Q 2
Q 3Q 2
1 1
Jo = 1
Design for Ko
Q 3Q 2 Q1Qo Q 1 Q o
Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
X X X
X 1 X 1
1 1 X 1
X X X X
Q 3Q 2
Q 3Q 2
Q 3Q 2
Ko = 1
i] De esign5 4 -2 -1 code conver rters. Solut tions: 5 4 -2 -1 code converters is used for d e decimal digits as given be s elow. Decimal digits l 0 1 2 3 4 5 6 7 8 9 Code C 5 0 0 0 0 0 1 1 1 1 1 4 0 1 1 1 1 0 1 1 1 1 -2 0 1 1 0 0 0 1 1 0 0 -1 1 0 1 0 1 0 0 1 0 1 0
Previous flip flop output Next required output (n+1) (n) Q3n Q2n Q1n Qon Q3(n+1) Q2(n+1) Q1(n+1) Qo(n+1) 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 1 0 0 0 0 0 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 1 0 0 Input to flip flop J3 0 0 0 0 1 X X X X X K3 X X X X X 0 0 0 0 1 J2 1 X X X X 1 0 X X X K2 X 0 0 0 1 X X 0 0 1 J1 1 X X 0 0 1 X X 0 0 K1 X 0 1 X X X 0 1 X X Jo 1 X 1 X 0 1 1 X X 0 Ko X 1 X 1 X 1 X 1 X 1
Design for J3
Q 3Q 2 Q1Qo Q 1 Q o
Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
0 1
X 0 X X
X 0 X X
X 0 X X
Q 3Q 2
Q 3Q 2
Q 3Q 2
X X
J 3 = Q2Q1Qo
Design for K3
Q 3Q 2 Q1Qo Q 1 Q o
Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
X X 1
X X 0 X
X X 0 X
X X 0 X
Q 3Q 2
Q 3Q 2
0
Q 3Q 2
K 3 = Q 2Q1Qo
Design for J2
Q 3Q 2 Q1Qo Q 1 Q o
Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
1 X
X X X X
X X 0 X
X X X X
Q 3Q 2
Q 3Q 2
Q 3Q 2
X 1
J 2 = Q1
Design for K2
Q 3Q 2 Q1Qo Q 1 Q o
Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
X 1 1
X 0 0 X
X 0 X X
X 0 X X
Q 3Q 2
Q 3Q 2
X
Q 3Q 2
K 2 = Q 1Qo
Design for J1
Q 3Q 2 Q1Qo Q 1 Q o
Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
1 0 0
X 0 0 X
X X X X
X X X X
Q 3Q 2
Q 3Q 2
Q 3Q 2
J1 = Q2
Design for K1
Q 3Q 2 Q1Qo Q 1 Q o
Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
X X
X X X X
X 0 0 X
X 1 1 X
Q 3Q 2
Q 3Q 2
Q 3Q 2
X X
K 1 = Qo
Design for Jo
Q 3Q 2 Q1Qo Q 1 Q o
Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
1 0 0
X X X X
X X X X
X 1 1 X
Q 3Q 2
Q 3Q 2
1
Q 3Q 2
Jo = Q 2 + Q 1Q 0
Design for Ko
Q 3Q 2 Q1Qo Q 1 Q o
Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
X X
X 1 1 X
X 1 1 X
X X X X
Q 3Q 2
Q 3Q 2
Q 3Q 2
X X
Ko = 1 (+5v)
Design MOD 3 UP-DOWN counter to count the fo N ollowing sequ uence. m] D 0 3 1
Solut tions: For up p-down counte one additio control in er onal nput I will be used. If I = 0 then counter will operate as up down r es n coun and the co nter ounting seque ence will be 0 0,3,1. If I = 1 then count will operat as down c ter tes counter and th counting se he equence will b 1,3,0. be Control input i Previous flip flop ) output (n) Q1n 0 1 0 0 1 0 Q0n n 0 1 1 1 1 0 required Next r outpu (n+1) ut Q1(n+1) 1 0 0 1 0 0 Q0(n+1) 1 1 0 1 0 1 o Input to flip flop
I 0 Up cou unter 0 0 1 1 1
J1 1 X 0 X 1 X
K1 1 X X X 1 X
Jo 1 X X X X 1
Ko X 0 1 0 1 X
Dow wn Cou unter ign for J1 Desi

I
I
Q1Qo 1
Q 1Q o
Q 1Q 0
Q 1Q 0
Q 1Q 0
1 0
0 1
X X
X X
Jo = I Qo + IQo

Desi ign for K1
I Q1Qo Q 1 Q o 1
I
Q 1Q 0
Q 1Q 0
Q 1Q 0
1 X
X X
X 1
X X
K 1 = 1
Desi ign for J0
I Q1Qo Q 1 Q o 1
I
Q 1Q 0
Q 1Q 0
Q 1Q 0
1 1
X X
X X
X X
J0 =1
ign for K0 Desi
I Q1Qo Q 1 Q o 1
I
Q 1Q 0
Q 1Q 0
Q 1Q 0
X X
1 0
0 1
X X
K 0 = I Q 1 + IQ 1
n] Design 3 bit synchronous UP-DOWN counter. Solutions: Transition table: Control input Previous flip flop output (n) Q2n 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 Q1n 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 Q0n 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 Next required output (n+1) Q2(n+ Q1(n+ Q0(n+ 1) 1) 1) 0 0 0 1 1 1 1 0 1 1 1 0 0 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 Input to flip flop J2 0 0 0 1 X X X X X X X X 0 0 0 1 K2 X X X X 0 0 0 1 0 0 0 1 X X X X J1 0 1 X X 0 1 X X 0 1 X X 0 1 X X K1 X X 0 1 X X 0 1 X X 0 1 X X 0 1 Jo 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X Ko X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1
I 0 Up 0 0 0 0 0 0 1 1 Down 1 1 1 1 1 Counter 1
Counter 0
Jo=Ko=(+5V)=(LOGIC1)
Design for J2
Q 3Q 2 Q1Qo Q 1 Q o
Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
0 X
0 X X 0
1 X X 0
0 X X 0
Q 3Q 2
Q 3Q 2
Q 3Q 2
X 1
Ko
= 1 (+5v)
Design for K2
Q 3Q 2 Q1Qo Q 1 Q o
Q 3Q 2
Q 1Q 0
Q 1Q 0
Q 1Q 0
X 0
X 0 0 X
X 1 0 X
X 0 0 X
Q 3Q 2
Q 3Q 2
Q 3Q 2
1 X
Ko = 1 (+5v)
Design for J1
Q 3Q 2 Q1Qo Q 1 Q o
Q 1Q 0
Q 1Q 0
Q 1Q 0
0 0 1 1
1 1 0 0
X X X X
X X X X
Q 3Q 2
Q 3Q 2 Q 3Q 2
Q 3Q 2
J 1 = Q 3Q 0 + Q 3 Q 0
Design for K1
Q 3Q 2 Q1Qo Q 1 Q o
Q 1Q 0
Q 1Q 0
Q 1Q 0
X X X X
X X X X
1 1 0 0
0 0 X 1
Q 3Q 2
Q 3Q 2 Q 3Q 2
Q 3Q 2
K 1 = Q 3Q 0 + Q 3 Q 0
Ack knowledge ement:

We are thankf to all th authors of Text B ful he Books of Subject: Dig gital Circuit & Funda ts amentals o of Micr roprocessor that are cited during the comp rs g pilation of th Question Bank to p his n provide to th students he s. Que estions, answ and re wers elated inform mation are c collectively compiled and presente in single form based ed d on th material cited from various cont he v tributions fro the auth and onlline sources om hors s. References:
Digital Design 3rd edition by M. Morris Ma D ano, Digital logic and Computer D D Design by M. Morris Mano, Digital Circuit & Design R Jain D R.P. Digital Circuit & Design - A P. Godse D A. Fundamentals Of Digital Ele ectronics A. Anand Kuma . ar cessor & contr roller V. J. V Vibhute 8 bit microproc 8 bit microproc cessor Gaon nkar

Digital Circuits &amp; Fundamentals of Microprocessor

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Nagpur Institute of Technology, Nagpur

Department of Computer Science & Engineering

Digital Circuits & Fundamentals of Micro Processor (III Sem-CSE)

= 1 81 + 5 8 0 + 7 8 1 + 3 8 2 = (13.92136) decimal = 2 81 + 2 8 0 = (18) decimal =7 80 = (7) decimal = 2 8 0 + 5 8 1 =(2.653)decimal

(110)H = (1 16 2 + 1 16 1 + 0 16 = (272) decimal (2A) H = (2 16 1 + A 16 0 ) = (42)D (DC)H = (D 16 1 + C 16 = (220)D

Ans: (272 ) (42 )

(9310 .25 )10 = (? )H

VI] (273 . 45 )O = (? )H Solutions:

(273.45) = (0 Ans: (0 BB.94 )H

d] (10110111) gray = (?)B Solutions: NagpurInstituteofTechnology,Nagpur

0.62 0.96 0.68 0.44

Quotient result 4.96 7.68 5.44 3.52

Solutions: 0 0 1 0 0 1 0 1 0 1 1 0 . 0 0 1 0 0 1 1 1 0 1 0 0 0 0 1 1 . 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 . 1 0 1 1 (invalid BCD) 0 0 0 0 0 0 0 0 0 0 0 0 . 0 1 1 0

2s Compliment of (315)D = ( 1 0 1 1 0 0 0 1 0 1 )B = (-315)D (+253)D + (-315)D = 0 1 1 011111101 011000101 111000010

i] Excess 3 code Subtractions (47.59)D (28.38)D (?)D Solutions:

2] AND gate using NAND gate:

Q.2) b] Prove that:

[(A.B + A.B )]+ [(A.B + A.B )] = [A .(B + B )] + [(A + A ). B ]

0 OR gate + NOR gate X-OR gate

1 AND gate . NAND gate X-NOR gate

(+) De-morgans 1st theorem Product term(.) SOP equations

(.) Demorgans 2nd theorem Sum term (+) POS equations

NOR gate L.H.S

Bubbled input AND gate R.H.S

Que estionBan nk:DCFM MIIISem CSE

NAND gate L.H.S

Bu ubbled input OR gate R.H H.S

purInstituteo ofTechnolog gy,Nagpur Nagp

Que estionBan nk:DCFM MIIISem CSE

purInstituteo ofTechnolog gy,Nagpur Nagp

Que estionBan nk:DCFM MIIISem CSE

Logi Ckt: ical

purInstituteo ofTechnolog gy,Nagpur Nagp

Que estionBan nk:DCFM MIIISem CSE

OUTPUT BI O INARY NUM MBER B2

B0 = ABC + ABC + AB + ABC BC

purInstituteo ofTechnolog gy,Nagpur Nagp

Que estionBan nk:DCFM MIIISem CSE

Logi Ckt: ical

purInstituteo ofTechnolog gy,Nagpur Nagp

Design k-map for Y1:

Design k-map for Y0:

Que estionBan nk:DCFM MIIISem CSE

Logi Ckt: ical

0 X(DONT CARE) C m10 TO m15=X

purInstituteo ofTechnolog gy,Nagpur Nagp

Design k-map for Y2:

Design k-map for Y1:

Design k-map for Y0:

Que estionBan nk:DCFM MIIISem CSE

Logi Ckt: ical

0,1,5,9,12 )+ d(3,7,11,1 + 15) m(0

purInstituteo ofTechnolog gy,Nagpur Nagp

Que estionBan nk:DCFM MIIISem CSE

Logi Ckt: ical

ND m(1,,2,7,9,15 ) + d(0,8,12) design NAN ckt.

purInstituteo ofTechnolog gy,Nagpur Nagp

Que estionBan nk:DCFM MIIISem CSE

Logi Ckt: ical

purInstituteo ofTechnolog gy,Nagpur Nagp

Design k-map for Y2:

Design k-map for Y1:

Design k-map for Y3:

Que estionBan nk:DCFM MIIISem CSE

Digital Circuits & Fundamentals of Microprocessor

Digital Circuits & Fundamentals of Microprocessor