BI TP

Mch cng ni tip

Mch cng 1/2

Mch cng y (Full adder)

CA HOC (OR)

MCH CNG NI TIP

FLIP FLOP
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity flop is Port ( reset,din,clk : in STD_LOGIC; qout : out STD_LOGIC:='0'); end flop; architecture Behavioral of flop is begin process (clk) begin if (clk='1' and clk'EVENT) then if reset ='1' then qout <='0' after 8 ns; else qout <=din after 8 ns; end if; end if; end process; end Behavioral;

entity counter is Port ( reset,clk : in STD_LOGIC; counting : out STD_LOGIC:='1'); end counter; architecture Behavioral of counter is begin process (clk) variable count: INTEGER:=4; begin if (clk='1' and clk'EVENT) then if reset ='1' then count:=0; else if count < 4 then count:= count+1; end if; end if; if count = 4 then counting <= '0' after 8 ns; count:=0; else counting <='1' after 8 ns; end if; end if; end process; end Behavioral;

MCH M (COUNTER)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity der_flop is Port ( din,reset,enable,clk : in STD_LOGIC; qout : out STD_LOGIC:='0'); end der_flop; architecture Behavioral of der_flop is begin process (clk) begin if (clk='1' and clk'EVENT) then if reset='1' then qout <='0' after 8 ns; else if enable = '1' then qout <= din after 8 ns; end if; end if; end if; end process; end Behavioral;

THANH GHI DCH (SHIFT REGISTER)

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity shifter is Port ( sin,reset,enable,clk : in STD_LOGIC; parout : inout STD_LOGIC_VECTOR (3 downto 0)); end shifter; architecture Behavioral of shifter is component der_flop is port (din,reset,enable,clk: in STD_LOGIC; qout: out STD_LOGIC); end component; begin b3: der_flop port map (sin,reset,enable,clk,parout(3)); b2: der_flop port map (parout(3),reset,enable,clk,parout(2)); b1: der_flop port map (parout(2),reset,enable,clk,parout(1)); b0: der_flop port map (parout(1),reset,enable,clk,parout(0)); end Behavioral;

MCH CNG NI TIP

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity serial_adder is Port ( a,b,start,clock : in STD_LOGIC; carry_out: inout STD_LOGIC; ready : out STD_LOGIC; result : inout STD_LOGIC_VECTOR (3 downto 0)); end serial_adder; architecture Behavioral of serial_adder is signal serial_sum,carry_in,counting: STD_LOGIC; component counter is port (reset,clk: in STD_LOGIC;counting: out STD_LOGIC); end component; component shifter is port (sin,reset,enable,clk: in STD_LOGIC;parout: inout STD_LOGIC_VECTOR (3 downto 0)); end component; component fulladder is port (a,b,cin: in STD_LOGIC;sum,cout: out STD_LOGIC); end component; component flop is port (reset,din,clk: in STD_LOGIC; qout:out STD_LOGIC); end component; begin u1: fulladder port map (a,b,carry_in,serial_sum,carry_out); u2: flop port map (start,carry_out,clock,carry_in); u3: counter port map (start, clock, counting); u4: shifter port map (serial_sum,start,counting,clock,result); u5: ready <= not counting; end Behavioral;