Ic Lab Manaul

MCET, DEPT OF ECE IC LAB MANUAL
EXPERIMENT NO: 1
1.1. NON LINEAR WAVE SHAPING CLIPPER CIRCUITS

AIM: To study the diode clipper circuit using ordinary and Zener Diodes.
APPARATUS REQUIRED:
1. Bread Board trainer - 1 no’s
2. CRO - 1 no’s
3. Function Generator. - 1 no’s
COMPONENTS
1. Capacitor- 0.1μf -1 no’s
2. IN 4007 diode-1No. -1 no’s
CIRCUIT DIAGRAM:
THEORY:
Clipping circuits are commonly realized with diodes and resistor and do
not contain any energy storing components. The function performed by the clipping
circuits essentially either limiting or slicing. These circuits also employ devices such as
diodes, Zener diodes, and transistors along with resistors. Amplitude selectors and
Amplitude limiters are the other names of the clipping circuits
B.E 3rd I SEM, ECE 1

PROCEDURE:
1. Connect the circuits as per the circuit diagram

2. Connect the CRO Ch-I to input and Ch-2II to output of the circuit.
3. Adjust the input sine wave amplitude to 5V P-P.
4. Connect the D.C.battery wherever necessary.
5. Observe the wave form in the CRO channel II and not the waveform.
EXPECTED WAVEFORM:
RESULT:
Diode clipper circuit using ordinary and Zener Diode are studied and observed the
waveforms.

1.2. NON LINEAR WAVE SHAPING CLAMPER

AIM: To study the Clamper circuits.
APPARATUS REQUIRED:
1. Bread Board trainer - 1 no’s
2. CRO - 1 no’s
3. Function Generator. - 1 no’s
COMPONENTS
1. Resistor- 1KΩ -1 no’s
2. IN 4007 diode-1No. -1 no’s
3. BZX6V2 diode - 2 no’s.
CIRCUIT DIAGRAM:
NEGATIVE CLAMPER POSITIVE CLAMPER
BIASED NEGATIVE CLAMPER BIASED POSITIVE CLAMPER
BIASED POSITIVE CLAMPER BIASED NEGATIVE CLAMPER

THEORY:
Clamping circuits do not make any effort to change the wave shape of any signal.
Their main concern is to introduce a dc shift into a waveform by altering its dc
component. In RC coupling and capacitive coupling, the blocking capacitor does not
allow the dc component of the applied signal to pass through it. Since all the sinusoidal
components pass through the blocking capacitor, the wave shape of the signal remains the
same after transmission while its dc level is brought down to zero. Clamping circuits are
essentially used to restore this lost dc component.
PROCEDURE:
1. Connect the circuits as per the circuit diagram

2. Connect the CRO Ch-I to input and Ch-2II to output of the circuit.
3. Adjust the input sine wave amplitude to 5V P-P.
4. For Zener diode clipper, increase the amplitude of the input Wave form to 15V P-P
5. Observe the wave form in the CRO, with and without connecting the D.C.battery (i.e.
biasing) and note the wave form from Ch-II of CRO.
EXPECTED WAVEFORM:
INPUT:

OUTPUT WAVEFORMS:
RESULT:

EXPERIMENT NO: 2
OP-AMP
2.1. VOLTAGE FOLLOWER
AIM: 1.To study the operation of AC voltage follower (AF = 1).
2. To study the operation of DC voltage follower.
APPARATUS REQUIRED:
1. Breadboard.
2. 1MHz function generator.
3. 20MHz Oscilloscope.
4. Digital Multimeter .
5. Connecting wires & Power supply.
COMPONENTS:
1. IC 741 – 1No.
2. 0.01μf Capacitor –1 No.
3. 100kΩ Resistors -1 No.
4. 10kΩ Resistor - 1No.
CIRCUIT DIAGRAM:
Fig (1)
THEORY:
The lowest gain can be obtained from a non-inverting amplifier with

feedback is 1. When the non-inverting amplifier is configured for unity gain, it is called
as Voltage follower because the output voltage is equal to and in phase with the input

voltage. The voltage follower is also called a non-inverting buffer amplifier because,
when placed between two networks, it removes the loading on the first network.
PROCEDURE:
1. Connect the circuit of voltage follower as shown in fig (1) on the breadboard.
2. Switch on the power supply and apply the voltage ±15V to the circuit.
3. Apply the input signal of 1 KHz through the function generator.
4. Measure the output voltage of the voltage follower by connecting the C.R.O at Output
terminals.
5. Calculate the gain of the voltage follower.
6. Repeat the above steps for different input voltages.
WAVEFORMS:
RESULT:

2.2. INVERTING AND NON- INVERTING AMPLIFIER
AIM: To find the voltage gain of Inverting and Non- Inverting amplifier Using IC 741
OP-AMP.
APPARATUS REQUIRED:
1. Bread board trainer.
2. 1MHz Function generator.
3. 20MHz C R O.
4. Digital multimeter.
5. Connecting wires.
Components required:
1. 741IC - 1No
2. 1KΩ resistor -1No
3. 10KΩ resistor - 1No
4. 100KΩ resistor- 1No
CIRCUIT DIAGRAM:
INVERTING AMPLIFIER:
Fig (1)

NON-INVERTING AMPLIFIER:
Fig (2)
THEORY:
When the input signal to an op-amp is supplied to the inverting input with non-
inverting input at ground, the amplifier operates in the inverting mode that is the output
differs in phase by 180 degrees with respect to the input. In an inverting amplifier the
gain is given by the relation A = -R1 /RF . Where RF and R1 are the feedback and input
resistor respectively. When operated in the non-inverting mode, the input signal is
applied to the non-inverting input with the inverting terminal grounded through a resistor.
The gain in this case is given by the relation A = 1+1 R/RF
PROCEDURE:
1. Connect the circuit as shown in fig (1)

2. Switch ‘ON’ the power supply and apply ± 15V to the circuit.
3. Apply input signal from the function generator of 1 KHz to the reference input
terminals. (Apply the sine wave in mill volts. Take care not to saturate the amplifier due
to excessive input voltage. It is preferred to keep the input below1 V).
4. Connect the 20MHz C.R.O at the output terminals.
5. Observe and record the output voltage waveforms.
6. Calculate the Vo of the inverting Amplifier as Vo = - R1/ RF ∗ Vin and find its gain.
7. Connect the circuit as shown in fig (2).
8. Apply an input sine wave of 1V p-p at 1 KHz from the function generator.
9. Connect the CRO at output terminals.

10. Observe and record the output voltage waveforms

11. Calculate the Vo of the Non-inverting amplifier as Vo = 1 + R1/RF ∗ Vin and find its
gain
12. Verify the results with theoretical values.
13. Repeat the above steps for input voltages.
WAVEFORMS:
INVERTING AMPLIFIER
NON-INVERTING AMPLIFIER
RESULT:

EXPERIMENT NO: 3
OP- AMP ARITHMETIC CIRCUITS
3.1. ADDER AND SUBTRACTOR
AIM: To design the adder and subtractor using IC 741 Op-amp.
APPARATUS REQUIRED:
1. Breadboard trainer.
COMPONENTS REQUIRED:
1. IC 741 – 1No.
2. 100kΩ Resistors -1 No.
CIRCUIT DIAGRAM:
Adder:
Subtractor:

PROCEDURE:
1. Connect the Adder circuit as shown in figure (1) and switch ON the trainer.
2. Apply the input voltages from the regulated supplies to the corresponding inputs.
3. Connect the voltmeter at the Out put terminals, and note down the values and verify
with theoretical values.
5. Now connect the subtractor circuit as shown in figure (2).
6. Repeat steps 2&3 and record the values.
CALCULATIONS:
RESULT: Adder and Subtractor are designed using 741 Op – Amp and verified practical
values with theoretical values.

3.2. INTEGRATOR AND DIFFERENTIATOR

AIM: To analyze and design the differentiator & integrator using op-amp IC 741.
APPARATUS REQUIRED:
1. Breadboard trainer.
5. Connecting wires & Power supply.
COMPONENTS REQUIRED:
1. IC 741 – 1No.
2. 0.047μf Capacitor –1 No.
3. 100KΩ, 1.5 KΩ , 100 Ω, –1 No.
4. 1.5 kΩ, Resistors -1 No.
CIRCUIT DIAGRAM:
INTEGRATOR:

DIFFERENTIATOR:
THEORY:
THE INTEGRATOR
A circuit in which the output voltage waveform is the integration of the input is
called integrator.
1. When we apply a sine wave the frequency response is as shown in Fig (1.a). The
equation (1) indicates that the output voltage is directly proportional to the negative
integral of the input voltage and inversely proportional to the time constant R1 CF . For
Example if the input is a sine wave output will be a cosine wave or if the input is a square
wave, the output will be a triangular wave.
2. When Vin = 0 the integrator works as an open – loop amplifier. This is because of the
capacitor CF acts as an open circuit (XCF = infinite) to the input offset voltage Vin. In
other words, the input offset voltage Vin and the part of the input current charging
capacitor CF produce the error voltage at the output of the integrator. To overcome this
problem RF is connected across the feed back capacitor CF . Thus RF limits the low-
frequency gain and hence minimizes the variations in the output voltage.
3. Frequency response (fb) of integrator at 0 dB is given by fb =1/2ΠR1CF .
4. Both the stability and the low – frequency roll-off problems can be corrected by the
addition of a resistors RF as shown in fig (2.a). The frequency response of practical
integrator is as shown in fig (2.c). by a dashed line . In this ‘f’ is relative operating
frequency and for ‘f’ and f3 the gain RF/R1 is constant.
However after fa the gain decreases at a rate of 20dB/decade. In other words, between fa
and fb the circuit acts as in integrator.
5. The input signal will be integrated properly if the time period T of the input signal as
larger than or equal to RF CF
THE DIFFERENTIATOR:
The differentiator circuit performs the mathematical operation of differentiation.
That is the output waveform is the derivative of the input waveform.
1. If a sine wave is applied to the input of the differentiator then the output is cosine
waveform.
2. The reactance of the circuit (RF/XC1) increase with increase in frequency at a rate of
20dB decade. This makes the circuit unstable
3. The input impedance XC1 decreases with increase in frequency, which makes the
circuit very susceptible to high frequency noise.
4. The frequency response of the basic differentiator is shown in figure.1.C. In this fig fa
is the frequency at which the gain is 0 dB .
5. Both the stability and the high – frequency noise problem can be corrected by the
addition of two components R1 and CF as shown in fig 2.a .The frequency response of
which is shown in fig 1.c by dashed line from f to fa the gain decrease at 20dB/decade.
This 40 dB/decade change in gain is caused by the R1 C1 and RF CF combinations.
The gain limiting frequency fb is given by
Where R1 C1 = RF CF.
R1 C1 and RF CF help to reduce significantly the effect of high – frequency input,
amplifier noise, and offsets.
Above all, it makes the circuit more stable by preventing the increase in gain with
frequency. General, the value of f1, and in turn R1 C1 and RF CF should be selected that
fa = fb = fc unit gain – bandwidth.
6. The input signal will be differentiated properly if the time period T of the input signal
is larger than or equal to RF C1.
PROCEDURE:
INTEGRATOR
1. Connect the integrator circuit as shown in fig 1.a.
2. Connect the 1MHz function generator to the terminals. Apply the input waveform.
4. Switch ON the trainer and see that the supply LED glows.

5. Observe and note down the output frequency and waveforms. (Sample output
waveforms are as shown in figures).
6. Fig (1.b) shows the frequency response of sine wave input.
7. Repeat the above procedure 1 – 5 to get the different waveforms, by varying the input
frequency.
8. Apply the square wave, and repeat the above steps and observe & record the waveform
(Ideal waveform are as shown in fig (1.b).
PROCEDURE:
DIFFERENTIATOR
1. Connect the differentiator as shown in fig 2.a
2. Connect the 1MHz function generators to the input terminals; apply sine wave at the
input terminals.
4. Switch ON the trainer and see that the supply LED glows.
5. Observe and record the output frequency of waveforms (Ideal output waveforms are as
shown in fig 2.b
6. Repeat the above steps from 1 to 5 and observe different output waveforms, by varying
the input frequency.
7. Apply the square wave, and repeat the above steps and observe & record the
waveform. (Ideal waveforms) are as shown in Fig (1.c). The frequency response graph of
basic differentiator circuit is also shown in the fig.
WAVEFORMS:

EXPECTED WAVEFORM:

RESULT:

EXPERIMENT NO: 4
OP-AMP ACTIVE FILTERS
4.1. HIGH PASS FILTER
AIM: To perform the operation of High pass filter and to observe the
frequency response.
APPARATUS REQUIRED:
1. Op amp 741 IC 1
2. Resistors R =10 KΩ 4
3. Capacitance C = 0.02μF 1
4. Function Generator 1
5. Bread Board Trainer 1
6. CRO 1
7. Connecting accessories Required
CIRCUIT DIAGRAM:
Fig: High Pass filter

THEORY:
High pass filters are often formed simply by interchanging
frequency determining resistors and capacitors in low pass filter. The
band of frequencies that are above the “fl” comes under “pass band”
and frequencies below “fl” comes under “stop band”. The cut-off

frequency “fl” is the frequency at which the magnitude of the gain is

0.707 times its pass band value.

WAVE FORMS:
Fig: Frequency Response of High Pass Filter
PROCEDURE:
1. Connect the circuit as shown in the circuit diagram.
2. Apply +Vcc =+15V and –Vee = – 15V to Pin 7 and 4 of μA741 IC.
3. Apply the input voltage Vin of 1Vp-p at 1Khz.
4. Observe the output at pin 6th of μA 741 IC on CRO.
5. Vary the i/p frequency and note down corresponding o/p voltages.
Calculate the gain in decibels.
6. Draw the frequency response curve on semi log sheet and calculate
the bandwidth.
OBSERVATIONS:
THEORITICAL CALCULATIONS:
Cut off frequency, fH = 1/(2RC)
RESULT:

The frequency response of High pass filter is observed and bandwidth

is calculated.

4.2. LOW PASS FILTER

AIM: To perform the operation of a Low pass filter and to observe the
frequency response.
APPARATUS REQUIRED:
1. Op amp 741 IC 1
2. Resistance R1 -10 KΩ 3
3.3 KΩ 1
4. Bread Board trainer 1
5. CRO 1
6. Function Generator 1
CIRCUIT DIAGRAM:
Fig: Low Pass Filter
THEORY:
A low pass filter is a filter that passes all low frequencies and
attenuates all high frequencies. From the graph the range of
frequencies that are passed up to “fh” comes under “pass band” and
the frequencies which are greater than “fh” comes under “stop band”.
The Op- Amp is used in the non inverting configuration; hence it does
not load down the RC network. The frequency “fh” is called cut-off
frequency because the gain of the filter at this frequency is 0.707
times to its pass band value.

WAVE FORMS:
Fig: Frequency response of a low pass filter.
PROCEDURE:
1. Connect the circuit as shown in circuit diagram.
2. Apply +Vcc =+15V and –Vee = – 15V to Pin 7 and 4 of μA741IC
3. Apply the input voltage Vin of 1V p-p at 1Khz frequency.
4. Observe the output waveform at 6th pin of μA 741 IC on CRO.
5. Vary the input frequency and note down the corresponding output
voltages.
6. Calculate the gain in decibels.
7. Draw the frequency response curve on semi log sheet and calculate
the bandwidth.
OBSERVATIONS:
THEORITICAL CALCULATIONS:
Cut off frequency, fH = 1/(2RC)

RESULT: The frequency response of low pass filter is studied and

bandwidth is calculated.
EXPERIMENT NO: 5
OPAMP OSCILLATORS
5.1. RC PHASE SHIFT OSCILLATOR
AIM: To Design a RC Phase Shift Oscillator using IC 741 Op-Amp.
APPARATUS REQUIRED:
1. CRO (Dual channel)
2. Bread Board trainer.
COMPONENTS:
1. Resistor 3.3 kΩ, 6.8 kΩ, 10k Ω – 1 No.
2. 33kΩ Resistor – 2 No.
3. 1MΩ Variable Resistor – 1 No.
4. 0.1 μF , 0.01 μF, 0.001 μF Capacitor – 1 No.
5. Operational Amplifier IC 741 – 1 No.
CIRCUIT DIAGRAM:
THEORY:
The Phase Shift Oscillator consist of an operational amplifier as the amplifying

stage and three RC cascaded networks as the feed back circuits the amplifier will
provide 180 degrees phase shift. The feed back network will provide another phase
shift of 180 degrees

PROCEDURE:
1. Connect the R1 C1 networks in the feedback circuit at TP1 & TP2 respectively as
shown in figure.
2. From the given values of R1 & C1 calculate theoretical frequency (f0 =
0.065/RC) and note down in the tabular column.
3. Connect Oscilloscope at output terminals V0 observe the output sine wave and
note down the practical frequency f0. Adjust gain and shape of the sine wave by
using potentiometer Rf..
4. Compare the theoretical and practical frequencies.
5. Repeat above steps 1 to 4 for R2 C2 and R3 C3 networks and compare the
theoretical and practical frequency.
OBSERVATIONS:
S.NO C R Theoretical Fo Practical Fo

1. C1= 0.1 μF R1=3.3 kΩ
2. C2=0.01 μF R2=6.8 kΩ
3. C3=0.001 μF R3=10k Ω
CALCULATIONS:
i. The frequency of oscillation fo is given by

1 0.065
fo= =
2π 6 RC RC
ii. The gain Av at the above frequency must be at least 29

RF
i.e. = 29
R1
GRAPH:
RESULT:
The frequency of oscillation of the RC phase shift oscillator = --------Hz

5.2. WEIN BRIDGE OSCILLATOR

AIM: To Design Wein Bridge Oscillator so that the output frequency is 965 Hz.
APPARATUS REQUIRED:
1. CRO (Dual channel) - 1 No
2. Bread Board trainer – 1 No
COMPONENTS:
3. 3.3kΩ Resistor – 1 No.
4. 0.05µ F Capacitor – 1 No.
5. Operational Amplifier – 1 No.
CIRCUIT DIAGRAM:
THEORY:
In this oscillator the Wein Bridge Circuit is connected between the

amplifier input terminals and the output terminal. The bridge has a series RC network
in one arm and parallel RC network in the adjoining arm. In the remaining two arms
of the bridge resistors R1 and RF are connected. The total phase-shift around the
circuit is 0o when the bridge is balanced.

PROCEDURE:
1. Construct the circuit as shown in the circuit diagram.
2. Adjust the potentiometer Rf such that an output wave form is obtained.
3. Calculate the output wave form frequency and peak to peak voltage.
4. Compare the theoretical and practical values of the output waveform frequency.
OBSERVATIONS:
The frequency of oscillation = ______
CALCULATIONS:
The frequency of oscillation fo is exactly the resonant frequency of the balanced Wein
Bridge and is given by fo = 1/ (2π RC) = 0.159 / RC
The gain required for sustained oscillations is given by Av= 3. i.e., Rf = 2R1
Let C = 0.05 µ F
Then fo = 1/ (2π RC)
 R = 1/ (2π foC)
 = 3.3 k Ω
Now let R1 = 12 kΩ , Rf= 2R1 = 24 kΩ , Rf = 50 kΩ potential meter.
GRAPH:
RESULT: The frequency of oscillation of the Wein Bridge oscillator =----------

EXPERIMENT NO: 7
FUNCTION GENERATOR
AIM: To generate Square wave and triangular waveforms using μA741 IC.
APPARATUS REQUIRED:
1. Op amp 741 IC 2
2. Resistors R -10 KΩ 3
-100KΩ 2
-15KΩ 1
-4.7KΩ 1
5. CRO 1
CIRCUIT DIAGRAM:
THEORY:
This is operated in astable mode. The op amp is operated in saturation region and
the output swings between ± Vsat. A Positive feedback of β = R2/R1+R2 is provided to the
non – inverting terminal. The output is fed back to the inverting terminal after integration
through a RC network. The frequency of oscillation of the output waveform is given by
fo=1/2RC.A triangular wave is obtained by integrating a square wave. The frequency of
oscillation is given by fo = R3/ (4R1C1R2) = 1/ (2П R3C2).

PROCEDURE:
2. Observe the output at 6th pin of 1st IC and it will be a square wave.
3. Calculate the output frequency of square wave and verify theoretical frequency.
4. Connect the output of the 1st IC to the Integrator.
5. Observe the output waveform at 6th pin of 2nd IC on CRO and determine the frequency
of triangular wave.
WAVE FORMS:
THEORETICAL CALCULATIONS:
For square wave

fo=1/2RC
For Triangular wave

fo=R3/(4R1C1R2)=1/(2ПR3C2)
RESULT:
The non-linear application of op–amp is studied and frequency of square and triangular
waveform is verified.

EXPERIMENT NO:8
IC 566- VCO APPLICATIONS
AIM: To perform Voltage controlled oscillator using IC 566.
APPARATUS REQUIRED:
1. IC 566 1
2. Resistors-1KΩ 1
-15KΩ 1
-470Ω 1
3. Capacitors-0.01μF 1
-0.001 μF 1
4. Function generator 1
5. Bread Board 1
6. CRO 1
7. Dual Regulated Power supply 1
CIRCUIT DIAGRAM:
THEORY:
In frequency modulation, tone generators and frequency shift

keying, the frequency needs to be controlled by means of an input
voltage called control voltage. This function is achieved in the voltage
controlled oscillator (VCO) and called a voltage to frequency converter.

It provides simultaneous square wave and triangular wave outputs as a
function of input voltage. The frequency of oscillation is determined by
an external resistor RT and CT, and the voltage VC applied to the control
terminal 5. The voltage VC can be varied by connecting a R1and R2
circuit as shown. The components RT and CT are first selected so that
VCO output frequency lies in the centre of operating frequency range.
PROCEDURE:
1. Connect the circuit as per the circuit diagram.
2. Apply the modulating signal (sinusoidal) of 5v p-p at 1KHZ using the
function generator to the 5th pin of IC 566.
3. Observe the output waveforms at pin4 and pin3 of IC 566
individually.
4. Vary the amplitude of the modulating signal and note down the
corresponding changes in the frequencies of the output signals.
THEORETICAL CALCULATION:
Frequency, fo=1/(4 RT CT)
WAVE FORMS:
RESULT:
Voltage controlled oscillator is constructed and operation is verified
using IC 566.

EXPERIMENT NO: 09
PHASE LOCKED LOOP AND APPLICATIONS USING LM 565.
AIM:
1. To study the operation of NE565 PLL
2. To use NE565 as a multiplier
APPARATUS REQUIRED:
1. CRO - 1 No.
2. Bread Board trainer - 1 No.
3. Function Generator - 1 No.
COMPONENTS:
1. 6.8 kΩ Resistor – 1 No.
2. µ F Capacitor – 1 No
3. µ F Capacitor – 2 Nos
4. IC565 - 1 No.
CIRCUIT DIAGRAM:
THEORY:
The 565 is available as a 14-pin DIP package. It is produced by Signatic
Corporation. The output frequency of the VCO can be rewritten as
0.25
fo = Hz
RT CT
Where RT and CT are the external resistor and capacitor connected to pin 8 and pin 9. A
value between 2 kΩ and 20 kΩ is recommended for RT. The VCO free running
frequency is adjusted with RT and CT to be at the centre fo the input frequency range.

PROCEDURE:
1. Connect the circuit using the component values as shown in the figure
2 .Measure the free running frequency of VCO at pin 4 with the input signal Vin set =
zero. Compare it with the calculated value = 0.25/ RTCT
3. Now apply the input signal of 1Vpp square wave at a 1kHz to pin 2
4. Connect 1 channel of the scope to pin 2 and display this signal on the scope
5 .Gradually increase the input frequency till the PLL is locked to the input
frequency. This frequency f1gives the lower ends of the capture range. Go on increase
the input frequency, till PLL tracks the input signal, say to a frequency f2. This
frequency f2 gives the upper end of the lock range. If the input frequency is increased
further the loop will get unlocked.
6. Now gradually decrease the input frequency till the PLL is again locked. This is
the frequency f3, the upper end of the capture range. Keep on decreasing the input
frequency until the loop is unlocked. This frequency f4 gives the lower end of the lock
range
± 7.8 fo
7 .The lock range ∆ fL = (f2 – f4) compare it with the calculated value of
12
Also the capture range is ∆ fc = (f3 – f1). Compare it with the calculated value of
capture range.
1/ 2
 ∆f L 
∆f c = ± 
 ( 2π )( 3.6)(10 ) xC ) 
3
8. To use PLL as a multiplie5r, make connections as shown in fig. The circuit uses a
4-bit binary counter 7490 used as a divide-by-5 circuit.
9. Set the input signal at 1Vpp square wave at 500Hz
10. Vary the VCO frequency by adjusting the 20KΩ potentiometer till the PLL is
locked. Measure the output frequency
11. Repeat step 9 and 10 for input frequency of 1 kHz and 1.5 kHz.

OBSERVATIONS:
fo = __________
fL = __________
fC = __________
CALCULATIONS:
± 7.8 fo
∆ fL = (f2 – f4) =
12
1/ 2
 ∆f L 
∆ fc = (f3 – f1) = = ±  
 (2π )(3.6)(10 ) xC ) 
3
GRAPH:
RESULT:
fo = __________ fL = __________ fC = __________

EXPERIMENT NO:10
VOLTAGE REGULATOR
AIM: To observe the operation of Voltage regulator using IC723.
APPARATUS REQUIRED:
1. IC 723 1
2. Resistors-1KΩ 2
-680Ω 1
-2.2KΩ 1
-33Ω 1
Potentiometer-10kΩ 1
3. Capacitor- 100pf 1
4. Function generator 1
5. Bread Board 1
6. CRO 1
7. Dual Regulated Power supply 1
CIRCUIT DIAGRAM:

THEORY:
A voltage regulator is a circuit that supplies constant voltage
regardless of changes in load current and changes in the input voltage.
It also has short circuit operation. These can be adjusted over a wide
range of both positive and negative regulated voltage. This IC is
inherently a low current device. But, can be boosted to provide 5amps
to more current by connecting external components. The limitation of
723 is that it has no inbuilt protection.
PROCEDURE:
1. Connect the circuit as shown in figure.
2. Connect a variable DC voltage source at the input of circuit.
3. Feed a Dc voltage of 10V at the input of the circuit, set the output
voltage of regulator at +5V, by varying the potentiometer position.
4. Now change the input voltage by 2V at either side of +10v (ie, 8V to
12V) measure the output voltage. Tabulate results and draw
conclusions.
5. Interchange the input terminals for negative voltage regulation and
repeat steps 3 to 5 of this case.
OBSERVATIONS:
RESULT:
A Voltage regulator is constructed using IC 723.


EXPERIMENT NO: D1
BCD TO EXCESS 3 AND EXCESS 3 TO BCD
AIM: To verify BCD to excess –3 code conversion using NAND gates. To study and
verify the truth table of excess-3 to BCD code converter.
APPARATUS:
2. IC 7400, IC 7410, etc.
CIRCUIT DIAGRAM:

EXCESS-3 TO BCD CODE:
PROCEDURE: (BCD Excess 3 and Vice Versa)

1. Make the connections as shown in the fig.
2. Pin [14] of all IC’S are connected to +5V and pin [7] to the ground.
3. The inputs are applied at E3, E2, E1, and E0 and the corresponding outputs at B3,
B2, B1, and B0 are taken for excess – 3 to BCD.
4. B3, B2, B1, and B0 are the inputs and the corresponding outputs are E3, E2, E1
and E0 for BCD to excess – 3.
5. Repeat the same procedure for other combinations of inputs.
6. Truth table is written.
TRUTH TABLE FOR CODE CONVERSION:

EXPERIMENT NO: D2
FLIP FLOP CONVERSIONS USING IC’S
AIM: Truth table verification of Flip-Flops: (i) JK Master Slave (ii) D- Type (iii) T- Type.
And realize T-Flip-flop, D-Flip-flop using JK flip-flop.
APPARATUS:
1. Bread board trainer kit.

2. IC 7476, IC 7400, IC 410 etc.
3. Digital multimeter.
CURCUIT DIAGRAMS:


PROCEDURE:
1. Connections are made as per circuit diagram.
2. The truth table is verified for various combinations of inputs.
FLIP FLOP CONVERSIONS:

LOGIC DIAGRAMS:
J-K FLIP-FLOP TRUTH TABLE
J K Q(t+1)
0 0 Q(t)
0 1 0
1 0 1
1 1 Q(t)’
T-FLIP-FLOP TRUTH TABLE
T Q(t+1)
0 Q(t)
1 Q(t)’
D-FLIP-FLOP TRUTH TABLE
D input Q(t+1)
0 0
1 1
PROCEDURE:
1. Connect the circuit as shown in the figure above.

2. Verify the truth table.
RESULT:
The truth tables are verified and the results are:

EXPERIMENT NO: D3
DESIGNING OF COUNTER AND MOD-N COUNTER
AIM: Realization of 3-bit counters as a sequential circuit and Mod-N counter design
(7476, 7490, 74192, 74193).
APPARATUS:
4. IC 7408, IC 7476, IC 7490, IC 74192, IC 74193, IC 7400, IC 7416, IC 7432 etc.
PROCEDURE:
1. Connections are made as per circuit diagram.
2. Clock pulses are applied one by one at the clock I/P and the O/P is observed at
QA, QB & QC for IC 7476.
3. Truth table is verified.
PROCEDURE (IC 74192, IC 74193):

1. Connections are made as per the circuit diagram except the connection from
output of NAND Gate to the load input.
2. The data (0011) = 3 is made available at the data i/ps A, B, C & D respectively.
3. The load pin made low so that the data 0011 appears at QD, QC, QB & QA
respectively.
4. Now connect the output of the NAND gate to the load input.
5. Clock pulses are applied to “count up” pin and the truth table is verified.
6. Now apply (1100) = 12 for 12 to 5 counter and remaining is same as for 3 to 8
counter
7. The pin diagram of IC 74192 is same as that of 74193. 74192 can be configured
to count between 0 and 9 in either direction. The starting value can be any number
between 0 and 9.
PIN DIAGRAM DETIALS OF IC 7476:






FUNCTION TABLE FOR 7490:
RESULT:

EXPERIMENT NO: D3
SHIFT REGISTER AND RIG COUNTER USING STANDARD IC’S
AIM: To construct and verify the operation of Shift register and Ring counter.
APPARATUS REQUIRED:
1. Bread board trainer kit.
2. IC 7476 - 3 no’s.
3. DMM - 1 no’s.
LOGIC DIAGRAM:
TRUTH TABLE:
IN Q1 Q2 Q3 Q4
1 1 0 0 0
0 0 1 0 0
0 0 0 1 0
1 1 0 0 1
1 1 1 0 0 PROCEDURE:
1 1 1 1 0 1. Connect the circuit as shown in the
1 1 1 1 1 figure using JK flip-flop IC’s on the
trainer kit.
2. And give the clock to the JK-flip flop at 1HZ and clear to the all flip-flops
3. While giving the input to the flip-flop it will shift to right.
4. Observe the out puts at Q0, Q1, Q2, and Q3.

RING COUNTER:
TRUTH TABLE
INPUT Q2 Q1 Q0
0 0 0 0
1 0 0 0
1 0 1 0
1 0 0 1
1 1 0 0
1 0 0 0
1 1 0 0
PROCEDURE:
1. Connect the circuit as shown in the figures in the flip flops trainer kit.
2. Apply the clock pulse to the circuit To, T1…….. Like that.
3. And observe the out put at Qo, Q1, and Q2.
RESULT:
Truth tables of counters verified.

EXPERIMENT NO: D4
HALF/FULL ADDER & HALF/FULL SUBTRACTOR
AIM: To realize half/full adder and half/full subtractor basic gates.
APPARATUS:
6. IC 7486, IC 7432, IC 7408, IC 7400, etc.
CIRCUIT DIAGRAM:
HALF ADDER USING ONLY NAND GATES:

FULL ADDER USING ONLY NAND GATES:
TRUTH TABLE:
HALF SUBTRACTOR:

HALF SUBTRACTOR USING NAND GATES:
FULL SUBTRACTOR USING NAND GATES:

TRUTH TABLES:
PROCEDURE:
1. Verify the gates.

2. Make the connections as per the circuit diagram.
3. Switch on VCC and apply various combinations of input according to truth table.
4. Note down the output readings for half/full adder and half/full subtractor
sum/difference and the carry/borrow bit for different combinations of inputs.
RESULT:

EXPERIMENT: D5
MUX/DEMUX USING 74153 & 74139
AIM: -To verify the truth table of multiplexer using 74153 & to verify a demultiplexer
using 74139. To study the arithmetic circuits half-adder half Subtractor, full adder and
full Subtractor using multiplexer.
APPARATUS:
8. IC 74153, IC 74139, IC 7404, etc..
PIN DETAILS OF IC 74153:
TRUTH TABLE:

PROCEDURE: (IC 74153)
1. The Pin [16] is connected to + Vcc.

2. Pin [8] is connected to ground.
3. The inputs are applied either to ‘A’ input or ‘B’ input.
4. If MUX ‘A’ has to be initialized, Ea is made low and if MUX ‘B’ has to be
initialized, Eb is made low.
5. Based on the selection lines one of the inputs will be selected at the output and
thus the truth table is verified.
6. In case of half adder using MUX, sum and carry is obtained by applying a
constant inputs at I0a, I1a, I 2a, I 3a and I 0b, I 1b, I 2b and I3b and the
corresponding values of select lines are changed as per table and the output is
taken at Z0a as sum and Z0b as carry.
7. In this case, the channels A and B are kept at constant inputs according to the
table and the inputs A and B are varied. Making Ea and Eb zero and the output is
taken at Za, and Zb.
8. In full adder using MUX, the input is applied at Cn-1, An and Bn. According to
the table corresponding outputs are taken at Cn and Dn.
CIRCUIT DIAGRAM:

PIN DETAILS OF IC 74139(DEMUX):

PROCEDURE :( IC 74139)
1. The inputs are applied to either ‘a’ input or ‘b’ input
2. The demux is activated by making Ea low and Eb low.
3. The truth table is verified.

RESULT:

EXPERIMENT NO: D6
DIGITAL TO ANALOG CONVERTER
AIM: To perform the operation of a 4 bit Digital to analog converter(R –

2R) circuit using Op-Amp.
APPARATUS REQUIRED:
1. IC 741 1
2. Resistors -10KΩ 4
-20KΩ 6
3. R.P.S. ±12 V 1
4. Digital multimeter 1
5. Bread Board 1
CIRCUIT DIAGRAM:
THEORY:
Analog signal is smooth but continuous time varying signal. It is

not possible to study such changing signals. In order to study such
signals we require discrete samples of the signal at different instances
of time i.e., we require digitized signal. This discrete signal obtained by
sampling analog signal is to be converted into Digital signal for the
purpose of analysis. This digital signal is to be converted back into

analog signal after analysis of the signal. Thus we require ADC and
DAC to analyze signals.

PROCEDURE:
2. Apply the different 4 bit digital inputs to the input terminals ( b0 b1 b2
b3)
3. Measure the analog output at pin 6 using multimeter.
4. Calculate the theoretical analog voltage and compare with the
practically obtained value.
5. Repeat the procedure for all possible input combinations.
6. Tabulate the observations.
WAVE FORM AND TABULAR FORM:
TABULAR COLUMNS:

RESULT: 4 bit R–2R Digital to Analog converter circuit has been

studied and output analog voltages for all 16 Digital input
combinations are observed and tabulated.

EXPERIMENT NO: D7
TRANSFER CHARACTERISTIC OF TTL AND CMOS
AIM: To study TTL & CMOS transfer characteristics.
APPARATUS REQUIRED:
1. Dual Power supply
2. Breadboard
3. Multimeter.
COMPONENTS:
4. ICs 74LS00, 74HC00.
CIRCUIT DIAGRAM:
THEORY:
A group of compatible ICs with the same logic levels and supply voltages
for performing various logic functions have been fabricated using a specific ckt.
Configuration which is referred to as a logic family. TTL (Transistor-Transistor logic) is
one of the saturated bipolar logic families. CMOS (Complementary metal oxide
semiconductor) is a unipolar logic family. Various chars. of digital ICs are used to
compare their performances.
Current & Voltage parameters :-

High level i/p voltage VIH: — this is the min. i/p voltage at the o/p corresponding to
logic1.
Low level i/p voltage VIL: — This is the max. i/p voltage which is recognized by the gate
as logic0.

High level output voltage VOH: — This is the min. voltage available at the o/p
corresponding to logic1.
Low level o/p voltage VOL: — This is the max. Voltage available at the o/p corresponding
to logic0.
PROCEDURE:
1) Connect the ckt. as per ckt. dgm. for TTL IC.

2) Vary the i/p voltage in steps & notedown corresponding o/p voltage.
3) Plot graph of Vi Vs Vo.
4) Repeat same procedure for CMOS IC.
OBSERVATIONS:
Vi Vout
RESULT: Thus transfer characteristics of TTL & CMOS ICs are studied.

EXPERIMENT NO: D8
APPLICATIONS OF IC 555
D81. MONOSTABLE MULTIVIBRATOR IC 555 TIMER
AIM: To perform the operation of a monostable multivibrator using a

555 timer and to draw the output waveforms.
APPARATUS REQUIRED:
1. IC 555 TIMER 1
-10KΩ 1
3. Capacitance C -0.1uf 1
-0.01uf 2

5. CRO 1
CIRCUIT DIAGRAM:
THEORY:
A Monostable multivibrator, often called a one – shot
multivibrator, is a pulse generating circuit in which the duration of the
pulse is determined by the RC network connected externally to the 555
timer. In a stable or standby state, the output of the circuit is
approximately zero or at logic low level. When an external trigger
pulse is applied, the output is forced to go high. The time for which the
output remains high is determined by the external RC network
connected to the timer. At the end of the timing interval, the output
automatically reverts back to its logic low stable state. The output
stays low until the trigger pulse is again applied.
The time during which the output remains high is given by

Tp = 1.1 RA C seconds
Where RA is in ohms and C is in Farads.
Once triggered, the circuit output will remain in high state until the set
time Tp elapses. The output will not change its state even if the input
trigger is applied again during this time interval Tp. However, the
circuit can be reset during the timing cycle by applying a negative
pulse to the reset terminal. The output will then remain in the low state
until a trigger is again applied.
PROCEDURE:
2. Apply the square wave input of 4Vp-p at 1 Khz to the trigger pin of
555 timer.
3. Observe the output at 3 pin of 555 timers and it will be a rectangular
pulse.
4. Calculate the pulse width and verify it with the theoretical value
Tp=1.1RC. Output signal will be 2/3Vcc.
MODEL WAVEFORMS:
Fig: Monostable multivibrator.

THEORITICAL CALCULATION:
Tp= 1.1 RC =
RESULT: Monostable Multivibrator using 555 Timer is observed and

the waveforms are plotted.
D8.2. ASTABLE MULTIVIBRATOR
AIM: To perform the operation of an Astable Multivibrator and to
observe the output waveforms.
APPARATUS REQUIRED:
1. IC 555 TIMER 1
-100KΩ 1
3. Capacitance C = 0.1uf 1
-0.01uf 1
4. Regulated Power supply 1
5. Bread Board 1
6. CRO 1
CIRCUIT DIAGRAM:
THEORY:

It is also called as free running multivibrator. This circuit doesn't

require an external trigger to change the state of output hence the
name free-running. Fig shows the 555 timer connected as an astable
multivibrator. Initially when the output is high capacitor C starts
charging towards Vcc through RA and RB. However as soon as voltage
across the capacitor equals 2/3 Vcc comparator triggers the flip-flop and
the output switches low. Now capacitor C starts discharging through RB
and transistor Ql. When the voltage across C equals 1/3 Vcc,
comparator 2's output triggers the flip-flop and the output goes high
then the cycle repeats. The capacitor is periodically charged and
discharged below 2/3 Vcc and 1/3 Vcc respectively.
The time during which the capacitor charges from 1/3 Vcc to 2/3 Vcc is
equal to
Tc =0.69 (RA+RB) C
Where RA and RB are in Ohms and C is in farads.
Similarly the time during which the capacitor discharges from 2/3 Vcc to
113 Vcc equal to the time the output is low and given by td = 0.69(RB)
C.
Where RB is in Ohms and C is in farads. Thus the total period of the
output waveform is T = tc + td = 0.69(RA + 2RB) C
Frequency, f= 1/T = 1.45/(RA + 2RB)C

The duty cycle is used in conjunction with the astable multivibrator.
The duty cycle is the ratio of time tc during which the o/p is high to the
total time period T. It is generally expressed as a percentage. In
equation form % duty cycle = tc/T x100 = RA+RB/RA+2RB
PROCEDURE:
1. Connect the circuit as per the circuit diagram.
2. Observe the output at the 3rd pin of the 555 timer and it will be a
square wave.
3. Observe the output at 6th pin of 555 timer and measure the
amplitudes as shown in the
Model waveform and also measure the time period.
MODEL WAVEFORM:

Fig: Astable multivibrator

THEORETICAL CALCULATIONS & PRACTICAL CALCULATIONS:
Thigh = 0.69(RA+RB)C =
Tlow = 0.69RBC =
Time period, T= Thigh+ Tlow =
T = 0.69(RA+2RB)C =
Frequency 1/T =
RESULT:
The Astable multivibrator is constructed and the frequency is
calculated for the output waveform.

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MCET, DEPT OF ECE IC LAB MANUAL

1.1. NON LINEAR WAVE SHAPING CLIPPER CIRCUITS

B.E 3rd I SEM, ECE 1

1. Connect the circuits as per the circuit diagram

B.E 3rd I SEM, ECE 2

1.2. NON LINEAR WAVE SHAPING CLAMPER

NEGATIVE CLAMPER POSITIVE CLAMPER

BIASED NEGATIVE CLAMPER BIASED POSITIVE CLAMPER

BIASED POSITIVE CLAMPER BIASED NEGATIVE CLAMPER

B.E 3rd I SEM, ECE 3

1. Connect the circuits as per the circuit diagram

B.E 3rd I SEM, ECE 4

B.E 3rd I SEM, ECE 5

The lowest gain can be obtained from a non-inverting amplifier with

B.E 3rd I SEM, ECE 6

B.E 3rd I SEM, ECE 7

2.2. INVERTING AND NON- INVERTING AMPLIFIER

B.E 3rd I SEM, ECE 8

1. Connect the circuit as shown in fig (1)

B.E 3rd I SEM, ECE 9

10. Observe and record the output voltage waveforms

B.E 3rd I SEM, ECE 10

B.E 3rd I SEM, ECE 11

B.E 3rd I SEM, ECE 12

3.2. INTEGRATOR AND DIFFERENTIATOR

B.E 3rd I SEM, ECE 13

B.E 3rd I SEM, ECE 15

B.E 3rd I SEM, ECE 16

B.E 3rd I SEM, ECE 17

B.E 3rd I SEM, ECE 18

Fig: High Pass filter

B.E 3rd I SEM, ECE 19

frequency “fl” is the frequency at which the magnitude of the gain is

B.E 3rd I SEM, ECE 20

Fig: Frequency Response of High Pass Filter

B.E 3rd I SEM, ECE 21

The frequency response of High pass filter is observed and bandwidth

B.E 3rd I SEM, ECE 22

4.2. LOW PASS FILTER

Fig: Low Pass Filter

B.E 3rd I SEM, ECE 23

Fig: Frequency response of a low pass filter.

B.E 3rd I SEM, ECE 24

RESULT: The frequency response of low pass filter is studied and

The Phase Shift Oscillator consist of an operational amplifier as the amplifying

B.E 3rd I SEM, ECE 25

S.NO C R Theoretical Fo Practical Fo

i. The frequency of oscillation fo is given by

ii. The gain Av at the above frequency must be at least 29

B.E 3rd I SEM, ECE 26

5.2. WEIN BRIDGE OSCILLATOR

In this oscillator the Wein Bridge Circuit is connected between the

B.E 3rd I SEM, ECE 27

RESULT: The frequency of oscillation of the Wein Bridge oscillator =----------

B.E 3rd I SEM, ECE 28

B.E 3rd I SEM, ECE 29

For square wave

For Triangular wave

B.E 3rd I SEM, ECE 30

AIM: To perform Voltage controlled oscillator using IC 566.

In frequency modulation, tone generators and frequency shift

controlled oscillator (VCO) and called a voltage to frequency converter.

B.E 3rd I SEM, ECE 32