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(19) KOREAN INTELLECTUAL PROPERTY OFFICE

KOREAN PATENT ABSTRACTS

(11)Publication number: 1020020073959 A
(43)Date of publication of application:
28.09.2002

(21)Application number: 1020010013930 (71)Applicant: SAMSUNG ELECTRONICS

(22)Date of filing: 17.03.2001 CO., LTD.
(72)Inventor: CHOI, JEONG DAL
(30)Priority:
KWAK, HONG SEOK
LIM, YONG SIK
SHIN, YU CHEOL
(51)Int. Cl H01L 21/8247

(54) NON-
NON-VOLATILE MEMORY DEVICE HAVING STRUCTURE OF MONOS GATE AND METHOD FOR
FABRICATING THE SAME

(57) Abstract:

PURPOSE: A non-volatile memory device having a

structure of a MONOS gate and a method for fabricating

the same are provided to optimize each structure of a

selective transistor, a low voltage MOS transistor, a high

voltage MOS transistor. CONSTITUTION: An isolation

layer(3) is arranged on a predetermined region of a

semiconductor substrate(1). The first well(5), the second

well(7b), and a pocket well(7a) are arranged on the

semiconductor substrate(1). The pocket well(7a) is

surrounded by the first well(5). The second active region

of the peripheral circuit region(b) is surrounded by the

second well(7b). A conductive type dopant different from the semiconductor substrate(1) is doped on the first

well(5). The same conductive type dopant as the semiconductor substrate(1) is doped on the pocket well(7a)

and the second well(7b). Accordingly, the pocket well(7a) is electrically isolated from the semiconductor

substrate(1). A high voltage gate pattern(24h) is formed on a predetermined region of the third active region.

The high voltage gate pattern(24h) has a high voltage gate insulating layer(17) and a high voltage gate

electrode(23h). A sidewall of the high voltage gate pattern(24h) is covered by a gate spacer(26b). A high

voltage source/drain region(30h) is formed at both sides of the high voltage gate pattern(24h). A low voltage

gate pattern(24l) including a lower voltage gate insulating layer(21) and a low voltage gate electrode(23l) is

formed on a predetermined region of the second active region. A sidewall of the low voltage gate pattern(24l)

is covered by the gate spacer(26b). A low voltage source/drain region(281) is formed at both sides of the low

voltage gate pattern(24l). A cell gate pattern(24c) is formed on the first region of the first active region. The

cell gate pattern(24c) is formed with a cell gate electrode(23c) and a cell gate insulating layer(14) including a

tunnel oxide layer(9), a silicon nitride layer pattern(11), and an upper oxide layer pattern(13). A selective gate

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pattern(24s) including a selective gate insulating layer(21) and a selective gate electrode(23s) is formed on the

second region of the first active region. A low density source/drain region(25) is formed on the first active

region of the both sides of the selective gate pattern(24s) and the cell gate pattern(24c). A cell array region(a)

is covered by a spacer insulating layer pattern(26a). The semiconductor substrate(1) is covered by an

interlayer dielectric(31).

copyright KIPO 2003

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