8 7 6 5 4 3 2 1

SOLTEK COMPUTER INC. MODEL: 694X + 686A

VER:0.4
D

SL-65KV 1999/11/29 D

TITLE SHEET
COVER SHEET 1

SOCKET 370 PROCESSOR 2

NORTH BRIDGE (VT82C694A/X) 3,4

SOUTH BRIDGE (VT82C686A) 5,6

USB2,3 & FREQUENCY RATIO 7

C C
SDRAM & LAN,MODEM WAKE UP FUNCTION 8,9

PCI SLOTS 10,11

AGP SLOT & AGP 2X/4X OPTION CIRCUITS 12

ISA SLOTS 13

IDE & PANEL 14

CLOCK SYNTHESIZER & KEYBOARD WAKE UP FUNCTION 15

ATX POWER CONNECTOR & BYPASS CAPACITORS 16

B
DC-DC CONVERTER 17 B
|LINK
| 2.SCH
| 3.SCH
PRINTER / COM PORT 18 | 4.SCH
| 5.SCH
| 6.SCH
| 7.SCH
AUDIO CODEC & AUDIO PORT & JOSTICK PORT 19 | 8.SCH
| 9.SCH
| 10.SCH
| 11.SCH
AMR SLOT 20 | 12.SCH
| 13.SCH
| 14.SCH
| 15.SCH
STR OPTION CIRCUITS 21 | 16.SCH
| 17.SCH
| 18.SCH
| 19.SCH
GTL-BUS 22 | 20.SCH
| 21.SCH
| 22.SCH

A
VIA TECHNOLOGIES ASSUMES NO RESPONSIBILITY FOR ANY ERRORS A

IN DRAWING THESE SCHEMATICS. THESE SCHEMATICS ARE SUBJECT

XXXXX TECHNOLOGIES, INC.

TO CHANGE AT ANY TIME WITHOUT NOTICE.

Title
COPYRIGHT 1999 VIA TECHNOLOGIES INCORPORATED. COVER SHEET

Size Document Number Rev

B VT5228A (Preliminary) 0.4

Date: Wednesday, January 12, 2000 Sheet 1 of 22

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

U5A
3 W1 AK8 A3 3
D0 D0 A3 A3
3 T4 AH12 A4 3
D1 D1 A4 A4
3 N1 AH8 A5 3 U5B
D2 D2 A5 A5
3 M6 AN9 A6 3 A37 U5
D3 D3 A6 A6 GND GND
VCC_CMOS 3 U1 AL15 A7 3 AB32 V2
D4 D4 A7 A8 A7 GND GND
3 S3 AH10 A8 3 AC33 V34
D5 D5 A8 A9 GND GND
3 T6 AL9 A9 3 AC5 X32
RN 1K D6 J1
D6 A9
AH6 A10 AD2
GND GND X36
RN12 3 A10 3
-SLP# D7 D7 A10 A11 GND GND
1 2 3 S1 AK10 A11 3 AD34 Y37
-CPUINIT# D8 D8 A11 A12 GND GND
3 4 3 P6 AN5 3 AF32 Y5
-SMI# D9 D9 A12 A13 A12 GND GND
D 5 6 3 Q3 AL7 A13 3 AF36 Z2 D
-STPCLK# D10 D10 A13 A14 GND GND CLKREF
7 8 3 M4 AK14 A14 3 AG5 Y33
D11 D11 A14 A15 GND CLKREF
3 Q1 AL5 A15 3 U7A AH2
D12 D12 A15 A16 GND
3 L1 AN7 A16 3 14 AH34 AJ31 C133-100-
D13 N3
D13 A16
AE1 A17 AJ11
GND BSEL1 AJ33
3 D14 D14 A17 A17 3 GND BSEL0 C100-66-
3 U3 Z6 A18 3 VCCP_GD 2 1 AJ15 AD36 VTT
D15 D15 A18 A18 GND VCC_1.5V
3 H4 AG3 A19 3 AJ19 Z36 VCC2_5
D16 D16 A19 A19 GND VCC_2.5V
3 R4 AC3 A20 3 7 AJ23 AB36 VCC_CMOS
D17 D17 A20 A20 GND VCC_CMOS
3 P4 AJ1 A21 3 74LVC07 AJ27 VCCP
D18 D18 A21 A21 GND
3 H6 AE3 A22 3 AJ3
D19 D19 A22 A23 A22 GND
3 L3 AB6 A23 3 AJ7 AA37
D20 D20 A23 A24 GND VCCCORE
3 G1 AB4 A24 3 AK36 AA5
D21 D21 A24 A25 GND VCCCORE
3 F8 AF6 A25 3 AK4 AB2
D22 D22 A25 A26 GND VCCCORE
3 G3 Y3 A26 3 AL1 AB34
D23 K6
D23 A26
AA1 A27 PW_GOOD AL3
GND VCCCORE AD32 VCC2_5
3 D24 D24 A27 A27 3 PW_GOOD GND VCCCORE
3 E3 AK6 A28 3 AM10 AE5
D25 D25 A28 A28 GND VCCCORE
3 E1 Z4 A29 3 AM14 AF2
D26 D26 A29 A29 GND VCCCORE
3 F12 AA3 A30 3 AM18 AF34
D27 D27 A30 A30 GND VCCCORE
3 A5 AD4 A31 3 Z34 AH24
D28 D28 A31 A31 GND VCCCORE
3 A3 X6 AM22 AH32 R67
D29 D29 A32# VCC_CMOS GND VCCCORE 150(1%)
3 J3 AC1 AM26 AH36
D30 D30 A33# GND VCCCORE
3 C5 W3 AM30 AJ13
D31 F6
D31 A34#
AF4 AM34 GND VCCCORE AJ17
3 D32 D32 A35# GND VCCCORE
3 C1 AM6 AJ21 CLKREF
D33 D33 GND VCCCORE
3 C7 AL25 -HIT AN3 AJ25
D34 D34 HIT GND VCCCORE C172
3 B2 AL23 -HITM B12 AJ29
D35 D35 HITM GND VCCCORE 1U R81
3 C9 AE35 R72 150 B16 AJ5
D36 A9
D36 IERR AG37 VCCP B20 GND VCCCORE AJ9 C62 150(1%)
3 D37 D37 IGNNE -IGNNE GND VCCCORE 1U
3 D8 AG33 -CPUINIT# B24 AK2
C D38 D10
D38 INIT M36 B28 GND VCCCORE AK34 C
3 D39 D39 LINT0/INTR INTR GND VCCCORE
3 C15 L37 VCC_CMOS B32 AM12
D40 D40 LINT1/NMI NMI GND VCCCORE
3 D14 AK20 -HLOCK B4 AM16
D41 D12
D41 LOCK J33 B8 GND VCCCORE AM20
3 D42 D42 PICCLK APICLK GND VCCCORE
3 A7 J35 R55 150 VTT D18 AM24
D43 A11
D43 PICD0 L35 R66 D2 GND VCCCORE AM28
3 D44 PICD1 150
D44 L15 GND VCCCORE
3 C11 W33 4.7UH(1206) D22 AM32
D45 D45 PLL1 C57 GND VCCCORE
3 A21 U33 22U D26 AM4
D46 D46 PLL2 GND VCCCORE
3 A15 A35 R50 56 D30 AM8
D47 D47 PRDY R65 GND VCCCORE
3 A17 J37 330 D34 B10
D48 D48 PREQ VCCP_GD GND VCCCORE
3 C13 AK26 VCCP_GD D4 B14
D49 D49 PWRGOOD GND VCCCORE
3 C25 X4 -CPURST E11 B18
VCC_CMOS VCC2_5 D50 D50 RESET2# GND VCCCORE
3 A13 AH4 E15 B22
D51 D16
D51 RESET# -HREQ[0..4] E19 GND VCCCORE B26
3 D52 D52 -HREQ[0..4] GND VCCCORE
3 A23 AK18 -HREQ0 E7 B30
R82 R56 D53 D53 REQ0 -HREQ1 GND VCCCORE
3 C21 AH16 F20 B34
2.7K 2.7K D54 D54 REQ1 -HREQ2 GND VCCCORE
3 C19 AH18 F24 B6
D55 D55 REQ2 -HREQ3 GND VCCCORE
3 C27 AL19 F28 C3
D56 A19 D56 REQ3 AL17 -HREQ4 F32 GND VCCCORE D20
-FERR 3 D57 D57 REQ4 GND VCCCORE
C 3 C23 F36 D28
Q6 D58 D58 GND VCCCORE
B 3 C17 C33 G5 D32
D59 D59 DEP0# GND VCCCORE
E2N3904 3 A25 C31 H2 D36
D60 D60 DEP1# GND VCCCORE
3 A27 A33 H34 D6
VCC_CMOS D61 D61 DEP2# GND VCCCORE
3 E25 A31 K36 E13
D62 D62 DEP3# VTT GND VCCCORE
3 F16 E31 L5 E17
D63 D63 DEP4# GND VCCCORE
JP1 C29 M2 E5
R68 DEP5# GND VCCCORE
3 E29 M34 E9
2.7K DEP6# GND VCCCORE
2 FERR# A29 P32 F14
1 DEP7# AL11 P36 GND VCCCORE F2
B
VCCP AP0# R86 GND VCCCORE B
AN13 Q5 F22
AP1# AK24 75 R34 GND VCCCORE F26
AERR# 1% C74 GND VCCCORE
R88 AC37 T32 F30
RSP# 0.01U GND VCCCORE
AG1 AN23 T36 F34
EDGCTRL/VRSEL RP# B36 VTT GND VCCCORE F4
BINIT# VCCCORE
51 V4 E33 H32
W37 BERR# F18 VREF0 VCCCORE H36
CPUCLK BCLK VREF1 VCCCORE
AH20 K4 J5
VTT C73 CM24 VREF2 VCCCORE
AE33 AN15 R6 K32
-A20M AN31 A20M VTT AN21 1U .1U V6 VREF3 VCCCORE K34
-ADS ADS VTT R85 VREF4 VCCCORE
AH14 AL13 AD6 M32
-BNR G33 BNR VTT AL21 150 AK12 VREF5 VCCCORE N5
BP2 VTT 1% VREF6 VCCCORE
E37 AN11 AK22 P2
BP3 VTT VREF7 VCCCORE
C35 AA33 P34
BPM0 VTT VCCCORE
E35 AA35 R32
BPM1 VTT CVID0 VCCCORE
AN17 G35 AL35 R36
-BPRI AN29 BPRI VTT S33 CVID1 AM36 VID0 VCCCORE S5
VCC_CMOS -BREQ0 BR0 VTT 0X4 CVID2 VID1 VCCCORE
S37 AL37 T2
VTT CVID3 VID2 VCCCORE
C37 U35 RN4 AJ37 T34
CPUPRES VTT CVID0 VID0 VID3 VCCCORE
AL27 U37 1 2 V32
-DBSY DBSY VTT CVID1 VID1 VCCCORE
AN19 E23 3 4 V36
-DEFER DEFER VTT CVID2 VID2 VCCCORE
AN27 AK16 5 6 W5
-RS[0..2] -DRDY FERR# DRDY VTT CVID3 VID3 VCCCORE
AC35 Q35 7 8 X34
-RS[0..2] 150 FERR NC VCC VCC3 VCCCORE
R69 AE37 Q37 RJ1 Y35
-RS0 FLUSH NC VCCCORE
AH26 N33 R43 1 Z32
-RS1 RS0 NC CVID4 VID4 VCCCORE
AH22 N35 2 K2
-RS2 AK28 RS1 NC G37 3 VCCCORE D24
VCC_CMOS RS2 NC VCCCORE
AH30 L33 0
-SLP# SLP NC
A AJ35 N37 U3 PGA370 A
-SMI# SMI NC I2CD2 I2CD1
AG35 Q33 1 14 I2CD1
-STPCLK# STPCLK NC I2CD2 CVID0 SDA VCC
R83 1K AL33 W35 2 13
TCK NC CVID1 I0 SCL VID0
R70 330 AN35 F10 3 12 VID0
TDI NC CVID2 I1 Y0 VID1
R71 150 AN37 Y1 4 11 VID1
TDO NC CVID3 I2 Y1 VID2 XXXXX COMPUTER INC.
E21 R290 5 10 VID2
AH28 NC E27 CVID4 6 I3 Y2 9 VID3
1K THERMTRIP NC I4 Y3 VID3
R84 AK32 R2 7 8 VID4
TMS NC R289 GND Y4 VID4
AL31 S35 XXX Title
THERMDP NC 694X
AL29 X2 XXX FM3540
THERMDN NC
AN25 AK30
-HTRDY AN33 TRDY NC AM2 Size Document Number Rev
R44 680 TRST NC B SOCKET 370 CPU
PGA370
Date: Wednesday, January 12, 2000 Sheet 2 of 22
8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D[0..63]

W21
M14

M16

M13

M11

M21
M22
N13

N14

N15

C18

H21

C22

N12

N24
P22

A14

E15

E12

E24
A26
2

F19
F21
D[0..63]

L15

L12
J24
H6

C5

C9

U6

U7
A1

E3

K1
F6

F8
VTT VTT

J3
U6A

D0 B22 K6 A_D0

VSSA
VSSA
VSSA
VSSA
VSSA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D0 AD0 A_D0 5,10,11 R108
D1 D22 K2 A_D1 5,10,11 R97 75(1%)
D2 D1 AD1 A_D2 A_D1 75(1%)
E21 K4 A_D2 5,10,11
D3 D2 AD2 A_D3 GTLVREFA GTLVREFB
A22 K3 A_D3 5,10,11
D4 D3 AD3 A_D4
D21 K5 A_D4 5,10,11
D5 D4 AD4 A_D5
C21 J1 A_D5 5,10,11 C95
D6 D5 AD5 A_D6 R96 R107
A21 J2 5,10,11 C86 .1u
D7 D6 AD6 A_D7 A_D6 .1u 150(1%) 150(1%)
D C20 H2 A_D7 5,10,11 D
D8 D7 AD7 A_D8
B21 H1 A_D8 5,10,11
D9 D8 AD8 A_D9
E20 J5 A_D9 5,10,11
D10 D9 AD9 A_D10
A20 H3 A_D10 5,10,11
D11 D10 AD10 A_D11
E19 H5 5,10,11
D12 D11 AD11 A_D12 A_D11
B20 H4 A_D12 5,10,11
D13 D12 AD12 A_D13
E18 G1 A_D13 5,10,11
D14 D13 AD13 A_D14
D20 G2 A_D14 5,10,11
D15 D14 AD14 A_D15
D19 G4 A_D15 5,10,11 U7F
D16 D15 AD15 A_D16
D18 D1 5,10,11 14
D17 D16 AD16 A_D17 A_D16
C19 D3 A_D17 5,10,11
D18 D17 AD17 A_D18
B19 D2 A_D18 5,10,11 12 13 -PCIRST
D19 D18 AD18 A_D19 -CPURST
A18 C1 A_D19 5,10,11
D20 D19 AD19 A_D20
A19 A2 A_D20 5,10,11 7
D21 D20 AD20 A_D21 74LVC07
B18 C3 A_D21 5,10,11
D22 D21 AD21 A_D22
C17 B3 A_D22 5,10,11
D23 D22 AD22 A_D23
E17 D4 A_D23 5,10,11
D24 D17 D23 AD23 E5 A_D24
D24 AD24 A_D24 5,10,11
D25 B17 A4 A_D25 5,10,11
D25 AD25 A_D25
D26 C16 D5 A_D26 5,10,11
D26 AD26 A_D26
D27 A17 B4 A_D27 5,10,11
D27 AD27 A_D27
D28 C15 B5 A_D28 5,10,11
D28 AD28 A_D28
D29 B16 A5 A_D29 A_D29 5,10,11 VCC3
D30 D29 AD29 A_D30
D16 E6 A_D30 5,10,11
D31 A16 D30 AD30 C6 A_D31
D31 AD31 A_D31 5,10,11
D32 B15
D33 D32 -FRAME
A15 E1 -FRAME 5,10,11
D34 D14 D33 FRAME F3 -DEVSEL -DEVSEL 5,10,11 U25C
D35 D34 DEVSEL -IRDY
D15 E2 -IRDY 5,10,11 14
C D36 B13 D35 IRDY F5 -TRDY C
D36 TRDY -TRDY 5,10,11
D37 C14 F4 -STOP 5,10,11 6 5
D37 STOP -STOP -SMI# -SMI
D38 E14 F2 -PLOCK 10,11
D38 PLOCK -PLOCK
D39 D13 B6 -PCIREQ -PCIREQ 5 7
D40 D39 PHOLD -PCIGNT 74LVC07
A13 D6 -PCIGNT 5
D41 D12 D40 PHLDA G5 PAR
D41 PAR PAR 5,10,11
D42 B12 F1 -SERR 5,10,11
D42 SERR -SERR
D43 B14
D44 C13 D43 A6 -PCIRST VCC3
D44 PCIRST -PCIRST 5,10,11,12
D45 E13 A3 -REQ0 10,11
D45 PREQ0 -REQ0
D46 D11 C7 -REQ1 10,11
D46 PREQ1 -REQ1
D47 A12 F10 -REQ2 11
D47 PREQ2 -REQ2
D48 B11 D8 -REQ3 11 U25A
D48 PREQ3 -REQ3
D49 A11 D10 -REQ4 -REQ4 11 14
D50 D49 PREQ4
B7
D51 C12 D50 E7 -GNT0 2 1
D51 PGNT0 -GNT0 10,11 -SLP# -SLP
D52 C8 D7 -GNT1 10,11
D52 PGNT1 -GNT1
D53 B10 E10 -GNT2 11 7
D53 PGNT2 -GNT2
D54 A10 E8 -GNT3 -GNT3
74LVC07
D55 D54 PGNT3 -GNT4
A9 E9 -GNT4
D56 A7 D55 PGNT4
D57 D56 C_-BE0
E11 J4 C_-BE0 5,10,11
D58 D57 C_BE0 C_-BE1 VCC3
D9 G3 C_-BE1 5,10,11
D59 C11 D58 C_BE1
E4 C_-BE2
D59 C_BE2 C_-BE2 5,10,11
D60 C10 C4 C_-BE3 5,10,11
D60 C_BE3 C_-BE3
D61 B8
D62 D61 VCC3
A8 U25B
D63 D62
B9 M25 R98 8.2K 14
D63 TESTIN
B B
2 -ADS K21 M24 VTT 4 3
-ADS ADS VTTA -CPUINIT# -CPUINIT
2 -BNR H24 F17
-BNR -BPRI BNR VTTB
2 H26 7
-BPRI -DBSY BPRI GTLVREFA 74LVC07
2 L23 M23
-DBSY -DEFER J26 HDBSY GTLVREFA E16 GTLVREFB
2 -DEFER DEFER GTLVREFB
2 -DRDY K23
-DRDY -HIT L24 HDRDY M26 -CRESET
2 -HIT HIT CRESET -CRESET 7
2 -HITM L22 VCC3
-HITM -HLOCK HITM NPCLK
2 K22 B2 NPCLK 15
-HLOCK -HREQ0 J22 HLOCK PCLKIN N23 HCLK VCC3_SB
2 -HREQ0 HREQ0 HCLKIN HCLK 15
2 -HREQ1 J23
-HREQ1 -HREQ2 K24 HREQ1 AF3 PW_GOOD
2 PW_GOOD 5,16,21 U25D
-HREQ2 -HREQ3 HREQ2 PWROK
2 K25 AA11 14
-HREQ3 -HREQ4 HREQ3 VSUS -SUSST
2 J25 AA12 -SUSST 5
-HREQ4 -HTRDY HREQ4 SUSTAT
2 H25 8 9 -STPCLK
-HTRDY -RS0 HTRDY -STPCLK#
2 K26 AE3
-RS0 -RS1 L26 RS0 WSC 7
2 -RS1 RS1
2 -RS2 L25 74LVC07
-RS2 RS2
VCCA
VCCA
VCCA
VCCA
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3

2 -CPURST B23
-CPURST CPURST
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31

-BREQ0 B26
A3
A4
A5
A6
A7
A8
A9

2 -BREQ0 BREQ0
M12

M15
G25

G23

G24

G26
G22

G21
H22

H23

D25
D26

C26

C25

D24
C23

C24

D23

N11

N16

N21
N22
E23
E26
E25

B25

A25

A24

B24

A23
E22

Y21
F26

F22
F23
F24
F25

F18
F20
L11

L13
L14

L16

VT82C694X
J21
G6

C2
B1

V6
F7
F9
J6

VCC2_5
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31

RN67
VCC3 1 2 -SLP
A 3 4 -CPUINIT A
2 A[3..31] 5 6 -SMI
A[3..31]
7 8 -STPCLK
XXX XXXXX TECHNOLOGIES, INC.

HCLK Title
TP12 NORTH BRIDGE VT82C694A/X-A
*near to chip
Size Document Number Rev
B VT5228A (Preliminary) 0.4

Date: Wednesday, January 12, 2000 Sheet 3 of 22

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

MD[32..63] 8,9
MD[32..63]

2,15

MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
MAB12 R95 100-66-
10K
*For 100/66 MHz selection

AC10

AD11

AD18

AD22
AB10

AB15

AB12

AA19

AB25
AB24

AA21

AE23
AF10

AF13

AF26
W23
W24
W26
W25
AD6

AC7

AC9

AD9

AC4
AE4

AE6
AB7

AB8
AB9

AE9

AA6
AA8
AF4

AF5

AF7

U24
U23

R24
R25

N25

R11

R13

R14

R16

R22

AF1
Y24
Y25

V26

P23

P12

P13

P14

P15

P26

V24
T22
T23
T26

T12

T15

N7
K7

P3
P7
Y3

Y7
Y8
D U6B D

MAA0 AF17 AB5 GD0

MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
8 MAA0 MAA0 GAD0 GD0 12
8 MAA1 AB16 AE1 GD1 MAB8 R91 10K 133-100-
MAA1 MAA1 GAD1 GD1 12
8 MAA2 AE17 AD3 GD2
MAA2 MAA2 GAD2 GD2 12 *For 133/100MHz selection
8 MAA3 AC17 AD2 GD3
MAA3 MAA3 GAD3 GD3 12
8 MAA4 AF18 AC2 GD4
MAA4 MAA4 GAD4 GD4 12
8 MAA5 AE19 AC3 GD5 GD5 12
MAA5 MAA6 MAA5 GAD5 GD6
8 AF19 AC1 GD6 12
MAA6 MAA7 AC18 MAA6 GAD6 AB4 GD7 VCC3
8 MAA7 MAA7 GAD7 GD7 12
8 MAA8 AC19 AB1 GD8 JP2
MAA8 MAA8 GAD8 GD8 12
8 MAA9 AE20 AA5 GD9 1
MAA9 MAA9 GAD9 GD9 12
8 MAA10 AD20 AB2 GD10 GD10 12 2 2
MAA10 MAA11 MAA10 GAD10 GD11
8 AF21 AA4 GD11 12 3 C133-100-
MAA11 MAA12 AC21 MAA11 GAD11 AA2 GD12
8 MAA12 MAA12 GAD12 GD12 12
8 MAA13 AF25 AA1 GD13
MAA13 MAA13 GAD13 GD13 12
8,9 MAA14 AB22 AD1 GD14
MAA14 MAA14 GAD14 GD14 12
W4 GD15 GD15 12
MAB0 GAD15 GD16
9 AD16 V2 GD16 12
MAB0 MAB1 AC16 MAB0 GAD16 V1 GD17
9 MAB1 MAB1 GAD17 GD17 12
9 MAB2 AD17 U4 GD18
MAB2 MAB2 GAD18 GD18 12
9 MAB3 AB17 U3 GD19
MAB3 MAB3 GAD19 GD19 12
9 MAB4 AE18 T4 GD20 GD20 12
MAB4 MAB5 MAB4 GAD20 GD21 133-100-
9 AD19 W1 GD21 12 133-100-
MAB5 MAB6 MAB5 GAD21 GD22
9 AB18 U1 GD22 12
MAB6 MAB7 MAB6 GAD22 GD23
9 AB19 T2 GD23 12
MAB7 MAB8 MAB7 GAD23 GD24
9 AF20 R5 GD24 12
MAB8 MAB9 AC20 MAB8 GAD24 U2 GD25
9 MAB9 MAB9 GAD25 GD25 12
9 MAB10 AB20 T1 GD26
MAB10 MAB10 GAD26 GD26 12
C
9 MAB11 AE21 R4 GD27 C
MAB11 MAB11 GAD27 GD27 12
9 MAB12 AD21 V3 GD28
MAB12 MAB12 GAD28 GD28 12
9 MAB13 AF22 R2 GD29
MAB13 MAB13 GAD29 GD29 12
9 MAB14 AE22 P6 GD30 GD30 12
MAB14 MAB14 GAD30 GD31
R1 GD31 12
-CSA0 AB14 GAD31
8 -CSA0 CSA0
8 -CSA1 AF15 AB3 -GBE0 12
-CSA1 CSA1 GC_BE0 -GBE0
8 -CSA2 AE15 Y4 -GBE1 12
-CSA2 CSA2 GC_BE1 -GBE1
8 -CSA3 AC15 V5 -GBE2 -GBE2 12
-CSA3 -CSA4 CSA3 GC_BE2 -GBE3
9 AD15 T3 -GBE3 12
-CSA4 -CSA5 CSA4 GC_BE3
9 AE16
-CSA5 CSA5 -GFRAME
W2 -GFRAME 12
-CSB0 GFRAME -GDEVSEL
8 AE25 W5 -GDEVSEL 12
-CSB0 -CSB1 AD24 CSB0 GDEVSEL W3 -GIRDY Install for CPU quick start.
8 -CSB1 CSB1 GIRDY -GIRDY 12
8 -CSB2 AD26 Y2 -GTRDY 12
-CSB2 CSB2 GTRDY -GTRDY
8 -CSB3 AC24 V4 -GSTOP 12
-CSB3 CSB3 GSTOP -GSTOP
9 -CSB4 AC26 Y1 GPAR VCC3
-CSB4 CSB4 GPAR GPAR 12
9 -CSB5 AB23
-CSB5 CSB5 L5 -GREQ
GREQ -GREQ 12
8,9 -DQMA0 AE14 L3 -GGNT 12 MAB10 R102 10K (OPT)
-DQMA0 DQMA0 GGNT -GGNT
8 -DQMA1 AC14
-DQMA1 -DQMA2 DQMA1 ST0
8,9 AA22 L4 ST0 12
-DQMA2 -DQMA3 DQMA2 ST0 ST1
8,9 AA24 L1 ST1 12
-DQMA3 -DQMA4 DQMA3 ST1 ST2
8,9 AD13 M4 ST2 12
-DQMA4 -DQMA5 DQMA4 ST2 Install for IOQ = 1
8 AC13
-DQMA5 -DQMA6 DQMA5 -PIPE
8,9 AC25 M3 -PIPE 12
-DQMA6 -DQMA7 DQMA6 PIPE -RBF MAB11
8,9 AB26 N6 -RBF 12 R100 10K (OPT)
-DQMA7 -DQMB1 DQMA7 RBF -WBF
9 AD14 M6 -WBF 12
-DQMB1 -DQMB5 AE13 DQMB1 WBF
B 9 -DQMB5 DQMB5 B
Y5 AD_STB0 12
AD_STB0 AD_STB0
8 -SRASA AF16 U5 -AD_STB0 12
-SRASA SRASA AD_STB0 -AD_STB0
9 -SRASB AA17 T6 AD_STB1 12
-SRASB SRASB AD_STB1 AD_STB1 * FOR TEST
T5 -AD_STB1 12
AD_STB1 -AD_STB1
8 -SCASA AF12 N3 SB_STB SB_STB 12
-SCASA -SCASB SCASA SB_STB -SB_STB
9 AB13 M5 -SB_STB 12
-SCASB SCASB SB_STB
8 -SWEA AE12
-SWEA -SWEB WEA SBA0
9 AC12 L2 SBA0 12
-SWEB WEB SBA0 M2 SBA1
SBA1 SBA1 12
8,9 MPD0 AF11 M1 SBA2 12 AGPVREF
MPD0 MECC0 SBA2 SBA2
8,9 MPD1 AD12 N2 SBA3 12
MPD1 MECC1 SBA3 SBA3
8,9 MPD2 AA25 P4 SBA4 12
MPD2 MECC2 SBA4 SBA4 C106
8,9 MPD3 Y22 P5 SBA5 12
MPD3 MECC3 SBA5 SBA5
8,9 MPD4 AE11 P2 SBA6 SBA6 12 .1u
MPD4 MPD5 MECC4 SBA6 SBA7
8,9 AA10 P1 SBA7 12
MPD5 MPD6 AA23 MECC5 SBA7
8,9 MPD6 MECC6
8,9 MPD7 AA26 N1 AGPVREF 12
MPD7 MECC7 AGPREF AGPVREF

21 CKE0 AC22 N5 GCLKIN

CKE0 CKE1 CKE0 GCLKIN GCLK
21 AF23 N4 R129 22
CKE1 CKE2 CKE1 GCLKOUT GCLKO
21 AE24 R128 22 12
CKE2 CKE2/CSA6 GCLKO
21 CKE3 AD23 AB21 R99 22 DCLKO 15
CKE3 CKE3/CSA7 DCLKO DCLKO
21 CKE4 AC23
CKE4 CKE5 CKE4/CSB6 DCLKWR
21 AF24 AD25 DCLKWR 15
CKE5 CKE5/CSB7 DCLKWR
AE2 NCOMP
VCCQQ
VCCQQ

AF2 PCOMP
VSSQQ
VSSQQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
VCCQ
AE8 MD10
AF9 MD11
AD10MD12
AE10MD13
MD14
AC11MD15
Y23 MD16
Y26 MD17
W22 MD18
MD19
V23 MD20
V25 MD21
U22 MD22
U25 MD23
U26 MD24
T24 MD25
T25 MD26
U21 MD27
MD28
R26 MD29
P24 MD30
P25 MD31

AA9 VCC3
T16 VCC3
AA18VCC3
AA20VCC3
V21 VCC3
N26 VCC3
AE26VCC3
P16 VCC3
VCC3
AF14 VCC3
T14 VCC3
T13 VCC3
R12 VCC3
T11 VCC3
P11 VCC3

C88
AC5 MD0
AE5 MD1
AB6 MD2
AC6 MD3
AF6 MD4
AD7 MD5
AE7 MD6
AC8 MD7
AD8 MD8
MD9

10P
AB11

A A
AD4

AD5
AA3
AA7
AF8

R23

R15
V22

GCLKIN VT82C694X
W6
R3
R6

R7

Y6
L7
L6

TP18
GCLK
TP17 XXXXX TECHNOLOGIES, INC.
DCLKO R114 60.4(1%)
TP4
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31

VDDQ
DCLKWR VCC3 VDDQ R142 60.4(1%)
TP13 Title
NORTH BRIDGE VT82C694A/X-B
MD[0..31] 8,9
MD[0..31]
Size Document Number Rev
B VT5228A (Prelimonary) 0.4

Date: Wednesday, January 12, 2000 Sheet 4 of 22

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

VCC3
U18A RN 4.7K RN61
14 PD_D[0..15] PD_D0 P16 W18 R212 22 BITCLK NMI_ 1 2
PD_D[0..15] PDD0 SDD0/BITCLK BITCLK
PD_D1 P18 V17 R211 22 -IGNNE_ 3 4
PDD1 *SDD1/SDIN SDIN 20
PD_D2 P20 Y17 R213 22 20 INTR_ 5 6
PDD2 *SDD2/SDIN2 SDIN2
PD_D3 R17 V16 R215 22 -A20M_ 7 8
PDD3 SDD3/SYNC SYNC 19,20
PD_D4 R19 Y16 R214 22 VCC3_SB
PD_D5 PDD4 SDD4/SDOUT SDOUT 19,20 -PCIGNT
T16 U15 R216 22 -ACRST 19,20 RN60 R208 10K
PD_D6 PDD5 SDD5/-ACRST JBCY SUS_CLK
T18 W15 JBCY 19 7 8
PD_D7 PDD6 SDD6/JBY JBCX -SUSST -PCIREQ
T20 U14 JBCX 19 5 6 R209 10K
PD_D8 PDD7 *:VSUS SDD7/JBX JACY -SMBALT
T19 Y15 JACY 19 3 4
PD_D9 T17 PDD8 SDD8/JAY
V15 JACX -EXTSMI 1 2 -CLKRUN
JACX 19 R235 10K
PD_D10 PDD9 SDD9/JAX JAB2
D R20 T15 JAB2 19 RN 10K RN59 D
PD_D11 PDD10 SDD10/JAB2 JAB1 -BATLOW
R18 W16 JAB1 19 1 RN 10K
2
PD_D12 R16 PDD11 SDD11/JAB1
U16 JBB2 -RI 3 4
PDD12 SDD12/JBB2 JBB2 19
PD_D13 P19 W17 JBB1 -SUSB 5 6
PDD13 SDD13/JBB1 JBB1 19
PD_D14 P17 Y18 MSO -SUSA 7 8
PD_D15 PDD14 SDD14/MSO MSI MSO 19
N20 Y19 MSI 19
PDD15 SDD15/MSI PD_80P R239 10K
14 PD_A0 M17 U19 SD_A0 14
PD_A0 PDA0 SDA0 SD_A0
14 PD_A1 M19 V18 SD_A1 14 SD_80P R240 10K
PD_A1 PDA1 SDA1 SD_A1
14 PD_A2 M18 U20 SD_A2 14
PD_A2 -PDCS_1 PDA2 SDA2 -SDCS_1 SD_A2 I2CD1
14 L20 U17 -SDCS_1 14 R244 4.7K
-PDCS_1 -PDCS_3 PDCS1 SDCS1 -SDCS_3
14 M16 U18 -SDCS_3 14
-PDCS_3 -DDACK_A PDCS3 SDCS3 -DDACK_B I2CD2
14 M20 V19 -DDACK_B 14 R243 4.7K
-DDACK_A DDREQ_A PDDACK SDDACK DDREQ_B
14 N19 Y20 DDREQ_B 14
DDREQ_A -DIOR_A N17 PDDREQ SDDREQ W19 -DIOR_B
14 -DIOR_A PDIOR SDIOR -DIOR_B 14
14 -DIOW_A N18 W20 -DIOW_B 14
-DIOW_A PDIOW SDIOW -DIOW_B
14 HDRDY_A N16 V20 HDRDY_B VCC3_SB
HDRDY_A PDRDY SDRDY HDRDY_B 14
VCC3_SB

3,5,10,11 A_D[0..31] A_D0 L17 Y7 -A20M_ 7

A_D[0..31] A_D1 AD0 A20M -A20M_ R237
L16 V8 R241
AD1 CPURST 4.7K 10K
A_D2 K20 V7 -FERR 2
AD2 FERR -FERR R236
A_D3 K19 Y8 -IGNNE_ 7 -PWRBTN 14,21 R242
AD3 IGNNE -IGNNE_ PW_BN
A_D4 K18 T6 -CPUINIT 2 C151 68 -PME_ 10,11
AD4 INIT -CPUINIT -PME
A_D5 K17 W8 INTR_ 7
A_D6 AD5 INTR NMI_ INTR_ .1u
K16 U7 NMI_ 7 0 (OPT)
A_D7 AD6 NMI -SLP
J20 T7 -SLP 2
A_D8 J18 AD7 SLP/GPO7 U6 -SMI
AD8 SMI -SMI 2
A_D9 J17 W7 -STPCLK 2
AD9 STPCLK -STPCLK
C A_D10 J16 VCC3 C
A_D11 AD10
H20 Y12 R231 10K
A_D12 AD11 CPUSTP/GPO4
H19 V12 R234 10K
A_D13 H18 AD12 PCISTP/GPO5
A_D14 AD13 -CLKRUN VCC3
H17 W12
A_D15 H16 AD14 CLKRUN V5 SPEAK
A_D16 AD15 SPKR
F16
A_D17 AD16
E20 T14 R210 10K
A_D18 E19 AD17 GPIOA/GPIO8
U8
AD18 GPIOD R238 10K
A_D19 E18 VCC
A_D20 E17 AD19
A_D21 AD20 PW_GOOD
D20 W6 PW_GOOD 3,16,21
A_D22 AD21 *PWRGD I2CD1
D19 U9 I2CD1 8,9,15
A_D23 D18 AD22 *SMBCLK T9 I2CD2
AD23 *SMBDATA I2CD2 8,9,15
A_D24 B20 VCC3_SB U21 R268

8
A_D25 A20 AD24 T8 1K
AD25 *GPO0 R252 10K
A_D26 A19 V10 -SUSST

VCC
AD26 *SUSST1/GPO6 -SUSST 3 PGO0
A_D27 B19 T10 SUS_CLK -SUSA 4 7
A_D28 A18 AD27 *SUSCLK R DIS
A_D29 AD28 -EXTSMI
B18 Y10 -EXTSMI 14,15
A_D30 C18 AD29 *EXTSMI
V11 -RI 2 R269
AD30 *RING/GPI7 -RI 9 TRIG 10K
A_D31 A17 T11 -PME_ 3
AD31 *PME/GPI5/THRM -BATLOW SUSLED OUT
U11
C_-BE[0..3] C_-BE0 J19 *BATLOW/GPI2 Y11 -PWRBTN 5 6

GND
3,10,11 C_-BE[0..3] C_BE0 *PWRBTN CV TH
C_-BE1 G20 V6 -RSMRST 21
C_BE1 *RSMRST -RSMRST
C_-BE2 F17 W11 PD_80P 14
C_BE2 *GPI1/IRQ8 PD_80P
C_-BE3 C19 U10 SD_80P 14 C159 LM555 C158
C_BE3 *LID/APICREQ/GPI3 SD_80P 0.1U 100U

1
W10 -SMBALT
-FRAME F18 *SMBALT/GPI6
B 3,10,11 -FRAME FRAME B
3,10,11 -IRDY F19 V9 -SUSA
-IRDY -TRDY IRDY *SUSA/APICACK/GPO1 -SUSB
3,10,11 F20 W9 -SUSB 21
-TRDY -STOP TRDY *SUSB/APICCS/GPO2 -SUSC
3,10,11 G17 Y9 -SUSC 21
-STOP -DEVSEL STOP *SUSC
3,10,11 G16
-DEVSEL -SERR G18 DEVSEL +12V
3,10,11 -SERR SERR
3,10,11 PAR G19 F15 V VCC3
PAR A_D18 C20
PAR GND G15 VCC3 SPEAK
3,5,10,11 IDSEL R251 1K
A_D18 -PCIREQ GND
3 L18 L15
-PCIREQ -PCIGNT REQ GND VCC2_5 NOTE: SECOND IDE BUS IS
3 L19 P15
-PCIGNT -PCIRST B16 GNT GND R15 R223 R230 ASSIGNED TO AUDIO/GAME
3,10,11,12 C148 R217 C149
-PCIRST PCIRST GND VCCP 10K 53K(1%) 16K(1%)
-INTR_A A16 .1u .1u
10,11,12 -INTR_A PINTA R224
10,11,12 -INTR_B D17 Y14
-INTR_B -INTR_C PINTB IN12
10,11 C17 10K(1%)
-INTR_C -INTR_D PINTC R218
10,11 B17 W14
-INTR_D PINTD IN5
10K(1%)
15 SPCLK E16 U13 CB54 1u
SPCLK PCICLK IN2A
CX2 10p Y5 V13 CB55 1u SPEAK 14,19,20
SPEAK
2

RTCX1 IN2B
X3
V14 R221 0(OPT)
VCC3_SB 32.768KHz W5 CHAS/GPIOC/GPIO10
RTCX2 L16 HM_GND
1

CX1 10p W13 RT1

VCC3_SB TSEN1
D7 1N5819 R9 R222 10K(1%) FB(0805)
t

VCCSUS CON-2
JBAT1 R10 T13
VCCSUS VREF 103JT-025
CB45 D6 1N5819 1 R225 10K(1%)
2 V_BAT Y6 Y13 L26
RT2
.1u VBAT TSEN2
R206 3 FB(0805)
t

1K H15 T12 CPUFAN1 CON-2

A VCC FAN1 CPUFAN1 16 103JT-025
A
CT31 C150 R226 J15
VCC CPUFAN2
1K K15 U12 CPUFAN2 16
10u .1u VCC FAN2/GPIOB/GPIO9 Place RT1 under CPU
M15
VCC3 VCC VCC3 XXXXX TECHNOLOGIES, INC.
N15
BAT1 VCC Place RT2 near NB
R7 R12 L27 FB
R8 VCC VCCHWM
VCC CB50 CT30
R11
R14 VCC R13 .1u 10u Title
VCC GNDHWM L28 FB
SOUTH BRIDGE VT82C686A-A
VT82C686A
HM_GND Size Document Number Rev
B VT5228A (Preliminary) 0.4

Date: Wednesday, January 12, 2000 Sheet 5 of 22

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

13,14 SD_D[0..15] VCC VCC

SD_D[0..15]
U18B
SD_D0 W1 B15 P_PRD0 18
SA0 PRD0 P_PRD[0..7]
SD_D1 V2 D15 P_PRD1
SD_D2 SA1 PRD1 P_PRD2 P_PRD[0..7] FS2 FS3
V1 A14
SD_D3 SA2 PRD2 P_PRD3 FUSE(2) FUSE(2)
U3 B14
SD_D4 SA3 PRD3 P_PRD4
U2 C14
SD_D5 SA4 PRD4 P_PRD5 OVER_C0 R38 R41 OVER_C1
U1 D14 7 OVER_C1 7,20
SD_D6 SA5 PRD5 P_PRD6 OVER_C0
T4 E14 470K 470K
SD_D7 SA6 PRD6 P_PRD7 R39 R40
T3 A13 C39 CM2 CM3 C40
SD_D8 SA7 PRD7 560K L9 L10 560K
T2
SD_D9 SA8 .001u FB 1u 1u FB .001u
D T1 B13 P_ACK 18 D
SD_D10 SA9 ACK
R5 C13 P_BUSY 18
SD_D11 SA10 BUSY
R4 D13 P_PE 18
SD_D12 SA11 PE
R3 E13 P_SLCT 18 USB1
SD_D13 SA12 SLCT
R2 A15 5 1
SD_D14 SA13 ERROR P_ERROR 18 USBDT0- USBDT1-
R1 C15 P_INIT 18 6 2
SD_D15 SA14 PINIT USBDT0+ USBDT1+
P5 C16 P_AUTOFD 18 7 3
SA[16..23] SA16 SA15 AUTOFD
13,14 P4 E15 P_SLCTIN 18 8 4
SA[16..23] SA17 SA16 SLCTIN
P3 D16 P_STROBE 18 C18 C22 C21 C19
SA18 SA17 STROBE
K2 CT2 C20 C17 CT1
SA19 SA18 TXD1 .1u(OPT)
K1 A11 TXD1 18
SA20 SA19 TXD1 DTR1 100uF .1u .1u 100uF
J5 D11 DTR1 18
SA21 LA20 DTR1 RTS1 .1u(OPT)
J4 B11 RTS1 18 .1u(OPT)
SA22 LA21 RTS1 CTS1
J3 C11 CTS1 18 .1u(OPT) L11 FB
SA23 LA22 CTS1 DSR1
J2 C12 DSR1 18
LA23 DSR1 DCD1 USB_GND1
A12 DCD1 18
SD[0..15] SD0 DCD1 RI1
7,13,14 Y1 E11 RI1 18
SD[0..15] SD1 Y2 SD0 RI1 B12 RXD1
SD1 RXD1 RXD1 18
SD2 W2
SD3 Y3 SD2 D10 TXD2
TXD2 18 RN63
SD4 SD3 TXD2 DTR2 USB_DT0- USBDT0-
W3 B9 DTR2 18 1 2
SD5 SD4 DTR2 RTS2 USB_DT0+ USBDT0+
V3 E10 RTS2 18 3 4
SD6 Y4 SD5 RTS2 A9 CTS2 USB_DT1- 5 6 USBDT1-
SD6 CTS2 CTS2 18
SD7 W4 C10 DSR2 18 USB_DT1+ 7 8 USBDT1+
SD7 DSR2 DSR2
SD8 L5 A10 DCD2 18
DCD2

8
6
4
2

7
5
3
1
SD9 SD8 DCD2 RI2
M2 C9 RI2 18 RN 27
SD10 SD9 RI2 RXD2 CN12 RN62
M4 B10 RXD2 18
SD11 N1 SD10 RXD2 VCC3 CN 47P RN 15K
SD12 SD11 USB_VCC
N3 F9 L29 FB
SD12 VCCUSB

8
6
4
2
C SD13 N5 C
SD14 SD13

7
5
3
1
P1 CB56 CT35
SD15 SD14
P2
SD15 .1u 10u
-DACK0 L2 F8 USB_GND L30 FB *FOR USB0 & USB1
13 -DACK0 DACK0 GNDUSB
13 -DACK1 E1
-DACK1 -DACK3 DACK1 USBCLK
13 D2 C3 USBCLK 15
-DACK3 -DACK5 DACK3 USBCLK USB_DT0+ USBMUX2 R261 X0(OP) OVER_C0
13 L4 A3
-DACK5 -DACK6 DACK5 USBP0+ USB_DT0-
13 M3 B3
-DACK6 -DACK7 DACK6 USBP0- USB_DT1+
13 N2 C4
-DACK7 DACK7 USBP1+ USB_DT1- USBMUX3 R265 X0(OP) OVER_C1
D4
USBP1- USBMUX3
H3
DREQ0 DRQ2/OC1/SERIRQ/GPIOE USBMUX2
13 L3 G5
DREQ0 DREQ1 E2
DRQ0 DACK2/OC0/GPIOF R262 0 -DACK2
13 DREQ1 DRQ1 -DACK2 13
13 DREQ3 D3 A4 USB_DT2+ 7
DREQ3 DRQ3 USBP2+ USB_DT2+
13 DREQ5 M1 B4 USB_DT2- 7
DREQ5 DRQ5 USBP2- USB_DT2-
13 DREQ6 M5 B5 USB_DT3+ 7
DREQ6 DRQ6 USBP3+ USB_DT3+
13 DREQ7 N4 E6 USB_DT3- 7 R266 0 DREQ2 13
DREQ7 DRQ7 USBP3- USB_DT3- DREQ2

13 AEN B2 E5 KB_CLK 15
AEN AEN KBCK KB_CLK
13 BALE H2 A5 KB_DATA 15
BALE BALE KBDT/KBRC KB_DATA
13 -SBHE F2 D5 MS_CLK 15
-SBHE SBHE MSCK/IRQ1 MS_CLK
7,13 -REFRESH E3 C5 15
MS_DATA
13
-REFRESH
-IOR
-IOR D1
REFRESH
IOR
MSDT/IRQ12 USB0 & USB1
13 -IOW C2 C1 -ROMCS 14 VCC3
-IOW IOW ROMCS -ROMCS
13,14 -MEMR U4 R248 4.7K
-MEMR -MEMW MEMR *Set INIT low active.
13,14 V4 D9 2 1
-MEMW -SMEMR MEMW DRVDEN0
13 A1 D6 4 3
-SMEMR -SMEMW B1 SMEMR DRVDEN1 R120 6 5
B 13 -SMEMW SMEMW B
13 -IOCS16 F3 D7 0(OPT) 8 7
-IOCS16 -MEMCS16 IOCS16 INDEX
13 F1 E9 10 9
-MEMCS16 IOCHRDY MEMCS16 MTR0
13 A2 A8 12 11
IOCHRDY -IOCHCK IOCHRDY DS1
13 F4 B8 14 13
-IOCHCK TC H1 IOCHK/GPI0 DS0 C8 16 15
13 TC TC MTR1
14 J1 D8 18 17
SIO_RES RSTDRV DIR E8 20 19
SIO_OSC STEP
15 E4 A7 22 21
SIO_OSC OSC WDATA
13 R250 33 H5 B7 24 23
SYS_CLK BCLK WGATE E7 26 25
IRRX TRAK00
5 D12 A6 28 27
IRRX IRTX E12 IRRX/GPO15 WRTPRT B6 30 29
5 IRTX IRTX/GPO14 RDATA
C7 32 31
IRQ3 HDSEL
13 G4 C6 34 33
IRQ3 IRQ4 IRQ3 DSKCHG
13 G3
IRQ4 IRQ5 IRQ4 FDD1
13 G2 F6
IRQ5 IRQ6 G1 IRQ5 GND F11
13 IRQ6 IRQ6/SLPBTN GND
13 IRQ7 F5 G6 VCC
IRQ7 IRQ9 IRQ7 GND
13 H4 J9 RN39
IRQ9 IRQ10 IRQ9 GND
13 K3 J10 8 7
IRQ10 IRQ11 IRQ10 GND
13 K4 J11 6 5
IRQ11 IRQ14 IRQ11 GND
13,14 L1 J12 4 3
IRQ14 IRQ15 IRQ14 GND
13,14 K5 K9 2 1
IRQ15 IRQ15 GND
K10
T5 GND K11 R121 1K1K
8P4R
-XOE XDIR/PCS0/GPO12 GND
13 U5 K12
-XOE XOE/GPO13 GND L6
GND
F7 L9
VCC GND C1
A F10 L10 A
F12 VCC GND L11 100U
VCC GND
F13 L12
VCC3 VCC GND
F14 M9
VCC GND XXXXX TECHNOLOGIES, INC.
H6 M10
VCC GND
J6 M11
K6 VCC GND M12
VCC GND
M6 P6
N6 VCC GND R6 Title
VCC GND SOUTH BRIDGE VT82C686A-B
VT82C686A
Size Document Number Rev
B VT5228A (Prelimonary) 0.4

Date: Wednesday, January 12, 2000 Sheet 6 of 22

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

VCC2_5 RJ5
3
VCC 2
1 U7B
14

3 4 -A20M 2
7
74LVC07

VCC3

D U7C D
14

7
5
3
1
RN38 5 6 2
10K 8P4R -IGNNE
SW1 U8 7

8
6
4
2
1 12 2 18 74LVC07
2 11 4 A0 Y0
16
A1 Y1
3 10 6 14
4 9 8 A2 Y2 12
A3 Y3
5 8 5 11 9
-A20M_ A4 Y4
6 7 5 13 7
-IGNNE_ A5 Y5
5 15 5 U7D
INTR_ A6 Y6
5 17 3 14
C100-66- NMI_ A7 Y7
100-66- VCC3 VCC2_5
1 9 8 INTR 2
OE0
19 20
OE1 V 7
R178 74LV244 74LVC07
10K

3 -CRESET
U10A U7E
1 2 14

74F04 R179 11 10 NMI 2

1K
7
C 74LVC07 C
R180
2K

VCC VCC U20

6 2 18 SD0 6,13,14
OVER_C0 A0 Y0
6,20 4 16 SD1 6,13,14
OVER_C1 OVER_C2 6
A1 Y1 14
OVER_C2 A2 Y2 SD2 6,13,14
FS5 FS4 OVER_C3 8 12 6,13,14
FUSE(2) FUSE(2) A3 Y3 SD3 Fraction
11 9
A4 Y4 /Ratio JFREQ1
13 7
OVER_C2 R53 R49 OVER_C3 A5 Y5 2 1-2,3-4,5-6,7-8
15 5
17 A6 Y6 3 3 1-2,5-6,7-8
470K 470K A7 Y7
C53 R54 CM5 CM4 R42 C43 4 3-4,5-6,7-8
560K L14 L13 560K 1 5 5-6,7-8
.001u FB 1u 1u FB .001u 6,13 -REFRESH OE0 5/2 1-2,3-4,7-8
19
OE1 7/2 1-2,7-8
74F244 9/2 3-4,7-8
USB2 11/2 7-8
1 9
2- 2 10
2+ 3 11
3- 4 12
B B
3+ 5 13
6 14
7 15
8 16

CT5 C52 C42 CT4

100uF .1u .1u 100uF JP6 JP3

1 2- 1 3-
USBDT2- 2 USBDT3- 2
3 USB_D2- 3 USB_D3-
RN65
6 USB_DT2+ 1 2 USBDT2+
USB_DT2+ USB_DT2- USBDT2-
6 3 4
USB_DT2- USB_DT3+ 5 6 USBDT3+
6 USB_DT3+
6 USB_DT3- 7 8 USBDT3-
USB_DT3-
RN 27 JP7 JP4
1 2+ 1 3+
2
4
6
8

2
4
6
8

USBDT2+ 2 USBDT3+ 2
CN13 RN64 3 3
CN 47P RN 15K USB_D2+ USB_D3+
1
3
5
7
1
3
5
7

A A

XXXXX TECHNOLOGIES, INC.

Title
USB2,3 / FREQ. RATIO

Size Document Number Rev

B VT5228A (Preliminary) 0.4

Date: Wednesday, January 12, 2000 Sheet 7 of 22

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

MD[0..63] 4,9
MD[0..63]

MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
D D

100
101
103
104
139
140
141
142
144
149
150
151
153
154
155
156
158
159
160
161
10
11
13
14
15
16
17
19
20
55
56
57
58
60
65
66
67
69
70
71
72
74
75
76
77
86
87
88
89
91
92
93
94
95
97
98
99
DIMM2

2
3
4
5
7
8
9
31

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
DU/OE0
44
MAA0 DU/OE2 -CSA0
4 33 30 -CSA0 4
MAA0 MAA1 117 A0 RAS0/S0 114 -CSA1
4 MAA1 A1 RAS1/S1 -CSA1 4
4 MAA2 34 45 -CSB0 4
MAA2 A2 RAS2/S2 -CSB0
4 MAA3 118 129 -CSB1 4
MAA3 A3 RAS3/S3 -CSB1
4 MAA4 35 28 -DQMA0 -DQMA0 4,8,9
MAA4 MAA5 A4 CAS0/DQMB0 -DQMA1
4 119 29 -DQMA1 4,8
MAA5 MAA6 36 A5 CAS1/DQMB1 46 -DQMA2
4 MAA6 A6 CAS2/DQMB2 -DQMA2 4,8,9
4 MAA7 120 47 -DQMA3 4,8,9
MAA7 A7 CAS3/DQMB3 -DQMA3
4 MAA8 37 112 -DQMA4 4,8,9
MAA8 A8 CAS4/DQMB4 -DQMA4
4 MAA9 121 113 -DQMA5 -DQMA5 4,8
MAA9 MAA10 A9 CAS5/DQMB5 -DQMA6
4 38 130 -DQMA6 4,8,9
MAA10 MAA11 122 A10 (AP) CAS6/DQMB6 131 -DQMA7
4 A11 (BS0) CAS7/DQMB7 -DQMA7 4,8,9

RFU/DQS1

RFU/DQS3

RFU/DQS5

RFU/DQS7
RFU/DQS8
MAA11

QS0/DQS0

QS2/DQS2

QS1/DQS4

QS3/DQS6
MAA12 39 27 -SWEA

DU/VREF
DU/VREF
4 MAA12 A12 (BS1) WE0 -SWEA 4,8
4 MAA13 123 48
MAA13 A13 WE2/DU

REGE
CKE0
CKE1
MAA14 126 111 -SCASA

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
SDA
4,9 4,8

SCL

CK0
CK1
CK2
CK3

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
-SCASA

SA0
SA1
SA2
MAA14 DU/A14 DU/CAS

NC
NC
NC
NC
132 115 -SRASA 4,8
DU/A15 DU/RAS -SRASA

165
166
167

128

146

125

163

102
110
124
133
143
157
168

105
106
136
137

145
164
147

108
109
135

134
DIMM

82
83

63
62

42

79

18
26
40
41
49
59
73
84
90

21
22
52
53

61
80

24
25
50
51

81
6
5,8,9,15 I2CD2
C I2CD2 I2CD1 C
5,8,9,15 I2CD1

MPD0
MPD1
MPD2
MPD3
MPD4
MPD5
MPD6
MPD7
21 V_DIM V_DIM
CKE_0
21 CKE_1
4,9 MPD[0..7]
MPD[0..7]
15 DCLK5
15 DCLK6
15 DCLK7
15 DCLK8
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
100
101
103
104
139
140
141
142
144
149
150
151
153
154
155
156
158
159
160
161
10
11
13
14
15
16
17
19
20
55
56
57
58
60
65
66
67
69
70
71
72
74
75
76
77
86
87
88
89
91
92
93
94
95
97
98
99
DIMM1
2
3
4
5
7
8
9

31
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
DU/OE0
44
MAA0 DU/OE2 -CSA2
33 30 -CSA2 4
MAA1 117 A0 RAS0/S0 114 -CSA3
B A1 RAS1/S1 -CSA3 4 B
MAA2 34 45 -CSB2 4
A2 RAS2/S2 -CSB2
MAA3 118 129 -CSB3 4
A3 RAS3/S3 -CSB3
MAA4 35 28 -DQMA0 4,8,9
A4 CAS0/DQMB0 -DQMA0
MAA5 119 29 -DQMA1 4,8
A5 CAS1/DQMB1 -DQMA1
MAA6 36 46 -DQMA2 -DQMA2 4,8,9
MAA7 A6 CAS2/DQMB2 -DQMA3
120 47 -DQMA3 4,8,9
MAA8 37 A7 CAS3/DQMB3 112 -DQMA4
A8 CAS4/DQMB4 -DQMA4 4,8,9
MAA9 121 113 -DQMA5 4,8
A9 CAS5/DQMB5 -DQMA5
MAA10 38 130 -DQMA6 4,8,9
A10 (AP) CAS6/DQMB6 -DQMA6
MAA11 122 131 -DQMA7 -DQMA7 4,8,9
A11 (BS0) CAS7/DQMB7

RFU/DQS1

RFU/DQS3

RFU/DQS5

RFU/DQS7
RFU/DQS8
QS0/DQS0

QS2/DQS2

QS1/DQS4

QS3/DQS6
MAA12 39 27 -SWEA
DU/VREF
DU/VREF

A12 (BS1) WE0 -SWEA 4,8

MAA13 123 48
A13 WE2/DU

REGE
CKE0
CKE1

MAA14 126 111 -SCASA

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
SDA

4,8
SCL

CK0
CK1
CK2
CK3

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
-SCASA
SA0
SA1
SA2

DU/A14 DU/CAS

NC
NC
NC
NC
132 115 -SRASA 4,8
DU/A15 DU/RAS -SRASA
165
166
167

128

146

125

163

102
110
124
133
143
157
168

105
106
136
137

145
164
147

108
109
135

134
DIMM
82
83

63
62

42

79

18
26
40
41
49
59
73
84
90

21
22
52
53

61
80

24
25
50
51

81
6

5,8,9,15 I2CD2
I2CD2 I2CD1
5,8,9,15 I2CD1
MPD0
MPD1
MPD2
MPD3
MPD4
MPD5
MPD6
MPD7

V_DIM V_DIM V_DIM

21 CKE_2
21 CKE_3
15 DCLK2
15 DCLK1
A 15 DCLK3 A
15 DCLK4

XXXXX TECHNOLOGIES, INC.

Title
SDRAM

Size Document Number Rev

B VT5228A (Preliminary) 0.4

Date: Wednesday, January 12, 2000 Sheet 8 of 22

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

MD[0..63] 4,8
MD[0..63]

MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
100
101
103
104
139
140
141
142
144
149
150
151
153
154
155
156
158
159
160
161
10
11
13
14
15
16
17
19
20
55
56
57
58
60
65
66
67
69
70
71
72
74
75
76
77
86
87
88
89
91
92
93
94
95
97
98
99
DIMM3

2
3
4
5
7
8
9
D D
31

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
DU/OE0
44
MAB0 DU/OE2 -CSA4
4 33 30 -CSA4 4
MAB0 MAB1 117 A0 RAS0/S0 114 -CSA5
4 MAB1 A1 RAS1/S1 -CSA5 4
4 MAB2 34 45 -CSB4 4
MAB2 A2 RAS2/S2 -CSB4
4 MAB3 118 129 -CSB5 4
MAB3 A3 RAS3/S3 -CSB5
4 MAB4 35 28 -DQMA0 4,8
MAB4 A4 CAS0/DQMB0 -DQMA0
4 MAB5 119 29 -DQMB1 4
MAB5 A5 CAS1/DQMB1 -DQMB1
4 MAB6 36 46 -DQMA2 4,8
MAB6 A6 CAS2/DQMB2 -DQMA2
4 MAB7 120 47 -DQMA3 4,8
MAB7 A7 CAS3/DQMB3 -DQMA3
4 MAB8 37 112 -DQMA4 4,8
MAB8 A8 CAS4/DQMB4 -DQMA4
4 MAB9 121 113 -DQMB5 -DQMB5 4
MAB9 MAB10 A9 CAS5/DQMB5 -DQMA6
4 38 130 -DQMA6 4,8
MAB10 MAB11 122 A10 (AP) CAS6/DQMB6 131 -DQMA7
4 A11 (BS0) CAS7/DQMB7 -DQMA7 4,8

RFU/DQS1

RFU/DQS3

RFU/DQS5

RFU/DQS7
RFU/DQS8
MAB11

QS0/DQS0

QS2/DQS2

QS1/DQS4

QS3/DQS6
MAB12 39 27 -SWEB

DU/VREF
DU/VREF
4 MAB12 A12 (BS1) WE0 -SWEB 4
4 MAB13 123 48
MAB13 A13 WE2/DU

REGE
CKE0
CKE1
MAB14 126 111 -SCASB

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
SDA
4 4

SCL

CK0
CK1
CK2
CK3

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
-SCASB

SA0
SA1
SA2
MAB14 DU/A14 DU/CAS

NC
NC
NC
NC
132 115 -SRASB 4
DU/A15 DU/RAS -SRASB

165
166
167

128

146

125

163

102
110
124
133
143
157
168

105
106
136
137

145
164
147

108
109
135

134
DIMM

82
83

63
62

42

79

18
26
40
41
49
59
73
84
90

21
22
52
53

61
80

24
25
50
51

81
6
5,8,15 I2CD2
I2CD2 I2CD1
5,8,15 I2CD1

MPD0
MPD1
MPD2
MPD3
MPD4
MPD5
MPD6
MPD7
V_DIM V_DIM V_DIM

21 4,8 MPD[0..7]
C CKE_4 MPD[0..7] C
21 CKE_5
15 DCLK9
15 DCLK10
15 DCLK11
15 DCLK12

D9
R286 1N4148 -XRI1
-XRI1 18
MAB5
R281 R282
10K -XRI2 18
Q15 -XRI2
D8 R279 10K D10
1K 1N4148
MMBT3904 2K

B
1N4148

5 -RI C E
-RI RING IN
JWOL1
5V_SB 1
R280 2
3
Q16
100 WAKE_CONN
B MMBT3904 B

B
LAN
C E
WAKE UP

A A

XXXXX TECHNOLOGIES, INC.

Title
SDRAM/LAN,MODEM WAKE UP FUNCTION

Size Document Number Rev

B VT5228A (Preliminary) 0.4

Date: Wednesday, January 12, 2000 Sheet 9 of 22

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

PCI1 PCI2 +12V

-12V 2 1 +12V -12V 2 1
-12V TRST# -12V TRST#
4 3 4 3
VCC3 6 TCK +12V
5 VCC3 VCC3 6 TCK +12V
5 VCC3
GND TMS GND TMS
8 7 8 7
TDO TDI TDO TDI
V 10 9 V V 10 9 V
+5V +5V -INTR_A +5V +5V -INTR_B
12 11 -INTR_A 5,11,12 12 11
-INTR_B +5V INTA# -INTR_C -INTR_C +5V INTA# -INTR_D
5,11,12 14 13 -INTR_C 5,11 14 13
-INTR_B -INTR_D INTB# INTC# -INTR_A INTB# INTC#
5,11 16 15 16 15
-INTR_D INTD# +5V INTD# +5V
D 18 17 18 17 D
PRSNT#1 RESERVED PRSNT#1 RESERVED
20 19 20 19
RESERVED +5V(I/O) RESERVED +5V(I/O)
22 21 22 21
PRSNT#2 RESERVED PRSNT#2 RESERVED
24 23 24 23
GND GND VCC3_SB GND GND VCC3_SB
26 25 26 25
GND GND GND GND
28 27 28 27
RESERVED 3.3VAUX -PCIRST RESERVED 3.3VAUX -PCIRST
30 29 -PCIRST 3,5,11,12 30 29
GND RST# GND RST#
15 32 31 15 32 31
PCICLK1 CLK +5V(I/O) -GNT0 PCICLK2 CLK +5V(I/O) -GNT1
34 33 -GNT0 3,11 34 33 -GNT1 3,11
-REQ0 GND GNT -REQ1 GND GNT
3,11 36 35 3,11 36 35
-REQ0 REQ# GND -PME -REQ1 REQ# GND -PME
38 37 -PME 5,10,11 38 37 -PME 5,10,11
A_D31 +5V(I/O) PME# A_D30 A_D31 +5V(I/O) PME# A_D30
3,5,11 40 39 A_D30 3,5,11 40 39
A_D31 A_D29 AD31 AD30 A_D29 AD31 AD30
3,5,11 42 41 42 41
A_D29 AD29 +3.3V A_D28 AD29 +3.3V A_D28
44 43 A_D28 3,5,11 44 43
A_D27 GND AD28 A_D26 A_D27 GND AD28 A_D26
3,5,11 46 45 A_D26 3,5,11 46 45
A_D27 A_D25 AD27 AD26 A_D25 AD27 AD26
3,5,11 48 47 48 47
A_D25 AD25 GND A_D24 AD25 GND A_D24
50 49 A_D24 3,5,11 50 49
C_-BE3 52 +3.3V AD24
51 A_D19 C_-BE3 52 +3.3V AD24
51 A_D20
3,5,11 C_-BE3 C/BE#3 IDSEL A_D19 3,5,10,11 C/BE#3 IDSEL A_D20 3,5,10,11
3,5,11 A_D23 54 53 A_D23 54 53
A_D23 56 AD23 +3.3
55 A_D22 56 AD23 +3.3
55 A_D22
GND AD22 A_D22 3,5,11 GND AD22
3,5,11 A_D21 58 57 A_D20 3,5,10,11 A_D21 58 57 A_D20
A_D21 AD21 AD20 A_D20 AD21 AD20
3,5,10,11 A_D19 60 59 A_D19 60 59
A_D19 62 AD19 GND
61 A_D18 62 AD19 GND
61 A_D18
+3.3V AD18 A_D18 3,5,11 +3.3V AD18
3,5,11 A_D17 64 63 A_D16 3,5,11 A_D17 64 63 A_D16
A_D17 AD17 AD16 A_D16 AD17 AD16
3,5,11 C_-BE2 66 65 C_-BE2 66 65
C_-BE2 C/BE#2 +3.3V -FRAME C/BE#2 +3.3V -FRAME
68 67 -FRAME 3,5,11 68 67
-IRDY GND FRAME# -IRDY GND FRAME#
3,5,11 70 69 70 69
-IRDY 72 IRDY# GND
71 -TRDY 72 IRDY# GND
71 -TRDY
+3.3V TRDY# -TRDY 3,5,11 +3.3V TRDY#
3,5,11 -DEVSEL 74 73 -DEVSEL 74 73
C -DEVSEL 76 DEVSEL# GND
75 -STOP 76 DEVSEL# GND
75 -STOP C
GND STOP# -STOP 3,5,11 GND STOP#
3,11 -PLOCK 78 77 -PLOCK 78 77
-PLOCK -PERR LOCK# +3.3V -PERR LOCK# +3.3V
11 80 79 80 79
-PERR 82 PERR# SDONE 81 82 PERR# SDONE 81
-SERR +3.3V SBO# -SERR +3.3V SBO#
3,5,11 84 83 84 83
-SERR 86 SERR# GND 85 PAR 86 SERR# GND 85 PAR
+3.3V PAR PAR 3,5,11 +3.3V PAR
3,5,11 C_-BE1 88 87 A_D15 3,5,11 C_-BE1 88 87 A_D15
C_-BE1 C/BE#1 AD15 A_D15 C/BE#1 AD15
3,5,11 A_D14 90 89 A_D14 90 89
A_D14 AD14 +3.3V A_D13 AD14 +3.3V A_D13
92 91 A_D13 3,5,11 92 91
A_D12 GND AD13 A_D11 A_D12 GND AD13 A_D11
3,5,11 94 93 A_D11 3,5,11 94 93
A_D12 A_D10 AD12 AD11 A_D10 AD12 AD11
3,5,11 96 95 96 95
A_D10 AD10 GND A_D9 AD10 GND A_D9
98 97 A_D9 3,5,11 98 97
GND AD9 GND AD9

3,5,11 A_D8 100 99 C_-BE0 3,5,11 A_D8 100 99 C_-BE0

A_D8 AD8 C/BE#0 C_-BE0 AD8 C/BE#0
3,5,11 A_D7 102 101 A_D7 102 101
A_D7 AD7 +3.3V A_D6 AD7 +3.3V A_D6
104 103 A_D6 3,5,11 104 103
A_D5 +3.3V AD6 A_D4 A_D5 +3.3V AD6 A_D4
3,5,11 106 105 A_D4 3,5,11 106 105
A_D5 A_D3 108 AD5 AD4 107 A_D3 108 AD5 AD4 107
3,5,11 A_D3 AD3 GND AD3 GND
110 109 A_D2 3,5,11 110 109 A_D2
GND AD2 A_D2 GND AD2
3,5,11 A_D1 112 111 A_D0 3,5,11 A_D1 112 111 A_D0
A_D1 AD1 AD0 A_D0 AD1 AD0
114 113 114 113
-ACK64 +5V(I/O) +5V(I/O) -REQ64 -ACK64 +5V(I/O) +5V(I/O) -REQ64
11 116 115 -REQ64 11 11 116 115 -REQ64 11
-ACK64 ACK64# REQ64# -ACK64 ACK64# REQ64#
118 117 118 117
+5V +5V +5V +5V
120 119 120 119
+5V +5V +5V +5V
PCI-AB PCI-AB

B B

A A

XXXXX TECHNOLOGIES, INC.

Title
PCI SLOT

Size Document Number Rev

B VT5228A (Preliminary) 0.4

Date: Wednesday, January 12, 2000 Sheet 10 of 22

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

PCI3 PCI4 PCI5

-12V 2 1 +12V -12V 2 1 +12V -12V 2 1 +12V
-12V TRST# -12V TRST# -12V TRST#
4 3 4 3 4 3
VCC3 6 TCK +12V
5 VCC3 VCC3 6 TCK +12V
5 VCC3 VCC3 6 TCK +12V
5 VCC3
GND TMS GND TMS GND TMS
D 8 7 8 7 8 7 D
TDO TDI TDO TDI TDO TDI
V 10 9 V V 10 9 V V 10 9 V
12 +5V +5V
11 -INTR_C 12 +5V +5V
11 -INTR_D 12 +5V +5V
11 -INTR_A
+5V INTA# -INTR_C +5V INTA# +5V INTA#
-INTR_D 14 13 -INTR_A -INTR_A 14 13 -INTR_B -INTR_B 14 13 -INTR_C
-INTR_D INTB# INTC# -INTR_A INTB# INTC# INTB# INTC#
-INTR_B 16 15 -INTR_C 16 15 -INTR_D 16 15
-INTR_B INTD# +5V INTD# +5V INTD# +5V
18 17 18 17 18 17
PRSNT#1 RESERVED PRSNT#1 RESERVED PRSNT#1 RESERVED
20 19 20 19 20 19
22 RESERVED +5V(I/O) 21 22 RESERVED +5V(I/O) 21 22 RESERVED +5V(I/O) 21
PRSNT#2 RESERVED PRSNT#2 RESERVED PRSNT#2 RESERVED
24 23 24 23 24 23
26 GND GND 25 VCC3_SB 26 GND GND 25 VCC3_SB 26 GND GND 25 VCC3_SB
GND GND GND GND GND GND
28 27 28 27 28 27
RESERVED 3.3VAUX -PCIRST RESERVED 3.3VAUX -PCIRST RESERVED 3.3VAUX -PCIRST
30 29 -PCIRST 30 29 30 29
32 GND RST# 31 32 GND RST# 31 32 GND RST# 31
PCICLK3 CLK +5V(I/O) -GNT2 PCICLK4 CLK +5V(I/O) -GNT3 PCICLK5 CLK +5V(I/O) -GNT4
34 33 -GNT2 34 33 34 33
-REQ2 36 GND GNT 35 -REQ3 36 GND GNT 35 -REQ4 36 GND GNT 35
-REQ2 REQ# GND -PME REQ# GND -PME REQ# GND -PME
38 37 -PME 38 37 38 37
A_D31 +5V(I/O) PME# A_D30 A_D31 +5V(I/O) PME# A_D30 A_D31 +5V(I/O) PME# A_D30
40 39 A_D30 40 39 40 39
A_D31 A_D29 42 AD31 AD30 41 A_D29 42 AD31 AD30 41 A_D29 42 AD31 AD30 41
A_D29 AD29 +3.3V A_D28 AD29 +3.3V A_D28 AD29 +3.3V A_D28
44 43 A_D28 44 43 44 43
A_D27 46 GND AD28 45 A_D26 A_D27 46 GND AD28 45 A_D26 A_D27 46 GND AD28 45 A_D26
A_D27 AD27 AD26 A_D26 AD27 AD26 AD27 AD26
A_D25 48 47 A_D25 48 47 A_D25 48 47
A_D25 AD25 GND A_D24 AD25 GND A_D24 AD25 GND A_D24
50 49 A_D24 50 49 50 49
C_-BE3 52 +3.3V AD24 51 A_D21 C_-BE3 52 +3.3V AD24 51 A_D22 C_-BE3 52 +3.3V AD24 51 A_D23
C_-BE3 C/BE#3 IDSEL A_D21 C/BE#3 IDSEL C/BE#3 IDSEL
A_D23 54 53 A_D23 54 53 A_D23 54 53
A_D23 AD23 +3.3 A_D22 AD23 +3.3 A_D22 AD23 +3.3 A_D22
56 55 A_D22 56 55 56 55
A_D21 GND AD22 A_D20 A_D21 GND AD22 A_D20 A_D21 GND AD22 A_D20
58 57 A_D20 58 57 58 57
A_D21 A_D19 AD21 AD20 A_D19 AD21 AD20 A_D19 AD21 AD20
60 59 60 59 60 59
A_D19 62 AD19 GND 61 A_D18 62 AD19 GND 61 A_D18 62 AD19 GND 61 A_D18
+3.3V AD18 A_D18 +3.3V AD18 +3.3V AD18
A_D17 64 63 A_D16 A_D17 64 63 A_D16 A_D17 64 63 A_D16
A_D17 AD17 AD16 A_D16 AD17 AD16 AD17 AD16
C C_-BE2 66 65 C_-BE2 66 65 C_-BE2 66 65 C
C_-BE2 C/BE#2 +3.3V -FRAME C/BE#2 +3.3V -FRAME C/BE#2 +3.3V -FRAME
68 67 -FRAME 68 67 68 67
-IRDY GND FRAME# -IRDY GND FRAME# -IRDY GND FRAME#
70 69 70 69 70 69
-IRDY 72 IRDY# GND 71 -TRDY 72 IRDY# GND 71 -TRDY 72 IRDY# GND 71 -TRDY
+3.3V TRDY# -TRDY +3.3V TRDY# +3.3V TRDY#
-DEVSEL 74 73 -DEVSEL 74 73 -DEVSEL 74 73
-DEVSEL 76 DEVSEL# GND 75 -STOP 76 DEVSEL# GND 75 -STOP 76 DEVSEL# GND 75 -STOP
GND STOP# -STOP GND STOP# GND STOP#
-PLOCK 78 77 -PLOCK 78 77 -PLOCK 78 77
-PLOCK -PERR LOCK# +3.3V -PERR LOCK# +3.3V -PERR LOCK# +3.3V
80 79 80 79 80 79
-PERR PERR# SDONE PERR# SDONE PERR# SDONE
82 81 82 81 82 81
-SERR +3.3V SBO# -SERR +3.3V SBO# -SERR +3.3V SBO#
84 83 84 83 84 83
-SERR SERR# GND PAR SERR# GND PAR SERR# GND PAR
86 85 PAR 86 85 86 85
C_-BE1 +3.3V PAR A_D15 C_-BE1 +3.3V PAR A_D15 C_-BE1 +3.3V PAR A_D15
88 87 A_D15 88 87 88 87
C_-BE1 A_D14 C/BE#1 AD15 A_D14 C/BE#1 AD15 A_D14 C/BE#1 AD15
90 89 90 89 90 89
A_D14 92 AD14 +3.3V 91 A_D13 92 AD14 +3.3V 91 A_D13 92 AD14 +3.3V 91 A_D13
GND AD13 A_D13 GND AD13 GND AD13
A_D12 94 93 A_D11 A_D12 94 93 A_D11 A_D12 94 93 A_D11
A_D12 AD12 AD11 A_D11 AD12 AD11 AD12 AD11
A_D10 96 95 A_D10 96 95 A_D10 96 95
A_D10 AD10 GND A_D9 AD10 GND A_D9 AD10 GND A_D9
98 97 A_D9 98 97 98 97
GND AD9 GND AD9 GND AD9

A_D8 100 99 C_-BE0 A_D8 100 99 C_-BE0 A_D8 100 99 C_-BE0

A_D8 AD8 C/BE#0 C_-BE0 AD8 C/BE#0 AD8 C/BE#0
A_D7 102 101 A_D7 102 101 A_D7 102 101
A_D7 AD7 +3.3V A_D6 AD7 +3.3V A_D6 AD7 +3.3V A_D6
104 103 A_D6 104 103 104 103
A_D5 +3.3V AD6 A_D4 A_D5 +3.3V AD6 A_D4 A_D5 +3.3V AD6 A_D4
106 105 A_D4 106 105 106 105
A_D5 A_D3 AD5 AD4 A_D3 AD5 AD4 A_D3 AD5 AD4
108 107 108 107 108 107
A_D3 AD3 GND A_D2 AD3 GND A_D2 AD3 GND A_D2
110 109 A_D2 110 109 110 109
A_D1 112 GND AD2 111 A_D0 A_D1 112 GND AD2 111 A_D0 A_D1 112 GND AD2 111 A_D0
A_D1 AD1 AD0 A_D0 AD1 AD0 AD1 AD0
114 113 114 113 114 113
-ACK64 +5V(I/O) +5V(I/O) -REQ64 -ACK64 +5V(I/O) +5V(I/O) -REQ64 -ACK64 +5V(I/O) +5V(I/O) -REQ64
116 115 116 115 116 115
118 ACK64# REQ64# 117 118 ACK64# REQ64# 117 118 ACK64# REQ64# 117
B +5V +5V +5V +5V +5V +5V B
120 119 120 119 120 119
+5V +5V +5V +5V +5V +5V
PCI-AB PCI-AB PCI-AB

V
RN 8.2K V
RN56 RN 2.2K
3,10 -GNT0 1 2 RN57 V
-GNT0 -GNT3 -REQ64 -REQ1
3 4 R233 2.2K 3,10 1 2
-GNT3 -GNT2 -REQ64 -ACK64 -REQ1 -REQ0
3,11 5 6 R207 2.2K 3,10 3 4
-GNT2 -GNT1 -ACK64 -REQ0 -REQ2
RN 4.7K 3,10 7 8 3,11 5 6
-GNT1 -REQ2 -REQ3
RN58 V 3,11 7 8
-FRAME -REQ3 -REQ4
1 2 R258 3 R259 2.2K
-IRDY -GNT4 -REQ4
3 4
-TRDY -GNT4
5 6
-DEVSEL 7 8 8.2K
-STOP 1 2 V
-PLOCK 3 4 -INTR_D R204 2.2K
-PERR 5 6 -INTR_C R220 2.2K
A
-SERR 7 8 A

RN66
RN 4.7K VCC3
XXXXX TECHNOLOGIES, INC.

-INTR_B R154 2.2K

-INTR_A R155 2.2K
Title
PCI SLOT

Size Document Number Rev

B VT5228A (Preliminary) 0.4

Date: Wednesday, January 12, 2000 Sheet 11 of 22

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

VDDQ V
VCC3 VDDQ VCC3
-GFRAME RN421 2RN 8.2K VDDQ R191
-GIRDY 3 4 10K
-GDEVSEL 5 6 AGP1 +12V
-GTRDY 7 8 B1 A1
OVRCNT# +12V -TYPEDET
V B2 A2
RN411 +5V TYPEDET#
2RN 8.2K B3 A3
-PIPE 3 4 USB_D2+ B4 +5V RESERVED
A4 USB_D2-
6 USB_D2+ USB+ USB- USB_D2- 6
-RBF 5 6 B5 A5
-WBF 7 8 -INTR_B B6 GND GND
A6 -INTR_A
5,10,11 -INTR_B INTB# INTA# -INTR_A 5,10,11
D 4 GCLKO B7 A7 -PCIRST 3,5,10,11 D
GCLKO CLK RST# -PCIRST
-GSTOP RN431 2RN 8.2K 4 -GREQ B8 A8 -GGNT 4
-GREQ REQ# GNT# -GGNT
-GPERR 3 4 B9 A9
-GSERR ST0 VCC3.3 VCC3.3 ST1
5 6 4 B10 A10 ST1 4
GPAR 7 8 ST0 ST2 B11 ST0 ST1
A11
4 ST2 ST2 RESERVED
R141 4 -RBF B12 A12 -PIPE 4 VDDQ VDDQ
-RBF RBF# PIPE# -PIPE
SB_STB B13 A13
B14 GND GND
A14 -WBF
R159 -WBF 4
AD_STB1 SBA0 RESERVED WBF# SBA1
8.2K 4 B15 A15 SBA1 4
SBA0 B16 SBA0 SBA1
A16 CB30 CB29
R161
AD_STB0 SBA2 VCC3.3 VCC3.3 SBA3 .1U .1U
8.2K 4 B17 A17 SBA3 4
SBA2 SB_STB SBA2 SBA3 -SB_STB
R157 4 B18 A18 -SB_STB 4
-GGNT SB_STB SB_STB SB_STB#
8.2K B19 A19
SBA4 GND GND SBA5
R156 4 B20 A20 SBA5 4
-GREQ SBA4 SBA6 B21 SBA4 SBA5
A21 SBA7
8.2K 4 SBA7 4
SBA6 SBA6 SBA7
B22 A22
RESERVED RESERVED
8.2K B23 A23
B24 GND GND A24
RESERVED RESERVED
B25 A25
GD31 B26 VCC3.3 VCC3.3 A26 GD30 VDDQ VDDQ VDDQ VDDQ
4 GD31 AD31 AD30 GD30 4
4 GD29 B27 A27 GD28 4
GD29 AD29 AD28 GD28
B28 A28
GD27 B29 VCC3.3 VCC3.3 A29 GD26
4 GD27 AD27 AD26 GD26 4
4 GD25 B30 A30 GD24 4 CB66 CB67 CB68 CB69
GD25 AD25 AD24 GD24 .1U .1U .1U .1U
AD_STB0 C111 22P (OPT) B31 A31
AD_STB1 GND GND -AD_STB1
4 B32 A32 -AD_STB1 4
AD_STB1 AD_STB1 GD23 AD_STB1 AD_STB1# -GBE3
C121 22P (OPT) 4 B33 A33 -GBE3 4
GD23 B34 AD23 C/BE3# A34
SB_STB GD21 VDDQ VDDQ GD22
C120 22P (OPT) 4 B35 A35 GD22 4
C GD21 GD19 B36 AD21 AD22 A36 GD20 C
4 GD19 AD19 AD20 GD20 4
-AD_STB1 C122 22P (OPT) B37 A37 VDDQ VDDQ VDDQ
GD17 GND GND GD18 C167
4 B38 A38 GD18 4
-AD_STB0 GD17 -GBE2 B39 AD17 AD18 A39 GD16 XXX
C112 22P (OPT) 4 GD16 4
-GBE2 C/BE#2 AD16
B40 A40 R288
-SB_STB -GIRDY B41 VDDQ VDDQ A41 -GFRAME CB70 CB71 CB72
C110 22P (OPT) 4 -GFRAME 4
-GIRDY IRDY# FRAME# .1U .1U .1U
B42 A42
-SB_STB R158 RESERVED RESERVED
8.2K B43 A43 0
B44 GND GND A44
-AD_STB1 R160 RESERVED RESERVED
8.2K B45 A45 R287
-GDEVSEL B46 VCC3.3 VCC3.3 A46 -GTRDY
4 -GDEVSEL DEVEL# TRDY# -GTRDY 4
-AD_STB0 R162 8.2K B47 A47 -GSTOP 4
VDDQ STOP# -GSTOP
-GPERR B48 A48 0
B49 PERR# PME# A49 C166
-GSERR GND GND GPAR XXX
2,3 B50 A50 GPAR 4
-GSERR -GBE1 SERR# PAR GD15
4 B51 A51 GD15 4
-GBE1 C/BE1# AD15 VCC3
B52 A52
GD14 VDDQ VDDQ GD13
4 B53 A53 GD13 4
GD14 GD12 B54 AD14 AD13 A54 GD11
4 GD12 AD12 AD11 GD11 4
B55 A55
GD10 B56 GND GND A56 GD9
4 GD10 AD10 AD9 GD9 4
4 GD8 GD8 B57 A57 -GBE0 4 R146
AD8 C/BE0# -GBE0 150(1%)
VDDQ B58 A58
AD_STB0 B59 VDDQ VDDQ A59 -AD_STB0 2N7002
C114 4 AD_STB0 -AD_STB0 4
GD7 AD_STB0 AD_STB0# GD6
4 GD7 B60 A60 GD6 4
B61 AD7 AD6 A61
GD5 GND GND GD4 Q9
560P 4 GD5 B62 A62 GD4 4 R145 U10B
R143 R144 GD3 AD5 AD4 GD2 R147 -TYPEDET
4 GD3 B63 A63 GD2 4 3 4
1K(1%) 75(1%) B64 AD3 AD2 A64 C116 100(1%)
B
GD1 VDDQ VDDQ GD0 B
4 GD1 B65 A65 GD0 4 .1u 1K 74F04
AGP_VREF B66 AD1 AD0 A66 AGPVREF
RESERVED RESERVED AGPVREF
AGPVREF
UAGP
R163 R164
1K(1%) 75(1%) C113 C115
C123 .1U .1U

560P

VCC3
R183 VCC3

X0 CB40
D

C131 CT25 .1U

+12V Q12 .1u 1000u/6.3V
+12V VCC3 G NDP6030L
3

U11A
8

RJ2 R185 R194 VDDQ

LM358
3
+
2

1
C124 220 1K 2
.1U CB39 - CT24 CT23
R165 R195 .1U R192 CB28
X0 1K CB38 2K 1% 0.1U
4

A
D5 X0.01U A
SC431L R184

X0 XXXXX TECHNOLOGIES, INC.

D

R193
10K 1%
2N7002
G -TYPEDET Title
Q10 AGP SLOT & AGP 2X/4X MODE OPTION CIRCUIT
S

Size Document Number Rev

B VT5228A (Preliminary) 0.4

Date: Wednesday, January 12, 2000 Sheet 12 of 22

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

SL1
-IOCHCK 6
B1 A1 -IOCHCK
14 RES_DRV SD7
RES_DRV B2 A2 SD7 6,14
V SD6
B3 A3 SD6 6,14
6 IRQ9 SD5
IRQ9 B4 A4 SD5 6,14
-5V SD4
DREQ2 B5 A5 SD3 SD4 6,14
6 DREQ2 B6 A6 SD3 6,7,14
-12V SD2
B7 A7 SD2 6,7,14
-0WS SD1
-0WS B8 A8 SD1 6,7,14
+12V SD0
B9 A9 SD0 6,7,14
IOCHRDY
-SMEMW B10 A10 AEN IOCHRDY 6
D 6 D
-SMEMW B11 A11 AEN 6
6 -SMEMR SA19
-SMEMR B12 A12 SA19 6,13
6 -IOW SA18
-IOW B13 A13 SA18 6,13
6 -IOR SA17
-IOR B14 A14 SA17 6,13,14
6 -DACK3 SA16 RP5
-DACK3 DREQ3 B15 A15 SA15 SA16 6,14
6 SA15 14 4.7K 9P8R R267 V
DREQ3 -DACK1 B16 A16 SA14 SA15 -REFRESH
6 SA14 14 2 1V
-DACK1 DREQ1 B17 A17 SA13 SA14
6 SA13 14 3 R270
DREQ1 -REFRESH B18 A18 SA12 SA13 -MEMCS16
6,7 SA12 14 4 330
-REFRESH SYS_CLK B19 A19 SA11 SA12 5
6 B20 A20 SA11 14 R271
SYS_CLK IRQ7 SA10 SA11 6 -IOCS16
6 SA10 14 330
IRQ7 IRQ6 B21 A21 SA9 SA10
6 SA9 14 7 R275 330
IRQ6 IRQ5 B22 A22 SA8 SA9 -MASTER
6 SA8 14 8 330
IRQ5 IRQ4 B23 A23 SA7 SA8
6 SA7 14 9
IRQ4 IRQ3 B24 A24 SA6 SA7 2 1V
6 IRQ3 B25 A25 SA6 14
6 -DACK2 SA5 SA6 3
-DACK2 B26 A26 SA5 14 R273 1K
6 TC SA4 SA5 4 RP6 IOCHRDY
TC B27 A27 SA4 14
6 BALE SA3 SA4 5
BALE B28 A28 SA3 14 4.7K 9P8R R272 1K
V SA2 SA3 6 -0WS V
B29 A29 SA2 14
15 ISA_OSC SA1 SA2 7
ISA_OSC B30 A30 SA0 SA1 14 SA1
SA0 14 8
B31 A31 SA0 9

6 -MEMCS16 -SBHE 6
-MEMCS16 D1 C1 -SBHE
6 -IOCS16 SA23 -SBHE 2 1V
-IOCS16 IRQ10 D2 C2 SA22 SA23 6 SA23
6 SA22 6 3
IRQ10 IRQ11 D3 C3 SA21 SA22
6 SA21 6 4 RP7
IRQ11 IRQ12 D4 C4 SA20 SA21 5
6 IRQ12 D5 C5 SA20 6 4.7K 9P8R
6,14 IRQ15 SA19 SA20 6
IRQ15 D6 C6 SA19 6,13
C
6,14 IRQ14 SA18 SA19 7 C
IRQ14 D7 C7 SA18 6,13
6 -DACK0 SA17 SA18 8
-DACK0 D8 C8 SA17 6,13,14
6 DREQ0 -MEMR SA17 9
DREQ0 D9 C9 -MEMR 6,14
6 -DACK5 -MEMW -MEMW 6,14
-DACK5 DREQ5 D10 C10 SD8
6 DREQ5 D11 C11 SD8 6
6 -DACK6 SD9
-DACK6 D12 C12 SD9 6
6 DREQ6 SD10 R274
DREQ6 D13 C13 SD10 6
6 -DACK7 SD11 SA16 V
-DACK7 D14 C14 SD11 6
6 DREQ7 SD12 SD12 6
DREQ7 D15 C15 SD13
V SD13 6 4.7K
-MASTER D16 C16 SD14
-MASTER D17 C17 SD14 6
SD15
D18 C18 SD15 6
SL2

C161 68p
RP4 RP2 IRQ10
4.7K 9P8R 4.7K 9P8R
SD7 2 1V -IOCHCK 2 1V C162 68p
SD6 3 -MEMR 3 IRQ11
SD5 4 IRQ9 4
SD4 5 -MEMW 5 C163 68p
U23 SD3 6 -SMEMW 6 IRQ12
6,14 SD_D[0..15] SD_D7 2 18 SA7 SD2 7 -SMEMR 7
SD_D[0..15] SD_D6 A0 B0 SA6 SD1 -IOW
3 17 8 8 C154 68p
SD_D5 4 A1 B1 16 SA5 SD0 9 -IOR 9 IRQ5
B
SD_D4 A2 B2 SA4 B
5 15
SD_D3 6 A3 B3 14 SA3
A4 B4 C155 68p
SD_D2 7 13 SA2 IRQ9
SD_D1 A5 B5 SA1
8 12
SD_D0 9 A6 B6 11 SA0 RP9 RP8 C156 68p
A7 B7 TC
4.7K 9P8R V P9A560
-MASTER 1 SD8 2 1 DREQ0 2 1
-XOE DIR SD9
19 3 3
OE SD10 DREQ5
4 4
74F245 SD11 5 5
SD12 6 DREQ6 6
SD13 7 7
U22 SD14 8 DREQ7 8
SD_D15 2 18 SA15 SD15 9 9
SD_D14 A0 B0 SA14
3 17
SD_D13 A1 B1 SA13
4 16
SD_D12 5 A2 B2 15 SA12
SD_D11 A3 B3 SA11
6 14 R249
SD_D10 A4 B4 SA10 DREQ1
7 13 RP3
SD_D9 8 A5 B5 12 SA9 4.7K 9P8R
SD_D8 A6 B6 SA8 IRQ7
9 11 2 1 V 560
A7 B7 IRQ4 3
-MASTER 1 IRQ5 4 R264
-XOE DIR IRQ6 DREQ2
6 19 5
-XOE OE IRQ3 6
74F245 IRQ10 7 560
IRQ11 8
IRQ12 9 R260
A
DREQ3 A

560

XXXXX TECHNOLOGIES, INC.

Title
ISA SLOT

Size Document Number Rev

B VT5228A (Preliminary) 0.4

Date: Wednesday, January 12, 2000 Sheet 13 of 22

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

R277
R278
22 SPEAK 4
CSPEAK
C 2.2K
BQ14 VCC VCC
HD_LED1
C165 E 2N3904
.1U VCC VCC
CON1
1 16 R276
SP1 HDLED+ R256
D 2 17 330 C164 D
NC HDLED- HD_LED1 4.7K
3 18 470P
SP3 HDLED-
4 19
RST_SW SPVCC HDLED+
5 20
RST_SW 6 RST1 KEY 21 IRTX
RSTGND IRTX IRTX
R257 7 22
KEY IRGND IRRX
8 23 IRRX
9 PLED+ IRRX 24
330 NC NC
10 25
11 PLED- IR_VCC 26
KLOCK KEY
12 27
GND PWRBT PW_BN
13 28 PW_BN
R247 14 KEY PWRBT# 29 -EXTSMI
G_LED S3_LED -EXTSMI
330 15 30
SUSLED GND GND
SOLTEK_CON

IDE1
C
5 PD_D[0..15] -IDERST 1 2 C
PD_D[0..15] PDD7 PDD8
3 4
PD_D9 1 2 PDD9 PDD6 5 6 PDD9
PD_D7 3 4 PDD7 RN45 PDD5 7 8 PDD10
PD_D8 5 6 PDD8 PDD4 9 10 PDD11
33 8P4R
U17 PD_D7 PD_D6 7 8 PDD6 PDD3 11 12 PDD12
FROM_128KX8 PD_D13 1 2 PDD13 R124 PDD2 13 14 PDD13
SA0 12 13 XD0 PD_D2 3 4 PDD2 5.6K PDD1 15 16 PDD14
13 SA0 A0 D0 14 RN52
13 SA1 11 XD1 PD_D12 5 6 PDD12 33 8P4R V PDD0 17 18 PDD15
SA1 SA2 A1 D1 XD2 R200 PD_D3 PDD3
13 10 15 7 8 19 20
SA2 SA3 A2 D2 17 XD3 10K PD_D11 PDD11 R125 DDREQA
13 9 1 2 21 22
SA3 SA4 A3 D3 XD4 PD_D4 PDD4 1K -DIOWA
13 8 18 3 4 RN51 23 24
SA4 SA5 A4 D4 XD5 PD_D10 PDD10 -DIORA
13 7 19 5 6 33 8P4R 25 26
SA5 SA6 6 A5 D5 20 XD6 PD_D5 7 8 PDD5 HDRDYA 27 28
13 SA6 A6 D6
13 SA7 5 21 XD7 PD_D15 1 2 PDD15 R171 -DDACKA 29 30
SA7 SA8 A7 D7 PD_D0 PDD0
13 27 3 4 RN50 6,13 31 32
SA8 SA9 A8 PD_D14 PDD14 IRQ14 PDA1
13 26 5 6 33 8P4R 33 34 PD_80P 5
SA9 SA10 A9 PD_D1 PDD1 PDA0 PDA2
13 23 7 8 82 35 36
SA10 SA11 25 A10 -PDCS1 37 38 -PDCS3
13 SA11 V R149 10K
SA12 A11 -DIOWA
13 4 5 R133 33 39 40
SA12 SA13 A12 -DIOW_A -DIORA
13 28 5 R170 33
SA13 SA14 A13 -DIOR_A -DDACKA
13 29 5 R134 33 V
SA14 SA15 A14 -DDACK_A
13 3
SA15 SA16 A15 R93
6,13 2
PGO0 SA16 SA17 A16 HDRDYA 4.7K
6,13 30 5 R132 82 V D3 1N4148
SA17 NC HDRDY_A DDREQA -DASP0
5 R131 82 HD_LED1 14
1

-ROMCS 22 1 DDREQ_A R92

6 -ROMCS CE VP V
6,13 -MEMR 24 4.7K
2 3 -MEMR 31 OE -PDCS1 -DASP1 D2 1N4148
WE 5 -PDCS_1 R148 33
B B
R283 5 R123 33 -PDCS3
-PDCS_3
4.7K IDE2
U24A SD7 XD7 -IDERST 1 2
74F125 SD7 SD6 XD6 SDD7 3 4 SDD8
SD6 SD5 XD5 SDD6 SDD9
5 6
SD5 SD4 XD4 SDD5 7 8 SDD10
-MEMW SD4 SD3 XD3 SDD4 9 10 SDD11
6,13 -MEMW SD3 SD2 XD2 SDD3 11 12 SDD12
SD2 SD1 XD1 SD_D[0..15] SDD2 13 14 SDD13
SD1 6,13 SD_D[0..15]
SD0 XD0 SDD1 15 16 SDD14
SD0 SD_D15 8 7 SDD15 R122 SDD0 17 18 SDD15
RN47 V
U10C U10D SD_D0 6 5 SDD0 5.6K 19 20
SIO_RES 5 6 9 8 R182 33 SD_D14 4 3 SDD14 33 8P4R R197 DDREQB 21 22
6 SIO_RES RES_DRV 13
SD_D1 2 1 SDD1 1K -DIOWB 23 24
74F04 74F04 SD_D7 SD_D4 8 7 SDD4 -DIORB 25 26
U10E SD_D5 6 5 SDD5 RN40 HDRDYB 27 28
11 10 R181 33 -IDERST SD_D6 4 3 SDD6 33 8P4R -DDACKB 29 30
SD_D7 2 1 SDD7 6,13 R187 82 31 32
R263 SD_D11 SDD11 IRQ15 SDA1
74F04 8 7 33 34 SD_80P 5
10K SD_D10 6 5 SDD10 RN44 SDA0 35 36 SDA2
SD_D9 4 3 SDD9 V R166 10K -SDCS1 37 38 -SDCS3
SD_D8 2 1 SDD8 33 8P4R -DASP1 39 40
SD_D13 8 7 SDD13
SD_D2 6 5 SDD2 RN48
RN46 SD_D12 4 3 SDD12 33 8P4R
5 SD_A2 1 2 SDA2 SD_D3 2 1 SDD3
SD_A2 SD_A0 3 4 SDA0
5 SD_A0 SD_A1 5 6 SDA1 R168 33 -DDACKB
A 5 SD_A1 5 -DDACK_B A
7 8 5 R169 33 -DIOWB
-DIOW_B -DIORB
5 R188 33
-DIOR_B
RN 33
RN49 5 R196 82 HDRDYB XXXXX TECHNOLOGIES, INC.
PD_A2 PDA2 HDRDY_B DDREQB
5 1 2 5 R130 82
PD_A2 PD_A0 3 4 PDA0 DDREQ_B
5 PD_A0
5 PD_A1 5 6 PDA1
PD_A1 7 8 -SDCS_1 -SDCS1 Title
5 R167 33
-SDCS_1 -SDCS_3 R186 33 -SDCS3 IDE/PANEL
5 -SDCS_3
RN 33
Size Document Number Rev
B VT5228A (Preliminary) 0.4

Date: Wednesday, January 12, 2000 Sheet 14 of 22

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

CPUCLK C15 10p DCLK5 CN2 1 2

HCLK C16 10p DCLK6 3 4
R58 10K MODE CK_VDD1 DCLKO C85 10p DCLK7 5 6
DCLK8 7 8
L12 VCC3 R75 NPCLK C65 10p CN 10P
CK_VDD1 200 SPCLK C70 10p
FB PCICLK1 C72 10p DCLK1 CN1 1 2
PCICLK2 C71 10p DCLK2 3 4
C60 C50 C37 C61 C51 C55 C38 R74 PCICLK3 C67 10p DCLK3 5 6
.1u .1u .1u .1u .1u .1u .1u 10K 133-100-
D U4 PCICLK4 C66 10p DCLK4 7 8 D
1 7 R73 22 NPCLK PCICLK5 C68 10p CN 10P
VDD1 MODE/PCI_F NPCLK 3
6 8 FS3 R59 22 PCICLK4
VDD2 PCI0 PCICLK4
14 10 R76 22 SPCLK DCLK9 CN5 1 2
VDD2 PCI1 SPCLK 5
19 11 R60 22 PCICLK3 11 DCLK6 C78 X10p DCLK10 3 4
VDD3 PCI2 PCICLK2 PCICLK3 DCLK5 DCLK11
30 12 R77 22 PCICLK2 10 C76 X10p 5 6
VDD3 PCI3 PCICLK1 DCLK2 DCLK12
36 13 R78 22 PCICLK1 10 C75 X10p 7 8
27 VDD3 PCI4 PCICLK5 DCLK1
R61 22 PCICLK5 C77 X10p CN 10P
VCC2_5 VDD4 DCLKO DCLK10
L8 48 15 R79 47 DCLKO 4 C79 X10p
CK_VDD2 42 VDDL1 BUFFER IN 47 APICLK DCLK9
R28 22 APICLK 2 C80 X10p
VDDL2 IOAPIC DCLK8
FB C45 X10p
C34 C36 C33 3 38 R21 DCLK1 DCLK7 C47 X10p
.1u .1u .1u GND SDRAM0 22 DCLK1 8
9 37 R32 22 DCLK2 8 DCLK4 C44 X10p
GND SDRAM1 DCLK2
16 35 R33 22 DCLK3 8 DCLK3 C46 X10p
GND SDRAM2 DCLK3
22 34 R34 22 DCLK4 8 DCLK12 C48 X10p
GND SDRAM3 DCLK5 DCLK4 DCLK11
33 32 R22 22 DCLK5 9 C49 X10p
GND SDRAM4 DCLK6
39 31 R35 22 DCLK6 9
45 GND SDRAM5 29 DCLK7 CPUCLK
R36 22 DCLK7 9 C41 X10p
GND SDRAM6 DCLK8 HCLK
28 R37 22 DCLK8 9 C87 X10p
I2CD2 23 SDRAM7 21 DCLK9 I2CD2
5,8,9 R64 22 DCLK9 8 C29 X10p
I2CD2 I2CD1 SDATA SDRAM8 DCLK10 I2CD1
5,8,9 24 20 R63 22 DCLK10 8 C31 X10p
I2CD1 SCLK SDRAM9 DCLK11
C59 12p 18 R62 22 DCLK11 8
2

4 SDRAM10/PCISP 17 DCLK12 NPCLK

X1 R80 22 DCLK12 8 C105 X10p
X X1 SDRAM11/CPUSP DCLKWR SPCLK
14.31818MHZ 5 40 R20 22 DCLKWR 4 C146 X10p
X2 SDRAM12 41 CK_VDD1
R31 10K
FS1 SDRAM13 PCICLK1
1

C64 12p 25 C144 X10p

USBCLK FS0 24M/FS1 CPUCLK PCICLK2
6 R52 22 26 44 R29 22 CPUCLK 2 C147 X10p
USBCLK SIO_OSC 2 48M/FS0 CPU0 43 HCLK PCICLK3
6 R57 22 R30 22 HCLK 3 C152 X10p
SIO_OSC ISA_OSC FS2 REF0 CPU1 PCICLK4
13 R47 22 46 C157 X10p
C ISA_OSC REF1/FS2 PCICLK5 C
C160 X10p
ICS9148-26/-39
IC WORKS-W144
APICLK C32 10p
SIO_OSC C63 10p

CK_VDD1
USBCLK C54 10p

R48 10K FS0 ISA_OSC C35 10p

R51 10K FS1

VCC

CK_VDD1

R45
200 VCC FS1
FUSE(2) VCCE
1A
2,4 100-66- R46 10K FS2 L1
100-66-
RN2
7 8 MSCLK FB BC1
5 6 MSDATA
3 4 KBCLK .1u
B B
1 2 KBDATA
KM1A
P8S4.7K 4 6
2
L2 FB(0805) KB_DT 1
3 5

L3 FB(0805) DP_KB/MS

RN1 KB_CK
MS_CLK 1 2 MSCLK KBDATA
MS_CLK MS_DATA 3 4 MSDATA KBCLK
MS_DATA KB_CLK KBCLK MSDATA
5 6
KB_CLK KB_DATA KBDATA MSCLK
7 8 KM1B
KB_DATA
10 12
P8S0 8
L4 FB(0805) MS_DT 7
9 11

L5 FB(0805) DP_KB/MS

MS_CK

PS2_STAXKED_CONN

A A
BC5 BC4 BC2 BC3
47P 47P 47P 47P
KEYBOARD WAKE UP
XXXXX TECHNOLOGIES, INC.

Title
CLOCK SYNTHESIZER/KB WAKE UP FUNCTION

Size Document Number Rev

B VT5228A (Preliminary) 0.4

Date: Wednesday, January 12, 2000 Sheet 15 of 22

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

VCC3

CB27 CB24 CB21 CB20 CB19 CB33 CB34 CB51 CB57

VTT .1u .1u .1u .1u .1u .1u .1u .1u .1u

CB14 CB23 CM32 C69 CM28 CT13 CM11

.1u .1u 1u 1u 1u 1000u 1u CT7 CT29 CT14 CB47 CB52 CB58 CB60 CB59
100U 1000u 1000u .1u .1u .1u .1uF .1uF
D D
VCCP

CB26 CB25 CB18 CB17 CB46 CB49 CT15 CT3

CM15 CM18 CM20 CM21 CM22 CM25 .1u .1u .1u .1u .1u .1u 1000u 1000u
1u 1u 1u 1u 1u 1u

V_DIM
CM12 CM17 CM10 CM19
1u 1u 1u 1u
CM36 CM37 CM31 CM7 CM30
.1u .1u .1u .1u .1u

CM9 CM29 CM26

1u 1u 1u
VCC_CMOS

CM8 CM27 CM23 CT6

1u 1u 1u CM16 CM13 CM14 CM34 CM33 CM35 CM6
1500u
1u .1u .1u .1u .1u .1u .1u

VCC3

R27
C 4.7K C
FAN1 +12V
+12V 1 5 VDDQ
CPUFAN1
2 CT33
3
CPU_FAN VCC3
CB37 CT18 CB35
R199 .1u 1500U .1u
4.7K
FAN2
+12V 1 5
CPUFAN2 CT10
2 -12V VCC3
3 22u/25V
CASE_FAN
V
5V_SB V V R253
R255 14 RST_SW
22
4.7K
CT12 PWR1
R89 22u/25V 11 1 PWGD R254 R245
4.7K 3.3V 3.3V PW_GOOD 3,5,21
12 2 100
-12V 3.3V 1K
13 3
14 GND GND 4 R246 CT36
PS-ON 5V 2.7K C153 10u
15 5
16 GND GND 6 5V_SB .1u
-5V GND 5V
R90 C 17 7
PWRON Q7 GND GND
21 B 18 8
PWRON 2N3904
E 19 -5V PW-OK 9
B 5V 5VSB B
1K 20 10
5V 12V
POWER-ATX1
CT11 CT9
100u/25V 100U -12V

V V V

+12V
CB63 CB16 .1uF

CB48

CT8 CB36
CT28
CB5 100U CT32 22u/25V
CB6
CB22
CT34 .1U
CB61

CB53

CB62
CB44
.1U CB65
.1uF

A
CB64 A

XXXXX TECHNOLOGIEA, INC.

Title
POWER CONNECTOR / BYPASS CAPACITORS

Size Document Number Rev

B VT5228A (Preliminary) 0.4

Date: Wednesday, January 12, 2000 Sheet 16 of 22

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

2,26 VID[4..0]
VID[4..0]

D R23 D
+12V
10/0805

L6
VCC PP14
1UHCOIL
C13 C11
C3 C28 + +
1U 1U C2
1U
C12
1000P
U1 1500U/6.3V

1
7
1500U/6.3V

VCC
PGOOD
10 20 PP2 R9 C4 X104P
RT OCSET1
2.7K
R18 10(0805) Q5
24 PP3 PP4 6030LS L7
UGATE1 PP6
23 VCCP
PHASE1
3UHCOIL
C25 C27 C26 C24 C23 C83
R8 10(0805) D1 + + + + + +
22 PP5 PP1 R1 R3
LGATE1 4.99K 220
Q1
6030LS
VCC3 12 21 PP9
C VSEN2 PGND 1500U/6.3V C
3.3V 1N5817 C5
19
VSEN1 0.68UF 1500U/6.3V 1500U/6.3V
18 PP12 R4 2.4K
FB1 VCCP
VCC C6 10P 1500U/6.3V
1500U/6.3V 1500U/6.3V
Q8 17 PP7
603ALS PP10 COMP1 R2
15 R6
GATE3 PP8 1K
470U
VTT PP11 16 C7 103P 20K
R10 FB3 VID0
1.5V 6
VID0 VID1
C56 C84 5
VID1 VID2
+ + 1.87K(1%) R26 R 4
CB3 VID2 VID3 R5 NEAR CPU
13 3
.1U Q3 VOUT2 VID3 2 VID4 750K
R25

FAULT
NDS351 PP13 VID4 PP16
11 9

GND
FB2 SS VCC
R7 10K(1%)
10K(1%)

14
8

C14 HIP6018 C30 RN3

470U + R24 0.047U VID0 7 8
10K(1%) VID1 5 6
VCC2_5
2.5V SGND VID2 3 4
220U/10V SGND VID3 1 2
SGND
RN 10K
R12
VID4
SGND SGND
10K
B B

5V_SB VCC3_SB VCC3_SB

VCC3_SB
R153 5V_SB
Q17
AMS1117-5.0
56 I O
C109 VIN VOUT
CT37
GND
XXX
.1U
+ C119 R285
C118 100u XXX
G

100U

R152 D4
150 ZD3.3V(D)
R284 CM40
XXX XXX

A A

XXXXX COMPUTER INC.

Title
VIA 82C694X

Size Document Number Rev

B SWITCH REGULATOR FOR VRM 0A

Date: Wednesday, January 12, 2000 Sheet 17 of 22

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

COM1, COM2 AND IR

with Bipolar drivers and receivers

VCC
U13
20 1 +12V
VCC VCC1
6 TXD1 16 5
TXD1 RTS1 DA1 DY1
6 15 6
RTS1 DTR1 DA2 DY2
D 6 13 8 PCC1B D
6
DTR1
DCD1
DCD1 19
DA3
RY1
DY3
RA1
2
26 31
COM1
6 RXD1 18 3
RXD1 DSR1 RY2 RA2 27 32
6 17 4
DSR1 CTS1 14 RY3 RA3 7 28 33
6 CTS1 RY4 RA4 29 34 -XRI1 9
6 RI1 RI1 12 9
RY5 RA5 30
11 10 -12V LPT-CC

2
4
6
8

8
6
4
2
GND VCC2
GD75232 -12V CN4
CN 100P
CN3
VCC +12V

1
3
5
7

7
5
3
1
U15
20 1 +12V
VCC VCC1 CN 100P
6 TXD2 16 5
TXD2 RTS2 DA1 DY1
6 15 6
RTS2 DTR2 13 DA2 DY2 8
6 PCC1C
6
DTR2
DCD2
DCD2 19
DA3
RY1
DY3
RA1
2
35 40
COM2
6 RXD2 18 3
RXD2 DSR2 17 RY2 RA2 4 36 41
6 DSR2 RY3 RA3 37 42
6 CTS2 14 7 9
CTS2 RY4 RA4 38 43 -XRI2
6 RI2 RI2 12 9
RY5 RA5 39
11 10 -12V LPT-CC

2
4
6
8

2
4
6
8
GND VCC2
GD75232
C C

CN10 CN11

1
3
5
7

1
3
5
7
JP200
1 2
CN 100P CN 100P CON-2
GND FOR SYSTEM GND FOR KEYBOARD,MOUSE,
VCC USB,COM,LPT,GAME.
7
5
3
1

7
5
3
1

1
3
5
7

7
5
3
1
RN16 RN19 RN22 RN14 R94
8P4R 2K 8P4R 2K 8P4R 2K 8P4R 2K 2K
PRINTER
8
6
4
2

8
6
4
2

2
4
6
8

8
6
4
2
6 ERROR
P_ERROR
RN54
6 1 2
P_AUTOFD 3 4
6 P_INIT
6 5 6 INIT
P_SLCTIN 7 8 AUTOFD
B 6 P_STROBE B
SLCTIN
8P4R 33 STROBE
RN55 PCC1A
6 P_PRD7 1 2
P_PRD7 P_PRD3 3 4 PRD0 1 14
6 P_PRD3 2 15
6 P_PRD2 5 6 PRD1
P_PRD2 P_PRD4 7 8 PRD2 3 16
6 P_PRD4 4 17
PRD3
PRD4 5 18
8P4R 33
PRD5 6 19
PRD6 7 20
PRD7 8 21
9 22
RN53
P_PRD6 10 23
6 7 8
P_PRD6 P_PRD1 11 24
6 5 6
P_PRD1 P_PRD5 12 25
6 3 4
P_PRD5 P_PRD0 1 2 13
6 P_PRD0
LPT-CC
8P4R 33
P_ACK
P_BUSY
P_PE
P_SLCT
C82
6
2
4
6
8

2
4
6
8

2
4
6
8

2
4
6
8

P_ACK 180PF
6 P_BUSY
6 P_PE
6 P_SLCT
A CN7 CN8 CN9 CN6 A
1
3
5
7

1
3
5
7

1
3
5
7

1
3
5
7

XXXXX TECHNOLOGIES, INC.

CN 180P CN 180P CN 180P CN 180P

Title
PRINTER / COM PORT

Size Document Number Rev

B VT5228A (Preliminary) 0.4

Date: Wednesday, January 12, 2000 Sheet 18 of 22

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

CD_IN1
WAFER-4
1 R175 C128 1u CDL
2 4.7K
3 VCC3 AVDD5 VDD5
4 R172 C126 1u CDR U12
CD_IN 4.7K
L25 1
DVDD1 AVDD1
25 L23
FB 9 38 FB
R173 R174 CB43 DVDD2 AVDD2
CD_IN2 4.7K CT27 CT26 CM38 CM39 CB41 CT22
CON-4\79 4.7K
1 C127 1u CDGND 100U 100U .1u 1u 4 26 1u .1u 100U
2 7 DVSS1 AVSS1 42
DVSS2 AVSS2
D 3 D
4 C168 GND_AUD
47 R202 4.7K
EAPD
JP5 5,20 10 48
1 SYNC 8 SYNC CHAIN_CLK/NC GND_AUD
xxx SDATA_IN
RJ3 JP9 R203
GSLM1C GND_AUD 2 5,20 5 46 3 1
LINE_R SDIN SDOUT SDATA_OUT CS1/ID1
27 R115 C107 1u 3 5,20 11 45 2 2
-ACRST RESET CS0/ID0
26 1K 5 6 1 3 4.7K
BITCLK BIT_CLK LINEOUTL
25 35
LINE_IN 24 R117 C102 1u LINE_L
SDIN_B
LINE_OUT_L
23 1K 14 36 LINEOUTR
AUX_L LINE_OUT_R
15
R116 AUX_R 37
GAME-AUDIO R126
4.7K (ADI) 4.7K (ADI) MONO_OUT 10u (VIA)
CT20
30K (VIA) 30K (VIA) 16 28
VIDEO_L VREFOUT .1u (VIA) GND_AUD
xxx 17 C132
GND_AUD VIDEO_R
C169 27
GND_AUD VREF
CB42 CT21
CDL 18 31 C136 1u (ADI)
CDR 20 CD_L FILT_R/NC 32 .1u 47u
C134 1u (ADI) L24
CDGND CD_R FILT_L/NC
19 33
SPEAK R198 CD_GND RX3D/NC C138
5,14,20 C130 X1u PC_BEEP 34 FB
SPEAK CX3D/NC C140 GND_AUD
X1K .047u (ADI)
LINE_L 23 39 .1u (ADI)
LINE_R 24 LINE_IN_L NC 40
R201 C137
SPEAK_IN X4.7K
X1000p
LINE_IN_R NC
NC
41
43 GND_AUD
PC_BEEP 12 NC 44
GND_AUD MICIN PC_BEEP NC
21
C VDD5 22 MIC1 29 C
R127 L22
PHONE MIC2 AFILT1
20 13 30
PHONE PHONE_IN AFILT2
FB C133 C135
C104 5.1K 2 3
100P XTL_IN XTL_OUT 560p (ADI) 560p (ADI)
GSLM1B
22 ADI1881/VT1661A 270p (VIA) 270p (VIA)
21 GND_AUD R119 (0805) (0805)
20 5.1K GND_AUD
L21
MIC_IN 19 C103 1u MICIN
18 FB(0805) 1 2
C108 220 X2 X
GAME-AUDIO 100P C143 C142
R118 24.576MHZ
22p 22p
GND_AUD
C170

VDD5 xxx
VDD5 R190 20K(1%) GND_AUD

C125 100p
R176 U9
10K GSLM1D
L19
LINE_OUT LINEOUTR C141 1u R189 20K(1%) 2
INA OUTA
1 CT17 470uF 32
5 8 FB(0805) 31
SDN VAA
3 4 L20 30
LINEOUTL BYPASS GND
C139 1u R151 20K(1%) 6 7 CT16 470uF 29
R177 INB OUTB 28
B
FB(0805) B
10K CB31 C101 C98
2308 GAME-AUDIO
C117 100p .1u 470p 470p
GND_AUD
R113 4.7K R150 20K(1%) GND_AUD GND_AUD
C171
GAME PORT R112 4.7K
R101 4.7K
xxx
R103 4.7K GND_AUD
V

R109
4.7K GSLM1A +12V Q11 VDD5
L18
V VCC_JOY 1 78L05
FB 9 I O
JAB1 VIN VOUT
5 2
JAB1 JBB1 CB1
10

GND
5 JBB1
5 JACX R111 2K JACX_ 3 CB32 CT19
JACX JBCX JBCX_ .1u
5 R110 2K 11
JBCX .1u 10u
4

G
5 MSO MSO 12
5
5 JBCY R105 2K JBCY_ 13
JBCY JACY JACY_ 6
5 R104 2K
JACY JBB2 14
5 JBB2
A 5 JAB2 7 A
JAB2 MSI
5 15
MSI
8
C99 C97
C100 C96 C89 GAME-AUDIO XXXXX TECHNOLOGIES, INC.
C92 C94
C90 C93 .1u
L17 100p .01u
FB Title
GND_MIDI AC97 AUDIO CODEC & AUDIO PORTS

Size Document Number Rev

B VT5228A (Preliminary) 1.4

Date: Wednesday, January 12, 2000 Sheet 19 of 22

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D

AMR1
B1 A1 C129
AUDIO_MUTE AUDIO_PWRDN
B2 A2 PHONE 19
C B3 GND MONO_PHONE
A3 C
5,14,19 SPEAK MONO_OUT/PC_BEEP RESERVED
GND_AUD B4 A4 1u
RESERVED RESERVED AMR_VCC3 VCC3_SB AMR_VCC 5V_SB
B5 A5
-12V B6 RESERVED RESERVED A6 AMR_VCC
PRIMARY_DN GND
B7 A7
+12V B8 -12V +5VDUAL/+5VSB A8
GND USB_OC OVER_C2 6,7
B9 A9
+12V GND
B10 A10 USB_D3+ 6
B11 GND USB+ A11
V +5VD USB- USB_D3- 6

B12 A12
GND GND
B13 A13
VCC3 B14 RESERVED S/P-DIF_IN A14 AMR_VCC3
RESERVED GND
B15 A15
B16 +3.3VD +3.3VDUAL/+3.3VSB A16
SDOUT GND GND SYNC
5,19 B17 A17 SYNC 5,19
SDOUT -ACRST AC97_SDATA_OUT AC97_SYNC
5,19 B18 A18
-ACRST B19 AC97_RESET GND A19 SDIN2
AC97_SDATA_IN3 R135 22 SDIN2 5
AC97_SDATA_IN1
B20 A20
GND GND SDIN_B
B21 A21 R137 22 5
AC97_SDATA_IN2 AC97_SDATA_IN0 SDIN_B
B22 A22
GND GND BITCLK
B23 A23 R140 22 BITCLK 5
AC97_MSTRCLK AC97_BITCLK
AMR

R136 R138 R139

B 10K (OPT) B
10K (OPT) 10K (OPT)

A A

XXXXX TECHNOLOGIES, INC.

Title
AMR SLOT

Size Document Number Rev

B VT5228A (Preliminary) 0.4

Date: Wednesday, January 12, 2000 Sheet 20 of 22

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

For STR function

5V_SB

5V_SB
14 V_DIM

14
2
5,21 -RSMRST 9 1 V3SB
-RSMRST
D 8 3 D
10
5V_SB
U19C U16A Q2
74F00 74F02 NDS351

14
5V_SB
3,5,16 12
PW_GOOD
11
-STR

14
13 U14A

4
+12V
U19D 2 5
74F00 D P Q VCC3
3 6 R219 U2
C Q 1 8
5V_SB S D
74HCT74 10K 2 7
S D

1
14
R227 3 6
S D
4 4 5
1K G D
6 5V_SB 5V_SB
5,21 5 FDS6670A
-SUSC
U19B 14 14 C
74F00 8 5 RJ4 B Q13
10 4 3 EMMBT3904
9 6 2 -STR C10 C81
5 -SUSB
1
1000u 1000u
U16C U16B
5V_SB
74F02 74F02
STR FUNCTION: 1-2 DISABLE
2-3 ENABLE
C
5V_SB 5V_SB C
14

1 14
3 11
2 13 PWRON 16,21
12
U19A
74F00
U16D
74F02

Q4 V3SB
2
VOUT
R13
5V_SB 54.9(1%)

14
10
3 1 U14B
VIN ADJ
+ C8 R228 JP8 4 CKE0 S9 CKE_0 8,21
LT1087 1000u/6.3V 5V_SB 12 9 3 4 S5 CKE_1 8,21
D P Q CKE1
1.5K 2 -RSMRST 4 S8 CKE_2 8,21
C9 CM1 R14 CKE2
5,14 11 8 R229 1 4 S7 CKE_3 8,21
100U 1u 100(1%) PW_BN C Q CKE3
4 CKE4 S11 CKE_4 9,21
74HCT74 3.3K 4 S3 9,21
13

CKE5 CKE_5

R205 C145
B VCC3_SB B
22K 1u

V_DIM

VCC3 V_DIM S10 8,21

CKE_0
S2 CKE_1 8,21
R15 0 (OPT) S6 8,21
CKE_2
S4 CKE_3 8,21
S12 CKE_4 9,21
R17 0 (OPT) S1 CKE_5 9,21

R19 0 (OPT)

R16 0 (OPT)

A
R11 0 (OPT) A

5,21 R232 0 (OPT)

-SUSC PWRON 16,21
XXXXX TECHNOLOGIES, INC.

For NON-STR function

Title
STR OPTION CIRCUIT

Size Document Number Rev

B VT5228A (Preliminary) 0.4

Date: Wednesday, January 12, 2000 Sheet 21 of 22

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

VTT

D D

CM41 CM42 CM43 C173 C174 CB7 CB11 CB2 CB4 CB8 CB10 CB9 CB12 CB13
.1U .1U .1U .1U .1U .1U .1U .1U .1U .1U .1U .1U .1U .1U

VTT
VTT VTT
VTT
C RN31 C
RN8 RN23 8 7 R87
A23
8 7 8 7 6 5
D60 6 5 D26 6 5 A20 4 3 -CPURST
D50 D25 A24
4 3 4 3 2 1 56
D61 2 1 D33 2 1 A30
D56 D19
56X4
56X4 56X4 RN30 RN5
RN9 RN24 8 7 1 2
A27 -ADS
8 7 8 7 6 5 3 4
D46 D16 A29 -BREQ0
6 5 6 5 4 3 5 6
D53 D21 A18 -RS2
4 3 4 3 2 1 7 8
D58 D23 A26 -DRDY
2 1 2 1
D62 D24
56X4 56X4
56X4 56X4 RN32 RN6
RN11 RN25 8 7 1 2
A19 -DBSY
8 7 8 7 6 5 3 4
D63 D20 A31 -RS0
6 5 6 5 4 3 5 6
D57 4 3 D3 4 3 A22 2 1 -HTRDY 7 8
D55 D7 A17 -HIT
2 1 2 1
D54 D30
56X4 56X4
56X4 56X4 RN33
RN13 RN26 8 7
A28
8 7 8 7 6 5 RN7
D40 D2 A10
6 5 6 5 4 3 1 2
D52 D14 A21 -RS1
4 3 4 3 2 1 3 4
D48 2 1 D11 2 1 A25 -HITM 5 6
D59 D13 -HREQ2
56X4 7 8
-HLOCK
56X4 56X4 RN34
B B
RN15 RN27 8 7 56X4
A16
8 7 8 7 6 5
D51 6 5 D10 6 5 A12 4 3 RN10
D49 D12 A13
4 3 4 3 2 1 1 2
D41 2 1 D18 2 1 A15 -HREQ3 3 4
D47 D9 -DEFER
56X4 5 6
-HREQ0 7 8
56X4 56X4 RN35
RN17 RN28 8 7 -HREQ4
A9
8 7 8 7 6 5 56X4
D45 6 5 D1 6 5 A6 4 3
D44 D5 A3
4 3 4 3 2 1
D42 2 1 D8 2 1 A5
D27 D17 VCC_CMOS
56X4
56X4 56X4 RN36
RN18 RN29 8 7 RP1
A14
8 7 8 7 6 5 1 2
D38 6 5 D0 6 5 A4 4 3 INTR 3 4
D36 D6 A8 NMI
4 3 4 3 2 1 5 6
D37 D15 A11 -IGNNE
2 1 2 1 7 8
D39 D4 -A20M
56X4
56X4 56X4 RN37 150X4
RN20 8 7
-BPRI
8 7 6 5
D28 -HREQ1
6 5 4 3
D22 -BNR VCC2_5
4 3 2 1
D34 A7
2 1
D43
56X4
56X4 R106
A RN21 A
VCCP_GD
8 7
D35
6 5 330
D32
4 3
D29 2 1
D31 XXXXXX COMPUTER INC
56X4

Title
694X

Size Document Number Rev

B GTL+ BUS

Date: Wednesday, January 12, 2000 Sheet 22 of 22

8 7 6 5 4 3 2 1