3 TO 8 DECODER USING 2TO4 DECODER

AIM:-To write and test the VHDL code of 3TO 8 DECODER, USING 2 TO 4 DECODER.

THEORY:-
Discrete quantities of information are represented in digital system with binary codes. A binary code of n
bits is capable of representing up to 2n distinct elements of the coded information. A decoder is a
combinational circuit that converts binary information from n input line to a maximum of 2n unique
output lines. If the n-bit decoded information has unused or don’t care combination, the decoder output
will have less than 2n outputs.

TOP LEVEL ENTITY NAME IS “decoder3to8”.

BLOCK DIAGRAM:-
FUNCTION TABLE:-

I2 I1 I0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0

 VHDL CODE

 BEHAVIOR MODEL
library ieee;
use ieee.std_logic_1164.all;
entity decoder3to8 is
port(I:in std_logic_vector(2 downto 0);
D:buffer std_logic_vector(0 to 7)
);
end decoder3to8;
architecture struct of decoder3to8 is
component decoder2to4 is
port(I:in std_logic_vector(1 downto 0);
D:buffer std_logic_vector(0 to 3);
en:in std_logic
);
end component;
begin
D0:decoder2to4 port map(I(2 downto 1),D(0 to 3),not I(0));
D1:decoder2to4 port map(I(2 downto 1),D(4 to 7), I(0));
end struct;
library ieee;
--PROGRAM OF 2TO4 DECODER-----------

use ieee.std_logic_1164.all;
entity decoder2to4 is
port(I:in std_logic_vector(1 downto 0);
D:buffer std_logic_vector(0 to 3);
en:in std_logic
);
end decoder2to4;
architecture beh of decoder2to4 is
begin
process(I,D,en)
begin
if en='1' then
case I is
when "00" =>
D<="1000";
when "01" =>
D<="0100";
when "10" =>
D<="0010";
when "11" =>
D<="0001";
end case;
else
D<="0000";
end if;
end process;
end beh;
 RTL VIEW OF 3 TO 8 DECODER USING 2 TO 4 DECODER

 SIMULATION RESULTS

 TIMING ANALYZER SUMMARY

  CONCLUSIONS:-

The 3 TO 8 DECODER has been implemented using VHDL code and the wave forms obtained are
observed. The worst case tpd actual time of decoder is 12.421ns.Also we can implement the higher
decoder using 3 to 8 or 2 to 4 decoder.