ETEC102 Assignment / Quiz 4

4-bit parallel adder

Total points: 10
Due date: December 3rd, 2010

Design a 4-bit parallel adder using the full-adder concept learned in class. To
get full mark, you will need to submit the following deliverables to
demonstrate that you understand arithmetic operation, logic design,
simulation, hardware, and VHDL.

• Truth table of full adder and 4-bit adder

• Schematic / block diagram of the full adder and 4-bit adder logic blocks
• VHDL that describes both the full adder and 4-bit adder
• At least 4-5 test cases to add two 4-bit binary numbers
• Simulation waveforms that demonstrate the above test cases. The
waveforms can be generated by Quartus 2 software or from other
simulator that you are familiar with
• If you choose to test your design in hardware (it’s a preferred choice!),
you can use the Altera board available in the lab and demonstrate the
addition operation to your instructor during open lab hours on Thursdays
from 12:30-2:20.

Bonus (2 points)
Modify the 4-bit adder to subtract two 4-bit binary numbers.