Sei sulla pagina 1di 3

ARM instructions must be

The condition code flags all in the top four bits of the register?
Exceptions are used to handle_________ events which arise during the execution of a program
The instruction is fetched from memory & placed in the ________
The ARM normally executes instruction from _____ addresses in memory
_____ is the difference between address of the target & the address of the branch instruction plus 8
To resolve data dependencies without stalling the pipeline is to introduce_____ paths
______ interrupt is also called a supervisior call
The ARM data processing instructions are used to modify_____ values in register
The ARM datapath is laid out to _____ pitch per bit
The thumb decompressor perform a static translation from _______ into ARM instruction
Breakpoint instructions are used for software_____ purposes
A data processing instruction requires
The ARM920T &ARM940T are leased upon the ______processor core
ARM810 is a high performance ARM CPU chip with an on-chip cache and _____
The major block on the ARM datapath is _____
Most thumb instructions are executed ________
The ARM7TDMI coprocesor interface is based on ______ technique
In a virtual memory system______ used pages are held on disc
ARM processor allow the memory system to fault on any______
word-aligned Address Aligned Data Aligned Memory Aligned
N&Z C&V n A&B
Expected Events unexpected events Triggered Events Clocked Events
Instruction pipeline Memory Pipeline Address Pipeline Data Pipeline
Sequential word Combinational word Synchronous Word Asynchronous word
Null Offset Onset All the above
Reversing path Direct Indirect forwarding
Hardware Software Clock Reset
Data Address Register Memory
Infinity Zero Iunity Constant
Thumb Instruction Thumb breakdown instruction Thumb data Thumb address
Bugging debugging Trouble shooting All the above
One operand Two Operands Four operands Six operands
ARM9TDMi ARM810TDMI ARM7TDMI None of these
Memory Management Unit Alu Register bank AMBA interface
Register Bank Address bank Memory bank Data bank
Conditionally Unconditionally Temporarily Permanently
Bus Watching Pipelining Parallel processing None of these
Infrequently Frequently Temporarily Permanently
Memory acess Data access Address access Control access
Word-aligned
N
Unexpected Events
Instruction Pipeline
Sequential word
Offset
Forwarding
Software
Data
Constant
Thumb instruction
debugging
Two Operands
ARM9TDMi
Memory Management Unit
Register Bank
Unconditionally
Bus watching
Infrequently
Memory acess

Potrebbero piacerti anche