Reg. No.

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Question Paper Code: J7602

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M.E. DEGREE EXAMINATION, JUNE 2010

First Semester

Applied Electornics

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AP9212 — ADVANCED DIGITAL SYSTEM DESIGN

(Common to M.E. VLSI Design)

(Regulation 2009)

Time : Three hours Maximum : 100 Marks

Answer ALL Questions

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PART A — (10 × 2 = 20 Marks)
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1. State the difference between Mealy and Moore state machine.

2. What are the basic building blocks of an ASM chart?

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3. What are races and cycles?

4. What is a Static hazard? Give example.

5. What is a Stuck-at fault?

6. State any two properties of Boolean difference.

7. What is the difference between PLA and PAL?

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8. Which programming technology is used in Xilmx 4000 serices FPGA?

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9. Give an example for the process statement.

10. Write a VHDL code to describe a 2 × 1 multiplexer using behavioural model.

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 PART B — (5 × 16 = 80 Marks)

11. (a) (i) With an example explain the state assignment rules. (6)

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(ii) Determine the minimal state equivalent of the state table given. (10)
Present

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Next State/ Output
State
Input Input
x=o x=1
q q /1 q /0
0 0 4

q q /0 q /0

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1 0 4

q2 q1/0 q5/0

q3 q1/0 q5/0

q4 q2/0 q6/1

q5 q2/0 q6/1

q6 q3/0 q7/1

q7 q3/0 q7/1

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Or
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(b) Design a serial adder using mealy model and Moore model. Also draw the
ASM chart for both the models. (16)

12. (a) Design an asynchronous sequential circuit that has two inputs X2 and X1
and one output Z. When X1 = 0, the output Z is 0. The first change in X2
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that occurs while X1 is 1 will cause output Z to be 1. The output Z

remains at 1 until X1 returns to 0. (16)
Or

(b) (i) Give an example for the mixed operating mode asynchronous
sequential circuit and explain. (6)

(ii) Determine whether the following state table contains essential

hazards or not. (10)
Present Next State Output
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State Z
Input Input
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X=0 X=1
A A B 0
B B C 0
C C D 0
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D D A 1

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13. (a) (i) Derive the test vector to detect the stuck-at-0 fault at line 3 of the
following logic circuit using path sensitization method. (8)

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(ii) With an example explain the Boolean difference method. (8)

Or

(b) (i) With an example explain the D-algorithm. (10)

(ii)

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Briefly explain the Built-In-Self-Test method. (6)
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14. (a) Design a 4-bit serial - in, serial - out shift register and implement it using
suitable sequential PAL. (16)

Or
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(b) Explain in detail the CLB and I/O block of a Xilinx 4000 series FPGA. (16)

15. (a) (i) Write a VHDL code to realise a 4-bit parallel adder using structural
modeling. (10)

(ii) Write a note on Compilation and Simulation of a VHDL code. (6)

Or

(b) Write a VHDL code to realise a 3 × 3 multiplier and a test bench to test
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its functionality. (16)

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