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e23Slab.doc

EEE 235 EE(II)S

Laboratory Organisation 2001 (revised 12th March 2001) Lab. 9.00 AM

1 st Lab Week = Wed 14 March 2001 Each Group does 2 labs. (i.e. 2 out of four sessions) See rota below for which mornings.

Dates of the 4 labs.

Wed. 9:00-12:00

14 March 2001 21 March 2001 25 April 2001

2 May 200

Lab. rota: Group number in table.

March 14 March 21 April 25 i}. May 2 ("3-J.S- Code Title Floor
Groups 1-12 Groups 13-25 Groups I-hff Groups 1.~9
1-6 13-18 7-12 19-25 0 "Op Amp" Floor 2
7-12 19-25 1-6 13-18 L "Logic" Floor 2 KEY

Code Experiment Full Title

Short Title

o = Operational Amplifier Principles L = Basic Logic Circuits

"Op Amp" "Logic"

L, 0, in E2.04 Floor 2 "Part I Lab"

Directions:

In EEE Merz Court building

E2.04 Floor 2 "Part I Lab" 0, L, experiments

Up to Floor 2, go through swing doors, tum left and go down corridor into lab directly ahead through further set of swing doors.

e2351ab.doc

Summary Report Submission

EEE 235 EE(II) Laboratories

A short written report. One satisfactory report submitted, plus a satisfactory attendance and laboratory log book (on request only). Only if unsatisfactory further reports. No report = zero mark for lab; poor attendance = reduced mark. Normal submission lab week 3 (Tues. 24th April, Wed. 25th Apri12001), on the first experiment done.

A separatejirmly bound (stapled or similar, not just a paper clip) report is required, i.e. not to be written in the log book. Front (outside) cover page to state at minimum:

students name,

course (Mech., Marine, Stage II, etc.), experiment title,

"For attention of Prof. Finch", date of experiment,

date of submission.

The usual report content will consist of:

Results, Graphs, Calculations, Discussion, and Conclusion. Contents of the lab sheet assumed. Most important section: is discussion, but great length is not expected.

Handed in person to the member of staff in charge, normally Prof JW Finch or Dr Russell, at the Laboratory or lecture session. Do not leave on bench, etc!

Lab. diaries available for inspection, and may be assessed. Separate bound lab diary for EEE labs. may be convenient.

JW Finch

12th March 2001

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CIRCUIT

MAKIN~ C HA NG.E5 Tl:I T1-IE

AND CHe:CI<: TH= CI~CVIT BEFORE .sWITCHING ON THE 5UI"PI..'r'_

UNiVERSITY OF NEWCASTLE UPON TYNE

DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING

EXPERIMENT NO. DEI1- 2000

BASIC LOGIC CIRCUITS

Bv the end of this Experiment yOU should be able to:

1. Use the L T3~5 Logic Tutor

2. Connect up basic logic circuits and record what happens.

3. Understand the difference between combinational and sequential logic

I. Equipment

You are provided with an L T345 Logic Tutor on which you should build all the circuits in this experiment. The LT345 is completely self-contained with its own power supply and display devices. Firstly, spend 5 minutes learning how it works by performing the simple exercises below:

a) First check and identify the correct components:

Type Number
-t-input AND gate 3
-l.-input OR gate 3
~-inIlut NAND Eate 4
-t-input NOR gate 2
NOT gate 6
2-inpu! AND _g_ate 3
2-input OR gate 3
J -K flip-flop 4-
LED displays (LP 1 to LP4) ~ Built in to the Logic Tutor are:

a number of slide switches (S I to S4)

a change-over switch (S5 - contacts not bounce free)

a second change-over switch (S6 - with latching circuit incorporated to eliminate contact bounce)

Binary-decimal decoder and seven segment display.

b) Connect up the 4-input logic gates (circuit symbols for the equivalent 2-input gates shown below) using S 1 to S-l. as the inputs and LP 1 as the output. Record the output for all 16 possible combinations of the ~inputs. Repeat for all the gates.

]

:·0·.··'.··'·.·

,'.'

"

c) Connect the switches S I to S4 to the inputs of the binary-decimal decoder and seven-segment display.

The a-input represents the first binary digit the b-input presents the second binary digit (powers of 2). the c-input represents the thrd binary digit (powers of 4) and the d-input represents the fourth binary digit (powers of 8) of a 4-bit binary number. TIle display should show the sum {a+b+c+d). Check that this occurs by counting through the binary sequence 0000 to 1111. Note that the display shows 8 if the inputs are not connected and shows blank ifa+b+c+d > 9.

•.· .. i .... ]

i

2. Boolean Algebra and DeMorgan's Laws

In this section, you need to construct logic circuits to prove that logic expressions are true. This is done by constructing a circuit for each side of the logic expression and then checking that the both circuits give the same outputs for all possible combinations of the inputs.

A +B.C = (A +B).(A +C)

ovo ()O f 010 U I! (00

10 (

r ({)

! ( 1

(A +B).(A +C) ~

o et G I

r ,

a) Show that

The two sides of the equation can be checked by constructing

A+B.C=>

A B

B

c

c

Connect up the circuits and record the outputs of each for all 9 possible combinations of the inputs. Is the equation correct?

b) By constructing the two circuits below. show that

(A + B).(C + D) = AB -i- C.D

,I .~

II

1:-1

3. Exclusive OR gate

Consider the two alternate logic statements for an Exclusive-OR gate below:

OR==AB+AB

OR == (AB).(A +B)

Draw circuit diagrams for these circuits and then construct them. Confirm that they both give the expected performance of an Exclusive-Oft gate.

:]

4. Half-Adder

A Half-Adder is a circuit that adds together two binary digits to give the Sum and the Carry, e.g. :

2b DOVQ a 0
o o U I 0 0
vUIO ( {
U U l I 0 o
o ! (J o 0 I
U I U I 0
() I I 0 I
o I I I I
( 0 Q 0 0
U 0 1- 0
V!<J
o I I D
I o o o
! I) t o
Iv I
I I I 0 +

Carry Out

I

t

o

'"

Sum

The Swn and the Carry can be computed using the simple logic expressions (see Stage 1 Digital Electronics notes):

Sum == AB+ AB

Carry/lui = A.B

To compute both of these. either of the circuits below can be used:

A B

CarryOut

A B

CarryOut

Construct both these circuits for the Half-Adder circuit Check that both circuits perform correctly using all possible combinations of the inputs.

5. FuIl-Adder

A Full-Adder is a circuit that adds two binary digits and a CarryIn digit together (this is useful when adding together larger numbers. e.g. two 8·bit numbers).

1 ....... 1---- 1

I + 1

'"

Sum

Carry In

I

t

Carry Out

As you might expect, a Full Adder can be constructed from two Half-Adders (see circuit below):

]

SUMl

A

lI2 Adder 1

CoutI

B

]

SUM

112 Adder 2

CarryOut

Carry In

J

Construct a Full-Adder and confirm that it performs correctly for all 9 possible combinations of the inputs.

J

=

CK (Input)

]

CLR

6. J-K Flip-flop, Counter and Shift Register

A flip-flop is an example of a sequential logic circuit. This is a circuit whose output depends not just on the input states but the order and past history of the inputs. The most common type of flip-flop is the J-K flip-flop shown below:

Pre

I
v
J Q

~ CK

K Q
n
I Connect:

Pre: SI Clr: S4 J: S2 K: $3 CK:$6 Q: LPI Q :LP2

CLR

a) Connect up the J-K flip-flop as shown above. The Clear (Clr) pin can be used to make Q=O by applying 0 to Clr (via S4). The Preset pin (Pre) can be used to make Q= I by applying 0 to Pre (via S 1). Now deactivate both the Clr and Pre pins by setting both S I and S4 to 1.

b) Set J=O and K=O and apply a Clock pulse by pressing S6 and releasing. Record in your lab book what you observe.

c) Repeat with J=O and K=I and apply a Clock pulse by pressing S6 and releasing. Record in your lab book what you observe.

d) Repeat with J= 1 and K =0 and apply a Clock pulse by pressing S6 and releasing. Record in your lab book what you observe.

e) Set J= 1 and K= L Now pulse CK repeatedly (slowly) and record what you observe.

7. Asynchronous Counter

a) Now use the other 1-K flip-flops to connect up the circuit shown below:

LPI

LP2

LP3

LP4

- JA QA H JB ,. 1c U
- QB - Qc I- 1D QD
---I ,...

- K", KB - Kc - KD
-
n 0 _Q 0
Connect the Clock (CK) to 56 and Clear (Clr) to S5b. The J and K inputs should be connected to the +Ve connection of the power supply (logic high).

This circuit is an example of an Asynchronous Counter (it is called Asynchronous because there is no global clock that drives all the flip-flops together - each flip-flop is clocked by the previous one in the chain). The counter should count from 0 to 1111 (15 in decimal) as the clock pin is pulsed.

£14$

:;$& x UUAU

' 'j .

. 'C,

]

]

J

I

The S6 switch incorporates a special latch circuit (known as a R-S flip-flop) which prevents what is known as switch bouncing (this occurs when the switch contacts do not operate cleanly but bounce on/off repeatedly as the switch is opened or closed). You can see the benefit of this by changing the CK connection to S5a (after removing the CIr lin from S5b). Try to make the counter go through the sequence with S5a - you should find that the sequence becomes random and disrupted because of the poor quality of the Clock signal from S5a

b) Now re-connect the CK pin to S6 and connect the lamps (LPI to LP4) to the Q pins instead and observe what happens. The counter should now count down.

c) To use the seven-segment LED display connect the outputs (QA to Qo) to the inputs (a to d) of the display decoder. Now make the counter go through the sequence and observe what happens. You should see the numbers a to 9 appear on the display but the display goes blank after that.

Try now to figure out a way to make the counter reset itself when it gets to 9 (hint: write out the binary numbers from 0 to III I in a table. Then look at the numbers and see if you can identify anything unique about the number 10. How can you use that feature to reset the flip-flops via the Clr pins when it reaches

IOn -

8. Shift Register

A register is a kind of temporary memory circuit (usually constructed from flip-flops) in which data can be manipulated. In this section, a Shift Register (in which data can be moved left or right) is constructed from the circuit shown below:

INPUT

LPI

LP3

LP2

LP4

1 1 1 J
JA JB lc JD
QA QB Qc QD
V~ . ..
~ ,..--I ~ ...
r--i .....
KA ~ KB lli ~ Qc KD Qn

Q Q_ n 0

CLR CK

Connect CK to S6 and CLR to S5b (as before).

a)

Serial-to-Parallel Conversion

A 4-bit number can be entered (bit by bit - serially) by setting the input signal as appropriate for four successive clock pulses. This is called serial entry. After 4 clock pulses. the data can be read out of the LP I to LP4 connections in parallel (all at once). Try this by entering some data to the chain and watch it clock down the chain at each clock pulse.

b)

Parallel-to-Serial Conversion

Parallel data entry can be ahieved by using the Preset pin to enter one data bit into each of the .:J. flipflops. If the Clock is now pulsed, the data should pass down the flip-flop chain and can be read off in serial from the LP4 pin. Check that this occurs by entering data via the Preset pin and clock in down the register to the LP4 pin.

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___ .___________________________________ _ ~~ ~~ 10

Current Gain CB) Stabilised Circuit.

In some amplifier designs the current and voltage on the collector depends upon the current gain ~ of the transistor. ~ is not only temperature dependent but varies from transistor to transistor even for the same type. A bias circuit which is independent of f3 is shown below.

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It is assumed that IB « 12:

and, VeE = Vee - JeRe - IERE·

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c) Setting '+ = V_

If all resistors have the same value; Vo= (VI-V2)·

DEP/1RTMENT OF MECHANICAL, MATEIUALS & MANUE1CTUlUNG ENGINEERING

Sam-C. P'-V?fWg-------------Swge 2, BEng(Hons) Mechanicsl Engineering

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1. Design a 'Fixed Bias t Circuit so that the quiescent operating point is V ce = 10V and Ic = 2mA when the amplifier is connected to a 20 volt supply. Given that ~ = 75 and Vbe = 0.7 volts.

(Rc = 5KQ Rb = 723KQ ).

2. In a fixed bias circuit Rb = 200K and Rc = 2K and the supply voltage V cc = 10Volts. Determine the Q-point (Ib, V ce and Ie) if the ~ of transistor 50 and Vbe = 0.7 Volts.

(46.5uA, 2.325mA and 5.35Volts)

3. Design a current gain stabilised circuit with a transistor having a f3 = 150, so that when the amplifier is connected to 16Volt supply the Q-point is V ce = 6volts and Ic = 1 rnA.

(Re = 1.6K, Rc = 8.4K, Rb2 = 24K and RbI = 143K)

4. Design a current gain stabilised circuit with a transistor having a f3 = 210, so that when the amplifier is connected to 20 Vol t supply the Q-point is Vee = 8 volts and Ie = I.SmA.

(Re = 1.33K, Rc = 6.67K, Rb2 = 28K and RbI = I80K).

5. For current gain stabilised circuitdetennine the values of Rbl, Rc, ~, V ce and the Collector Power dissipation. Given that Ie = 2mA,

Vbe = 0.7 Volts, Vcb = 9.3 Volts, Re = 1.25K nad Rb2 = 10K.

(Vee = 25V, ~ = 80, Re = 6.25K, RbI = 68.1K, Pc = 20mW).

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Tl: Commutative Law.

a) A +B=B+A

b) A.B = B. A

U: Associative Law.

a) (A + B) + C = A + (B + C)

b) (A. B) • C = A. (B • C) ----

T3: Distributive Law.

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T4: Identity Law.

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TS: Negation Law.

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Simplfify the following Boolean Expressions:

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~ --

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3) W = XYZ +XYZ +XYZ +XYZ

4)W=XY+(XY)Z

5) W = X(X + Y) + Z + Zy 6)V=W+WX+YZ

1

- 7) V = W[X + Y(Z + W)]

8) X = ABC + ACD + BCD

[C(A + B)] [ABC]

[XV +Z]

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[W +X Y +XZ] [C(AB + D)]

9) V = WXY + WXY + YZ+ X(Z + ZW) [X(W + Y + Z) +YZ]

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Performance calculations for 3-phase induceiQD_motors based on the equivalent circuit.

1. Draw the so called 'exact theoretical', per-phase equivalent circuit for a 3-phase induction motor, with all parameters referred to the stator side. Specify the meaning of each parameter.

Show how the circuit can be. modified for the calculation of output performance by an application o~ Thevenin's theorem.

2. Using the Thevenin-modified form of the equivalent circuit derive expressions for:

3.

(a) (b) (c) (d)

the rotor current (.referred to the stator)· the total mechanical power developed

the slip sMp at which the mechanical power developed is a maximum the total torque developed"

the total 'torque in synchronous watts' (so called)

the slip sMT at which the torque developed is a maximum

the external resistance required to ensure that maximum torque is developed at standstill

the two values of slip sp at which a particular value of power Pp is developed

the twa values of slip sT at which a particular value of torque TSWT (synchronous watts) is developed.

(e) (f)

(g) (h)

(a) Sketch a typical rotor cur.rentr-s Hp curve and show how it is modified when ~xternal resistors are connected in series with the rotor.

(b) Repeat for the torque-slip curve.

4. The parameters of the 'exact theoretical' equipment circuit of a 3-phase, 500 V, star-connected, SO-Hz, a-pole induction motor, with all values referred to the stator side are

R1=R2=O.l30, Xl=X2=O.60, ~=2s00, Xm=20n (Mechanical loses may be neglected)

For a slip of 0.05, calculate:

(a) (b) (c) (d) (e) (f) (g)

the the the the the the the

o

9g.~ I::;}o ·2oft

O· Si:J+O 13'9g kW

(referred to the stator) 'l'f" '33 A

8S?>·1 N,.,.. 6S.,,," kw

89 ·1~1.

stator current. input power factor input power rotor current torque

output power efficiency

5. Derive the Thevenin-modified form of the equivalent circuit of the motor specified in 4 above.

circuit.

Calculate the rotor current (referred to the stator) using the modified

(For the calculations which follow the data will be presented in the Theveninmodified form - and only output performance data will be called for).

6. The parameters of the Thevenin-modified form of the equivalent circuit of a 3-phase 4-pole ~9-Hz induction motor are:

Calculate:

(a) the slip at which maximum torque is developed (b) maximum torque

(c) output power at maximum torque

(d) resistance to be added to the rotor to ensure that the maximum torque occurs at standstill, given that the effective ratio of stator to rotor turns is 1.5 (e) the slip at which the power developed is a maximum

(f) the maximum power developed. [Note the difference between c and f]

0·14 (,1 303'1 N"" ~g.~ kW

o-esr St. e .If(,'" 3"1.3~ kW

7. The parameters of the Thevenin-modified form of the equivalent circuit of a 3-phase. 6-pole, 50-Hz induction motor CL~e:

R.r = 0.46 X-r - l.15

RZ = 0.6 X2 - 1. 6

n

Calculate:

(a) the slip at which maxim~ torque is developed (b) the maximum torque

(c) the torque and power developed at a speed of 920 rpm.

0·2152..a.ll·3 N,..

\4-'\'3 ~~ 1lf"3~ kW

8. Using the data of 7. calculate

(a) the speed at which a torque of 149.3 Nm is developed (b) the speed at which a power of 14.38 kW is developed

9. The parameters of the Thevenin-modified form of the equivalent circuit of a 3-phase, 8-pole, 50-Hz induction motor are:

R, - 0.062, R2 - 0.066, ly - X2 - 0.22

n

The motor opera~es at constant voltage and drives a particular load at a slip of 0.022.

Show that the machine would stall at a speed of about 640 rpm if the load torque were slowly increased to a value

of 3.2 times th~t of the original load.

10. The parameters of the Thevenin-modified form of the equivalent circuit of a 3-phase induction motor are

VT = 243V, R.r - 0.24, R.r .. 0.22, X-r .. X2 - 0.6 n.

Calculate the slip at which the motor develops a power of 35 h.p. when driving a load of the constant torque type.

Verify the answer by calculating the power developed at the slip obtained.

4

,7) Tutorial problems

7.1 A synchronous motor, having a synchronous reactance of 0.7 p.u. and negligible resistance operates at its rated terminal voltage, rated current, and field-induced EMF I Efl = 0.95 p.u. Determine the power factor. The excitation is adjusted until the numerical value of the power factor is the same initially, but the sign of the reactive power 'is changed. Determine the new value of I Efl.

Ans: 0.91; 1.44 p.u.

7.2 A 3-phase, 50-Hz, 8-pole, 100 kV A synchronous motor, having a synchronous reactance of 0.5

p. u.and negligible resistance, operates at rated voltage, rated current and field-induced EMF of 1.3 p.u. Calculate, (a) the load angle, (b) the power factor, (c) the torque. Calculate also the maximum torque the machine can develop when, with the excitation unchanged the load is steadily increased. Ans: (a) 20.3 , (b) 0.902 (leading), (c) 1150 Nm, (d) 3310 Nm.

7.3 A 3-phase, 50-Hz, 8-pole, 500 kVA synchronous motor, having a synchronous reaction of 1.0 p.u. and negligible resistance, operates at rated voltage, rated current and with a field-induced EMF of 1.0 p.u. The EMF is increased to 1.5 p.u, and the power is increased by a ratio of2/v3. Determine the current, power factor and torque for the new conditions.

Ans: (Initial power =?) I = 1.005 p.u., cos ~ = 0.993 (leading), torque = 6,366 Nm.

7.4 A 3-phase, 50-Hz, 4-pole, 1000 kVA synchronous generator having a synchronous reactance of 1.0 p.u, and negligible resistance, operation at rated voltage and current and load angle w = arc tan 0.5. Calculate the power factor, the power, and the torque.

Ans: cos ~ = 0.8 (current leading), power = 800 kW, torque = 5,093 Nm.

7.5 A 3-phase, 50-Hz, 4-pole, 10 kVA synchronous machine, having a synchronous reactance of 1.0 p.u. and negligible resistance, is coupled to a separately excited D.C. machine which is connected to a battery. The synchronous machine operates on a motor at rated voltage and current and a lagging power factor of 0.8. Draw the corresponding phasor diagram to scale and calculate the load angle and the torque developed.

Ans. 63.4°,51 Nm.

Draw phasor locus diagrams to illustrate the changes consequent on the following sequence of events:

(a) excitation of D.C. machine fixed, excitation of A.C. machine increased until its current regains

original numerical value,

(b) then excitation of AC. machine fixed at its new value, and excitation of D.C. machine reduced

until current of AC. machine again regains original numerical value.

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ELECTRICAL ENGINEERING IT

SECrIONB

3.

a) A cylindrical rotor field winding excited synchronous machine is operating as a motor. Starting from consideration of a phasor diagram representing a simple steady-state equivalent circuit, work out a torque expression in terms of load angle. Resistance may be neglected.

b) A 3~phase, 500 k VA, 50 Hz, 4-pole cylindrical rotor synchronous motor is mains supplied with rated voltage at 50 Hz. It has 1 p.u. synchronous reactance and negligible resistance. It draws rated current and has an initial load angle of 60°. Carefully draw and label a phasor diagram which illustrates this initial operating point.

Calculate:

c) the torque, and

d) the power factor of the current drawn from the supply.

The field excitation is now changed until unity power factor is given at the same output torque.

Find:

e) the ratio of increase in the field induced e.m.f needed, and

f) the new load angle.

g) If the field excitation were increased further what would happen to the current?

Briefly explain why this can be of practical significance.

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SOME REVISION NOTES ON SYNCHRONOUS MACHINES

OF UNIFORM AIR GAP (NON·SALIENT)

1) An equivalent circuit

. for the armature circuit

- note that the field circuit does not enter directly into steady state performance calculations.

Using Sink Convention

R... .;-x'.(

v

(a) Complete V-Ra+jXcI+jXaI+EF

per-phase quantities

V terminal voltage

I armature currrent

Ra armature resistance

jXa - armature reaction reactance jXi - armature leakage reactance EF - voltage induced in armature

phase by field excitation

I

(b) Simplified V-jXSI+EF

for simplified circuit neglect Ra

jXs - j(Xi+Xa)

jXs is the 'synchronous reactance'

2) A typical phasor diagram correponding to the simplified equivalent circuit.

(Xs ~ 1 per unit)

~ = phase angle between V and I

cos 1> = power factor k 1/;1

o - load angle /

Power = (3) Ivi I I I cos 1> But xslII cos ¢ = Efl sin 0

~ Power - (3) Ivl IEfl sin 0

iE"Fls;...,f

:- - --~

I I I

I

".

2

3) Operation at constant power, varying excitation

(Xs=l per unit)

:~-"C'<-J

I CrrJ...,uD'

I

I

Phasors with suffix L correspond to the limit of steady-state stability.

Suffix 0 corresponds to zero load Suffix M corresponds to 'motoring' Suffix G corresponds to 'generating'

N.B. In all phasor diagrams here Xs-l per unit

4) Operation at constant excitation varying power

Suffix 0 corresponds to zero load Suffix M corresponds to 'motoring' Suffix G corresponds to 'generating'

\

Phasors with suffix L correspond to the limit of steady-state stability.

3

5)

A typical phasor dia~ram for a synchronous machine when actin~ as a ~enerator, but using the 'sink'convention as previously

6)

A typical phasor diagram

for a synchronous machine when acting as a generator using the 'source' convention

Sink convention V-Ef+jXsI

r

Source convention V-Ef*jXsI

" /

Y / I

/

/

I

The directions of the I and jXsI phasors are here reversed, as compared with their directions in the diagram opposite.

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