Basic Differential Pair Layout

D1 D2

Q1 Q2
G1 30/1 30/1 G2

active S
poly

D1 D2
G1 G2
S S

Good matching in the absence of cross-chip gradients; both drain currents flow in same
direction.

Alternative Differential Pair Layout

D1 D2

Q1 Q2
G1 30/1 30/1 G2

S
active
poly

G1 D1
S
G2
D2

More compact, but worse matching than previous case; drain currents flow in opposite
directions.
 Common Centroid Layout

D1 D2

Q1 Q2
G1 15/1 15/1 G2
M=2 M=2

active
poly S

D1 D2
G1 G2
S S

D2 D1
G2 G1
S S

Q1 and Q2 have a “common centroid”, which makes them immune from cross-chip
gradients. Best matching performance possible.

Alternative Common-Centroid Layout

D1 D2

Q1 Q2
G1 15/1 15/1 G2
M=2 M=2

active

poly S

G1 D1 D2 G2
S S
G2 G1
D2 D1

Immune from cross-chip gradients like previous case, but area is saved by sharing
sources.
 Differential Pair with Very Wide Transistors

D1 D2

Q1 Q2
G1 30/1 30/1 G2

active
S

poly

G1 D1
S
G2
D2

Very wide transistors can lead to awkward layout and significant series gate resistance.

Multi-Finger Transistors

D1 D2

Q1 Q2
G1 30/1 30/1 G2
M=2 M=2

active S
poly

S S
G1 G2
D1 D2

S S

Multi-fingered gates save space and reduce series resistance in gate. Notice that drains
are selected to minimize parasitic capacitance to bulk.
 Common Centroid Layout with Multi-Fingered Gates

D1 D2

Q1 Q2
G1 15/1 15/1 G2
M=4 M=4

active S
poly

S S
G1 G2
D1 D2
S S

G2 D2 D1 G1

S S

Drain-to-bulk parasitic capacitance is minimized; sources are partially shared to save

area.

“Doughnut” Transistors

Q1
G 16/1

S
active

poly

S
G
D
G D
S

Gives the minimum Cgd (gate-to-drain overlap) and Cdb (drain-to-bulk) parasitic
capacitances for a given W/L ratio. May be used to minimize Miller effect when high
speed is desired and a dominant pole is created elsewhere.