TC1

Termen limita: 10 marite 2010, 8pm

Problemele 1.1 si 1.2 (vezi pag. 19 din text book).

Problem 1.1
Let be the full 4-bit adder described in the following Verilog module:
module fullAdder( output [3:0] out ,
output crOut , // carry output
input [3:0] in0 ,
input [3:0] in1 ,
input crIn ); // carry input
wire [4:0] sum ;
assign sum = in0 + in1 + crIn ;
assign out = sum[3:0] ;
assign crOut = sum[4] ;
endmodule
Use the module fullAdder to design the following 16-bit full adder:
module bigAdder( output [15:0] out ,
output crOut , // carry output
input [15:0] in0 ,
input [15:0] in1 ,
input crIn ); // carry input
// ???
endmodule
The resulting project will be simulated designing the appropriate test module.

`timescale 1ns / 1ps

module fullAdder(
output [3:0] out ,
output crOut ,
input [3:0] in0 ,
input [3:0] in1 ,
input crIn );
wire [4:0] sum ;
assign sum = in0 + in1 + crIn ;
assign out = sum[3:0] ;
assign crOut = sum[4] ;

endmodule

module bigAdder(
output [15:0] out ,
output crOut ,
input [15:0] in0 ,
input [15:0] in1 ,
 input crIn );
wire [15:0] sum ;
wire c1 ;
wire c2 ;
wire c3 ;

fullAdder modul1(.out(sum[3:0]),
.crOut(c1),
.in0(in0[3:0]),
.in1(in1[3:0]),
.crIn(crIn)
),
modul2(.out(sum[7:4]),
.crOut(c2),
.in0(in0[7:4]),
.in1(in1[7:4]),
.crIn(c1)
),
modul3(.out(sum[11:8]),
.crOut(c3),
.in0(in0[11:8]),
.in1(in1[11:8]),
.crIn(c2)
),
modul4(.out(sum[15:12]),
.crOut(crOut),
.in0(in0[15:12]),
.in1(in1[15:12]),
.crIn(c3)
);
assign out = sum[15:0];
endmodule

//test module

module testBigAdder;
reg [15:0] out;
reg [15:0] in0;
reg [15:0] in1;
reg crIn=0;
reg clk;
wire [15:0] sum;
initial begin
clk = 0 ;
forever #1 clk = ~clk;
end
initial begin
in1 = 16'b1000010100010101;
in0 = 16'b1000000000000000;
 #2 in1 = 16'b0000000000000001;
in0 = 16'b1000000000000000;

#2 in1 = 16'b0010000000000000;
in0 = 16'b0011000000000000;

#2 in1 = 16'b0010000000000000;
in0 = 16'b0011000000000000;
$stop ;
end

initial $monitor("time = %d clk = %b in1 = %b in0 = %b sum = %b crOut = %b crIn = %b",

$time, clk, in1, in0, sum, dut.crOut,dut.crIn);

bigAdder dut(sum,crOut,in0,in1,crIn);
endmodule

Dupa simulare obtinem urmatoarele rezultate:

This is a Lite version of ISE Simulator(ISim).

Simulator is doing circuit initialization process.

Finished circuit initialization process.
time = 0 clk = 0 in1 = 1000010100010101 in0 = 1000000000000000 sum =
0000010100010101 crOut = 1 crIn = 0
time =1 clk = 1 in1 = 1000010100010101 in0 = 1000000000000000 sum =
0000010100010101 crOut = 1 crIn = 0
time =2 clk = 0 in1 = 0000000000000001 in0 = 1000000000000000 sum =
1000000000000001 crOut = 0 crIn = 0
time =3 clk = 1 in1 = 0000000000000001 in0 = 1000000000000000 sum =
1000000000000001 crOut = 0 crIn = 0
time =4 clk = 0 in1 = 0010000000000000 in0 = 0011000000000000 sum =
0101000000000000 crOut = 0 crIn = 0
time =5 clk = 1 in1 = 0010000000000000 in0 = 0011000000000000 sum =
0101000000000000 crOut = 0 crIn = 0
Problem 1.2
Draw the block schematic of the following design:

module topModule( output [7:0] out,

input [7:0] in1,
input [7:0] in2,
input [7:0] in3);
wire [7:0] wire1, wire2;
bottomModule mod1( .out(wire1 ),
.in1(in1 ),
.in2(in2 )),
mod2( .out(wire2 ),
.in1(wire1 ),
.in2(in3 )),
mod3( .out(out ),
.in1(in3 ),
.in2(wire2 ));
endmodule

module bottomModule( output [7:0] out,

input [7:0] in1,
input [7:0] in2);
// ...
endmodule
Synthesize it to test your solution.