December 10,2001

CmpE 344 Computer Organization

Answers for Midterm Exam #2

P.1 Time to refresh single row =4 cycles * [1/133*106 sec/cycle]

=30*10-9 sec.

= 30 nsec.

Time to replace all rows = 8K * 30 nsec.

= 8*1024*30 nsec.

=245760 nsec.

Time to replace all rows = 0.24576 msec.

Time percentage for actual use =(64-0.24576)/64

= 0.996

Time percentage for actual use = 99.6%

P.2
0
1
0
1
2 Set #0
3

60
61
62 Set #15
16K -1 63
Main Cache

a) xxxxxxxxxxxxxxxxxxxx

10-bit TAG 4-bit 6-bit

set addr word addr

b) xxxxxxxxxxxxxxxxxxxx

8-bit TAG 6-bit 6-bit

index word addr
c) xxxxxxxxxxxxxxxxxxxx 0
1 set #0
14-bit TAG 6-bit 2
word addr 3
4
d) 00000000100001000010 5 set #1
6
TAG set #=1 word # 7

Cache address = 0 0 0 1 1 1 0 0 0 0 1 0

Cache block word #

#=7

P.3
a) Direct
0 2 4 6 2 8 2 0 4 2
0 0 4 4 4 8 8 0 4 4

0 2 2 6 2 2 2 2 2 2

M M M M M M H M M H h=2/10=0.2

b) Full Assoc.&FIFO
0 2 4 6 2 8 2 0 4 2
0 0 0 0 0 8 8 8 8 8
2 2 2 2 2 2 0 0 0
4 4 4 4 4 4 4 2
6 6 6 6 6 6 6
M M M M H M H M H M h=3/10=0.3

c) Full Assoc.&LRU
0 2 4 6 2 8 2 0 4 2
0 0 0 0 0 8 8 8 8 8
2 2 2 2 2 2 2 2 2
4 4 4 4 4 0 0 0
6 6 6 6 6 4 4
M M M M H M H M M H h=3/10=0.3

d) Full Assoc.&Optimum
0 2 4 6 2 8 2 0 4 2
0 0 0 0 0 0 0 0 0 0
2 2 2 2 2 2 2 2 2
4 4 4 4 4 4 4 4
6 6 8 8 8 8 8
M M M M H M H H H H h=5/10=0.5
e) Set Assoc.(set size=2) & FIFO
0 2 4 6 2 8 2 0 4 2
0 0 4 4 2 2 2 0 0 2
2 2 6 6 8 8 8 4 4

M M M M M M H M M M h=1/10=0.1

f) Set Assoc.(set size=2) & LRU

0 2 4 6 2 8 2 0 4 2
0 0 4 4 2 2 2 2 4 4
2 2 6 6 8 8 0 0 2

M M M M M M H M M M h=1/10=0.1

g)Set Assoc.(set size=2) & Optimum

0 2 4 6 2 8 2 0 4 2
0 0 4 6 6 8 8 0 4 4
2 2 2 2 2 2 2 2 2

M M M M H M H M M H h=3/10=0.3

h)Conclusion:
For this particular pattern “Direct Mapping” and “Set-Associative Mapping” are no
good(Only half of the cache is utilized).LRU and FIFO makes no difference in “Full
Associative Mapping” and the “Optimum Mapping” provides the best hit ratio (h=0.5)

P.4 a) Ta= tc + (1-h)tm

= T + 0.1*10T
Ta= 2T
Access Speed Ratio =(1/2T) / (1/10T) = 5
Access Speed Ratio = 5 (i.e.5 times faster)
b) Ta= h1*t1 + (1-h1)*[h2*t2 + (1-h2)*(tm+t2)+t1]
= 0.9*T +0.1*[0.9*2T + 0.1*(10T+2T)+T]
= 0.9T + 0.1*[1.8T+1.2T+T]
= 0.9T + 0.1*4T
Ta= 1.3T
Access Speed Ratio=(1/1.3T) / (1/2T) = 1,54
Access Speed Ratio=1.54(i.e.1.54 times faster)

P.5 Synchronous Input :

Bus cycle=Bus propog.delay for address + bus skew for address + Addr.Decode time +
setup time + hold time
= 10 nsec. + 1 nsec. + 7 nsec. + 10 nsec. + 1 nsec. + 2 nsec. + 2 nsec.
Bus cycle= 33 nsec.
Bandwidth= 1/(33*10-9) = 109 / 33
Bandwidth=30 MHz.
 Synchronous Output:
Bus cycle=Bus Propg.delay for address and data + bus skew + Addr.decode time + setup
time + hold time
= 10 nsec. + 1 nsec. + 7 nsec. + 2 nsec. + 2 nsec.
Bus cycle= 22 nsec.
Bandwidth= 1/(22*10-9) = 109 / 22
Bandwidth= 45.5 MHz.