Analog Power Management Ic Design Copec

ECEN4827/5827
Analog IC Design
• Instructor: Dragan Maksimovic

• Office: OT346, phone: 303-492-4863, fax: 303-492-2758
• E-mail: maksimov@colorado.edu
• Office hours: Wednesday 10-11am, Thursday 10am-12pm (Mountain)
• Course web site:
• http://ecee.colorado.edu/~ecen4827
• Announcements, course materials (including lecture slides), assignments,
solutions (password protected)
ECEN4827/5827 Analog IC Design 1

Assignments
• Weekly homeworks (11 total), 35% of the grade
• Midterm exam (open book/notes, take-home), 25% of the grade
• Final exam (comprehensive, open book/notes, take-home), 40% of the grade
• All assignments, due dates, and solutions posted on the course web site
• Off-campus students:
• Postmarked, emailed or faxed by the due date posted on the course web site
• Mail assignments to:
Dragan Maksimovic
ECEE Department
425 UCB
University of Colorado
Boulder, CO 80309-0425
• or E-mail (as single pdf file) to maksimov@colorado.edu,
• or Fax to: 303-492-2758 (note: Dragan Maksimovic, ECEN5827)
• Keep a copy of your work

Course Policies*
• No late work accepted (except in cases of documented emergencies)
• Homeworks
o Collaboration with other students taking the course in this semester is
encouraged
o Copying someone else’s work or collaborating in any form with
anyone not taking the course in this semester is not allowed
• Exams
o No collaboration of any kind allowed
• 5827 versus 4827: some additional assignments for ECEN5827 students
• Grading
o HW and exam scores taken at face value, no curving
o Final grades based on total scores, 4827 and 5827 curved separately
o Extra credit assignments: optional, can only improve the final grade
*Details can be found on the course website

Course materials
• Textbook: none required. Reference books (recommended)
• P. Gray, P. Hurst, S. Lewis, R. Meyer, "Analysis & Design of Analog Integrated
Circuits," 5th Edition, WILEY, 2009.
• P. Allen, D. Holberg, "CMOS Analog Circuit Design, Second Edition," Oxford, 2002.
• D. Johns, K. Martin, "Analog Integrated Circuit Design," Wiley, 1997.
• Sedra, Smith, "Microelectronics Circuits," 5th Edition, Oxford (from ECEN3250).
• Course notes and lecture slides posted on the course web site
• Software: schematic capture and Spice simulations
• LTspice/SwitcherCAD (free, unrestricted tool available from Linear
Technology)
http://www.linear.com/designtools/software/
• IC process example: a standard 0.35u CMOS process
Device symbols and models available from the course web site

Analog microelectronics
The Real Signal Analog Signal

World Conditioning Conversion
to Digital
Temperature
Pressure
Position 0101010110100101010101010101010101010
0001011010010101011101101010110110101
1101010101010101010001010100101011010
Speed Power Digital
0110101010101010101000010101010111100
1010101010101010101010101010010010010
Flow
Management Processor
1010101010101010101010101010010010101
0110101010101011110010110110101010101
0111110101010101010101010101011100100
1010101010101010010101010101010101010
Humidity
Sound
Light
RF transmission
Signal Digital Signal
Conditioning Conversion
to Analog

Example: mobile phone
Battery example: single-cell Lithium-Ion Battery Charger

Power distribution: Vbat = 2.7-5.5 V
PS PS PS PS
3.6 V 2.5 V 1.5 V 0.5-Vbat
Antenna
Display
µP/DSP D/A PA
core LO
PS Audio
A/D LNA
2.7-5.5 V I/O
Baseband digital Analog/RF
Interface
2.5 V 2.5 V 2.5 V
PS PS PS
PS Linear or switched-mode voltage regulators (power supplies)

Analog IC application areas
• Signal conditioning (amplification and analog filtering)
• A/D and D/A conversion
• Power conversion and power management
• Wireless communication
• Up-conversion and down-conversion
• RF amplification, filtering and transmission

Example:
linear voltage regulator as power supply
Series pass transistor
Iload
Q
+ Load
Vbat + C Vo
–
–
“Error amplifier” with
loop compensation
+
Bandgap
- Vref
reference
Relatively simple, low noise, small footprint area

Output voltage lower than the battery voltage
High efficiency only if Vo is close to input voltage Vbat = Vg

Linear voltage regulator power model
Ig Rs Io
+
Vg + Vo
–
Bias current
IQ
–
I g = Io + IQ
Vo I o Vo I o
Efficiency: η= =
V g I g Vg ( I o + I Q )
Linear regulator efficiency cannot be greater than
Vo
η<
the ratio of the output and the input voltage Vg
Linear regulator efficiency example
100
90
80
Example:
70
Vg = 3.6 V
60
Efficiency [%]
Vo = 1.5 V
50
IQ = 50 µA
40
30
.
0 < Io < 300 mA
20
10
0
0.1 1 10 100 1000
Io [mA]

Buck (step-down) switching power converter*
Low-pass LC filter
Ig L Io
1
+ +
2
Vg + vs(t) C v(t)
– Load
– –
vs(t) fs = 1/Ts = switching

Vg
frequency
DTs D' Ts D = switch duty cycle
0
0 DTs Ts
Conversion ratio:
t
Switch
Vo
position: 1 2 1 M ( D) = = D
Vg
*ECEN5797 Introduction to Power Electronics covers details of analysis,
modeling and design of switched-mode power converters
Efficiency as a function of load current
100
90
80
Buck regulator
70 Example:
Vg = 3.6 V
Efficiency [%]
60
50 Vo = 1.5 V
Linear regulator 0 < Io < 300 mA
40
.
30
20
10
0
0.1 1 10 100 1000
Io [mA]

PWM Switched-Mode Power Supply
Power
input iL(t) L Io Load
+ + vL(t) – +
iC(t)
vg(t) + vsw(t) C v(t)

–
– – Feedback
connection
Gate
drivers
p n
Dead-time Compensator
Pulse-width vc v
modulator Gc(s)
p(t) vc(t) Voltage

reference Vref
dTs Ts t t
Controller chip

Pulse-Width Modulator
VM vsaw(t)
Saw-tooth
p(t ) waveform vsaw (t ) vc(t)
+
Q R _
vc 0
t
S control
input p(t)
clock
OSC
0 dTs Ts 2Ts
clock

LTspice behavioral model: 5827_PWM1.asc
Buck switched-mode DC-DC converter
.model SW SW(Ron=.05 Roff=1Meg Vt=0.5 Vh=0)
SW
S1
L1
g sw out
Vg 1µ
SW R1
C1 I1
1
PWL(0A 0 800u 0A 801u 1A)
3.3 100µ
S2
cinv
ECEN4827/5827 PWM controller behavioral model

c
R3 C2 R4 C3
A1
30k 0.1n 1k 0.5n
R2
U1
ctrl
100k
t
ref
Bpwm
.lib opamp.sub
V=if(v(ctrl,t)+0.5,1,0) Vref
Vsaw
PWL(0 0 500u 1)
PULSE({Vlow} {Vhigh} 0 {Tr} {Ts-Tr} 0 {Ts})

.param Fs=1meg Tr={0.9/Fs} Ts={1/Fs} Vlow=1 Vhigh=2
.tran 0 1000u 0 2n

I(L1)
2.7A
2.4A
2.1A Inductor current
1.8A
1.5A
1.2A
0.9A
0.6A
0.3A
0.0A
-0.3A
V(out) V(ctrl)
1.5V
1.3V Control voltage
1.1V
0.9V
0.7V
0.5V
0.3V
Output voltage
0.1V
-0.1V
0µs 100µs 200µs 300µs 400µs 500µs 600µs 700µs 800µs 900µs 1000µs

Voltage regulation during step-load transient
Inductor current I(L1)

2.8A
2.6A
2.4A
2.2A
2.0A
1.8A
1.6A
1.4A
1.2A
1.0A
0.8A
0.6A
0.4A
V(out) V(ctrl)
1.020V
1.014V
1.008V Output voltage
1.002V
0.996V
0.990V
0.984V
0.978V
0.972V
0.966V
0.960V
0.954V
798µs 801µs 804µs 807µs 810µs 813µs 816µs 819µs 822µs 825µs 828µs 831µs 834µs

ECEN4827/5827 course topics
SW
S1
L1
g sw out
Vg 1µ
SW R1
C1 I1
1
PWL(0A 0 800u 0A 801u 1A)
3.3 100µ
S2
cinv

c
R3 C2 R4 C3
A1
30k 0.1n 1k 0.5n
R2
U1
ctrl
100k
t
ref
Bpwm
.lib opamp.sub
Vsaw
PWL(0 0 500u 1)

.tran 0 1000u 0 2n
Focus on transistor-level integrated circuit design techniques

SW
S1
L1
g sw out
Vg 1µ
SW R1
C1 I1
1
PWL(0A 0 800u 0A 801u 1A)
3.3 100µ
S2
cinv

c
R3 C2 R4 C3
A1
30k 0.1n 1k 0.5n
R2
U1
ctrl
100k
t
ref
Bpwm
.lib opamp.sub
V=if(v(ctrl,t)+0.5,1,0) Vref Op-amp
Vsaw
PWL(0 0 500u 1) application
circuits and
.param Fs=1meg Tr={0.9/Fs} Ts={1/Fs} Vlow=1 Vhigh=2 transistor-level
.tran 0 1000u 0 2n op-amp design

Transistor-level op-amp design example
VDD
L = 2U U8 U5 L = 2U U7 L = 2U U10 L = 2U VDD
W = 2U W = 10U W = 50U W = 50U DC = 3.3
N2
out 0
N1
U1 U2
2
inp Ibias inp U9 L = 1U
Vp W = 50U W = 50U W = 200U
1u L = 1U L = 1U
inm {Cc} Cc
N3 1
DC = 1.65
L = 2U U3 U4 L = 2U U6 L = 2U PARAMETERS:
AC = 0 W = 10U W = 10U W = 100U Cc = 10p
0
TRAN = PULSE(1.6 1.7 100n 1n 1n 500n 1u)
0 Vz
1Vac
Design:
• Circuit configuration
• DC biasing
• device W/L aspect ratios

SW
S1
L1
g sw out
Vg 1µ
SW R1
C1 I1
1
PWL(0A 0 800u 0A 801u 1A)
3.3 100µ
S2
cinv

c
R3 C2 R4 C3
A1
30k 0.1n 1k 0.5n
R2
U1
ctrl
100k
t
ref
Bpwm
.lib opamp.sub
Vsaw
PWL(0 0 500u 1)
PULSE({Vlow} {Vhigh} 0 {Tr} {Ts-Tr} 0 {Ts}) Design of

.tran 0 1000u 0 2n
bandgap
references

Bandgap reference example
ECEN4827/5827 bandgap1 using
NMOS, PMOS and WDIODE devices
from 0.35u CMOS library
5827_035.lib vdd
U7 U2 U8
L = 5u L = 5u L = 5u
W = 10U W = 10U W = 10U
VDD
DC = 3.3V
VIref
DC = 0
U3 U1
0
W = 5U W = 5U
L = 5u L = 5u
ref
VREF
0 0
U4 U9
RPN RPN
W = 1u W = 1u
PARAMETERS:
L = {LR1} L = {LR2}
LR2 = to be determined
LR1 = to be determined
U6 U5 U10
WDIODE WDIODE WDIODE
n=1 n=8 n=1
0 0 0

SW
S1
L1
g sw out
Vg 1µ
SW R1
C1 I1
1
PWL(0A 0 800u 0A 801u 1A)
3.3 100µ
S2
cinv

c
R3 C2 R4 C3
A1
30k 0.1n 1k 0.5n
R2
U1
ctrl
100k
t
ref
Bpwm
.lib opamp.sub
Vsaw
PWL(0 0 500u 1)

Transistor-level design of
.tran 0 1000u 0 2n PWM oscillators,
waveform generators,
and voltage comparators
SW
S1
L1
g sw out
Vg 1µ
SW R1
C1 I1
1
PWL(0A 0 800u 0A 801u 1A)
3.3 100µ
S2
cinv

c
R3 C2 R4 C3
A1
30k 0.1n 1k 0.5n
MOSFETs and U1
R2
ctrl
driver circuits t
100k
ref
Bpwm
.lib opamp.sub
Vsaw
PWL(0 0 500u 1)

.tran 0 1000u 0 2n

SW
S1
L1
g sw out
Vg 1µ
SW R1
C1 I1
1
PWL(0A 0 800u 0A 801u 1A)
3.3 100µ
S2
cinv

c
R3 C2 R4 C3
A1
30k 0.1n 1k 0.5n
R2
U1
ctrl
100k
t
ref
Bpwm
.lib opamp.sub
Vsaw
PWL(0 0 500u 1) Feedback
.tran 0 1000u 0 2n

ECEN 4827/5827 outline
1. Real op-amp characteristics and limitations, impact on application circuits
• Open-loop gain, input and output impedance, output voltage swing
• Introduction to feedback
• Voltage offset and drift, input bias current and offset
• Introduction to component tolerances and temperature drift
• Input common-mode voltage range, CMRR, PSRR
2. Transistor-level analysis and design of a two-stage CMOS op-amp
• CMOS process technology, 0.35u CMOS process example
• Basic principles of analog IC design via examples: matching, process and temperature
variations
• DC biasing
• Small-signal modeling and design of gain stages
3. Current and voltage references
• Current mirrors, design of current sources
• Temperature drift and supply voltage sensitivity
• Bandgap references
4. Frequency responses of gain stages
• Device high-frequency models and parasitic capacitances
• Design-oriented analysis techniques: zero-value time constant (ZVTC) method, and N-extra
element theorem (NEET) method
5. Frequency response, stability and design-oriented analysis of negative feedback circuits
• Loop gain, phase margin and compensation
6. IC application examples
• Design of linear voltage regulators
• Design of pulse-width modulation controllers for switched-mode power converters

ECEN 4827/5827 outline
1. Real op-amp characteristics and limitations, impact on application circuits
• Open-loop gain, input and output impedance, output voltage swing
• Introduction to feedback
• Voltage offset and drift, input bias current and offset
• Introduction to component tolerances and temperature drift
• Input common-mode voltage range, CMRR, PSRR
2. Transistor-level analysis and design of a two-stage CMOS op-amp
• CMOS process technology, 0.35u CMOS process example
• Basic principles of analog IC design via examples: matching, process and temperature
variations
• DC biasing
• Small-signal modeling and design of gain stages
3. Current and voltage references
• Current mirrors, design of current sources
• Temperature drift and supply voltage sensitivity
• Bandgap references
4. Frequency responses of gain stages
• Device high-frequency models and parasitic capacitances
• Design-oriented analysis techniques: zero-value time constant (ZVTC) method, and N-extra
element theorem (NEET) method
5. Frequency response, stability and design-oriented analysis of negative feedback circuits
• Loop gain, phase margin and compensation
6. IC application examples
• Design of linear voltage regulators
• Design of pulse-width modulation controllers for switched-mode power converters

Op-amp characteristics
Ideal op-amp:

Real op-amp characteristics
Op-amp data sheets:
10’s of pages
Objectives:
• Understand
impact of
various op-amp
imperfections in
applications
• Motivate follow-
up study of
transistor-level
design
techniques

(1) DC and low-frequency small-signal characteristics
• Open-loop low-frequency voltage gain Ao = vo/(v(+) - v(-))
• Output resistance, rout
• Input resistance, rin
• Supply voltages VDD, -VSS (or VCC, -VEE); supply currents IDD, ISS (or ICC, IEE)
• Output saturation limits, VOmin, VOmax
Output voltage swing VOmin < VO < VOmax
• Maximum output (source or sink) current
• Input offset voltage, VOS; temperature drift of the input offset voltage ∆VOS/∆T [mV/oC]
• Input bias current, IB = (IB+ + IB-)/2; temperature drift ∆IB/∆T
• Input offset current, IOS = IB+ - IB-; temperature drift ∆IOS/∆T
• Common-mode rejection ratio CMRR
• Power-supply rejection ratio PSRR
• Input common-mode voltage range, VCMmin < VCM < VCMmax
Common-mode input: VCM = (v(+) - v(-))/2

(2) Small-signal and large-signal dynamic characteristics
• Open-loop transfer function AOL(s)
• Gain-bandwidth product GBW, or unity-gain bandwidth
• Input and output impedances, Zin(s), Zout(s)
• Slew-rate SR
• Frequency-dependent common-mode rejection ratio CMRR(f)
• Frequency-dependent power-supply rejection ratio PSRR(f)
• Input noise

Application example 1: inverting amplifier
R2
VDD
R1
_
vO
+
vI +
– −VSS

Model with finite open-loop gain Ao
+
– A (v(+)−v(−))
o

Model with finite open-loop gain Ao
R2
R2
VDD
R1
R1
_ −
vO vo
+ + +
– vi – A (v(+)−v(−))
vI + o
– −VSS +

R2
Find closed-loop gain
ACL = vo/vi R1
−
vo
+ +
– vi – A (v(+)−v(−))
o

Loop gain T
R2
R1
−
vo
+ +
– vi – A (v(+)−v(−))
o

Model with finite open-loop gain Ao, rin and rout
+ rout
rin +
– A (v(+)−v(−))
o

Model with finite open-loop gain Ao, rin and rout
+ rout
rin +
– A (v(+)−v(−))
o
R2
R1
− rout
vo
+ rin +
– vi – A (v(+)−v(−))
o
T rout rin 1
ACL = ( ACL )ideal +
1 + T rout + R2 + R1 || rin rin + R1 1 + T
R1 || rin
T = Ao
R1 || rin + R2 + rout

Announcements
• Homework 1 (posted on the course website) is due (for all students)
Friday Sept. 4
• For easier note taking: handout slides will be posted before lectures
(typically a day before)
• Complete annotated slides will be posted after lectures
• Send an email to maksimov@colorado.edu from your preferred
email address, otherwise I will use your colorado.edu email
• Use 5827 in the subject line for e-mail questions

• Input offset voltage, VOS; temperature drift of the input offset voltage ∆VOS/∆T
[mV/oC]

Static transfer characteristic: output voltage swing
_ Vo
VDD
+ Vomax
output voltage swing

Vomin < Vo < Vomax
slope = Ao v(+) − v(−)
Vomin
−VSS

Application example 2: analog integrator
C
VDD
R
_
vO
+
vI +
– −VSS

Input offset voltage
Vo
VDD
Vomax
output voltage swing

Vomin < Vo < Vomax
slope = Ao v(+) − v(−)
Vomin
−VSS

Input offset voltage: random quantity
TLV2721 data sheet VOS spec:

Typical: 0.5 mV
Max: 3 mV

Model with input offset voltage VOS
+ +
VOS
zero-offset
− −

+ +
VOS
vO
zero-offset
R
− −
C
vI +
–
_ vC +

Model with input bias currents
+ +
IB
zero-input-bias
− −
IB

+ +
IB
vO
zero-input-bias
R
− −
IB
C
vI +
–
_ vC +

Cancellation of input bias current effects
+ +
IB
vO
zero-input-bias
R
− −
IB
C
vI +
–
_ vC +
Simple and general approach:
Resistances seen (at DC) from + input to DC

ground, and from – input to DC ground should be
the same

Cancellation of input bias current effects
+ +
IB
vO
zero-input-bias
R
− −
IB
C
vI +
–
_ vC +
Simple and general approach:
Resistances seen (at DC) from + input to DC

ground, and from – input to DC ground should be
the same

Input offset current
+ +
IB
zero-input-bias
− −
IB

Model with input offset voltage, input bias
current and input offset current
+ +
IB VOS
zero-offset,
IOS / 2 zero-input-bias
− −
IB
• Polarity and nominal value of IB is known

• VOS and IOS are treated as random quantities with
zero mean values
• VOS, IB and IOS have temperature drifts

Introduction to Component Tolerances and Temperature Drift
• Key issues in analog design, especially IC design: components with precisely
known values are rarely available
• Design must take into account significant process and temperature variations
• Example: resistor
Nominal value: R
Tolerance
– Relative tolerance ∆R/R (in %)
– Ractual can be considered a random variable with mean value R
Temperature drift
– Fractional temperature coefficient TCF(R) (in ppm/oC)
ppm = parts per million = 10-6, 1% = 10000 ppm

Application example: precision DC current reference

Precision DC current reference: a circuit realization
VCC
+
VREF –
• Basic circuit operation

• Negative feedback
• BJT operating region

Tolerances and temperature drift
Op-amp
• Ao
VCC
• VOS = ±3 mV, ∆VOS/∆T = 10µV/oC
• IB = 1 µA, IOS = ±10 nA
• Bandgap reference
• VREF = 1.26V ± 1 mV
• TCF(VREF) = + 100 ppm/oC
+
VREF –
• Resistor
R • ∆R/R = ± 1%
• TCF(R) = +1000 ppm/oC
• BJT: npn bipolar junction transistor
• β = 100 ± 50%
• TCF(β) = −1%/oC

IREF as a function of VREF, VOS, R, and β
VCC
+
VREF –

Tolerances: ∆IREF/IREF

Tolerances and temperature drift
Op-amp
• Ao
VCC
• VOS = ±3 mV, ∆VOS/∆T = 10µV/oC
• IB = 1 µA, IOS = ±10 nA
• Bandgap reference
• VREF = 1.26V ± 1 mV
• TCF(VREF) = + 100 ppm/oC
+
VREF –
• Resistor
R • ∆R/R = ± 1%
• TCF(R) = +1000 ppm/oC
• BJT: npn bipolar junction transistor
• β = 100 ± 50%
• TCF(β) = −1%/oC

IREF as a function of VREF, VOS, R, and β
VCC
+
VREF –



Temperature drift: TCF(IREF)

• Input offset voltage, VOS; temperature drift of the input offset voltage ∆VOS/∆T
[mV/oC]

Differential and common-mode input

CMRR

CMRR

Input common-mode voltage range

PSRR

Next: 2-stage CMOS op-amp
• Transistor-level view of a 2-stage CMOS op-amp
• DC biasing
• Small-signal analysis of open-loop gain
• Output voltage swing, Input common-mode voltage range
• Input offset voltage
• Introduction to 0.35u CMOS process
Review background materials

MOS transistor characteristics and operating regions, large-signal and
small-signal models
• Notes on the course web site
• [Sedra, Chapter 4]
• [Gray, Chapter 2]
• [Allen, Chapters 2, 3]
• [Johns, sections 1.1-1.3]

Announcements
• Turn in HW1
• Solution password for HW1 will be sent by email
• HW2 is due Friday, Sept 11.

Next: 2-stage CMOS op-amp
• Transistor-level view of a 2-stage CMOS op-amp
• DC biasing
• Small-signal analysis of open-loop gain
• Output voltage swing, Input common-mode voltage range
• Input offset voltage
• Introduction to 0.35u CMOS process
Review background materials

MOS transistor characteristics and operating regions, large-signal and
small-signal models
• Notes on the course web site
• [Sedra, Chapter 4]
• [Gray, Chapter 2]
• [Allen, Chapters 2, 3]
• [Johns, sections 1.1-1.3]

Basic 2-stage CMOS op-amp
+VDD
M3 M4
M6
M1 M3
M8
M5 M7
-VSS

DC bias solution
+VDD
M3 M4
M6
M1 M2
M8
M5 M7
-VSS

Review: NMOS operating regions and characteristics

Review: PMOS operating regions and characteristics

2-stage op-amp DC solution: numerical example
• VDD = +5V, -VSS = -5V
• Desired DC bias currents:
IB = 1 µΑ
ΙΒ1 = 10 µΑ +VDD
ΙΒ2 = 100 µΑ M3 M4
• NMOS: M6
µnCox = 60 µA/V2
Vtn = + 1 V
M1 M2
• PMOS: IB = 1 µΑ
µpCox = 20 µA/V2 ΙΒ2 = 100 µΑ
Vtp = -1 V ΙΒ1 = 10 µΑ
M8
M5 M7
-VSS

Basic 2-stage CMOS op-amp
+VDD
M3 M4
M6
M1 M3
M8
M5 M7
-VSS

2-stage op-amp DC solution: numerical example
• VDD = +5V, -VSS = -5V
• Desired DC bias currents:
IB = 1 µΑ
ΙΒ1 = 10 µΑ +VDD
ΙΒ2 = 100 µΑ M3 M4
• NMOS: M6
µnCox = 60 µA/V2
Vtn = + 1 V
M1 M2
• PMOS: IB = 1 µΑ
µpCox = 20 µA/V2 ΙΒ2 = 100 µΑ
Vtp = -1 V ΙΒ1 = 10 µΑ
M8
M5 M7
-VSS

DC bias solution: IB
+VDD
M3 M4
M6
M1 M3
M8
M5 M7
-VSS

DC bias solution: IB1
+VDD
M3 M4
M6
M1 M2
M8
M5 M7
-VSS

Current mirror

DC bias solution: ID1, ID2
+VDD
M3 M4
M6
M1 M2
M8
M5 M7
-VSS

DC bias solution: ID1, ID2
+VDD
M3 M4
M6
M1 M2
M8
M5 M7
-VSS

Announcements
• Turn in HW2. Solution password will be sent by email

• HW3 is due Friday, September 18

2-stage op-amp: summary of DC bias solution thus far
+VDD = 5 V
act/sat (W/L)3,4 = 20 act/sat
M3 M4
RB = 8.8 MΩ M6
+ 3.84 V
ID1 = 5 µA ID2 = 5 µA
IB = 1 µA M1 M2
(W/L)1,2 = 100
act/sat act/sat
−1.04 V
IB2 = 100 µA
IB1 = 10 µA
M8
M5 M7
−3.8 V
(W/L)8 = 1
act/sat (W/L)5 = 10
act/sat
-VSS = −5 V

Channel-Length Modulation

iD versus vDS characteristic

DC bias solution: V1
+VDD = 5 V
M3 M4
RB = 8.8 MΩ M6
+ 3.84 V
ID1 = 5 µA ID2 = 5 µA
IB = 1 µA M1 M2
(W/L)1,2 = 100
act/sat act/sat
−1.04 V
IB2 = 100 µA
IB1 = 10 µA
M8
M5 M7
−3.8 V
(W/L)8 = 1
act/sat (W/L)5 = 10
act/sat
-VSS = −5 V

DC bias solution: IB2, VOUT
+VDD = 5 V
M3 M4
RB = 8.8 MΩ M6
+ 3.84 V
ID1 = 5 µA ID2 = 5 µA
IB = 1 µA M1 M2
(W/L)1,2 = 100
act/sat act/sat
−1.04 V
IB2 = 100 µA
IB1 = 10 µA
M8
M5 M7
−3.8 V
(W/L)8 = 1
act/sat (W/L)5 = 10
act/sat
-VSS = −5 V

DC bias solution: VOUT

DC bias solution: IB2, VOUT
+VDD = 5 V
M3 M4
RB = 8.8 MΩ M6
+ 3.84 V
ID1 = 5 µA ID2 = 5 µA
IB = 1 µA M1 M2
(W/L)1,2 = 100
act/sat act/sat
−1.04 V
IB2 = 100 µA
IB1 = 10 µA
M8
M5 M7
−3.8 V
(W/L)8 = 1
act/sat (W/L)5 = 10
act/sat
-VSS = −5 V


Output voltage swing
+VDD = 5 V
M3 M4
RB = 8.8 MΩ M6
+ 3.84 V
ID1 = 5 µA ID2 = 5 µA
IB = 1 µA M1 M2
(W/L)1,2 = 100
act/sat act/sat
−1.04 V
IB2 = 100 µA
IB1 = 10 µA
M8
M5 M7
−3.8 V
(W/L)8 = 1
act/sat (W/L)5 = 10
act/sat
-VSS = −5 V

+VDD = 5 V
M3 M4
RB = 8.8 MΩ M6
+ 3.84 V
ID1 = 5 µA ID2 = 5 µA
IB = 1 µA M1 M2
(W/L)1,2 = 100
act/sat act/sat
−1.04 V
IB2 = 100 µA
IB1 = 10 µA
M8
M5 M7
−3.8 V
(W/L)8 = 1
act/sat (W/L)5 = 10
act/sat
-VSS = −5 V


Input Common-Mode Voltage Range
+VDD = 5 V
M3 M4
RB = 8.8 MΩ M6
+ 3.84 V (W/L)6 = 400
ID1 = 5 µA ID2 = 5 µA
IB = 1 µA M1 M2
(W/L)1,2 = 100
act/sat act/sat
−1.04 V
IB2 = 100 µA
IB1 = 10 µA
M8
M5 M7
−3.8 V
(W/L)8 = 1
act/sat (W/L)5 = 10 (W/L)7 = 100
act/sat
-VSS = −5 V

Input Common-Mode Voltage Range
+VDD = 5 V
M3 M4
RB = 8.8 MΩ M6
+ 3.84 V (W/L)6 = 400
ID1 = 5 µA ID2 = 5 µA
IB = 1 µA M1 M2
(W/L)1,2 = 100
act/sat act/sat
−1.04 V
IB2 = 100 µA
IB1 = 10 µA
M8
M5 M7
−3.8 V
(W/L)8 = 1
act/sat (W/L)5 = 10 (W/L)7 = 100
act/sat
-VSS = −5 V

Open-loop differential-mode gain Ao
+VDD = 5 V
(W/L)3,4 = 20
M3 M4
RB = 8.8 MΩ M6
(W/L)6 = 400
ID1 = 5 µA ID2 = 5 µA
IB = 1 µA M1 M2
(W/L)1,2 = 100
IB2 = 100 µA
IB1 = 10 µA
M8
M5 M7
(W/L)8 = 1
(W/L)5 = 10 (W/L)7 = 100
-VSS = −5 V

Basic MOS small-signal model

+VDD = 5 V
(W/L)3,4 = 20
M3 M4
RB = 8.8 MΩ M6
(W/L)6 = 400
ID1 = 5 µA ID2 = 5 µA
IB = 1 µA M1 M2
(W/L)1,2 = 100
IB2 = 100 µA
IB1 = 10 µA
M8
M5 M7
(W/L)8 = 1
(W/L)5 = 10 (W/L)7 = 100
-VSS = −5 V

Basic MOS small-signal model

Basic NMOS small-signal model
id
G D
+ +
gmvgs
vgs vds
_ ro
_
∂iD 2I D
gm = = 2 K (VGS − Vtn ) = 2 KI D =
∂vGS VGS , I D
(VGS − Vtn )
−1
 ∂iD  1
ro = rds =   =
 ∂vDS  λI D
VGS , I D

Basic PMOS small-signal model
id
G D
+ +
gmvgs
vgs vds
_ ro
_
∂iD
gm =
∂vGS
(
= 2 K VSG − Vtp = 2 KI D = ) 2I D
(VSG − Vtp )
VSG , I D
−1
 ∂iD  1
ro = rds =   =
 ∂vDS  λI D
VSG , I D

Open-loop differential-mode gain Ao: A2
+VDD = 5 V
(W/L)3,4 = 20
M3 M4
RB = 8.8 MΩ M6
(W/L)6 = 400
ID1 = 5 µA ID2 = 5 µA
IB = 1 µA M1 M2
(W/L)1,2 = 100
IB2 = 100 µA
IB1 = 10 µA
M8
M5 M7
(W/L)8 = 1
(W/L)5 = 10 (W/L)7 = 100
-VSS = −5 V


Second stage gain: A2 = vout/v1
Common-source amplifier with active load:

+VDD = 5 V
(W/L)3,4 = 20
M3 M4
RB = 8.8 MΩ M6
(W/L)6 = 400
ID1 = 5 µA ID2 = 5 µA
IB = 1 µA M1 M2
(W/L)1,2 = 100
IB2 = 100 µA
IB1 = 10 µA
M8
M5 M7
(W/L)8 = 1
(W/L)5 = 10 (W/L)7 = 100
-VSS = −5 V

Basic differential amplifier
+VDD = 5 V
R R
M1 M2
(W/L)1,2 = 100
−vid/2 + +
+vid/2
– –
IB1 = 10 µA
−VSS

Differential amplifier: large-signal characteristic
+VDD = 5 V
R R
M1 M2
(W/L)1,2 = 100
−vid/2 + +
+vid/2
– –
IB1 = 10 µA
−VSS

Basic differential amplifier: half-circuit analysis
R R
M1 M2
(W/L)1,2 = 100
−vid/2 + +
+vid/2
– –

R R
M1 M2
(W/L)1,2 = 100
−vid/2 + +
+vid/2
– –

Announcements
• Turn in HW3
• HW4 is due Friday, September 25
• I will be away on a trip Monday-Thursday next week: no lectures on
Monday or Wednesday, no office hours
• Make-up lectures (same room)
• Today 2:30-3:20pm
• Friday, Sept 25, 11-11:50am

+VDD = 5 V
(W/L)3,4 = 20
M3 M4
RB = 8.8 MΩ M6
(W/L)6 = 400
ID1 = 5 µA ID2 = 5 µA
IB = 1 µA M1 M2
(W/L)1,2 = 100
IB2 = 100 µA
IB1 = 10 µA
M8
M5 M7
(W/L)8 = 1
(W/L)5 = 10 (W/L)7 = 100
-VSS = −5 V

+VDD = 5 V
(W/L)3,4 = 20
M3 M4
RB = 8.8 MΩ M6
(W/L)6 = 400
ID1 = 5 µA ID2 = 5 µA
IB = 1 µA M1 M2
(W/L)1,2 = 100
IB2 = 100 µA
IB1 = 10 µA
M8
M5 M7
(W/L)8 = 1
(W/L)5 = 10 (W/L)7 = 100
-VSS = −5 V

R R
M1 M2
(W/L)1,2 = 100
−vid/2 + +
+vid/2
– –

R R
M1 M2
(W/L)1,2 = 100
−vid/2 + +
+vid/2
– –

R R
M1 M2
(W/L)1,2 = 100
−vid/2 + +
+vid/2
– –

+VDD = 5 V
(W/L)3,4 = 20
M3 M4
RB = 8.8 MΩ M6
(W/L)6 = 400
ID1 = 5 µA ID2 = 5 µA
IB = 1 µA M1 M2
(W/L)1,2 = 100
IB2 = 100 µA
IB1 = 10 µA
M8
M5 M7
(W/L)8 = 1
(W/L)5 = 10 (W/L)7 = 100
-VSS = −5 V

Small-signal (incremental) resistance of
a diode-connected device

Small-signal current-mirror model

(W/L)3,4 = 20
M3 M4
RB = 8.8 MΩ M6
(W/L)6 = 400
M1 M2
(W/L)1,2 = 100
−vid/2 + +
+vid/2
– –
IB1 = 10 µA
M8
M5 M7
(W/L)8 = 1
(W/L)5 = 10 (W/L)7 = 100

(W/L)3,4 = 20
M3 M4
RB = 8.8 MΩ M6
(W/L)6 = 400
M1 M2
(W/L)1,2 = 100
−vid/2 + +
+vid/2
– –
IB1 = 10 µA
M8
M5 M7
(W/L)8 = 1
(W/L)5 = 10 (W/L)7 = 100

(W/L)3,4 = 20
M3 M4
RB = 8.8 MΩ M6
(W/L)6 = 400
M1 M2
(W/L)1,2 = 100
−vid/2 + +
+vid/2
– –
IB1 = 10 µA
M8
M5 M7
(W/L)8 = 1
(W/L)5 = 10 (W/L)7 = 100

Basic differential amplifier: CMRR
+VDD = 5 V
R R
M1 M2
−vid/2 + +
+vid/2
– –
M8 M5
−VSS

Basic differential amplifier: diff-mode gain
+VDD = 5 V
R R
M1 M2
−vid/2 + +
+vid/2
– –
M8 M5
−VSS

Basic differential amplifier: common-mode gain
+VDD = 5 V
R R
M1 M2
+vcm + +
– – +vcm
M8 M5
−VSS

Common-mode half-circuit analysis
+VDD = 5 V
R R
M1 M2
+vcm + +
– – +vcm
M8 M5
−VSS

Common-mode half-circuit analysis

+VDD = 5 V
R R
M1 M2
−vid/2 + +
+vid/2
– –
M8 M5
−VSS

CMRR improvement:
IB1 current sink with larger output resistance

Announcements
• Another make-up lecture today at 11am in CAETE studio CS1B28
• Turn in HW4 now or at 11am
• HW5 due next Friday

+VDD = 5 V
R R
M1 M2
−vid/2 + +
+vid/2
– –
M8 M5
−VSS

CMRR improvement:
IB1 current sink with larger output resistance

Output resistance of a cascode current mirror

CMRR in the basic differential amplifier with
cascode current sink
+VDD
R R
M1 M2
+ +
– –
IB1
M10 M9
M8 M5
−VSS

CMRR of a diff amp with current-mirror load
+VDD
Differential-mode gain
M3 M4
M1 M2
−vid/2 + +
+vid/2
– –
IB1 = 10 µA
M8
M5
−VSS

+VDD Common-mode gain
M3 M4
M1 M2
+vcm + +
– – +vcm
IB1 = 10 µA
M8
M5
−VSS

Common-mode gain
CMRR

Announcements
• If you have not done this already, turn in HW4

Two-stage op-amp output resistance
+VDD = 5 V
(W/L)3,4 = 20
M3 M4
RB = 8.8 MΩ M6
(W/L)6 = 400
ID1 = 5 µA ID2 = 5 µA
IB = 1 µA M1 M2
(W/L)1,2 = 100
IB2 = 100 µA
IB1 = 10 µA
M8
M5 M7
(W/L)8 = 1
(W/L)5 = 10 (W/L)7 = 100
-VSS = −5 V

Basic (class-A) output stage
Common-drain (source follower) amplifier
+VDD = 5 V
(W/L)3,4 = 20
M3 M4
RB = 8.8 MΩ M6
(W/L)6 = 400
ID1 = 5 µA ID2 = 5 µA
IB = 1 µA M1 M2
(W/L)1,2 = 100
IB2 = 100 µA
IB1 = 10 µA
M8
M5 M7
(W/L)8 = 1
(W/L)5 = 10 (W/L)7 = 100
-VSS = −5 V

+VDD = 5 V
(W/L)3,4 = 20
M3 M4
RB = 8.8 MΩ M6
(W/L)6 = 400
ID1 = 5 µA ID2 = 5 µA M11

IB = 1 µA M1 M2
(W/L)1,2 = 100
IB2 = 100 µA
IB1 = 10 µA
M8
M5 M7
(W/L)8 = 1 M12
(W/L)5 = 10
(W/L)7 = 100
-VSS = −5 V

Source follower gain and output resistance

+VDD = 5 V
(W/L)3,4 = 20
M3 M4
RB = 8.8 MΩ M6
(W/L)6 = 400
ID1 = 5 µA ID2 = 5 µA M11

IB = 1 µA M1 M2
(W/L)1,2 = 100
IB2 = 100 µA
IB1 = 10 µA
M8
M5 M7
(W/L)8 = 1 M12
(W/L)5 = 10
(W/L)7 = 100
-VSS = −5 V

Body effect
NMOS and PMOS transistor in a “vanilla” N-well CMOS process

Announcements
• Move Midterm exam from Oct 16-23 to Oct 23-30?

+VDD = 5 V
(W/L)3,4 = 20
M3 M4
RB = 8.8 MΩ M6
(W/L)6 = 400
ID1 = 5 µA ID2 = 5 µA M11

IB = 1 µA M1 M2
(W/L)1,2 = 100
IB2 = 100 µA
IB1 = 10 µA
M8
M5 M7
(W/L)8 = 1 M12
(W/L)5 = 10
(W/L)7 = 100
-VSS = −5 V

Body effect
NMOS and PMOS transistor in a “vanilla” N-well CMOS process

Body effect: large-signal model

Body effect: small-signal model

Op-amp in N-Well CMOS process
+VDD = 5 V
(W/L)3,4 = 20
M3 M4
RB = 8.8 MΩ M6
(W/L)6 = 400
M11
ID1 = 5 µA ID2 = 5 µA
IB = 1 µA M1 M2
(W/L)1,2 = 100
IB2 = 100 µA
IB1 = 10 µA
M8 M12
M5 M7
(W/L)8 = 1
(W/L)5 = 10
(W/L)7 = 100
-VSS = −5 V

Source follower gain and output resistance
including body effect

PMOS source follower (in N-well CMOS process)
+VDD = 5 V
(W/L)3,4 = 20
M3 M4
RB = 8.8 MΩ M6
(W/L)6 = 400
ID1 = 5 µA ID2 = 5 µA
IB = 1 µA M1 M2
(W/L)1,2 = 100
IB2 = 100 µA
IB1 = 10 µA
M8
M5 M7
(W/L)8 = 1
(W/L)5 = 10
(W/L)7 = 100
-VSS = −5 V

PMOS source follower (in N-well CMOS process)
+VDD = 5 V
(W/L)3,4 = 20
M3 M4
RB = 8.8 MΩ M6
(W/L)6 = 400
ID1 = 5 µA ID2 = 5 µA
IB = 1 µA M1 M2
(W/L)1,2 = 100
IB2 = 100 µA
IB1 = 10 µA
M8
M5 M7
(W/L)8 = 1
(W/L)5 = 10
(W/L)7 = 100
-VSS = −5 V

ECEN4827/5827
Introduction to 0.35u CMOS process

Spice models and Spice simulations using LTspice

Announcements
• Midterm exam has been rescheduled to Oct 23-30

Typical CMOS process (minimum channel length: 0.35µm)
Thick field
Polysilicon SiO2 oxide
(POLY): (FOX)
NMOS and
PMOS
gates
n+ diffusion p+ diffusion
(S and D of (S and D of
NMOS) PMOS)
• p substrate
• p well (body) for NMOS transistors, n well (body) for PMOS transistors
• n+ and p+ source/drain diffusions
• 1 or more polysilicon layers (2 POLY layers in this example)
• 2 or more metal layers (4 metal layers in this example)
inverter_intro.asc
metal
B S D
poly
L
G
D S B
layout
W
G

Spice model library: 5827_035.lib
NMOS transistor
NMOS B (p substrate) must be tied to most negative
nmos_035.asy
supply rail
PMOS transistor
PMOS B is n-well, usually most positive supply rail
pmos_035.asy
Rsheet = 1.2 kΩ/square, TC = −400 ppm/oC

RPN
rpn_035.asy “square” = L/W
RPP Rsheet = 50 Ω/square, TC = +830 ppm/oC

rpp_035.asy “square” = L/W
Unit-area (5µ*5µ) p+ diffusion to n-well diode

WDIODE n = area multiple. Cathode must be tied to the
wdiode.asy
most negative supply rail

Example: NMOS model D
B
G
S
nmos_035.asy
… more (BSIM3 model is very detailed and complicated)…
• W, L are circuit design parameters, minimum 0.35µ, minimum increment 0.1µ

• NMOS Spice model can be used as is a subcircuit, which allows automatic adjustments of AS
(source area), PS (source perimeter), DS (drain area) and PD (drain perimeter) as functions of W, or
as a native MOS device (user must then manually specify AS, PS, DS, PD)
• Very detailed BSIM3 model (industry standard)

Approximate models for hand
calculations
Vtn ≈ 0.48 V
µnCox ≈ 90 µA/V2
NMOS λn ≈ 0.035 1/V (L=1µ)
nmos_035.asy 0.025 1/V (L=2µ)
<0.015 1/V (L>4µ)
PMOS Vtp ≈ −0.62 V

pmos_035.asy µpCox ≈ 36 µA/V2
λp ≈ 0.046 1/V (L=1µ)
0.019 1/V (L=2µ)
<0.01 1/V (L>4µ)
Beware: do not expect very accurate results using hand

calculations, especially for short channel lengths (L < 2 µ)

Setting up 0.35u CMOS symbols and model library for
LTspice
Option 1: local (does not require administrative privileges)
• Place all symbol files (*.asy files) and model library (5827_035.lib) in a
working folder, together with schematics
Option 2: make symbols and model library globally available
• Place all symbols (*.asy files) in a new folder (e.g. 5827) in
C:\Program Files\LTC\SwCADIII\lib\sym
• Add model library 5827_035.lib to
C:\Program Files\LTC\SwCADIII\lib\sub
In any case, an LTspice schematic must include:
.lib 5827_035.lib

LTspice schematic entry
Run simulation Enter component Enter Spice

“dot”
commands
include
5807_035.lib
library

Use of NMOS symbol in LTspice
(1) place nmos_035 symbol (2) CTRL-right click to open Attribute Editor
(3) Change Prefix to X to use subcircuit model

with automatic adjustments of AS, PS, AD, PD
The same applies to pmos_035

Basic Spice simulations
Bias Point (.op)
• View DC operating point voltages and currents, and device small-signal
model parameters in (text)
DC Sweep (.dc)
• Plot DC (or temperature) characteristics
AC Sweep (.ac)
• Plot small-signal frequency responses
Transient (.tran)
• Plot large-signal (total) waveforms

DC sweep example: inverter VOUT versus VIN
Right-click to add cursors

AC sweep example: inverter as an amplifier, magnitude response ||vout/vin|| [dB]

Transient example: inverter vOUT(t) for pulsating vIN(t)

Hierarchical schematic entry
Inverter circuit with
ports labeled (using
Edit, Label Net, or Symbol representing the inverter circuit
F4 key)
inverter_035_1.asc inverter_035_1.asy
names must match
Symbols
used to
enter larger
circuits
test_inverter_035_1.asy

HW5 problem S8
vdd
VDD M8 M5 M7
b
W=10u W=50u W=250u
L=2u L=2u L=2u
3.3V
s
I1 M1 M2 p out
.lib 5827_035.lib Vp
W=50u W=50u
;dc Vin 0 3.3 0.01 L=1u L=1u 1.65
.op 1µA AC 1
;ac dec 200 10 100meg C1
1
3
M3 M4 1pF M6
W=10u W=10u W=100u
L=2u L=2u L=2u

Design of voltage and current references
Purpose: bias and active loads
Goals: set DC bias operating point
independent of
• Component tolerances
• Supply voltages
• Temperature ∆I ref
I ref I ref p ∂I ref
Sensitivity with respect to parameter p S p = =
∆p I ref ∂p
p
Fractional temperature coefficient
∆I ref
1 ∂I ref 1 I ref
I ref
TC F ( I ref ) = = = ST
∆T I ref ∂T T

Announcements
• Turn in HW5
• HW 2-4 have been graded
• HW6 is due Friday, Oct. 9
• Midterm exam has been rescheduled to Oct 23-30

independent of
• Supply voltages
∆p I ref ∂p
p
∆I ref
1 ∂I ref 1 I ref
I ref
TC F ( I ref ) = = = ST
∆T I ref ∂T T

Design problem (updated 10/04/09)
iout = +1 µA ±5% for vp = 0V
+VDD iout = −10 µA ±5% for vp = VDD
RB Wide-swing cascode
M5 M3 PMOS current mirrors
M4 i2
M2
iout
I5 I4 I3 I7 I6
+ vp +
– M1 – VO
i1
0.5 V ≤ VO ≤ 2.5 V
Wide-swing cascode NMOS current mirrors

Self-biased references: the need for a start-up
(“bootstrap”) circuit

Self-biased references: the need for a start-up
(“bootstrap”) circuit

independent of
• Supply voltages
∆p I ref ∂p
p
∆I ref
1 ∂I ref 1 I ref
I ref
TC F ( I ref ) = = = ST
∆T I ref ∂T T

Temperature dependences
Threshold voltage, TCF(Vt) ≈ −3000 ppm/oC
Resistors
Positive and negative TC resistors are available
Example 0.35u CMOS process: -400ppm/oC and +830ppm/oC
Mobility, and MOSFET conductance parameter TCF(µCox) » −5000 ppm/oC
Forward biased pn-junction (VEB, VBE or VD), −2mV/oC
Thermal voltage VT = kT/q = 26mV at 300oK,
+3300ppm/oC at room temperature

Fractional temperature coefficient: simple examples

Introduction to bandgap references
Idea: a combination of forward-biased pn junction voltage and a voltage
proportional to the thermal voltage can result in ideally zero
temperature coefficient (at one temperature)

pn-junction in an n-well process
(WDIODE component in the CMOS 0.35u process)

Introduction to bandgap references
Idea: a combination of forward-biased pn junction voltage and a voltage
proportional to the thermal voltage can result in ideally zero
temperature coefficient (at one temperature)

pn-junction in an n-well process
(WDIODE component in the CMOS 0.35u process)

How to obtain voltage proportional to VT?

A bandgap reference circuit example



Announcements
• Turn in HW6
• HW7 is due next Friday, Oct. 16
• Take-home midterm exam will be handed out on Friday, Oct. 23


Bandgap reference: temperature dependence*
*Reference: Gray, Hurst, Lewis, Meyer, Analysis and Design of Analog Integrated Circuits
Bandgap reference: temperature dependence

Mismatch effects in Analog CMOS IC design
Matching is a key idea in analog IC design
• Absolute tolerances in device parameters are relatively large
• Identically sized devices on the same Silicon die:
– Have (nearly) the same parameters
– Operate at (nearly) the same temperature
Application examples studied so far:
• Distribution of bias currents using current mirrors
• Differential amplifiers
• Cancellation of temperature dependences
Next topic: effects of (small, random) mismatches in device parameters
• Input offset voltage in a differential amplifier with active load
• Current mirror mismatches

Random mismatches
Sources of random mismatch include:
• Edge effects (rough edges)
• Material imperfections
• Variations in mobility
Device mismatch parameters:

• MOSFET
Threshold voltage Vt,
Conductance parameter K = (µCox/2)(W/L) = β/2
Body effect parameter γ
• Resistors
ρ (resistivity)
• Capacitors
Oxide thickness variation

Threshold Voltage Mismatch
The threshold voltages among a group of transistors

has a Gaussian profile about a mean. Experimentally,
it has been shown that the difference in threshold
voltages between 2 identically sized transistors behaves as:
AVt
σ ∆V =
t
Note that to reduce the mismatch by ½ takes 4 times the area…
WL
A fab will create test structures and measure ∆Vt multiple times per wafer for various
sizes of transistors and collect ongoing statistics to monitor the process over time

NMOS
The mismatch constant, AVT, varies roughly linearly with process size. For p substrates, the PMOS
has AVT ~ 1.5*AVT NMOS.

Conductance Parameter Mismatch
σ (∆β ) Aβ
=
β WL
Typical Aβ = 2%µm
Reference: Marcel J. M. Pelgrom, Matching properties of MOS

transistors, IEEE JSSC, Oct. 1989

Application Example: Input Offset Voltage in
a 2-stage CMOS op-amp
+VDD
M3 M4
M6
M1 M2
M8
M5 M7
-VSS

Input Offset Voltage in Differential Amplifier
with Active (Current-Mirror) Load
+VDD
M3 M4
M1 M2
-VSS

Design Problem D.1
Solution posted with HW6 solutions

Continue Vos analysis taking into account
random mismatches

The threshold voltages among a group of transistors
has a Gaussian profile about a mean. Experimentally,
it has been shown that the difference in threshold
voltages between 2 identically sized transistors behaves as:
AVt
 V 
t
Note that to reduce the mismatch by ½ takes 4 times the area…
WL
A fab will create test structures and measure Vt multiple times per wafer for various
sizes of transistors and collect ongoing statistics to monitor the process over time

Conductance Parameter Mismatch
   A

 WL
Typical A = 2%m
Reference: Marcel J. M. Pelgrom, Matching properties of MOS

transistors, IEEE JSSC, Oct. 1989

Application Example: Input Offset Voltage in
a 2-stage CMOS op-amp
+VDD
M3 M4
M6
M1 M2
M8
M5 M7
-VSS

+VDD
M3 M4
M1 M2
-VSS

+VDD
M3 M4
M1 M2
-VSS

Current-Mirror Mismatch
+VDD
M3 M4
M1 M2
-VSS

Announcements
Office hours tomorrow: 9-11am (not 10-12)

+VDD
M3 M4
M1 M2
-VSS

+VDD
M3 M4
M1 M2
-VSS

+VDD
M3 M4
M1 M2
-VSS

+VDD
M3 M4
M1 M2
-VSS

VOS calculation example
vdd
VDD
M8 M5 M7
b
W=10u W=50u W=250u
L=2u L=2u L=2u
3.3V
VSG1 - |Vtp| = 2.37-1.65-0.62 = 0.1 V s
I1 M1 M2 out
p
Vp
.lib 5827_035.lib
W=50u W=50u
;dc Vin 0 3.3 0.01 L=1u L=1u 1.65
.op 1µA AC 1
;ac dec 200 10 100meg C1
3
1
1pF
M3 M4 M6
W=10u W=10u W=100u

L=2u L=2u L=2u
VGS3 - Vtn = 0.58 - 0.48 = 0.1 V
Process parameters: AVtn = 8 mVµm, AVtp = 12 mVµm, Aβ = AK = 2%µm
AVt σ (∆K ) σ (∆β ) A

σ ∆V = = = β
t
WL K β WL

VOS calculation example

pdf
Normal distribution

Input offset voltage analysis, example 2*
Analysis
1. Calculate ∆Vgs of input pair
2. Calculate ∆Ιd/Id of current

mirror and reflect to input
using gm of input pair
3. Combine to find standard

deviation of VOS
Check using Spice Monte
Carlo analysis
CAD tools: Cadence
*This example in 0.5µ

CMOS process was
prepared by Art Zirger,
National Semiconductor

DC operating point

Offset analysis: ∆VGS of the NMOS diff pair
W/L = 20u/.5u, AVt = 16mVµm
gm_M0/M1 = 55.8µA/V, Id = 2.5µA, Αβ ~ 2%µm
2
 σ (∆β ) I D 
( )
σ ∆Vgs =   + (σ (∆VT ))2
 β gm 
AVt 16mVµm
σ ∆V = = = 5.06mV
t
WL 20 µm * 0.5µm
σ (∆β ) I D .02µm 2.5µA

= * = .28mV
β gm 20µm * 0.5µm 55.8 µA
V
σ (∆Vgs ) = (.28mV )2 + (5.06mV )2 = 5.07mV

Offset analysis: ∆ID of the PMOS mirror
2
2 2
 .02 µm 
2  7.32 µA 
σ (∆I D )  σ (∆β )   g m   23mVµm 
=   +  σ (∆VT ) =  
 + V
 = .025
ID  β   ID   2 µm * 4µm   2.5µA 2µm * 4 µm 
 
Effects on the input offset voltage:
 σ (∆I D ) 
σ ∆Vgs =   * I D / g mN = .025 * 2.5µA / 55.8 µA = 1.12mV
V
 ID 

Input offset voltage
σ ∆Vgs _ total = (5.07mV )2 + (1.12mV )2 = 5.19mV

input pair current mirror
Given a choice to add area to current mirrors or input pair, in this example,
more to be gained by using the area for the input pair.

CAD Tools for Checking Effects of Tolerances or Mismatches
Spice “Monte Carlo” (.mc) analysis*
• Device models must include statistical parameters (distribution, mean,
standard deviation)
• In Monte Carlo simulation, parameters of individual elements are selected
randomly based on the statistical distribution specified in the device model
• It is necessary to perform a large number of simulations (100’s) to develop
good statistics
*in LTSpice, Monte Carlo simulations can be done using mc(x,y) function, which generates a random number
between x*(1+y) and x*(1-y) with uniform distribution
Models available for the 0.35u process do not include statistical parameters

Example: Monte Carlo analysis of the input
offset voltage
1000 simulation runs

Result is a histogram of VOS values,
together with mean and standard
deviation
pdf
Normal distribution

Frequency responses of CMOS amplifiers
• Capacitances of MOS transistors
• Bandwidth limitations
• Frequency response of common-source amplifiers, dominant
pole concept
• BW estimation using Zero-Value Time-Constant (ZVTC)
techniques
• BW improvements via circuit design techniques
• Evaluation of frequency responses using NEET technique
• Frequency responses and compensation of feedback
amplifiers

MOS transistor capacitances:
(1) pn-junction capacitances
G
B S D
p+ n+ n+
channel
depletion region
Csb Cdb
p-sub
C sbo Cdbo
Csb = C db =
V V
1 + SB 1 + DB
ψo ψo

Junction capacitances as functions of AS, PS, AD, PD
D
B
G
S
nmos_035.asy

(2) Gate-to-Source capacitance
L
W
C gs = Coverlap + C gate−to − channel
G
B S D
Coverlap = Col × W
p+ n+ n+
channel
2
depletion region C gate −to −channel = Cox × W × L
Csb Cdb 3
p-sub
2
overlap
C gs ≈ C gate−to −channel = CoxWL
3
G
S
n+
p-sub
Col = ∆ × Cox

(3) Gate-to-Drain capacitance
W Col = ∆ × Cox
G
B S D C gd = Coverlap = ColW
p+ n+ n+
channel
depletion region
Csb Cdb
p-sub

Announcements
• Turn in HW7
• Take-home midterm exam handed out next Friday
• Best reported PDD in the design problem:
• ECEN4827: 7.82 uW
• ECEN5827: 5.275 uW

Frequency responses of CMOS amplifiers
• Capacitances of MOS transistors
• Bandwidth limitations
• Frequency response of common-source amplifiers, dominant
pole concept
• BW estimation using Zero-Value Time-Constant (ZVTC)
techniques
• BW improvements via circuit design techniques
• Evaluation of frequency responses using NEET technique
• Frequency responses and compensation of feedback
amplifiers

(1) pn-junction capacitances
G
B S D
p+ n+ n+
channel
depletion region
Csb Cdb
p-sub
C sbo Cdbo
Csb = C db =
V V
1 + SB 1 + DB
ψo ψo

Junction capacitances as functions of AS, PS, AD, PD
D
B
G
S
nmos_035.asy

(2) Gate-to-Source capacitance
L
W
C gs = Coverlap + C gate−to − channel
G
B S D
Coverlap = Col × W
p+ n+ n+
channel
2
depletion region C gate −to −channel = Cox × W × L
Csb Cdb 3
p-sub
2
overlap
C gs ≈ C gate−to −channel = CoxWL
3
G
S
n+
p-sub
Col = ∆ × Cox

(3) Gate-to-Drain capacitance
W Col = ∆ × Cox
G
B S D C gd = Coverlap = ColW
p+ n+ n+
channel
depletion region
Csb Cdb
p-sub

MOS transistor model with capacitances
B
S D
Csb Cgs Cgd Cdb

0.35u CMOS process: approximate
models for hand calculations
Cgs ≈ [3 fF/(µm)2]*W*L
NMOS Cgd ≈ [0.3 fF/(µm)]*W
nmos_035.asy Cdb ≈ [1.5 fF/(µm)]*W
Csb ≈ [1.5 fF/(µm)]*W + [0.75 fF/(µm)2]*W*L
Cgs ≈ [3 fF/(µm)2]*W*L
PMOS
pmos_035.asy Cgd ≈ [0.15 fF/(µm)]*W
Cdb ≈ [2.5 fF/(µm)]*W
Csb ≈ [2.5 fF/(µm)]*W + [1.25 fF/(µm)2]*W*L
Beware: do not expect very accurate results using hand calculations,

especially for short channel lengths (L < 2 µ)

fT of MOS transistors

fT of MOS transistors

CS amplifier frequency responses
+VDD
M2 M3
VO+vo
Rin
M1 CL
VI+vi +
–

CS amplifier small-signal model
+VDD
M2 M3
VO+vo
Rin
M1 CL
VI+vi +
–

CS amplifier frequency responses
+VDD
M2 M3
VO+vo
Rin
M1 CL
VI+vi +
–

CS amplifier small-signal model
+VDD
M2 M3
VO+vo
Rin
M1 CL
VI+vi +
–

CS amplifier A(s)
Cgd1
Rin
+ +
vi + Cgs1 vgs1
– R2 C2 vo
gm1vgs1
_ _

CS amplifier A(s)

CS amplifier magnitude response and BW
20 log A( jω ) [dB]
f [Hz] (log scale)

Dominant pole approximation

Zero-value time constant (ZVTC) method

ZVTC method applied to the CS amplifier
Cgd1
Rin
+ +
vi + Cgs1 vgs1
– R2 C2 vo
gm1vgs1
_ _

τgs1
Rin
+ +
vgs1 R2 vo
gm1vgs1
_ _

τ2
Rin
+ +
vgs1 R2 vo
gm1vgs1
_ _

τgd1
Rin
+ +
vgs1 R2 vo
gm1vgs1
_ _

Announcements
The Renewable & Sustainable Energy Institute (RASEI), a joint effort between CU Boulder and
National Renewable Energy Lab (NREL), is holding a Research Symposium today in the
UMC (Glen Miller Ballroom, 2nd floor). 105 posters on various energy related topics will be
presented in two sessions: 11am-12:30pm and 2-3:30pm.
Our group has 4 posters:
• poster #68 (11am-12:30pm) New Balance-of-System Architectures for Building-
Integrated Photovoltaics, Bob Erickson, Aaron Rogers and David Jones
• poster #69 (2-3:30pm) New Low-Cost High-Efficiency Module-Mounted Photovoltaic
Microinverters, Dan Friedrichs, Joshua Johnson, Bob Erickson
• poster #103 (2-3:30pm) Study of Plug-In Hybrid Electric Vehicles in Colorado, Dragan
Maksimovic, Li Shang, Tony Markel, Terry Penney
• poster #105 (2-3:30pm) Multi-Cell Battery Systems, Dragan Maksimovic, Regan Zane,
Bob Erickson

Dominant pole approximation

Zero-value time constant (ZVTC) method

ZVTC method applied to the CS amplifier
Cgd1
Rin
+ +
vi + Cgs1 vgs1
– R2 C2 vo
gm1vgs1
_ _

τgs1
Rin
+ +
vgs1 R2 vo
gm1vgs1
_ _

τ2
Rin
+ +
vgs1 R2 vo
gm1vgs1
_ _

τgd1
Rin
+ +
vgs1 R2 vo
gm1vgs1
_ _

Cgd is a “Miller” capacitor

CS dominant pole estimation using ZVTC

Possible improvements?
+VDD
M2 M3
VO+vo
Rin
M1 CL
VI+vi +
–

Improvement 1: Cascode
+VDD
M2 M3
VO+vo
VBIAS
M4
CL
Rin
M1
VI+vi +
–

Announcements
• Turn in HW8
• Pick up Midterm Exam
• Take home, open notes, book, on-line course materials
• Absolutely no collaboration is allowed. You may not consult
with anyone about the exam problems or use anyone else’s
work related to solutions of the exam problems in any form
– Violation of this rule will result in (at least) an immediate zero
credit on the midterm exam for all parties involved
• Due: in class next Friday
• Request exam by email upon completion of HW8
• Due by the end of the day, one week after you received a copy by
email

Midterm Exam Design Problem 5
IDD VOUT
Voltage
regulator
VDD + IOUT
–
Microprocessor
1. VDD = DC voltage in the range from 3.3V to 3.6V.

2. Temperature range: −20oC to 100oC.
3. Microprocessor DC load current: 0 ≤ IOUT ≤ 10 mA.
4. VOUT is within 1.5 V ± 0.5% over all specified DC load currents IOUT at room
temperature (27oC, the default temperature in Spice simulations), for two input
voltages VDD = 3.3 V, and VDD = 3.6 V.
5. VOUT is within 1.5 V ± 0.5% over all specified temperatures, for VDD = 3.3 V,
and for two load currents, IOUT = 0 mA, and IOUT =10 mA.

Possible improvements?
+VDD
M2 M3
VO+vo
Rin
M1 CL
VI+vi +
–

Improvement 1: Cascode
+VDD
M2 M3
VO+vo
VBIAS
M4
CL
Rin
M1
VI+vi +
–

+VDD
M2 M3
VO+vo
VBIAS
M4
CL
Rin
M1
VI+vi +
–

+VDD
M2 M3
VO+vo
VBIAS
M4
CL
Rin
M1
VI+vi +
–

+VDD
M2 M3
VO+vo
VBIAS
M4
CL
Rin
M1
VI+vi +
–

Application of ZVTC when stages are decoupled

Further improvement opportunities?
+VDD
M2 M3
VO+vo
VBIAS
M4
CL
Rin
M1
VI+vi +
–

Handling large capacitive loads:
source-follower (common-drain) stage


Source follower small-signal model
Cgd
Rin
vi + Cgs vgs
– ro
gmvgs gmbvbs
_
+
CL vo

Low-frequency gain A(0)
Rin
vi + vgs
– ro
gmvgs gmbvbs
_
+
vo
_

τgd
Rin
vi + vgs
– ro
gmvgs gmbvbs
_
+
vo
_

τL
Rin
vi + vgs
– ro
gmvgs gmbvbs
_
+
vo
_

τgs
Rin
vi + vgs
– ro
gmvgs gmbvbs
_
+
vo
_

Source follower BW estimate using ZVTC

Finding complete A(s) using NEET
NEET = “N-Extra-Element-Theorem”
R.D.Middlebrook, Vatché Vorpérian, and John Lindal, “The N Extra Element Theorem,” IEEE
Trans. on Circuits and Systems I: Fundamental Theory and Applications, vol. 45, no. 9, Sept.
1998; pp. 919-935.
+
+ Low-frequency small-signal model vo
vi (linear)
–
_
C1 C2 Cn
vo 1 + b1s + ... + bm s m
A( s ) = = A(0)
vi 1 + a1s + ... + an s n

A( s ) =
vo
vi
= A(0)
1 + b1s + ... + bm s m
1 + a1s + ... + an s n
A(0)
+
+ Low-frequency small-signal model
vi vo
– (linear)
_

vo 1 + b1s + ... + bm s m
A( s ) = = A(0)
vi 1 + a1s + ... + an s n a1
+
Low-frequency small-signal model
(linear) vo
_

A( s ) =
vo
vi
= A(0)
1 + b1s + ... + bm s m
1 + a1s + ... + an s n
a2
+
(linear) vo
_

vo 1 + b1s + ... + bm s m
A( s ) = = A(0)
vi 1 + a1s + ... + an s n a3
+
(linear) vo
_


Source follower small-signal model
Cgd
Rin
vi + Cgs vgs
– ro
gmvgs gmbvbs
_
+
CL vo

Low-frequency gain A(0)
Rin
vi + vgs
– ro
gmvgs gmbvbs
_
+
vo
_

τgd
Rin
vi + vgs
– ro
gmvgs gmbvbs
_
+
vo
_

τL
Rin
vi + vgs
– ro
gmvgs gmbvbs
_
+
vo
_

τgs
Rin
vi + vgs
– ro
gmvgs gmbvbs
_
+
vo
_

Source follower BW estimate using ZVTC

Finding complete A(s) using NEET
NEET = “N-Extra-Element-Theorem”
R.D.Middlebrook, Vatché Vorpérian, and John Lindal, “The N Extra Element Theorem,” IEEE
Trans. on Circuits and Systems I: Fundamental Theory and Applications, vol. 45, no. 9, Sept.
1998; pp. 919-935.
+
+ Low-frequency small-signal model vo
vi (linear)
–
_
C1 C2 Cn
vo 1 + b1s + ... + bm s m
A( s ) = = A(0)
vi 1 + a1s + ... + an s n

A( s ) =
vo
vi
= A(0)
1 + b1s + ... + bm s m
1 + a1s + ... + an s n
A(0)
+
vi vo
– (linear)
_

vo 1 + b1s + ... + bm s m
A( s ) = = A(0)
vi 1 + a1s + ... + an s n a1
+
(linear) vo
_

A( s ) =
vo
vi
= A(0)
1 + b1s + ... + bm s m
1 + a1s + ... + an s n
a2
+
(linear) vo
_

vo 1 + b1s + ... + bm s m
A( s ) = = A(0)
vi 1 + a1s + ... + an s n a3
+
(linear) vo
_

vo 1 + b1s + ... + bm s m
A( s ) = = A(0)
vi 1 + a1s + ... + an s n b1
+
vi (linear) vo 0
–
_

vo 1 + b1s + ... + bm s m
A( s) = = A(0)
vi 1 + a1s + ... + an s n b2
+
vi (linear) vo 0
–
_

A simple NEET application example

Example: source follower A(s)
Rin
vi + vgs
– ro
gmvgs gmbvbs
_
+
vo
_

Rin
vi + vgs
– ro
gmvgs gmbvbs
_
+
vo
_

Rin
vi + vgs
– ro
gmvgs gmbvbs
_
+
vo
_

Rin
vi + vgs
– ro
gmvgs gmbvbs
_
+
vo
_

Rin
vi + vgs
– ro
gmvgs gmbvbs
_
+
vo
_

Rin
vi + vgs
– ro
gmvgs gmbvbs
_
+
vo
_

Rin
vi + vgs
– ro
gmvgs gmbvbs
_
+
vo
_

Rin
vi + vgs
– ro
gmvgs gmbvbs
_
+
vo
_

Rin
vi + vgs
– ro
gmvgs gmbvbs
_
+
vo
_

Source-follower A(s)

Source-follower A(s)

Announcements
Turn in Midterm exam
HW9 is due Friday, Nov. 6

Feedback Circuits
• Feedback theorem (due to Prof. David Middlebrook, Caltech)
• Closed-loop response as a function of
– Ideal closed loop gain
– Loop gain
– Direct transmission through the feedback path
• Frequency responses of feedback circuits based on op-amps with
approximately single-pole open-loop response
• Op-amp gain-bandwidth product, GBW
• Cross-over frequency fc and closed-loop bandwidth BWCL
• Stability and compensation of feedback circuits
• Loop-gain magnitude and phase responses
• Phase margin, gain margin
• Relationship between phase margin and closed-loop responses:
how much phase margin is required?
• Compensation
• 2-stage CMOS op-amp: dominant-pole (“Miller”) compensation
• Large-signal dynamic responses limitations: slew-rate

A Single-Loop Feedback System
+
+ –

Middlebrook’s Feedback Theorem*
+
+ –
*For derivation, see notes posted on the course website

Example

Comments

Feedback circuits based on op-amps with
single-pole open-loop response A(s)

Reminder: NMOS and PMOS models in LTspice
(1) place nmos_035 symbol (3) Change Prefix to X to use the subcircuit model
The same applies to pmos_035 with automatic adjustments of AS, PS, AD, PD,
which affect the values of Csb and Cdb capacitors
(2) CTRL-right click to open

Attribute Editor To get credit for LTspice
simulation problems (e.g. S10 and
S11 in HW9), all devices must use
the subcircuit (X) models

Feedback circuits based on op-amps with
single-pole open-loop response A(s)

Example: non-inverting amplifier

Summary: single-pole open-loop response,
loop gain and closed-loop response

Example: inverting amplifier

Dominant-pole A(s) in 2-stage CMOS op-amp
+VDD = 5 V
(W/L)3,4 = 20
M3 M4
M6
ID1 = 5 µA ID2 = 5 µA
IB = 1 µA M1 M2
(W/L)1,2 = 100
IB2 = 100 µA
IB1 = 10 µA
M8
M5 M7
(W/L)8 = 1
(W/L)5 = 10 (W/L)7 = 100
-VSS = −5 V

Dominant-pole due to Cc (Miller cap) and GBW


Example: inverting amplifier

+VDD = 5 V
(W/L)3,4 = 20
M3 M4
M6
ID1 = 5 A ID2 = 5 A
IB = 1 A M1 M2
(W/L)1,2 = 100
IB2 = 100 A
IB1 = 10 A
M8
M5 M7
(W/L)8 = 1
(W/L)5 = 10 (W/L)7 = 100
-VSS = 5 V

Dominant-pole due to Cc (Miller cap) and GBW

+VDD = 5 V
(W/L)3,4 = 20
M3 M4
M6
ID1 = 5 A ID2 = 5 A
IB = 1 A M1 M2
(W/L)1,2 = 100
IB2 = 100 A
IB1 = 10 A
M8
M5 M7
(W/L)8 = 1
(W/L)5 = 10 (W/L)7 = 100
-VSS = 5 V

Time-domain: closed-loop step response

Slew-rate limitation
+VDD = 5 V
(W/L)3,4 = 20
M3 M4
M6
ID1 = 5 A ID2 = 5 A
IB = 1 A M1 M2
(W/L)1,2 = 100
IB2 = 100 A
IB1 = 10 A
M8
M5 M7
(W/L)8 = 1
(W/L)5 = 10 (W/L)7 = 100
-VSS = 5 V

Summary: GBW and SR limitations

Stability of feedback circuits: introduction

Stability of feedback circuits: introduction

Announcements
Turn in HW9
HW10 is due Friday, Nov. 13
Pick up graded midterm exam

Averages:
ECEN4827: 68
ECEN5827: 87
Best designs
ECEN4827: 30.7uA (by Greg Stahl)
ECEN5827: 1.9uA (by Eric Pahlke)

Midterm Exam Solutions: problem 3
+VDD
M11 M13
M9 M10 M12
ID13
ID12
ID10 ID11
M1 M2
100/1 100/1
I M3 M4 M5
V1 V2
M6 M7 M8

Midterm exam solutions: design problem

Midterm Exam Design Problem Solution
Design by Dave E. Norton Jr. (Fall 2008), meets all specs with IQ = 4.39uA
Fall 2008 ECEN4827/5827 midterm exam, design problem 4

Solution by Dave E. Norton Jr.
IQ = 4.39 uA
M2 M1 M3 M9 M15 M14 M10

W=111u W=10u W=20u W=10u W=10u W=10u W=1000u
L=2u L=2u L=2u L=2u L=2u L=2u L=1u
2.3uA 1.5V
1.43uA 0.11uA VO
vbg 0.24uA 0.11uA
VDD U5 W=2u
U4 W=1u RPN L=87u
RPN L=500u
3.3V Iout
M4 M5
W=100u W=100u M11 M12
L=1u L=1u C1 vbg
W=50u W=50u 0
U3 W=1u 1.38V L=1u L=1u
1pf
RPN L=495u
0.2uA U6 W=1u
M7 M6 M8 M13 .lib 5827_035.lib RPN L=500u
U1 U2
n=1 n=1 .op
W=10u W=10u W=10u W=20u
L=2u L=2u L=2u L=2u .step temp -20 100 2 Iout 0 10m 10m VDD 3.3 3.6 0.3
;dc Iout 0 10m 10u VDD 3.3 3.6 0.3

Midterm Exam Design Problem Solution
V(vo)
1.5075V
1.5065V
1.5055V
1.5045V
1.5035V
1.5025V
VDD=3.6V, Iout=0mA
1.5015V
VDD=3.3V, Iout=0mA
1.5005V
1.4995V
VDD=3.6V, Iout = 10mA
1.4985V
1.4975V
1.4965V
VDD=3.3V, Iout=10mA
1.4955V
1.4945V
1.4935V
1.4925V
-20°C -10°C 0°C 10°C 20°C 30°C 40°C 50°C 60°C 70°C 80°C 90°C 100°C


+VDD = 5 V
(W/L)3,4 = 20
M3 M4
M6
ID1 = 5 µA ID2 = 5 µA
IB = 1 µA M1 M2
(W/L)1,2 = 100
IB2 = 100 µA
IB1 = 10 µA
M8
M5 M7
(W/L)8 = 1
(W/L)5 = 10 (W/L)7 = 100
-VSS = −5 V

Stability assessment via loop gain:
cross-over frequency and phase margin

Compensation of feedback circuits
Shape loop gain T(s) so that
1. Cross-over frequency fc is as high as possible
(to maximize closed-loop bandwidth BWCL)
2. Maintain large enough phase margin
PM > 0 is required for stability
Larger PM is required for
(a) well-behaved closed-loop response
(b) robustness, i.e., maintain stability and well-
behaved closed-loop responses over process and
temperature variations
How much phase margin is required?
Assume 2nd-order T(s)
Case #1: fp2 > T(0)fp1

IQ=1.87uA
1.35uA 79nA
0.18uA
0.18uA
78nA
1.333V
1.5V

VDD=3.6V, Iout=0
VDD=3.6V, Iout=10mA
VDD=3.3V, Iout=0
VDD=3.3, Iout=10mA


+VDD = 5 V
(W/L)3,4 = 20
M3 M4
M6
ID1 = 5 A ID2 = 5 A
IB = 1 A M1 M2
(W/L)1,2 = 100
IB2 = 100 A
IB1 = 10 A
M8
M5 M7
(W/L)8 = 1
(W/L)5 = 10 (W/L)7 = 100
-VSS = 5 V

Stability assessment via loop gain:
cross-over frequency and phase margin

Compensation of feedback circuits
Shape loop gain T(s) so that
1. Cross-over frequency fc is as high as possible
(to maximize closed-loop bandwidth BWCL)
2. Maintain large enough phase margin
PM > 0 is required for stability
Larger PM is required for
(a) well-behaved closed-loop response
(b) robustness, i.e., maintain stability and well-
behaved closed-loop responses over process and
temperature variations
How much phase margin is required?
Assume 2nd-order T(s)
Case #1: fp2 > T(0)fp1

Case #2: fp2 < T(0)fp1

Relationship between PM and closed-loop responses

Relationship between PM and closed-loop responses
Frequency domain Time domain: step-response
PM QCL p [%]
0o 100
30o 1.9 40
45o 1.2 16
60o 0.8 9
65o 0.7 5
76o 0.5 0
Example: problem D.3. solutions









Next: Dominant-pole compensation of the 2-stage CMOS op-amp
+VDD = 5 V
(W/L)3,4 = 20
M3 M4
M6
ID1 = 5 µA ID2 = 5 µA
IB = 1 µA M1 M2
(W/L)1,2 = 100
IB2 = 100 µA
IB1 = 10 µA
M8
M5 M7
(W/L)8 = 1
(W/L)5 = 10 (W/L)7 = 100
-VSS = −5 V

Announcements
• Turn in HW10
• HW11 due Friday, Nov.20 in class

Dominant-pole compensation of the 2-stage CMOS op-amp
+VDD = 5 V
(W/L)3,4 = 20
M3 M4
M6
ID1 = 5 µA ID2 = 5 µA
IB = 1 µA M1 M2
(W/L)1,2 = 100
IB2 = 100 µA
IB1 = 10 µA
M8
M5 M7
(W/L)8 = 1
(W/L)5 = 10 (W/L)7 = 100
-VSS = −5 V

2-stage CMOS op-amp model: A(s) including Cc and high-frequency dynamics



Unity-gain feedback circuit: T(s) = A(s)

Phase margin, fc, high-frequency pole, and RHP zero

RHP Zero Cancellation
+VDD = 5 V
(W/L)3,4 = 20
M3 M4
M6
ID1 = 5 µA ID2 = 5 µA
IB = 1 µA M1 M2
(W/L)1,2 = 100
IB2 = 100 µA
IB1 = 10 µA
M8
M5 M7
(W/L)8 = 1
(W/L)5 = 10 (W/L)7 = 100
-VSS = −5 V


Dominant-pole compensation of the 2-stage CMOS op-amp
+VDD = 5 V
(W/L)3,4 = 20
M3 M4
M6
ID1 = 5 A ID2 = 5 A
IB = 1 A M1 M2
(W/L)1,2 = 100
IB2 = 100 A
IB1 = 10 A
M8
M5 M7
(W/L)8 = 1
(W/L)5 = 10 (W/L)7 = 100
-VSS = 5 V




Unity-gain feedback circuit: T(s) = A(s)

Phase margin, fc, high-frequency pole, and RHP zero

+VDD = 5 V
(W/L)3,4 = 20
M3 M4
M6
ID1 = 5 A ID2 = 5 A
IB = 1 A M1 M2
(W/L)1,2 = 100
IB2 = 100 A
IB1 = 10 A
M8
M5 M7
(W/L)8 = 1
(W/L)5 = 10 (W/L)7 = 100
-VSS = 5 V



RHP Zero Cancellation: Implementation
+VDD = 5 V
(W/L)3,4 = 20
M3 M4
M6
ID1 = 5 A ID2 = 5 A
IB = 1 A M1 M2
(W/L)1,2 = 100
IB2 = 100 A
IB1 = 10 A
M8
M5 M7
(W/L)8 = 1
(W/L)5 = 10 (W/L)7 = 100
-VSS = 5 V

Examples of more advanced op-amp architectures
(on-line course notes)
• Rail-to-rail input stage

• Low-output resistance rail-to-rail output stage
• Class-AB rail-to-rail output stage
• Fully-differential amplifiers

+VDD = 5 V
(W/L)3,4 = 20
M3 M4
M6
ID1 = 5 A ID2 = 5 A
IB = 1 A M1 M2
(W/L)1,2 = 100
IB2 = 100 A
IB1 = 10 A
M8
M5 M7
(W/L)8 = 1
(W/L)5 = 10 (W/L)7 = 100
-VSS = 5 V

Introduction to analog IC design in
power management applications
• Power management application example: battery-powered mobile electronics

• Brief introduction to operation and steady-state analysis of PWM switched-
mode power converters*
• Low-power monolithic DC-DC converter ICs: power MOSFETs and gate-drivers
• PWM controller architectures and analog IC building blocks
• Examples of PWM controller realizations
*ECEN5797 Introduction to Power Electronics provides in-depth coverage of this material

State-of-the-art portable applications, “smart phones”
• Much increased functionality
• Voice, data communication
• Applications
• Audio, Video, Camera
• Backlit touch-screen color display
• Multiple radios
• High-speed wireless (3G, e.g. WCDMA)
• Wi-Fi, Bluetooth
• GPS receiver
• Much increased processing power and data rates
• Much more activity in the usage model
• Severe impact on the battery life

Simplified system block diagram
Major power consumers: PA, baseband digital, display lighting, analog

Different voltage/current requirements
Antenna
Display
P/DSP D/A PA
core LO
Audio
A/D LNA
I/O
Interface
Multiple radio transceivers
Basic power management:

• Efficient distribution of required voltage/current levels
• ON/OFF control for all functional blocks

Power distribution
PS PS PS PS
3.6 V 2.5 V 1.5 V 0.5-Vbat
Antenna
Display
P/DSP D/A PA
core LO
PS Audio
A/D LNA
2.7-5.5 V I/O
Interface
2.5 V 2.5 V 2.5 V
PS PS PS
PS Power supply choices: (1) nothing, (2) LDO, (3) switcher, or (4) switched-cap

Power for P/DSP core
VDD
P/DSP P  CVDD
2
f c  VDD I off
core
• Dynamic or AC power: C(VDD)2fc

• Static or DC or leakage power: VDDIoff
• VDD down to 1-2 V or less, load current up to several 100 mA
C constant proportional to the number of gates and switching activity
fc clock frequency
Ioff leakage current proportional to the number of gates, increases with reduced
device threshold voltages Vtn, Vtp

Power Supply Example:
Step-Down Voltage Regulator
Battery Charger
Power distribution: Vg = 2.7-5.5 V
PS PS PS Step-down PS
voltage regulator
3.6 V 2.5 V
1.5 V 1-3.6 V Antenna
Display
P/DSP D/A PA
core LO
PS Audio
A/D LNA
2.7-5.5 V I/O
Interface
2.5 V 2.5 V 2.5 V
PS PS PS
Step-down regulators are used as power supplies for baseband

digital core and the RF power amplifier (PA)
Efficiency
Ig Io
Power
supply +
P/DSP
Vg + Vo core
–
_
output DC power Po Vo I o
  
input DC power Pg Vg I g
Vg = Vbat = input DC (battery) voltage

Linear voltage regulator as power supply
Series pass transistor
Q Iload
+ Load
Vbat + C Vo
–
–
“Error amplifier” with
loop compensation
+
Bandgap
- Vref
reference
Simple, low noise, small footprint area

Output voltage lower than the battery voltage
High efficiency only if Vo is close to input voltage Vbat = Vg

Linear regulator power model
Ig Rs Io
+
Vg + Vo
–
Bias current
IQ
–
I g  Io  IQ
Vo I o Vo I o
Efficiency: η 
Vg I g Vg ( I o  I Q )
Vo
Linear regulator efficiency cannot be greater than η
the ratio of the output and the input voltage Vg
Linear regulator efficiency example
100
90
80
Example:
70 Vg = 3.6 V
60 Vo = 1.5 V
Efficiency [%]
50
IQ = 50 A
0 < Io < 300 mA
40
.
30
20
10
0
0.1 1 10 100 1000
Io [mA]

Buck (step-down) switching power converter
Low-pass LC filter
Ig L Io
1
+ +
2
Vg + vs(t) C v(t)
– Load
– –
vs(t)
Vg fs = 1/Ts = switching
frequency
DTs D' Ts
D = switch duty cycle
0
0 DTs Ts t Conversion ratio:
Switch
Vo
position: 1 2 1
M (D)   D
Vg

Steady-state waveforms
iL
Vg
iL  (1  D) D
2 Lf s
v
Vg
v  2
(1  D) D
16CLf s

Switch-Mode Power Supplies
• Step-up, step-down and inverting configurations available
• Switching converters are ideally 100% efficient
• Real efficiency can be close to 100%; depends on operating
conditions and implementation
• Converters generate switching noise
• Discrete filter components (L, C) are required
• Higher switching frequency => smaller L, C
• Closed-loop output voltage control: switch duty cycle is the
control variable

SMPS efficiency as a function of load
100
90
80
Buck regulator
Example:
70
Vg = 3.6 V
Efficiency [%]
60
Vo = 1.5 V
50 0 < Io < 300 mA
Linear regulator
40
.
30
20
10
0
0.1 1 10 100 1000
Io [mA]

Impact of efficiency: a system example
uP/DSP core mode Stand-by Wait Run1 Run2 FullRun
% of time in this mode 90.0 4.0 3.0 2.5 0.5
Load current Io [mA] 0.1 1.0 10.0 100.0 300.0
Linear regulator Efficiency [%] 34.7 40.9 41.6 41.7 41.7

Battery current Ig [mA] 0.12 1.02 10.02 100.02 300.02
Average Ig in this mode [mA] 0.11 0.04 0.30 2.50 1.50
Total linear reg average Ig [mA] 4.45
SMPS Efficiency [%] 29.1 78.4 93.7 93.0 87.7

Battery current Ig [mA] 0.14 0.53 4.45 44.82 142.60
Average Ig in this mode [mA] 0.13 0.02 0.13 1.12 0.71
Total SMPS average Ig [mA] 2.12
100
90
Example: 80
Vg = 3.6 V
70
Efficiency [%]
60
Vo = 1.5 V 50
0 < Io < 300 mA 40

.
30
20
10
0
0.1 1 10 100 1000
Io [mA]

Impact of efficiency
• SMPS results in significantly lower average battery current
• High efficiency over a wide range of loads is important
• Low zero-load bias current IQ is particularly important for mobile
systems that spend significant amount of time in “stand-by” modes

Announcements
• Turn in HW11
• HW12 due Friday, December 4 in class

Switch realization with a synchronous rectifier
“Synchronous Buck”
PMOS: NMOS: synchronous rectifier
main switch PMOS ip(t) iL(t) L Io
+ + v ((t)) – +
in(t) L iC(t)
vp
Vg + NMOS vsw(t) C v(t)
– vn
– –
n
drivers
p
p Dead times are

Switch
used to prevent
control
short-circuit
h i i current
signals n
through PMOS/NMOS
td1 td2
“dead” times

“Non-synchronous Buck”
Switch realization with diode rectifier

PMOS: diode rectifier
+ + v (t) – +
in(t) L iC(t)
vp
Vg + vsw(t) C v(t)
–
– –
p
drivers
Switch
control p
signal
The diode rectifier is an on-chip body diode or an external Schottky rectifier

Switch currents
Average and RMS values
i p (t )
I p  i p (t )  DI o
I p ,rms  i p2 (t )  D I o
t
in (t )
I n  in (t )  (1  D ) I o
t I n ,rms  in2 (t )  1  D I o
Switch on-resistance and forward voltage drops result in switch conduction losses

Conduction-loss models
vON _
+ _
body diode vON +
body diode
ip(t) Ron,p ip(t)
in((t)) Ron,n in(t)
+
vON _ _
+ _
vSG vON +
_ vp ON OFF
vGS
vn ON OFF
+
PMOS: On-resistance NMOS: On-resistance Ron,n

Ron,p
_ vON +
in(t) L iL((t))
VD ideal
RD in(t) RL L iL(t)
vL _
_ vON + winding +
resistance
Diode: Forward voltage drop VD in

Inductor: Winding
g resistance RL
series
i with
ith on-resistance
it RD

Buck circuit when the PMOS is ON
ideal
Ron,p ip(t) RL L iL(t) Io
_ +
vON _ winding + vL
+
resistance
+ Vg V
–
vL  Vg  ( Ron , p  RL )iL  v  Vg  ( Ron , p  RL ) I o  V
i g  iL  I o

Buck circuit when the rectifier is ON
ideal
RL L iL(t) Io
vL _
winding +
resistance +
+ Vg V
–
vL  ( RD  RL )iL  VD  v  ( RD  RL ) I o  VD  V
ig  0

Steady-state model with conduction losses
Inductor volt-second balance:
vL  0
V  DVg  ( DRon , p  (1  D ) RD  RL ) I o  (1  D )VD
Input current:
I g  ig  DI o
Equivalent steady-state circuit model with conduction losses:

Ig DRon,p + (1-D)RD + RL Io
+
((1-D)V
) D
Vg + DIo + DVg R V
– –

Example:
synchronous rectifier versus diode rectifier
• Given Vg=3.6V, Vo=1.5V, Io=300mA

• Regulator A uses a PMOS switch with Ron,p
on p=0.4
0.4 and a Schottky
rectifier with VD=0.5 V, RD=0.1
• Regulator B uses a PMOS switch with Ron,p=0.4, and a synchronous
rectifier with Ron,n
on n=0.5
• Ripples are small and other losses of the two regulators are
comparable
• Which regulator has higher efficiency?

Solution
Use the equivalent circuit model to find the duty
cycle D:
Ig DRon,p + (1
(1-D)R
D)RD + RL Io
+
(1-D)VD
Vg + DIo + DVg R V
– –
V  DVg  ( DRon , p  (1  D ) RD  RL ) I o  (1  D )VD

VD  ( RD  RL ) I o
1 Note: because of losses,
V V V
D the duty cycle is greater D
Vg ( Ron , p  RD ) I o  VD Vg
1 than ideal steady-state
Vg

Find component losses, regulator A
D  0.54
PMOS: Ron , p DI o2  19mW

W
Diode: RD (1  D ) I o2  (1  D )VD I o  73mW
Inductor: RL I o2  1mW
Total conduction loss: Ploss  93mW

Po
Effi i
Efficiency (neglecting
( l ti other ) 
th losses):
l  83%
Po  Ploss

Find component losses, regulator B
D  0.46
PMOS: Ron , p DI o2  17 mW
NMOS: Ron ,n (1  D ) I o2  19mW
I d
Inductor: RL I o2  1mW
W
Total conduction loss: Ploss  37 mW

Po
Efficiency (neglecting other losses):    92%
Po  Ploss
Conclusion: the synchronous buck regulator B has

significantly lower conduction loss

Switching losses
Switching losses are losses proportional to the switching frequency
Switching loss mechanisms:
• Charging/discharging
g g g g of p
parasitic circuit capacitances
p including
g
– Capacitance at the switching node (vsw)
– Gate capacitances of the power switches
• Body-diode
B d di d reverse recovery
• Oscillator and other misc. controller losses
• Inductor eddy-current and core losses

Switching Losses in Synchronous Buck
PMOS ip(t) iL(t) L Io

+ + v (t) – +
in((t)) L iC((t))
vp
– vn
– –
n
Nodes with significant
drivers capacitances
p
p Dead times are

Switch
used to prevent
control
short circuit current
short-circuit
signals n
through PMOS/NMOS
td1 td2
“dead” times

Switching waveforms
PMOS switch PMOS switch
turn-on turn-off
3.6 V
0V
500 mA
0 mA
A
Example: Vg = 3.6 V, Vo = 1.8 V, Iload = 500 mA, fs = 1 MHz

Details of PMOS turn-on transition
3.6 V
b d di d
body-diode RoniL
conduction
0V
td1
dead-time
body-diode reverse recovery and charging

of capacitance at the “sw” node
500 mA
0 mA
A
Example: Vg = 3.6 V, Vo = 1.8 V, Iload = 500 mA, fs = 1 MHz 16

ECEN4827/5827 Analog IC Design
Typical experimental waveforms
Source: LM2608 data sheet,
iL (t ), 500 mA/div
vs (t ), 2 mA/div
Body-diode f s  670 KHz

conduction
An external Schottky diode can be used to eliminate or reduce body-diode conduction

and improve efficiency
More advanced solutions:

Adaptive adjustment of the dead times to
• pprevent
eve short-circuit
s o c cu current
cu e spikes
sp es andd
• minimize body diode conduction

Improving light-load efficiency
• In PWM mode, light-load efficiency is reduced because a significant portion of

switching losses does not scale with load
• In PWM mode, the oscillator and the power switches are always switching at high
switching frequency
• Low-power modes are based on the idea of reducing the switching frequency in
proportion to the load
• If the switching frequency is proportional to load, high efficiency can be
maintained over a very wide range of loads

Improving light-load efficiency using
pulse frequency modulation (PFM)
Drive signals in
Ts
constant-frequency
constant frequency
p
n PWM mode
Psw = approx. constant

t t
“Discontinuous conduction” Variable-frequency

iL (DCM) Ipeak PFM mode
Psw = approx.
p pproportional
p to
n
load current
Switching frequency in PFM mode
LI peak
Ipeak tp 
iL
Vg  Vo
LI peak
I o  iL tn 
Vo
tp tn
Ts
1
I o  I peak (t p  t n ) f s
2
2Vo I o  Vo 
fs  2 1  
LI peak  V 
 g 
In PFM, the switching frequency is directly proportional to the load current

Output voltage ripple in PFM
Ipeak
iL
I o  iL
tp tn
Ts
2
I peak LI peak Vg
(2v)  (t p  t n ) 
2C 2C Vo (Vg  Vo )
The output voltage ripple is typically higher in PFM

than in constant-frequency
q y PWM mode

Experimental waveforms in PFM
A triangle pulse of
inductor current is
d li
deliveredd to the
h output
filter capacitor only when
needed
PMOS turned on when the
output voltage drops to a
lower threshold, turned off
when the output voltage
exceeds an upper threshold
Source: LM2614 data sheet,


Efficiency analysis example:
battery
yppower as a function of load p
power
10000
1000
100
Pbat [mW]]
10 LDO
PWM
1 PWM/PFM
0.1
0.01
0.001
0.001 0.01 0.1 1 10 100 1000
Pout [mW]
Example: Vbat = 3.6 V, Vo = 1.8 V, 0 < Io < 500 mA

Efficiency comparison example
100
90
80
70
%]
Efficiency [%
60
LDO
50 PWM
PWM/PFM
40
30
20
10
0
0.01 0.1 1 10 100 1000
Iload [mA]
Example: Vbat = 3.6 V, Vo = 1.8 V, 0 < Io < 500 mA

Power Converter Operating Modes
• Best efficiency at moderate to
heavy load
• Constant
Constant-frequency,
frequency, low
switching noise
• Synchronization to external
PWM clock possible
• Relatively
R l ti l high
hi h IQ andd poor
light-load efficiency
• LDO: linear regulator

• Low-noise
LDO PFM
• Veryy low IQ
• Simple controller • High efficiency over very wide load range
• Very low IQ
• Simple controller
• Increased output voltage ripple and noise

Switch realization with a synchronous rectifier
“Synchronous Buck”
PMOS: NMOS: synchronous rectifier
+ + v ((t)) – +
in(t) L iC(t)
vp
– vn
– –
n
drivers
p
p Dead times are

Switch
used to prevent
control
short-circuit
h i i current
signals n
through PMOS/NMOS
td1 td2
“dead” times

Power MOSFETs and Gate Drivers
iL
iin iout
Mmain
Control FETSync FET
+ L +
+ 33% 33%
vin Mrect vout RL
CZVS C
- -
Switch Drive
d(t)
34%
d(t)
Example Loss
Distribution
 Large PMOS and NMOS power switches require large drivers
 Driver: a chain of logic inverters increasing in size (tapered buffers); driver
losses must be taken into account
 Concurrent designg optimization:
p select the sizes of the ppower FETs and the
driver stages to minimize the total loss: best conduction versus switching
loss trade-off
Power MOSFETs
Conduction (Ron) losses
dVds 1 W
Rst  
dI ds Vds 0 W
C ox (V gs  VT )
L L 
Power MOSFET
example in 0.5 m :
W=99 mm
W

NMOS on-resistance (0.35u CMOS process)
.lib 5827_035.lib
.param W=1u
Vds
Id
M1
VGS W={W}
L=0.35u 0
3.3V
.step dec param W 1000u 100000u 1

.dc Id 1m 1 1m

.lib 5827_035.lib
.param W=1u
Vds
W = 1000u, Ron = 1.94 
M1
Id @0.3A W = 10000u, Ron = 0.157 
VGS
3.3V
3 3V
W={W}
L=0.35u 0 W = 100000u, Ron = 0.0155 
.dc Id 1m 1 1m Ron(NMOS)  1.6 km/W
V( d )/Id
V(vds)/Id
10
0.1
0.01
0.001
0.1A 0.2A 0.3A 0.4A 0.5A 0.6A 0.7A 0.8A 0.9A

PMOS on-resistance (0.35u CMOS process)
.lib 5827_035.lib
.param W=1u
Vd
VGS M1 Id
3 3V
3.3V W={W}
W {W}
L=0.35u
0
Vs

.dc Id 1m 1 1m

.lib 5827_035.lib
.param W=1u W = 1000u, Ron = 35.4 
W = 10000u, Ron = 0.623 
Vd
VGS
3.3V
M1
W={W}
Id
@0.3A
W = 100000u, Ron = 0.060 
L=0.35u
0
Vs
Ron(PMOS)  6.5 km/W

.dc Id 1m 1 1m
(V( d) V( ))/Id
(V(vd)-V(vs))/Id
100
10
0.1
0.01
0.1A 0.2A 0.3A 0.4A 0.5A 0.6A 0.7A 0.8A 0.9A

Buck converter example in 0.35u CMOS
W=20000 0u
.tran
tran 0 100u 0 100n ECEN5827 open
open-loop
loop buck converter example
L=0.35u
.lib 5827_035.lib
M1
L1
VDD sw out
Vg 2 H
2µH
C1
M2 R1
g1 W=10000u 10µF 5
3.3V L=0.35u
Vg1 g2 Vg2
PULSE(3.3 0 0 10n 10n 460ns 1u PULSE(0 3.3 500ns 10n 10n 460n 1u

Start-up transient
V(sw)
4.5V
3.5V
2.5V
1.5V
0.5V
-0.5V
-1.5V
V(g1) V(g2)
3.3V
1.7V
0.0V
V(out)
2.0V
0 9V
0.9V
-0.2V
I(L1)
2.7A
1.1A
-0.6A

V(sw)
4.0V
3.0V
2.0V
1.0V
0 0V
0.0V
-1.0V
V(g1) V(g2)
3.6V
3.0V
2.4V
1.8V
1 2V
1.2V
0.6V
0.0V
V(out)
1.48V
1.47V
1.46V
1.45V
1.44V
1.43V
1.42V
I(L1)
1.0A
0.8A
0.6A
0.4A
0.2A
0.0A
60.0µs 60.2µs 60.4µs 60.6µs 60.8µs 61.0µs 61.2µs 61.4µs 61.6µs 61.8µs 62.0µs 62.2µs 62.4µs 62.6µs 62.8µs 63.0µs 63.2µs 63.4µs 63.6µs 63.8µs 64.0µs

Announcements
• Do not forget to do the on-line course FCQ
• Thursday, Dec.3: annual meeting of the Colorado Power Electronics
Center (CoPEC), our industry sponsored research center
• 10 sponsoring companies, 20+ graduate students
• Poster sessions: 10:30am-12pm and 1-3pm in EE1B65 (Power
Electronics Lab)
• Project topics:
– Digital control of switching power converters
– Custom ICs for power management applications
– Energy efficient lighting
– Energy harvesting
• Office hours on Dec.3: 4-5pm

.lib 5827_035.lib
.param W=1u
Vds
Id
M1
VGS W={W}
L=0.35u 0
3.3V

.dc Id 1m 1 1m

.lib 5827_035.lib
.param W=1u
Vds
W = 1000u, Ron = 1.94 
M1
Id @0.3A W = 10000u, Ron = 0.157 
VGS
3.3V
3 3V
W={W}
L=0.35u 0 W = 100000u, Ron = 0.0155 
.dc Id 1m 1 1m Ron(NMOS)  1.6 km/W
V( d )/Id
V(vds)/Id
10
0.1
0.01
0.001
0.1A 0.2A 0.3A 0.4A 0.5A 0.6A 0.7A 0.8A 0.9A

.lib 5827_035.lib
.param W=1u
Vd
VGS M1 Id
3 3V
3.3V W={W}
W {W}
L=0.35u
0
Vs

.dc Id 1m 1 1m

.lib 5827_035.lib
.param W=1u W = 1000u, Ron = 35.4 
W = 10000u, Ron = 0.623 
Vd
VGS
3.3V
M1
W={W}
Id
@0.3A
W = 100000u, Ron = 0.060 
L=0.35u
0
Vs
Ron(PMOS)  6.5 km/W

.dc Id 1m 1 1m
(V( d) V( ))/Id
(V(vd)-V(vs))/Id
100
10
0.1
0.01
0.1A 0.2A 0.3A 0.4A 0.5A 0.6A 0.7A 0.8A 0.9A

Buck converter example in 0.35u CMOS
W=20000 0u
.tran
tran 0 100u 0 100n ECEN5827 open
open-loop
loop buck converter example
L=0.35u
.lib 5827_035.lib
M1
L1
VDD sw out
Vg 2 H
2µH
C1
M2 R1
g1 W=10000u 10µF 5
3.3V L=0.35u
Vg1 g2 Vg2
PULSE(3.3 0 0 10n 10n 460ns 1u PULSE(0 3.3 500ns 10n 10n 460n 1u

Start-up transient
V(sw)
4.5V
3.5V
2.5V
1.5V
0.5V
-0.5V
-1.5V
V(g1) V(g2)
3.3V
1.7V
0.0V
V(out)
2.0V
0 9V
0.9V
-0.2V
I(L1)
2.7A
1.1A
-0.6A

V(sw)
4.0V
3.0V
2.0V
1.0V
0 0V
0.0V
-1.0V
V(g1) V(g2)
3.6V
3.0V
2.4V
1.8V
1 2V
1.2V
0.6V
0.0V
V(out)
1.48V
1.47V
1.46V
1.45V
1.44V
1.43V
1.42V
I(L1)
1.0A
0.8A
0.6A
0.4A
0.2A
0.0A
60.0µs 60.2µs 60.4µs 60.6µs 60.8µs 61.0µs 61.2µs 61.4µs 61.6µs 61.8µs 62.0µs 62.2µs 62.4µs 62.6µs 62.8µs 63.0µs 63.2µs 63.4µs 63.6µs 63.8µs 64.0µs

PMOS and NMOS instantaneous power dissipation
V(sw,VDD)*Id(M1)+V(g1,VDD)*Ig(M1) V(sw)*Id(M2)+V(g2)*Ig(M2)
1.8W
1.6W
1.4W
1.2W
1.0W
0.8W
0.6W
0.4W
0.2W
0.0W
-0.2W
V(sw)
4.0V
3.5V
3.0V
2.5V
2 0V
2.0V
1.5V
1.0V
0.5V
0.0V
-0.5V
-1.0V
-1.5V
60.88µs 60.96µs 61.04µs 61.12µs 61.20µs 61.28µs 61.36µs 61.44µs 61.52µs 61.60µs 61.68µs 61.76µs
I(L1)
600mA
500mA
400mA
300mA
200mA
100mA
0mA
60.88µs 60.96µs 61.04µs 61.12µs 61.20µs 61.28µs 61.36µs 61.44µs 61.52µs 61.60µs 61.68µs 61.76µs

Gate drivers

Inverter with size parameter x
VDD
M2
W={x*3u}
L=0.35u
in out
M1
W={x*1u}
L=0.35u
GND

Buck converter with gate drivers
000u
.tran 0 100u 0 100n ECEN5827 open-loop buck converter example
L=0.35u
W=200
.lib 5827_035.lib
M1
L1
VDD sw out
Vg 2µH
C1
g1
g
M2 R1
W=10000u
W 10000 10 F
10µF 5
3.3V L=0.35u
g2
VDD
x=100 x=20 x=4 x=1 Vg2
PULSE(0 3.3 500ns 10n 10n 460n 1u)

VDD
x=200 x=40 x=8 x=1 Vg1
PULSE(3.3 0 0 10n 10n 460ns 1u)

Gate-drive waveforms
V(sw)
4.0V
3.5V
3.0V
2.5V
2.0V
1.5V
1.0V
0.5V
0 0V
0.0V
-0.5V
-1.0V
V(g1) V(g1in) V(g2) V(g2in)
4.0V
3.5V
3 5
3.0V
2.5V
2.0V
1.5V
1.0V
0.5V
0.0V
-0.5V
-1.0V
57.960µs 57.974µs 57.988µs 58.002µs 58.016µs 58.030µs

Dead-time circuit: an example
000u
.tran 0 100u 0 100n ECEN5827 open-loop buck converter example
5u
W=200
L=0.35
.lib
lib 5827_035.lib
5827 035 lib
M1
L1
VDD sw out
Vg 2µH
C1
M2 R1
g1
W=10000u 10µF 5
3 3V
3.3V L 0 35
L=0.35u
g2
VDD
VDD
VDD
g2in
g2inv
pwm
x=1
x=100 x=20 x=4 x=1 x=1 Vpwm
R2
1meg
R3
VDD
VDD 1meg PULSE(0 3.3 0 0.1n 0.1n 460ns 1
g1in VDD
x=200
x 200 x=40
x 40 x=8 x=1
x=1

Leading PWM edge
V(pwm) V(g2in) V(g1in) V(sw)
4.0V
3.5V
3.0V
2.5V
2.0V
1.5V
1 0V
1.0V
0.5V
0.0V
-0.5V
-1.0V
75 999µs
75.999µs 76 001µs
76.001µs 76 003µs
76.003µs 76 005µs
76.005µs 76 007µs
76.007µs 76 009µs
76.009µs

Trailing PWM edge
V(pwm) V(g2in) V(g1in) V(sw)
4.0V
3.5V
3.0V
2.5V
2.0V
1.5V
1.0V
0.5V
0.0V
-0.5V
-1.0V
-1.5V
75.458µs 75.460µs 75.462µs 75.464µs 75.466µs 75.468µs 75.470µs

Closed-loop (feedback) control
iL(t) L Io
+ + vL(t) – +
iC(t)
Vg + vsw(t) C v(t)
–
– –
n
Controller
Vref
p
• The output
o tp t voltage
oltage is compared to a bandgap reference Vref
• The controller generates pulsating switch-control waveforms
(p and n) to (ideally) null the error
• Bandgap design is critical for voltage-regulation and IQ specs

Closed-loop (feedback) control
iL(t) L Io
+ + vL(t) – +
iC(t)
Vg + vsw(t) C v(t)
–
– –
n
Controller
Vref
p
• The output
o tp t voltage
oltage is compared to a bandgap reference Vref
• The controller generates pulsating switch-control waveforms
(p and n) to (ideally) null the error
• Bandgap design is critical for voltage-regulation and IQ specs

Voltage regulation objectives
Static voltage regulation
• DC output voltage precision, i.e., % variation (1% typical)
with
i h respect to the
h nominal
i l valuel over:
– input voltage range (“line regulation”)
– output
p load range
g ((“load regulation”)
g )
– process and temperature variations
Dynamic voltage regulation
• “Load transient response,” including peak output voltage
variation and settling time for a step load transient
• “Line transient response,” including output voltage variation
and settling time for a step input voltage transient

Two standard control approaches in
constant-frequency
constant frequency PWM converters
Voltage-mode control
• The switch duty cycle is controlled based on
output voltage sensing
Current-mode control
• The switch duty cycle is controlled based on
output voltage and switch current sensing

Voltage-Mode PWM Control Architecture
Power
input iL(t) L Io Load
+ + vL(t) – +
iC(t)
vg(t) + vsw(t) C v(t)

–
– – Feedback
Gate connection
drivers
p n
Dead time
Dead-time Compensator
Pulse-width vc v
modulator Gc(s)
p(t) vc(t) V lt
Voltage
reference Vref
dTs Ts t t
Controller chipp

HW circuit example

HW circuit example

VM vsaw(t)
Saw-tooth
p (t ) waveform vsaw (t ) vc(t)
+
Q R _
vc 0
t
S control
input p(t)
clock
OSC
0 dTs Ts 2Ts
clock
Improvement: PWM with feed-forward compensation:

VM proportional to the input voltage vg

PWM model
VC  vˆc 1 D  dˆ Vc
D
VM VM
VM is the amplitude of the saw-tooth

saw tooth waveform
1 dˆ 1
is the gain of the Pulse-Width Modulator 
VM vˆc VM
With feed-forward compensation: VM = k Vg
1 Vc 1
D DVg  Vc => improved line regulation
k Vg k

HW11 (improved compensation problem)
gm6 = 572 A/V, 1/gm6 = 1.75 k

Loop gain T magnitude and phase responses

Cc = 10 pF, ideal output buffer


Cc = 10 pF, source follower

Cc = 10 pF, source follower

Cc = 10 pF, source follower, v(out)/v(2)



Original circuit, Cc = 1 pF, source follower
gm6 = 572 A/V, 1/gm6 = 1.75 k

Original circuit, Cc = 1 pF, source follower, v(out)/v(2)

Loop gain T magnitude and phase responses

Modified compensation, Cc = 0.5 pF, source follower

Modified compensation, Cc = 0.5 pF, source follower

Feedback loop design around a switching converter
(HW circuit example)

VM vsaw(t)
Saw-tooth
p (t ) waveform vsaw (t ) vc(t)
+
Q R _
vc 0
t
S control
input p(t)
clock
OSC
0 dTs Ts 2Ts
clock
Improvement: PWM with feed-forward compensation:

VM proportional to the input voltage vg

PWM model
VC  vˆc 1 D  dˆ Vc
D
VM VM
VM is the amplitude of the saw-tooth

saw tooth waveform
1 dˆ 1
is the gain of the Pulse-Width Modulator 
VM vˆc VM
With feed-forward compensation: VM = k Vg
1 Vc 1
D DVg  Vc => improved line regulation
k Vg k

Converter transfer functions*
(small-signal averaged model)
vˆ  Gvc ( s )vˆc  Gvg ( s )vˆg  Z out ( s )iˆo
Control to output transfer function, relevant for closing
Control-to-output
Gvc (s
( )
the feedback loop around the converter
Line-to-output transfer function, relevant for finding
Gvg (s )
output voltage variations due to battery-voltage
battery voltage variations
Output impedance, relevant for finding output voltage
Z out (s )
variations due to load current variations
Vg d
L iL
+
vg + D iL + D vg C R v io
– –
Io d
–
*Material covered in detail in ECEN4797/5797

Example:
voltage-mode control-to-output response
Derive open-loop voltage-mode model of the buck converter that

includes conduction losses due to the switch on-resistances
Ron,p=Ron,n=Ron, the inductor winding resistance RL and the
capacitor ESR Resr
Given:
• Ron,p=Ron,n=Ron = 0.4
• L = 10 
H, RL = 0.1
• C = 22 F, Resr = 10 m
• Vg=3.6V, Vo=1.5 V, Io=300 mA, VM=1V
sketch the magnitude and phase responses of the control-to-output
transfer function

Small-signal dynamic (AC) model
Vg d
Ron + RL L iL
+
Resr
vg + D iL + D vg R v io
– –
Io d C
–
Standard circuit analysis yields converter open-loop transfer

functions

Solution: converter control-to-output response
s 1 R
1 wo  Q
Vg wz LC L/C
Gvc ( s )  2
VM 1 s  s 1 1 C
1     ( Ron  RL  Resr )
Qr wo  wo  Qr Q L
Notes:
• The center frequency of the pair of poles is essentially
the same as without losses
• The qqualityy factor Qr can be significantly
g y reduced
because of the losses
• The transfer function includes a high-frequency zero
due to the capacitor ESR

Solution: numerical results
Vg
Low-frequency gain: Gvc (0)   3.6  11 dB
VM
Pole center frequency: 1 1

fo   11 KHz
2 LC
R
Q factor without losses:
Q-factor Q  7.4  17 dB
L/C
Q factor with losses:

Q-factor 1
Qr   1.1
1 C
 ( Ron  RL  Resr )
Q L

Solution: control-to-output
magnitude and phase responses
100. 500. 1000. 5000. 10000. 50000.
30
20
No losses
Magnitude response Withh
Wi
losses
10
20 log Gvc ( jw) [dB] 0
-10
-20
100
100. 500
500.
500. 1000
1000.
1000. 5000
5000.
5000. 10000
10000.
10000. 50000
50000.
50000. 100000.
Phase response 0
-100
-200
-300
500. 1000. 5000.

10000. 50000. 100000.
23
HW circuit example Gm  100μA/V
Gm
 1.6 kHz
2Cc
Vg R
Gvc (0)   3.3  10.4 dB Q  17.9  25 dB
VM L/C
1
1 1 Qr   1.6  4 dB
fo   36 KHz 1 C
2 LC  ( Ron )
Q L
 G 
f c   m Gvc (0)  5.3 kHz
 2Cc  25
Start-up and load transient

Dynamic response improvements
Modify the error amplifier frequency response to shape the loop gain
• Increase cross-over
cross over frequency while keeping adequate phase
margin
• An error amplifier with “PID”

PID (proportional
(proportional-integral-derivative)
integral derivative)
frequency response is commonly applied (an example is shown on
the next page)
It is possible to obtain cross-over frequencies up to about 1/5 of the

converter switching frequency

Example: 5827_PWM1.asc
SW
S1
L1
g sw out
Vg 1
1µ
SW R1
C1 I1
1
PWL(0A 0 800u 0A 801u 1A)
3.3 100µ
S2
cinv

c
R3 C2 R4 C3
A1
30k 0 1n
0.1n 1k 0 5n
0.5n
Control R2
voltage vc U1
ctrl
100k
t
ref
Bpwm
.lib opamp.sub
V=if(v(ctrl t)+0 5 1 0)
Vsaw
PWL(0 0 500u 1)

.tran
tran 0 1000u 0 2n

Start-up and load transient
I(L1)
2.7A
2.4A
2.1A Inductor current
1.8A
1.5A
1.2A
0.9A
0.6A
0.3A
0.0A
-0.3A
V(out) V(ctrl)
1.5V
1.3V Control voltage
1 1V
1.1V
0.9V
0.7V
0.5V
0 3V
0.3V
Output voltage
0.1V
-0.1V

Voltage regulation during step-load transient
Inductor current I(L1)

2.8A
2.6A
2.4A
2 2A
2.2A
2.0A
1.8A
1.6A
1.4A
1.2A
1.0A
0 8A
0.8A
0.6A
0.4A
V(out) V(ctrl)
1.020V
1.014V
1.008V Output voltage
1 002V
1.002V
0.996V
0.990V
0.984V
0.978V
0.972V
0.966V
0.960V
0.954V
798µs 801µs 804µs 807µs 810µs 813µs 816µs 819µs 822µs 825µs 828µs 831µs 834µs

Announcements: final exam
On-campus students
• Will be handed out on Friday, Dec.11 in class.
• Due
D b by 10am on Wednesday,
W d d December
D b 16, in
i the
h iinstructor's
' office
ffi (OT346)
(OT )
Off-campus students
• Request the exam by e-mail
• The exam is then due in 5 days
• All off-campus work must be received by Monday, Dec.21

Introduction to voltage comparators

Open-loop op-amp as voltage comparator

Propagation delay test circuit

Open-loop op-amp as a comparator: propagation delays

No negative feedback: no need for compensation

Propagation delays without Cc

Reduce component aspect ratios: reduce parasitic caps

Reduced (W/L)’s: propagation delays

Increase bias current

Ibias = parameter: 1u, 2u, 5u, 10u



Application: PWM

PWM operation

PWM operation details

Other major application area for comparators:
A/D conversion
A/D conversion time limited by comparator propagation delay
A/D resolution limited by comparator input offset voltage

Comparator input offset voltage

Offset cancelation technique

High-speed regenerative comparators
Chapter 8 of Allen/Holberg, CMOS Analog Circuit Design, 2nd edition, Oxford 2002

Positive feedback: time constants

Example

High-speed regenerative comparators
Chapter 8 of Allen/Holberg, CMOS Analog Circuit Design, 2nd edition, Oxford 2002

Positive feedback: time constants

Example

Final Exam
4 problems = 100 points, extra-credit up to 20 pts
Policy and instructions
• 5-day, open-notes, open-book test
• Absolutely no collaboration or use of someone else’s work in any
form are allowed
• Please show your work in the space provided, turn in only the exam
sheets (except for design problem 4)
On-campus
On campus students: exam is due by 10am on Wednesday,
Wednesday
Dec.16
Off-campus
O ca pus stude
students:
ts request
equest tthe
eeexam
a by e
email,
a , due in 5
days; all class work must be received by Monday, Dec.21
Final Exam Design Problem
vp(t)
IDD VDD
VDD/2
vt(t)
+ + vpwm(t) t
VDD triangle-wave Ts/2 Ts/2
– generator _
comparator vt(t)
VH
vc + VM
–
VL
t
Ts/2 Ts/2
IB1 IB2
vpwm(t)
biasing circuit VDD
VDD/2
t
DTs
Ts = 1/fs
A. The pulsating output waveforms vp(t) and vpwm(t) have 0 and VDD
levels. The pulse widths of the waveforms should be measured
using
i cursors between
b t th points
the i t when
h theth waveforms
f cross VDD/2.
/2
B. Triangle-wave vt(t) frequency: fs = 1/Ts = 2 MHz ± 1%
C. Triangle-wave vt(t) peak-to-peak amplitude: VM = 1 V ± 10%  P 
2

D. Triangle-wave is symmetric, duty cycle of vp(t) is: (50 ± 5)% EC  round  20 DD min  
 
  DD 
P
E. Dutyy cycle
y D of vpwm((t)) is: 
a. D = (10 ± 1)% when vc = VL + 0.1 VM
b. D = (50 ± 1)% when vc = VL + 0.5 VM
c. D = (90 ± 1)% when vc = VL + 0.9 VM
Analog IC Topics Beyond
ECEN4827/5827
More advanced circuit design techniques
• Output
O t t stages
t
• Voltage comparators
• Fully differential circuits
• C
Currentt moded circuits,
i it currentt feedback
f db k
• Sampling, switched-capacitor and switched-current techniques
• Low voltage (rail-to-rail) or low power techniques
Noise
Layout issues
Use of CAD tools
Application areas: signal conditioning, power management, A/D
and D/A conversion, RF circuits
Major Analog IC Application Areas
PS PS PS PS
3.6 V 2.5 V 1.5 V 0.5-Vbat
Antenna
Display
P/DSP D/A PA
core LO
PS Audio
A/D LNA
2.7-5.5 V I/O
Interface
2.5 V 2.5 V 2.5 V
PS PS PS
General purpose amplifiers, comparators, sensors, etc.

P
Power managementt
• Linear voltage regulators, switched-mode power converters and controllers,
switched-cap (charge-pump) converters
Nyquist-rate and oversampling
g () D/A and A/D converters
RF circuits
• Oscillators, mixers, RF power amplifiers, low-noise amplifiers, etc.
Opportunities for further study
ECEN 5837 Mixed-Signal IC Design
Power Electronics Courses
• ECEN4797/5797 Intro
I t tot PE (prerequisite
( i it for
f the
th rest),
t) Fall
F ll semesters
t
• ECEN4517/5517 Lab (Spring 2010)
• ECEN5817 Resonant and Soft-Switching Tech (Spring 2010)
• ECEN5807 Modeling and Control of PE (Spring 2011)
Independent study
Research

ECEN 5837: Mixed-Signal IC Design
Spring 2010
Mixed-signal
g ICs
• Combination of analog blocks based on transistor-
level circuit design, and digital blocks based on
synthesis to gates from HDL (Verilog or VHDL)
• Hierarchical design
Project-oriented
Project oriented class
• Comprehensive “front-to-back” CAD tools (Cadence)
• Complete
p IC ready
y for “tape-out”
p
Contact: Prof. Regan Zane
Independent Study Opportunities
Literature review
eta ed ttransistor-level
Detailed a s sto e e ccircuit
cu t des
design
g aand
d
evaluation of advanced power control techniques
and power converter topologies
Topic examples
• Control of multi-phase converters
• Control of multi-level converters
• Control of buck/boost converters
• Nonlinear and adaptive power control techniques
• On-line efficiency optimization techniques
• A/D and D/A conversion for digital power control
• ….
Research: Colorado Power Electronics Center
http://ece.colorado.edu/copec
CoPEC faculty: Research and education programs

Bob Erickson
in smart power electronics for energy efficiency
Dragan Maksimovic
Regan
g Zane and renewable energy applications and systems
Zoya Popovic (RF Lab)
Luca Corradini (Research Associate)
CoPEC students: 22 Ph.D., 8 M.S. and 3 B.S. students
From FPGA-based digital

g
SMPS control …
… to energy harvesting …
…to custom IC
controller designs
for power
electronics …
…and energy efficient lighting

systems
Thanks for the g
good semester,,
good luck with the finals,
and have a great break

Analog Power Management Ic Design Copec

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ECEN4827/5827

• Instructor: Dragan Maksimovic

ECEN4827/5827 Analog IC Design 1

ECEN4827/5827 Analog IC Design 2

*Details can be found on the course website

ECEN4827/5827 Analog IC Design 3

ECEN4827/5827 Analog IC Design 4

The Real Signal Analog Signal

ECEN4827/5827 Analog IC Design 5

Battery example: single-cell Lithium-Ion Battery Charger

PS Linear or switched-mode voltage regulators (power supplies)

ECEN4827/5827 Analog IC Design 6

ECEN4827/5827 Analog IC Design 7

Relatively simple, low noise, small footprint area

ECEN4827/5827 Analog IC Design 8

ECEN4827/5827 Analog IC Design 10

vs(t) fs = 1/Ts = switching

ECEN4827/5827 Analog IC Design 12

vg(t) + vsw(t) C v(t)

p(t) vc(t) Voltage

ECEN4827/5827 Analog IC Design 13

ECEN4827/5827 Analog IC Design 14

.model SW SW(Ron=.05 Roff=1Meg Vt=0.5 Vh=0)

ECEN4827/5827 PWM controller behavioral model

30k 0.1n 1k 0.5n

PULSE({Vlow} {Vhigh} 0 {Tr} {Ts-Tr} 0 {Ts})

ECEN4827/5827 Analog IC Design 15

ECEN4827/5827 Analog IC Design 16

Inductor current I(L1)

ECEN4827/5827 Analog IC Design 17

.model SW SW(Ron=.05 Roff=1Meg Vt=0.5 Vh=0)

ECEN4827/5827 PWM controller behavioral model

30k 0.1n 1k 0.5n

PULSE({Vlow} {Vhigh} 0 {Tr} {Ts-Tr} 0 {Ts})

Focus on transistor-level integrated circuit design techniques

ECEN4827/5827 Analog IC Design 18

.model SW SW(Ron=.05 Roff=1Meg Vt=0.5 Vh=0)

ECEN4827/5827 PWM controller behavioral model

30k 0.1n 1k 0.5n

ECEN4827/5827 Analog IC Design 19

ECEN4827/5827 Analog IC Design 20

.model SW SW(Ron=.05 Roff=1Meg Vt=0.5 Vh=0)

ECEN4827/5827 PWM controller behavioral model

30k 0.1n 1k 0.5n

PULSE({Vlow} {Vhigh} 0 {Tr} {Ts-Tr} 0 {Ts}) Design of

ECEN4827/5827 Analog IC Design 21

ECEN4827/5827 Analog IC Design 22

.model SW SW(Ron=.05 Roff=1Meg Vt=0.5 Vh=0)

ECEN4827/5827 PWM controller behavioral model

30k 0.1n 1k 0.5n

PULSE({Vlow} {Vhigh} 0 {Tr} {Ts-Tr} 0 {Ts})

.model SW SW(Ron=.05 Roff=1Meg Vt=0.5 Vh=0)

ECEN4827/5827 PWM controller behavioral model

30k 0.1n 1k 0.5n

PULSE({Vlow} {Vhigh} 0 {Tr} {Ts-Tr} 0 {Ts})

ECEN4827/5827 Analog IC Design 24

.model SW SW(Ron=.05 Roff=1Meg Vt=0.5 Vh=0)

ECEN4827/5827 PWM controller behavioral model

30k 0.1n 1k 0.5n

ECEN4827/5827 Analog IC Design 25

ECEN4827/5827 Analog IC Design 26

ECEN4827/5827 Analog IC Design 1