4004 SINGLE CHIP 4-BIT P-CHANNEL MICROPROCESSOR = 4-Bit Parallel CPU With 46 «= CPU Directly Compatible Instructions With MCS-40 ROMs and a Instruction Set Includes RAMs Conditional Branching, = Easy Expansion—One CPU Jump to Subroutine and can Directly Drive up to Indirect Fetching 32,768 Bits of ROM and up = Binary and Decimal to 5120 Bits of RAM Arithmetic Modes «= Standard Operating 7 Temperature Range of = 10.8 Microsecond kK _ Instruction Cycle 0° to 70°C = Also Available With -40° to +85°C Operating Range ‘The Intel® 4004 is a complete 4-bit parallel central processing unit (CPU). The 4004 easily interfaces with keyboards, switches, displays, A-D converters, printers and other peripheral equipment. ‘The CPU oan directly address 4K 8-bit instruction words of program memory and 5120 bits of data storage RAM. Sixteen index registers are provided for temporary data storage. Up to 16 4-bit input ports and 16 4-bit output ports may also be directly addressed. “The 4004 is fabricated with P-channel silicon gate MOS technology. act a se “Lt | [a Ts ome: 8154004 Pin Description oo Henan para |" fm ra | nestoay ‘te count Wo oy [J omnam, | ourrur Ps icunans “eq D v0 exer ‘uenony agetlecd Ficwvon | Eom mejor] [rer ult? } seme CY Freer Do-Da BIDIRECTIONAL DATA BUS. All address and data communication between the processor and the RAM and ROM chips occurs on these 4 lines. RESET RESET input. A logic ""1” level at this input clears. all flags and status registers and forces the program counter. to zero. To completely clear all address and index registers, RESET must be applied for 64 clock cycles (8 machine cycles). TEST TEST input. The logical state of this signal may be tested with the JCN instruction. syNC ‘SYNC output. Synchronization signal generated by the processor and set to the ROM and RAM chips. It indicates the beginning of an instruction cycle. a6 is the ROM selection signal sent out by the processor when data is required from program memory. CM-RAMp — CM-RAM3 CM-RAM outputs. These are the bank selection sig- nals for the 4002 RAM chips in the system. $4. b Two phase clock inputs. Vss Most positive voltage, Vop Veg -15 +5% main supply voltage.4004 Instruction Set Format A. Machine Instructions © 1 word instruction — 8-bits requiring 8 clock periods (instruction cycle). ¢ 2.word instruction — 16-bits requiring 16 clock periods (2 instruction cycles). Each instruction is divided into two four-bit fields. The upper 4-bits is the OPR field containing the ‘operation code, The lower 4-bits is the OPA field containing the modifier. For two word instructions, the second word contains address information or data. The upper 4-bits (OPR) will always be fetched before the lower 4-bits (OPA) during My and Mz times respectively. ‘ONE WORD INSTRUCTIONS ‘TWO WORD INSTRUCTIONS oe NO mle aa ele PP PPP Paes on on orn ‘0Fcope wooIFiER [eb Les aon pam iare aR PEL Le, TCE RS=.) ERE SEs E EE ee EEE ° ae Table |. Machine Instruction Format B. Input/Output and RAM Instructions and Accumulator Group instructions In these instructions (which are all single word) the OPR contains a 4-bit code which identifies either the I/O instruction or the accumulator group instruction and the OPA contains a 4-bit code which identifies the operation to be performed. Table I! illustrates the contents of each 4-bit field. o_o Table II, 1/0 and Accumulator Group Instruction Formats a74004 4004 Instruction Set BASIC INSTRUCTIONS (* = 2 Word Instructions) OPA ‘DESCRIPTION OF OPERATION D,0,0, 0.0.0 Nooperatin Jump t9 ROM adress yy Aa Ba As As Ay (wii the same ‘ROM that contains ths JEN instruction) if condition G, CC, c tet wvenone., O78 00 NOP_000 1 cu Is tue, oterwise go to the net instruction in sequence er Fetch immediate (arect om ROM Data 0,0, 0, 0; 0,0,0,, {0 index register par location ARR, Feich indirect fr ROW. Send contents of adex register par 3. FN Tecation out as an adress, Data fetch fs placed int egister Bair location RAR. 011 AAA 1 WTO indrect. Send conens of repiter par ARR ou as an adress ae RAN Rear A tie nthe suction eee 4 sayy P92 AA ALAs dum uncondtiona to ROM ales A, AVAL AL AAs e Ahk KAAK ARAK ee ung 01.9.1 AvAsAAs Jump to subroutine ROM adress A sh AB Bye - Ah AGA, By Ay SE ot Gass (yp leven slack) NOt Increment contents ofgister AAR. ; Ineementeortntot enter RRA, Got ROM aHeess AA, a +2 ‘Avs B A (win ihe sare ROW tatconansiistSzincn) ifresult 0. of wise goto the net instruction Load contents of egit Exchange contents of index register ARR and accumulator Branch back (down 1 level in stack and load data 0000 to accumulator 0 04 O00 0 tow daa 000016 1100-00 Clear bah Acumsatr and cary) 100-01 Cea cay 0-010 0-0 11 Colement cary. o1o0 OF 0-1 Rode et. Accumulate scar 01 4.0 Rotate right. (Accumulator and carry) 11 Tans cary occur nd car car 100-0 Oucrenet accomutor.— 10sec subacl ndCarGy — 1010 ry 1110 11 Ona ast acenaar fo KP 1411 1100 OER OceaeTEai 8184001/4002/4008/4009/4289 4004 INPUT/OUTPUT AND RAM INSTRUCTIONS Hex “OPA OPA 2. src 0010 RAAY fo WAM 1110 0000 B oWMP 11410 0004 f WAR 1110 0010 3 WwM 1110 00714 Wao & wa 1110 0107 “6 wa i110 0110 we tte nig “1000, a 01001 Fe ADM 1140 1014 Fe eee eo ADL 1410 41014 Be AD eo) & moO 1110 4444 Cote NNEMONICD, 0.0, 0, 0,0;0,0,_ ____ instruction cycle, 110 0100 fA ROR 1110 1010 "DESCRIPTION OF OPERATION ‘Send tepister control. Send the address (contents of index register par RAR) to ROM and RAM 2tX, and, time in the Weite the contents ofthe accumulator into the previously selected _RAM main memory character. : Wie the contents ofthe accumulator into the previously select __ARM output port. (Output Lines) Write the contents of the accumulator into the previously selected OW outout port, (VO Line) _ Wt the contents of he accumulator no ihe prevousy sowed al yt of ealwnte program memory (sea 4008/4008 4289 ony) _ Wit the contents of ie accumulator ino the orevousyseeced _RAM status ¢ ‘Write the contents ofthe accumulator into the previously selected RAM status character 1. oom Write the contents ofthe accumulaor ito the previously selected RAM status characer 2. Wie the contents ofthe accumulator into the previously selected AM status characer 3. Subtract the previously selected RAM main memory character tom accumulator with Bortow. Read the previously selected RAM main memory character into the accumulator, ead the contents of the previously selected ROM input port into the accumulator (0 Lines) ‘Aad the previously selected RAM main accumulator with cary Read the previously selected RAM status character O into accumulator Read the previously selected RAM status ehara accumulator, ead the previously selected RAM status character 2 into accumulatr, ead the previously selected RAM status character 3 lato B194004 Instruction Codes Hex Mnemonic Hex Mnemonic Hox Mnemonie Hex. Mnemonic oO = 40 JUN 80 ADD 0 co BBL on - 41 JUN Bi ADD 1 cr ppt 1 a - 42. JUN 82 ADD 2 co BBL 2 - 43° JUN 83 ADD 3 3 BBL 3 om = 44° JUN 84 ADD 4 ch eBL 4 = 45 JUN 85 ADD § cS BBL OS % 46 JUN 8 ADD 6 cé BBL OG a - 47 JUN 87 ADD 7 cr BBL 7 og = 48 JUN 88 ADD 8 ce BBL OB oo = 43° JUN 89 ADD 3 co eB 9 oA 4A JUN 8A ADD 10 cA BBL 10 oe 48 JUN 88 ADD 11 ce BBL 11 oc 4c JUN 8c ADD 12 co BBL 2 op 40 JUN 80 ADD 13 co BBL 13 oe - ae Jun | Secondhex | 8€ ADD 14 ce BBL 14 oF af sun | digitispart | 8F ADD 15 CF BBL 15 10 Jon 50 JMS Pot jump 90 SUB 0 do wom oO 1 JN 51 JMS | addcess, 31 SUB t oY LOM + 12 Jen 52. JMS 92 SUB 2 02 Lom 2 13 JON 53. JMS 93 SUB 3 03 Lom 3 14 JON 54 JMS a SUB 4 oa tom 4 15 JON 56 IMS 95 SUB 5 06 LOM 5 16 Jen 56 JMS 98 SUB 6 Ds LOM 6 17 JN 57 IMS 97 SUB 7 07 Lom 7 18 JN 58 JMS 98 SUB 8 08 LOM 8 13. JN 59 IMS 93 SUB 9 og Lom 3 1A JeN 5A JMS 9A SUB 10 DA LOM 10 18 Jen 58 JMS 98 SUB IT 0B Lom 11 1c Jen ¢ JMS gc SUB 12 Oc Lom 12 1D Jen 50 JMS 90 sus 13 00 Lom 13 te Jen 5E JMS ge SUB 14 DE Lom 14 1F Jew SF JMS oF SUB 15 DF Lom 15 20 FIN 60 cD Ao uD 0 £0 wRM 21 sre 1 INC 4 aru ot E1 WMP 2 FIM 2 62 INC 2 ze) = a F2 WRR 23 sro 2 62 Inc 3 Ag LD 3 £3 WPM 24 FIM 4 4 INC 4 Ad uo 4 Ea WRO 2 SRC 4 65 INC 5 AS UD 5 5 WRI 2 FIM 6 66 INC 8 AG LD 6 6 WR2 a sac 6 67 INC 7 Ar 07 ET WR3 2 FIM 8 se Nc 8 ag LD 8 ES som 2 sRc 8 69 INC 9 ag uo 8 F9 ROM 2a FIM 10 6A INC 10 AA LO 10 EA ROR 28 SRC 10 8 ive 11 AB LD 11 EB ADM 2c FIM 12 sc INC 12 AC LD 12 EC RDO 20 SRC 12 80 INC 13 AD LD 13 ED RDI 2 FIM 14 8 INC 18 AE WW 14 FE RD2 2 SRC 14 eF INC 15 AF LD 15 EF RO3 30 FIN oo m 182 0 80 XCH 0 FO cla © 31 uN 0 nits 81 XCH 1 FI cue 32 FIN 2 m Wz 2 82 XCH 2 F2 ‘IAC 33 JIN 2 3 Sz 3 83 XCH 3 F3 cue 34 FIN 4 m4 Sz 4 Ba xXcH 4 Fa CMA 3 IN 4 15 1825 85 XCH 5 F5 RAL 36 FIN 6 1 sz og 86 XCH 6 F5 RAR a7 NG m7 sz 7 87 XcH 7 F7 Tec 38 FIN 8 7 ISZ 8B 88 xXCH 8 Fa DAC 3 N 8 19 182 9 89 XCH 9 F9 Tes 3A FIN. 10 7A 18210 BA XCH 10 FA STC 38 JIN 10 7B 1sz 1 BB XCH 11 FB DAA 3c FIN 12 me 182 12 BC XCH 12 FC KBP 30 IN 12 ™ 62 13 8D XcH 13 3e FIN 14 TE 1sz 18 BE XCH 1a oF JIN 4 TF SZ 18 BF XCH 15 8204004 ‘Absolute Maximum Ratings* OC 10 70°C *commeNT: “eseG to + 128°C Saaee0 above those lsted under “Absolute Maximum Ratings" may eause permanent damage oth device. This is astress rating ‘persion of the device a these or any other +0.8V to -20V conattions above tose indicated nthe operational sections ofthis 1.0 Watt specitoaion i not implies ‘ambient Temperature Under Bias Storage Temperature se... input Voltages and Supply Voltage wwith respect t0 VSS : Power Dissipation D.C. and Operating Characteristics Tq 20°C to 70°C; Ves “Von = 15V # 5%; tgpy = tg01 = 400 nsec; logic “0” is defined as the more postive vottage {W. Vor); loge "1" is dined as the more negative voltage (Vi. Vor); Unless Otherwise Specified. supPLY CURRENT symbol Parameter Min. Tye’ Max, | Unit | Test Conditions “po | Avene Supply Current ee INPUT CHARACTERISTICS Tur__| Input Leakage Current 10 [A | Yu=Voo Vin | Input High Voltage (Except Clocks) Ves-18 Tie | Trput Low Voltage (Except Clocks) Yoo Vino | Input Low Voltage Yoo 4004 TEST Input Vine | Input High Voltage Clocks Ves-1.8 “Vine | Input Low Voltage Clocks op ‘OUTPUT CHARACTERISTICS ito | Data Bus Output Leakage Current 70 [uA Von | Output High Voltage Ves-5V Ves V_| Capacitance Load Tou | Date Lines Sinking Current 8 16 mA | Vour=Ves To.__| CM-ROM Sinking Current es 12 mA | Vour=Ves Tou__| OMRAM Sinking Current 25. 6 mA | _Vour=Ves You | Outout Low Vortago, Data Bus, OM, SYNC Vos? Ves-65| V | tou=0.5mA Ron | Output Resistance, Data Line “0” Level 150 250 | & | Vour=Ves--5V Fon | CN-ROM Output Resistance, Dato Line “O” Level 320600 | @ | Vour=VWsr8V Fon | CM-RAM Output Resistance, Data Line "0" Level WW 18 | k@ | Vour=Vos-5V CAPACITANCE & Clock Capacitance : 4 20 | pF | Vin=Ves Cos | Data Bus Capacitance 710 | pF | Vin=Ves Giv__| Input Capacitance 10 | oF Cour | Output Capacitance 70 | oF | Vin=Ves 821Typical D.C. Characteristics 4004 T 8 ‘ean = to = 40 F (G02 0 me ge PSone es i Jatt 5 A.C. Characteristics Ta20°C to 70°C, Vss-Vop = 15V 28% Limi symbol Parameter Fit agg, | Unit | Test Conditions toy | Clock Period 1.35) 20 | usec ton | Clock Rise Time 50 | ne tyr | Glock Fall Times 50 | as ‘gpm | Glock Width 380 480 | ae tyo1 | Clock Delay # to ¢2 400 550 | ns teo2 | Clock Delay 2 to $1 150 ns w Data-In, CM, SYNC Write Time 350 100 ns tu!t)_ | Data-tn, CM, SYNC Hold Time 40 20 ns ‘twl3l_ | ‘Data Bus Hold Time During My-X, and 150 ns | and Xo-X3 Transition = tosl2_| Set Time (Reference) ° ns taco | DataOut Access Time conre Data Lines 930 | ns | 500pF Data Lines Data Lines 700 | ns | 200pF Data Linest#l SYNC 930 | ns | 500pF SYNC cM-ROM 930 | ns | 160pF cM-ROM CM-RAM 930 | ns | S0pF CM-RAM ton | Dat-Out Hold Time 50160 ns | Cour=20pF Notes: 1.24 measured mith tora = Ons. 2.Tagc is Date Bus, SYNC and Chine output access time referred to the $2 taling edge which clocks these ines out. tog isthe same output access time raforred tothe leading edge of the next clock pulse 3. MCS-40 components which may transmit instruction ar date to the 4004 at My and Xz always enter afloat state until the 4004 takes over the dota bus at X; and X3 time, herefore the ty, requirement is always insured since each component contributes 1014 of leskoge current and TOpF of capacitance wiich guarantees that the data ous eannot change faster than V/s. 4.C$oATA BUS" 2008 IF 4008 and 4009 or 4289 is used. 8224004 4 ™ pa oes * T I l 7 a { sc + nnn nose 1 a Figure 1. Timing Diagram, Figure 2. Timing Detail