M.tech Class 2

CMOS Transistor Theory
11/11/10 Faculty: Rekha S S, Sr.lecturer, dept. of TE Slide 1

Introduction
• So far, we have treated transistors as ideal
switches
• An ON transistor passes a finite amount of
current
– Depends on terminal voltages
– Derive current-voltage (I-V) relationships
• Transistor gate, source, drain all have
capacitance
– I = C (∆ V/∆ t) -> ∆ t = (C/I) ∆ V
– Capacitance and current determine speed
• MOS transistor symbol
CMOS VLSI Design

Conduction characteristics for enhancement and
depletion mode MOS transistors (assuming fixed Vds)
Enhancement mode
Depletion Mode
CMOS VLSI Design

nMos Enhancement Transistor
CMOS VLSI Design

Accumulation, Depletion and inversion modes in an MOS
structure
• Gate and body form MOS capacitor

• Operating modes
– Accumulation
CMOS VLSI Design

structure contd..,
– Depletion
CMOS VLSI Design

structure contd..,
– Inversion
CMOS VLSI Design

Terminal Voltages
Vg
• Mode of operation depends on Vg, Vd, Vs
+ +
– Vgs = Vg – Vs Vgs Vgd
- -
– Vgd = Vg – Vd
Vs Vd
- +
– Vds = Vd – Vs = Vgs - Vgd Vds
• Source and drain are symmetric diffusion terminals

– By convention, source is terminal at lower voltage
– Hence Vds ≥ 0
• nMos body is grounded.
• Three regions of operation
– Cutoff
– Linear
– Saturation
CMOS VLSI Design
nMos Cutoff
• No channel
• Ids = 0
Vgs = 0 Vgd
+ g +
- -
s d
n+ n+
p-type body
b
CMOS VLSI Design

nMOS Linear
• Channel forms
• Current flows from d +to s Vgs > Vt
g +
Vgd = Vgs
- -
– e from s to d
- s d
Vds = 0
n+ n+
• Ids increases with Vds p-type body

b
• Similar to linear resistor Vgs > Vt

Vgs > Vgd > Vt
+ g +
- - Ids
s d
n+ n+
0 < Vds < Vgs-Vt
p-type body
b
CMOS VLSI Design

nMOS Saturation
• Channel pinches off
• Ids independent of Vds
• We say current saturates
• Similar to current source Vgs > Vt
g Vgd < Vt
+ +
- -
s d Ids
n+ n+
Vds > Vgs-Vt
p-type body
b
CMOS VLSI Design

I-V Characteristics
• In Linear region, Ids depends on
– How much charge is in the channel?
– How fast is the charge moving?
CMOS VLSI Design

Channel Charge
• MOS structure looks like parallel
plate capacitor while operating in
inversion
– Gate – oxide – channel
• Qchannel =
gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
channel
tox n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, εox = 3.9) p-type body
p-type body
CMOS VLSI Design

Channel Charge
inversion
• Qchannel = CV
gate
• C= polysilicon +
Vg
+
gate source Vgs Cg Vgd drain
W
Vs - - Vd
channel
tox n+ - + n+
SiO2 gate oxide
Vds
L
p-type body
CMOS VLSI Design

Channel Charge
inversion
– Gate – oxide – channel Cox = ε ox / tox
• Qchannel = CV
gate
• C = Cg = ε oxWL/tox = CoxWL +
polysilicon
source V
gate gs
Vg
Cg
+
Vgd drain
W
Vs - - Vd
• V= tox
L SiO2 gate oxide
n+ -
channel
Vds
+ n+
p-type body
CMOS VLSI Design

Channel Charge
• MOS structure looks like parallel plate
capacitor while operating in inversion
• Qchannel = CV Cox = ε / tox
ox
• C = Cg = ε oxWL/tox = CoxWL
• V = Vgc – Vt = (Vgs – Vds/2) – Vt +
gate
Vg
+
source Vgs Cg Vgd drain
polysilicon - -
gate Vs channel Vd
W n+ - + n+
Vds
tox
p-type body
L SiO2 gate oxide
n+ n+ (good insulator, εox = 3.9)
p-type body
CMOS VLSI Design
Carrier velocity
• Charge is carried by e-
• Carrier velocity v proportional to
lateral E-field between source and
drain
• v=
CMOS VLSI Design

Carrier velocity
drain
• v=µ E µ called mobility
• E=
CMOS VLSI Design

Carrier velocity
drain
• E = Vds/L
• Time for carrier to cross channel:
–t=
CMOS VLSI Design
Carrier velocity
drain
• E = Vds/L
• Time for carrier to cross channel:
–t=L/v
CMOS VLSI Design
nMOS Linear I-V
• Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to
I ds =cross
CMOS VLSI Design

nMOS Linear I-V
• Now we know
Qchannel
I ds =cross
t
=
CMOS VLSI Design

nMOS Linear I-V
• Now we know
Qchannel
I ds =cross
t
W V − V − Vds V
= µCox  gs t  ds
L  2 
W
= β Vgs − Vt − ds Vds
V β = µCox
 2 L
CMOS VLSI Design

nMOS Saturation I-V
• If Vgd < Vt, channel pinches off near
drain
– When Vds > Vdsat = Vgs – Vt
• Now drain voltage no longer
I ds =
increases current
CMOS VLSI Design

nMOS Saturation I-V
drain
• Now drain  voltage
Vdsat no longer
I ds = β  Vgs − Vt − Vdsat
increases  current2 
CMOS VLSI Design

nMOS Saturation I-V
drain
I ds = β Vgs − Vt − dsat Vdsat
V
• Now drain  voltage2 no longer
increases β current
= ( Vgs − Vt )
2
CMOS VLSI Design

nMOS I-V Summary
• Shockley 1st order transistor models

 0 Vgs < Vt cutoff

  Vds V V < V
I ds =  β Vgs − Vt −  ds linear
 2 
ds dsat

 β
( Vgs − Vt )
2
 Vds > Vdsat saturation
2
CMOS VLSI Design

Example
• We will be using a 0.6 µ m process
for your project
– From AMI Semiconductor
2.5
Vgs = 5
– tox = 100 Å 2
– µ = 350 cm2/V*s 1.5 Vgs = 4
Ids (mA)
V
– t = 0.7 V 1
Vgs = 3
0.5
• Plot Ids vs. Vds 0
Vgs = 2
Vgs = 1
0 1 2 3 4 5
– VWgs = 0,  3.91, 2, 3, 4, 5 W
• 8.85 ⋅ 10   W 
−14 Vds
β = µC = ( 350 )    L  = 120 L µ A / V
2
= 4/2 λ 
ox −8
⋅
– Use W/L
L  100 10
CMOS VLSI Design

pMOS I-V
• All dopings and voltages are inverted for
pMOS
• Mobility µ p is determined by holes
– Typically 2-3x lower than that of electrons µ n
– 120 cm2/V*s in AMI 0.6 µ m process

• Thus pMOS must be wider to provide same
current
– In this class, assume µ n /µ p =2
– *** plot I-V here

CMOS VLSI Design
Capacitance
• Any two conductors separated by an insulator
have capacitance
• Gate to channel capacitor is very important
– Creates channel charge necessary for operation
• Source and drain have capacitance to body
– Across reverse-biased diodes
– Called diffusion capacitance because it is
associated with source/drain diffusion
CMOS VLSI Design

Gate Capacitance
• Approximate channel as connected
to source
• Cgs = ε oxWL/tox = CoxWL = CpermicronW
• Cpermicron is typically
polysilicon
about 2 fF/µ m
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, εox = 3.9ε0)
p-type body
CMOS VLSI Design


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CMOS Transistor Theory

11/11/10 Faculty: Rekha S S, Sr.lecturer, dept. of TE Slide 1

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

• Gate and body form MOS capacitor

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

• Source and drain are symmetric diffusion terminals

CMOS VLSI Design

• Ids increases with Vds p-type body

• Similar to linear resistor Vgs > Vt

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

CMOS VLSI Design

– µ = 350 cm2/V*s 1.5 Vgs = 4

CMOS VLSI Design

– 120 cm2/V*s in AMI 0.6 µ m process

– *** plot I-V here

CMOS VLSI Design

CMOS VLSI Design

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