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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TKBSTP is
Port ( pkeycol : in std_logic_vector (3 downto 0);
pkeyrow : out std_logic_vector (3 downto 0);
pstpsig : out std_logic_vector(3 downto 0);
pclk100K : in std_logic );
end TKBSTP;
begin
-- clkdivider
process(pclk100k)
begin
if( rising_edge(pclk100k)) then
sclkdiv <= sclkdiv+1;
end if;
-- key process
-- out key row = 0 check key col
pkeyrow <= "0000";
process(pkeycol)
begin
if(pkeycol(0) = '0' or
pkeycol(1) = '0' or
pkeycol(2) = '0' or
pkeycol(3) = '0' ) then skeyhit <= '0';
else skeyhit <= '1';
end if;
end process;
-- latch key press
process(skeyhit)
begin
if( falling_edge(skeyhit)) then
skeysts <= pkeycol;
end if;
end process;
-- 4 step counter
process(sstpclk)
begin
if(rising_edge(sstpclk)) then
if(skeysts(0) = '0') then
sstpcnt <= sstpcnt+1;
elsif(skeysts(1) = '0') then
sstpcnt <= sstpcnt-1;
end if;
end if;
end process;
end behavioral;
#PINLOCK_BEGIN
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TKBELE is
Port ( pkeyret : in std_logic_vector(3 downto 0);
pkeyscn : out std_logic_vector(3 downto 0);
pdspseg : out std_logic_vector (6 downto 0);
pdspmux : out std_logic_vector (3 downto 0);
pclk100K : in std_logic
);
end TKBELE;
begin
-- process keypress
process(pkeyret)
begin
case pkeyret is
when "1110" => skeyhit <= '1';
when "1101" => skeyhit <= '1';
when "1011" => skeyhit <= '1';
when "0111" => skeyhit <= '1';
when others => skeyhit <= '0';
end case;
end process;
process(skeyhit)
begin
if( rising_edge(skeyhit)) then
lkeyscn <= skeyscn;
lkeyret <= pkeyret;
end if;
end process;
-- process keyval
process(skeyhit)
begin
if( rising_edge(skeyhit)) then
if(lkeyscn = "1110" and lkeyret = "1110")
then skeyflr <= 0;
elsif(lkeyscn = "1110" and lkeyret = "1101")
then skeyflr <= 1;
elsif(lkeyscn = "1110" and lkeyret = "1011")
then skeyflr <= 2;
elsif(lkeyscn = "1110" and lkeyret = "0111")
then skeyflr <= 3;
elsif(lkeyscn = "1101" and lkeyret = "1110")
then skeyflr <= 4;
elsif(lkeyscn = "1101" and lkeyret = "1101")
then skeyflr <= 5;
elsif(lkeyscn = "1101" and lkeyret = "1011")
then skeyflr <= 6;
elsif(lkeyscn = "1101" and lkeyret = "0111")
then skeyflr <= 7;
elsif(lkeyscn = "1011" and lkeyret = "1110")
then skeyflr <= 8;
elsif(lkeyscn = "1011" and lkeyret = "1101")
then skeyflr <= 9;
elsif(lkeyscn = "1011" and lkeyret = "1011")
then skeyflr <= 10;
elsif(lkeyscn = "1011" and lkeyret = "0111")
then skeyflr <= 11;
elsif(lkeyscn = "0111" and lkeyret = "1110")
then skeyflr <= 12;
elsif(lkeyscn = "0111" and lkeyret = "1101")
then skeyflr <= 13;
elsif(lkeyscn = "0111" and lkeyret = "1011")
then skeyflr <= 14;
elsif(lkeyscn = "0111" and lkeyret = "0111")
then skeyflr <= 15;
end if;
end if;
end process;
#PINLOCK_BEGIN
#PINLOCK_END
*****END OF ELEVATOR
******HEX KEY PAD
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TKBHKY is
Port ( pkeyret : in std_logic_vector(3 downto 0);
pkeyscn : out std_logic_vector(3 downto 0);
pdspseg : out std_logic_vector (6 downto 0);
pdspmux : out std_logic_vector (3 downto 0);
--pledind : out std_logic_vector (7 downto 0);
pclk100K : in std_logic
);
end TKBHKY;
begin
-- process keypress
process(pkeyret)
begin
case pkeyret is
when "1110" => skeyhit <= '1';
when "1101" => skeyhit <= '1';
when "1011" => skeyhit <= '1';
when "0111" => skeyhit <= '1';
when others => skeyhit <= '0';
end case;
end process;
process(skeyhit)
begin
if( rising_edge(skeyhit)) then
lkeyscn <= skeyscn;
lkeyret <= pkeyret;
end if;
end process;
-- process keyval
process(skeyhit)
begin
if( rising_edge(skeyhit)) then
if(lkeyscn = "1110" and lkeyret = "1110")
then skeyval <= 0;
elsif(lkeyscn = "1110" and lkeyret = "1101")
then skeyval <= 1;
elsif(lkeyscn = "1110" and lkeyret = "1011")
then skeyval <= 2;
elsif(lkeyscn = "1110" and lkeyret = "0111")
then skeyval <= 3;
elsif(lkeyscn = "1101" and lkeyret = "1110")
then skeyval <= 4;
elsif(lkeyscn = "1101" and lkeyret = "1101")
then skeyval <= 5;
elsif(lkeyscn = "1101" and lkeyret = "1011")
then skeyval <= 6;
elsif(lkeyscn = "1101" and lkeyret = "0111")
then skeyval <= 7;
elsif(lkeyscn = "1011" and lkeyret = "1110")
then skeyval <= 8;
elsif(lkeyscn = "1011" and lkeyret = "1101")
then skeyval <= 9;
elsif(lkeyscn = "1011" and lkeyret = "1011")
then skeyval <= 10;
elsif(lkeyscn = "1011" and lkeyret = "0111")
then skeyval <= 11;
elsif(lkeyscn = "0111" and lkeyret = "1110")
then skeyval <= 12;
elsif(lkeyscn = "0111" and lkeyret = "1101")
then skeyval <= 13;
elsif(lkeyscn = "0111" and lkeyret = "1011")
then skeyval <= 14;
elsif(lkeyscn = "0111" and lkeyret = "0111")
then skeyval <= 15;
end if;
end if;
end process;
end behavioral;
*****ucf file
#PINLOCK_BEGIN
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TKBDCM is
Port ( psw : in std_logic_vector(2 downto 0);
pdcm : out std_logic;
p100k : in std_logic
);
end TKBDCM;
begin
-- 1f4,320,44c,578,6a4,7d0,8fc,9c4
if(psw = "000" and sclkdiv = "000111110100") then vdcm := '0';
elsif(psw = "001" and sclkdiv = "001100100000") then vdcm := '0';
elsif(psw = "010" and sclkdiv = "010001001100") then vdcm := '0';
elsif(psw = "011" and sclkdiv = "010101111000") then vdcm := '0';
elsif(psw = "100" and sclkdiv = "011010100100") then vdcm := '0';
elsif(psw = "101" and sclkdiv = "011111010000") then vdcm := '0';
elsif(psw = "110" and sclkdiv = "100011111100") then vdcm := '0';
elsif(psw = "111" and sclkdiv = "100111000100") then vdcm := '0';
end if;
end process;
end behavioral;
****UCF FILE
#PINLOCK_BEGIN
*****END OF DC MOTOR
********LCD DISPLAY
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tkblcd is
Port (
plcddat : out std_logic_vector (7 downto 0);
plcdrs,plcdrw,plcden : out std_logic;
pclk100K : in std_logic
);
end tkblcd;
begin
-- clkdivider
process(pclk100k)
begin
if( rising_edge(pclk100k)) then
sclkdiv <= sclkdiv+1;
end if;
-- display
process(sdspclk)
variable vdspseq : integer range 0 to 15;
variable vdspnum : integer range 0 to 15;
variable i1 : integer;
begin
if(falling_edge(sdspclk) ) then
vdspseq := vdspseq+1;
end if;
if(falling_edge(sdspclk) ) then
if(vdspseq > 3) then
vdspnum := vdspnum+1;
end if;
end if;
end process;
end behavioral;
*******UCF FILE
#PINLOCK_BEGIN
#PINLOCK_END