Computer System Architecture
Processor Part IIT
Chalermek Intanagonwiwat
‘Shides courtesy of John Hemessy and David Patterson
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What's wrong with our CPI=1
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Abstract View of our single mmrcemans
cycle processor
Ma
oo. Contr
Result Store
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instruction Fe ure tlood >
many cycle tire eal
oT niy Instruction ees?
conmetcatouean _ PrOCeSSOr? | _Memory Access Time
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(eC [inst emer [Reg Fie Im ALD [Data em acres ‘atte
sranch
eco $ sense aps
+ Long Cycle Time
+ All instructions take as much time as the slowest
+ Real memory is not so nice as our idealized memory
= cannot always get the job done in one (short) cycle
+ Physics => fast memories are small
(large memories are slow)
Huds memory coctuweniy ngs oA nextMemory Access Time (cont.)
+ => Use a hierarchy of memories
woods
svlrsensin} iow abil
ihm, ( vinsormenihna 5.55 2 ly
ae
2 [memoy
| 20-50 eyces
Basic Limits on Cycle Time
Next address logic
- PC <= branch ? PC + offset : PC +4
Instruction Fetch
= InstructionReg <= Mem{PC]
Register Access
-A&Rirs]
ALU operation
-ReA+B
Reducing Cycle Time
+ Cut combinational dependency graph and
insert register / latch
+ Do same work in two fast cycles, rather
than one slow one e sone
‘oyeic
‘Combinational
‘agi (A)
ge ee,
cory:
‘Aoyele cote
Combinatonat
Logie (8)
Eatragesement
eccets dole
fener
Ssaaesiemen] °°
Basic Limits on Cycle Time (cont.)
Mem
Access
Rest Store
manera pamile| Tntnnefesby
Btisivirounismuceeitucdug finitePartitioning the CPI=1 Datapath
+ Add registers between smallest steps |
tenn yegistey sin b
| cohanrsres
pregenrevonebil >
Example Multicycle Datapath
Equal
3
3
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Recall: Step-by-step Processor Step 4: R- “type (ada, sub, )
Design * Logical Register ony ae an enti i
Transfer
Step 1: ISA => Logical Register Transfers + Physical _ pe
Register
Step 2: Components of the Datapath Tronefers :
Step 3: RTL + Components => Datapath
t ot |
Equal
Step 4: Datapath + Logical RTs => Physical
fe kg
PS register ooshinhy ia vege 4-5, F6,28 Hhinaetht Lagica! Reiter a 2
feel: Horete “cennaouTinnitefaciu register les sf
Step 5: Physical RTs => Control “wenn o>
Perec” euiteinne